Commit Graph

79 Commits

Author SHA1 Message Date
9909b3bbdb sw: usb-desc: set product name to "Fomu Bootloader"
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-11 11:50:55 +08:00
f5fd282d61 sw: usb-dev: remove errant i++
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 22:46:02 +08:00
5bcd6c44fb deps: update valentyusb to working rev
This revision works, although more tuning needs to be done.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 22:43:28 +08:00
d64f88d995 sw: usb-epfifo: mostly-working commit
Still has issues with large reads.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 22:42:14 +08:00
c180c1b1b8 sw: usb-epfifo: increase packet size to 64 bytes
This masks some problems we're seeing.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 22:41:22 +08:00
a552d1eb91 usb-dev: limit the size of outgoing packets
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 22:40:52 +08:00
2d7c7794f5 hw: foboot-bitstream: remove debug pins, use epfifo
Remove the debug pins to let timing close.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:06:37 +08:00
0c6e444789 hw: foboot-bitstream: add -relut and friends to nextpnr
Shrink the resulting gate count by adding -relut and adjusting the
number of luts that a CE signal can use.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:51 +08:00
8aed600cd6 hw: foboot-bitstream: specify additional clock domain constraints
Specify all the clock domain constraints for every possible signal, to
work around the fact that nextpnr currently will pick one and ignore the
rest.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:12 +08:00
6638801886 hw: foboot-bitstream: remove clk48_in signal
It's unused.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:04:19 +08:00
8fb6b5977b hw: foboot-bitstream: remove unused clk48 net
We only use the raw and usb48 nets.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 20:53:58 +08:00
69f7b5d836 csr: replace with latest generated version
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 20:53:30 +08:00
c98017cbc9 client: working on the client
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 15:25:33 +08:00
13360015db Merge branch 'master' of github.com:xobs/foboot 2019-03-08 20:49:13 +08:00
d603113b6f foboot-bitstream: send clk48 through shifter, then through pll
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-08 20:47:42 +08:00
44ee19c8b4 valentyusb: use latest fix for metastable transmissions
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-06 14:06:17 +08:00
f34601df98 hw: lxbuildenv: fix uninitialized repo issue
We would get stuck in a loop.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 22:08:11 +08:00
3df59a866d metastable fix: wip
Trying to figure out what's causing this problem.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 20:28:54 +08:00
c0842737bf sw: usb-unififo: add code to test usb RX
This just reads SOF packets and validates they're correct.  This ensures
that bitstuffing is good.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 15:50:36 +08:00
ce071dac67 sw: main: remove usb_sync() call
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 15:50:08 +08:00
7f30d7f79b sw: Makefile: hardcode project name to "foboot"
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 15:49:21 +08:00
380a4f1fa2 sw: unififo: print out SOF frames, to ensure link integrity
Print out the SOF frames so that we can make sure the Rx path is good.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 14:52:42 +08:00
73176b65de hw: lxbuildenv: fix detection of .git directory
It was giving an incorrect path, which would cause it to refresh
submodules during every build.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 13:20:54 +08:00
c78e9ab214 sw: add missing include files
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 12:02:02 +08:00
ffd0285613 main: more work on fixing stuff
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 11:54:48 +08:00
1c38c58a6f Merge branch 'master' of git.xobs.io:xobs/foboot 2019-03-05 09:18:20 +08:00
350497924e README: add simple readme file
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:17:20 +08:00
74ec6be245 hw: remove gitignore
It's stored in the root now

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:16:52 +08:00
1c8634e954 gitmodules: add hw deps
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:16:36 +08:00
8fe27d9371 Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'
git-subtree-dir: hw
git-subtree-mainline: e4af98b4aa
git-subtree-split: d812378c4d
2019-03-05 09:05:50 +08:00
e4af98b4aa generated: update generated csr, mem, and ld files
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:05:29 +08:00
d812378c4d deps: update valentyusb
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 08:56:30 +08:00
84d4b40897 foboot: move software stuff to sw directory
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 08:54:51 +08:00
b06cd3b807 usb-epfifo: something is actually responding now
Making good progress. Still not reliable, but there's something to work on now.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-04 15:46:59 +08:00
d18e0cba0d include: regenerate included headers
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-04 15:46:47 +08:00
a897c7f2fa foboot-bitstream: remove cas module from imports
It's unused in the current implementation.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:52:06 +08:00
6a147c4333 valentyusb: pull latest version
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:51:35 +08:00
2ac79e45e9 Makefile: don't re-set GIT_VERSION
Use := to only set GIT_VERSION once.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:49:02 +08:00
1048cbf999 third_party: minor formatting cleanups
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:48:47 +08:00
fae65117cd usb: work-in-progress for USB development
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:48:25 +08:00
1cb67f8f8d crc5-test: add simple program to generate SOF frames
This can be used to tell if we're properly decoding packets.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:45:37 +08:00
cad2ae01d7 foboot-bitstream: use crystal for 12 MHz clock
This fixes heterodyning that was occurring in the USB block, as it
transitioned from the 48 MHz down to the 12 MHz domain.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-27 14:20:04 +08:00
dd7839cc68 deps: migen: fix upstream ref
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:36:21 +08:00
05480670c5 migen: update submodule
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:32:48 +08:00
6ca4b6a398 deps: valentyusb: update submodule
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:32:28 +08:00
5fbd0fc667 lxbuildenv: riscv: also allow riscv32 toolchain
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:25:16 +08:00
d42418d62a foboot-bitstream: mark executable
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:22:05 +08:00
7caff80f6b foboot-bitstream: change line endings
These matter on non-Windows machines.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:21:23 +08:00
6771d28fb4 foboot-bitstream: work-in-progress commit
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:19:17 +08:00
8b54d5addb csr-test: add simple program to test CSRs
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:19:01 +08:00