Sean Cross 6ca4b6a398 deps: valentyusb: update submodule ...

Signed-off-by: Sean Cross <sean@xobs.io>

2019-02-25 16:32:28 +08:00

bin

initial commit

2019-02-18 10:48:43 +08:00

deps

deps: valentyusb: update submodule

2019-02-25 16:32:28 +08:00

.gitignore

gitignore: ignore env, build, pycache

2019-02-18 12:44:19 +08:00

.gitmodules

deps: add valentyusb

2019-02-18 12:43:09 +08:00

csr-test.py

csr-test: add simple program to test CSRs

2019-02-25 16:19:01 +08:00

foboot-bitstream.py

foboot-bitstream: mark executable

2019-02-25 16:22:05 +08:00

lxbuildenv.py

lxbuildenv: riscv: also allow riscv32 toolchain

2019-02-25 16:25:16 +08:00

Description

No description provided

2.4 MiB

Languages

Verilog 79.3%

C 15.5%

Python 4.7%

Makefile 0.4%