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Sean Cross 8fe27d9371 Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458' 
git-subtree-dir: hw
git-subtree-mainline: e4af98b4aae1ae8481adff1c6af32251ff64b7a8
git-subtree-split: d812378c4d61f7c957ac4bcba15a8344fb7fb458
2019-03-05 09:05:50 +08:00
hw
Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'
2019-03-05 09:05:50 +08:00
sw
generated: update generated csr, mem, and ld files
2019-03-05 09:05:29 +08:00
.gitignore
initial "working" version
2019-01-01 22:10:02 +08:00
LICENSE
initial commit
2019-01-01 10:24:08 +08:00
README.md
initial commit
2019-01-01 10:24:08 +08:00

README.md

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Description
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Readme 2.4 MiB
Languages
Verilog 79.3%
C 15.5%
Python 4.7%
Makefile 0.4%