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hw: foboot-bitstream: specify additional clock domain constraints

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Specify all the clock domain constraints for every possible signal, to
work around the fact that nextpnr currently will pick one and ignore the
rest.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-03-10 21:05:12 +08:00
parent 6638801886
commit 8aed600cd6
1 changed files with 1 additions and 0 deletions
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hw/foboot-bitstream.py
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@ -132,6 +132,7 @@ class _CRG(Module):
i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
o_GLOBAL_BUFFER_OUTPUT=clk12,
)
platform.add_period_constraint(clk12_raw, 1e9/12e6)
self.specials += Instance(
"SB_PLL40_CORE",