Sean Cross 6a147c4333 valentyusb: pull latest version ...

Signed-off-by: Sean Cross <sean@xobs.io>

2019-02-28 10:51:35 +08:00

bin

initial commit

2019-02-18 10:48:43 +08:00

deps

valentyusb: pull latest version

2019-02-28 10:51:35 +08:00

.gitignore

gitignore: ignore env, build, pycache

2019-02-18 12:44:19 +08:00

.gitmodules

deps: add valentyusb

2019-02-18 12:43:09 +08:00

crc5-test.c

crc5-test: add simple program to generate SOF frames

2019-02-28 10:45:37 +08:00

csr-test.py

csr-test: add simple program to test CSRs

2019-02-25 16:19:01 +08:00

foboot-bitstream.py

foboot-bitstream: use crystal for 12 MHz clock

2019-02-27 14:20:04 +08:00

lxbuildenv.py

lxbuildenv: riscv: also allow riscv32 toolchain

2019-02-25 16:25:16 +08:00

Description

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2.4 MiB

Languages

Verilog 79.3%

C 15.5%

Python 4.7%

Makefile 0.4%