2d7c7794f5
hw: foboot-bitstream: remove debug pins, use epfifo
...
Remove the debug pins to let timing close.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:06:37 +08:00
0c6e444789
hw: foboot-bitstream: add -relut and friends to nextpnr
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Shrink the resulting gate count by adding -relut and adjusting the
number of luts that a CE signal can use.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:51 +08:00
8aed600cd6
hw: foboot-bitstream: specify additional clock domain constraints
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Specify all the clock domain constraints for every possible signal, to
work around the fact that nextpnr currently will pick one and ignore the
rest.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:12 +08:00
6638801886
hw: foboot-bitstream: remove clk48_in signal
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It's unused.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:04:19 +08:00
8fb6b5977b
hw: foboot-bitstream: remove unused clk48 net
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We only use the raw and usb48 nets.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 20:53:58 +08:00
69f7b5d836
csr: replace with latest generated version
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 20:53:30 +08:00
c98017cbc9
client: working on the client
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 15:25:33 +08:00
13360015db
Merge branch 'master' of github.com:xobs/foboot
2019-03-08 20:49:13 +08:00
d603113b6f
foboot-bitstream: send clk48 through shifter, then through pll
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-08 20:47:42 +08:00
44ee19c8b4
valentyusb: use latest fix for metastable transmissions
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-06 14:06:17 +08:00
f34601df98
hw: lxbuildenv: fix uninitialized repo issue
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We would get stuck in a loop.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 22:08:11 +08:00
3df59a866d
metastable fix: wip
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Trying to figure out what's causing this problem.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 20:28:54 +08:00
c0842737bf
sw: usb-unififo: add code to test usb RX
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This just reads SOF packets and validates they're correct. This ensures
that bitstuffing is good.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 15:50:36 +08:00
ce071dac67
sw: main: remove usb_sync() call
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 15:50:08 +08:00
7f30d7f79b
sw: Makefile: hardcode project name to "foboot"
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 15:49:21 +08:00
380a4f1fa2
sw: unififo: print out SOF frames, to ensure link integrity
...
Print out the SOF frames so that we can make sure the Rx path is good.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 14:52:42 +08:00
73176b65de
hw: lxbuildenv: fix detection of .git directory
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It was giving an incorrect path, which would cause it to refresh
submodules during every build.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 13:20:54 +08:00
c78e9ab214
sw: add missing include files
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 12:02:02 +08:00
ffd0285613
main: more work on fixing stuff
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 11:54:48 +08:00
1c38c58a6f
Merge branch 'master' of git.xobs.io:xobs/foboot
2019-03-05 09:18:20 +08:00
350497924e
README: add simple readme file
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:17:20 +08:00
74ec6be245
hw: remove gitignore
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It's stored in the root now
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:16:52 +08:00
1c8634e954
gitmodules: add hw deps
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:16:36 +08:00
8fe27d9371
Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'
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git-subtree-dir: hw
git-subtree-mainline: e4af98b4aa
git-subtree-split: d812378c4d
2019-03-05 09:05:50 +08:00
e4af98b4aa
generated: update generated csr, mem, and ld files
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:05:29 +08:00
d812378c4d
deps: update valentyusb
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 08:56:30 +08:00
84d4b40897
foboot: move software stuff to sw directory
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 08:54:51 +08:00
b06cd3b807
usb-epfifo: something is actually responding now
...
Making good progress. Still not reliable, but there's something to work on now.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-04 15:46:59 +08:00
d18e0cba0d
include: regenerate included headers
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-04 15:46:47 +08:00
a897c7f2fa
foboot-bitstream: remove cas
module from imports
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It's unused in the current implementation.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:52:06 +08:00
6a147c4333
valentyusb: pull latest version
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:51:35 +08:00
2ac79e45e9
Makefile: don't re-set GIT_VERSION
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Use := to only set GIT_VERSION once.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:49:02 +08:00
1048cbf999
third_party: minor formatting cleanups
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:48:47 +08:00
fae65117cd
usb: work-in-progress for USB development
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:48:25 +08:00
1cb67f8f8d
crc5-test: add simple program to generate SOF frames
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This can be used to tell if we're properly decoding packets.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-28 10:45:37 +08:00
cad2ae01d7
foboot-bitstream: use crystal for 12 MHz clock
...
This fixes heterodyning that was occurring in the USB block, as it
transitioned from the 48 MHz down to the 12 MHz domain.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-27 14:20:04 +08:00
dd7839cc68
deps: migen: fix upstream ref
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:36:21 +08:00
05480670c5
migen: update submodule
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:32:48 +08:00
6ca4b6a398
deps: valentyusb: update submodule
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:32:28 +08:00
5fbd0fc667
lxbuildenv: riscv: also allow riscv32 toolchain
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:25:16 +08:00
d42418d62a
foboot-bitstream: mark executable
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:22:05 +08:00
7caff80f6b
foboot-bitstream: change line endings
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These matter on non-Windows machines.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:21:23 +08:00
6771d28fb4
foboot-bitstream: work-in-progress commit
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:19:17 +08:00
8b54d5addb
csr-test: add simple program to test CSRs
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 16:19:01 +08:00
44880465e6
Merge branch 'master' of git.xobs.io:xobs/foboot-bitstream
2019-02-25 15:16:57 +08:00
49b22a1962
foboot-bitstream: use new-style random rom
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Use a new pattern with a new function to generate the random ROM, used
for ROM patching.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-25 15:16:19 +08:00
e66f909bfd
lxbuildenv: add '-r' command to run modules under lxbuildenv
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This will allow us to e.g. run tests.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-18 13:54:26 +08:00
30d5a097d2
gitignore: ignore env, build, pycache
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-18 12:44:19 +08:00
21cdcaaee8
foboot-bitstream: first full build
...
This actually compiles now, hooray! But does it work? No.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-18 12:43:29 +08:00
ee006eff90
deps: add valentyusb
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-02-18 12:43:09 +08:00