This has more copper, which might make hand-soldering easier. Though
this PCB isn't going to be hand-soldered.
Signed-off-by: Sean Cross <sean@xobs.io>
FPGAs are great, because if there's an alternate method that's easier to
route -- go for it! This modifies some of the connections to ease
routing constraints.
Signed-off-by: Sean Cross <sean@xobs.io>
This is the first cut of a schematic layout of DVT1.
It includes all the decoupling caps still. We'll need to see if they're
kept around.
Signed-off-by: Sean Cross <sean@xobs.io>
This removes much of the support debugging stuff from evt1. Still to
do:
- Assign footprints
- Figure out which PU resistor to include (if any)
- Figure out if we need to keep the USB buffering
- Remove extra decoupling caps
Signed-off-by: Sean Cross <sean@xobs.io>
Add a footprint from KiCad for the power regulator we'll use.
It refers to a 3D file that doesn't exist, so we'll need to find that
first.
Signed-off-by: Sean Cross <sean@xobs.io>
evt1 and evt2 were never produced. They also would never have worked,
because the USB connector was drawn mirrored.
Remove these and replace them with a single `evt1` that was actually
produced.
This reflects the fact that the `evt1` boards actually say "EVT1" on
them.
Signed-off-by: Sean Cross <sean@xobs.io>
Move some vias around to get the 5V plane more breathing room. Add a
small pour to give more copper and stabilize the net.
Signed-off-by: Sean Cross <sean@xobs.io>
Add more 5V vias near the 1.2V regulator, and replace a manual trace
with a copper pour. This will increase the amount of copper going to
both the 3.3V and 1.2V regulators, which should improve stability.
While we're at it, remove an errant silk artifact on the USB connector.
Signed-off-by: Sean Cross <sean@xobs.io>
Add a note indicating the PCB thickness and color.
Also, move the drill origin to the lower-left corner, to aid in machine
assembly.
Signed-off-by: Sean Cross <sean@xobs.io>
Add more silk, indicating website and other info.
While we're at it, move some traces around to give more copper area, and
drop some more vias to improve ground performance.
Signed-off-by: Sean Cross <sean@xobs.io>
The Kicad default footprints seem volatile and unreliable. Going
between two machines that both have "Kicad 5.0.0" installed results in
incompatibilities because KiCad has renamed their footprint libraries.
Also, for some reason it's going to Github to get footprints instead of
using local copies.
Copy every model and footprint we use into a local tomu-fpga.pretty.
This lets us ensure we can work offline, and also allows us to modify
footprints, e.g. by adding a "Pin 1" marker.
Signed-off-by: Sean Cross <sean@xobs.io>
It's much cleaner if we put power pins on one side and signal pins on
the other. This removes the ratsnest that was building up.
Signed-off-by: Sean Cross <sean@xobs.io>
Add a crystal, so we can test to make sure it works.
Also add a second regulator dedicated to VCCPLL in an effort to
cost-down the capacitor and large components that shouldn't be
necessary.
Signed-off-by: Sean Cross <sean@xobs.io>
For some reason, this pin was listed as a `power output`, which does not
appear to be the case. Due to this error, the DRC would fail when using
a regulator directly connected to the pin.
Mark this pin as a `power input` to fix this, since it's really where
power goes into the chip.
Signed-off-by: Sean Cross <sean@xobs.io>
