follow #1
seperate files from latest SDK (currently 14.2.0) from good old non- secure bootloader sdk 11
This commit is contained in:
hathach
155
lib/sdk/components/device/compiler_abstraction.h
Normal file
155
lib/sdk/components/device/compiler_abstraction.h
Normal file
@ -0,0 +1,155 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
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#ifndef _COMPILER_ABSTRACTION_H
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#define _COMPILER_ABSTRACTION_H
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/*lint ++flb "Enter library region" */
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#if defined ( __CC_ARM )
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE __inline
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#endif
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#ifndef __WEAK
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#define __WEAK __weak
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||||
#endif
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|
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#ifndef __ALIGN
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||||
#define __ALIGN(n) __align(n)
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||||
#endif
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#ifndef __PACKED
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#define __PACKED __packed
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#endif
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#define GET_SP() __current_sp()
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#elif defined ( __ICCARM__ )
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#ifndef __ASM
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#define __ASM __asm
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#endif
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|
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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|
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#ifndef __WEAK
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#define __WEAK __weak
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#endif
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#ifndef __ALIGN
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#define STRING_PRAGMA(x) _Pragma(#x)
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#define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
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#endif
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|
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#ifndef __PACKED
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#define __PACKED __packed
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#endif
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#define GET_SP() __get_SP()
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|
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#elif defined ( __GNUC__ )
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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|
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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|
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#ifndef __ALIGN
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#define __ALIGN(n) __attribute__((aligned(n)))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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|
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#define GET_SP() gcc_current_sp()
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static inline unsigned int gcc_current_sp(void)
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{
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register unsigned sp __ASM("sp");
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return sp;
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}
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#elif defined ( __TASKING__ )
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#ifndef __ASM
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#define __ASM __asm
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#endif
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||||
|
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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|
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __ALIGN
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#define __ALIGN(n) __align(n)
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#endif
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|
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/* Not defined for TASKING. */
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#ifndef __PACKED
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#define __PACKED
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#endif
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#define GET_SP() __get_MSP()
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#endif
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/*lint --flb "Leave library region" */
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#endif
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102
lib/sdk/components/device/nrf.h
Normal file
102
lib/sdk/components/device/nrf.h
Normal file
@ -0,0 +1,102 @@
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/*
|
||||
|
||||
Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
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#ifndef NRF_H
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#define NRF_H
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/* MDK version */
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#define MDK_MAJOR_VERSION 8
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#define MDK_MINOR_VERSION 15
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#define MDK_MICRO_VERSION 0
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/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
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#if defined (NRF52)
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#ifndef NRF52832_XXAA
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#define NRF52832_XXAA
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#endif
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#endif
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/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */
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#if defined (NRF52810_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52840_XXAA)
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#ifndef NRF52_SERIES
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#define NRF52_SERIES
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#endif
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#endif
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#if defined(_WIN32)
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/* Do not include nrf specific files when building for PC host */
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#elif defined(__unix)
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/* Do not include nrf specific files when building for PC host */
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#elif defined(__APPLE__)
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/* Do not include nrf specific files when building for PC host */
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#else
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/* Device selection for device includes. */
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#if defined (NRF51)
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#include "nrf51.h"
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#include "nrf51_bitfields.h"
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#include "nrf51_deprecated.h"
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#elif defined (NRF52840_XXAA)
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#include "nrf52840.h"
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#include "nrf52840_bitfields.h"
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#include "nrf51_to_nrf52840.h"
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#include "nrf52_to_nrf52840.h"
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#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
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#include "nrf52.h"
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#include "nrf52_bitfields.h"
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#include "nrf51_to_nrf52.h"
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#include "nrf52_name_change.h"
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#elif defined (NRF52810_XXAA)
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#include "nrf52810.h"
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#include "nrf52810_bitfields.h"
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#include "nrf51_to_nrf52810.h"
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#include "nrf52_to_nrf52810.h"
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#else
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#error "Device must be defined. See nrf.h."
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#endif /* NRF51, NRF52832_XXAA, NRF52832_XXAB, NRF52810_XXAA, NRF52840_XXAA */
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#include "compiler_abstraction.h"
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#endif /* _WIN32 || __unix || __APPLE__ */
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#endif /* NRF_H */
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963
lib/sdk/components/device/nrf51_to_nrf52.h
Normal file
963
lib/sdk/components/device/nrf51_to_nrf52.h
Normal file
@ -0,0 +1,963 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
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||||
#ifndef NRF51_TO_NRF52_H
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#define NRF51_TO_NRF52_H
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||||
|
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/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices.
|
||||
* It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
|
||||
* from the nrf51_deprecated.h file. */
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
|
||||
#define UART0_IRQHandler UARTE0_UART0_IRQHandler
|
||||
#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
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#define ADC_IRQHandler SAADC_IRQHandler
|
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#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define SWI0_IRQHandler SWI0_EGU0_IRQHandler
|
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#define SWI1_IRQHandler SWI1_EGU1_IRQHandler
|
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#define SWI2_IRQHandler SWI2_EGU2_IRQHandler
|
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#define SWI3_IRQHandler SWI3_EGU3_IRQHandler
|
||||
#define SWI4_IRQHandler SWI4_EGU4_IRQHandler
|
||||
#define SWI5_IRQHandler SWI5_EGU5_IRQHandler
|
||||
|
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#define UART0_IRQn UARTE0_UART0_IRQn
|
||||
#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
|
||||
#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
|
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#define ADC_IRQn SAADC_IRQn
|
||||
#define LPCOMP_IRQn COMP_LPCOMP_IRQn
|
||||
#define SWI0_IRQn SWI0_EGU0_IRQn
|
||||
#define SWI1_IRQn SWI1_EGU1_IRQn
|
||||
#define SWI2_IRQn SWI2_EGU2_IRQn
|
||||
#define SWI3_IRQn SWI3_EGU3_IRQn
|
||||
#define SWI4_IRQn SWI4_EGU4_IRQn
|
||||
#define SWI5_IRQn SWI5_EGU5_IRQn
|
||||
|
||||
|
||||
/* UICR */
|
||||
/* Register RBPCONF was renamed to APPROTECT. */
|
||||
#define RBPCONF APPROTECT
|
||||
|
||||
#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos
|
||||
#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk
|
||||
#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled
|
||||
#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled
|
||||
|
||||
|
||||
/* GPIO */
|
||||
/* GPIO port was renamed to P0. */
|
||||
#define NRF_GPIO NRF_P0
|
||||
#define NRF_GPIO_BASE NRF_P0_BASE
|
||||
|
||||
|
||||
/* QDEC */
|
||||
/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
|
||||
#define PSELLED PSEL.LED
|
||||
#define PSELA PSEL.A
|
||||
#define PSELB PSEL.B
|
||||
|
||||
|
||||
/* SPIS */
|
||||
/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
|
||||
#define PSELSCK PSEL.SCK
|
||||
#define PSELMISO PSEL.MISO
|
||||
#define PSELMOSI PSEL.MOSI
|
||||
#define PSELCSN PSEL.CSN
|
||||
|
||||
/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
|
||||
#define RXDPTR RXD.PTR
|
||||
#define MAXRX RXD.MAXCNT
|
||||
#define AMOUNTRX RXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
|
||||
#define TXDPTR TXD.PTR
|
||||
#define MAXTX TXD.MAXCNT
|
||||
#define AMOUNTTX TXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
|
||||
/* MPU */
|
||||
/* Part of MPU module was renamed BPROT, while the rest was eliminated. */
|
||||
#define NRF_MPU NRF_BPROT
|
||||
|
||||
/* Register DISABLEINDEBUG macros were affected. */
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled
|
||||
|
||||
/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */
|
||||
#define PROTENSET0 CONFIG0
|
||||
#define PROTENSET1 CONFIG1
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos
|
||||
#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk
|
||||
#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos
|
||||
#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk
|
||||
#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos
|
||||
#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk
|
||||
#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos
|
||||
#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk
|
||||
#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos
|
||||
#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk
|
||||
#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos
|
||||
#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk
|
||||
#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos
|
||||
#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk
|
||||
#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos
|
||||
#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk
|
||||
#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos
|
||||
#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk
|
||||
#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos
|
||||
#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk
|
||||
#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos
|
||||
#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk
|
||||
#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos
|
||||
#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk
|
||||
#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos
|
||||
#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk
|
||||
#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos
|
||||
#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk
|
||||
#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos
|
||||
#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk
|
||||
#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos
|
||||
#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk
|
||||
#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos
|
||||
#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk
|
||||
#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos
|
||||
#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk
|
||||
#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos
|
||||
#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk
|
||||
#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos
|
||||
#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk
|
||||
#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos
|
||||
#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk
|
||||
#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos
|
||||
#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk
|
||||
#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos
|
||||
#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk
|
||||
#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos
|
||||
#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk
|
||||
#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos
|
||||
#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk
|
||||
#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos
|
||||
#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk
|
||||
#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos
|
||||
#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk
|
||||
#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos
|
||||
#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk
|
||||
#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos
|
||||
#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk
|
||||
#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos
|
||||
#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk
|
||||
#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos
|
||||
#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk
|
||||
#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos
|
||||
#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk
|
||||
#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos
|
||||
#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk
|
||||
#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos
|
||||
#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk
|
||||
#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos
|
||||
#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk
|
||||
#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos
|
||||
#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk
|
||||
#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos
|
||||
#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk
|
||||
#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos
|
||||
#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk
|
||||
#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos
|
||||
#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk
|
||||
#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos
|
||||
#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk
|
||||
#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos
|
||||
#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk
|
||||
#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos
|
||||
#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk
|
||||
#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos
|
||||
#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk
|
||||
#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos
|
||||
#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk
|
||||
#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos
|
||||
#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk
|
||||
#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos
|
||||
#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk
|
||||
#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos
|
||||
#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk
|
||||
#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos
|
||||
#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk
|
||||
#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos
|
||||
#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk
|
||||
#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos
|
||||
#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk
|
||||
#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos
|
||||
#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk
|
||||
#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos
|
||||
#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk
|
||||
#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos
|
||||
#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk
|
||||
#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos
|
||||
#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk
|
||||
#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos
|
||||
#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk
|
||||
#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos
|
||||
#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk
|
||||
#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos
|
||||
#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk
|
||||
#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos
|
||||
#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk
|
||||
#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos
|
||||
#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk
|
||||
#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos
|
||||
#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk
|
||||
#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos
|
||||
#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk
|
||||
#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos
|
||||
#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk
|
||||
#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos
|
||||
#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk
|
||||
#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos
|
||||
#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk
|
||||
#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled
|
||||
|
||||
|
||||
/* From nrf51_deprecated.h */
|
||||
|
||||
/* NVMC */
|
||||
/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
|
||||
#define ERASEPROTECTEDPAGE ERASEPCR0
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* COMP module was eliminated. Adapted to nrf52 headers. */
|
||||
#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn
|
||||
|
||||
|
||||
/* REFSEL register redefined enumerated values and added some more. */
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
|
||||
|
||||
|
||||
/* RADIO */
|
||||
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
|
||||
|
||||
|
||||
/* FICR */
|
||||
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
|
||||
#define DEVICEID0 DEVICEID[0]
|
||||
#define DEVICEID1 DEVICEID[1]
|
||||
|
||||
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
|
||||
#define ER0 ER[0]
|
||||
#define ER1 ER[1]
|
||||
#define ER2 ER[2]
|
||||
#define ER3 ER[3]
|
||||
|
||||
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
|
||||
#define IR0 IR[0]
|
||||
#define IR1 IR[1]
|
||||
#define IR2 IR[2]
|
||||
#define IR3 IR[3]
|
||||
|
||||
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
|
||||
#define DEVICEADDR0 DEVICEADDR[0]
|
||||
#define DEVICEADDR1 DEVICEADDR[1]
|
||||
|
||||
|
||||
/* PPI */
|
||||
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
|
||||
#define TASKS_CHG0EN TASKS_CHG[0].EN
|
||||
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
|
||||
#define TASKS_CHG1EN TASKS_CHG[1].EN
|
||||
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
|
||||
#define TASKS_CHG2EN TASKS_CHG[2].EN
|
||||
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
|
||||
#define TASKS_CHG3EN TASKS_CHG[3].EN
|
||||
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
|
||||
|
||||
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
|
||||
#define CH0_EEP CH[0].EEP
|
||||
#define CH0_TEP CH[0].TEP
|
||||
#define CH1_EEP CH[1].EEP
|
||||
#define CH1_TEP CH[1].TEP
|
||||
#define CH2_EEP CH[2].EEP
|
||||
#define CH2_TEP CH[2].TEP
|
||||
#define CH3_EEP CH[3].EEP
|
||||
#define CH3_TEP CH[3].TEP
|
||||
#define CH4_EEP CH[4].EEP
|
||||
#define CH4_TEP CH[4].TEP
|
||||
#define CH5_EEP CH[5].EEP
|
||||
#define CH5_TEP CH[5].TEP
|
||||
#define CH6_EEP CH[6].EEP
|
||||
#define CH6_TEP CH[6].TEP
|
||||
#define CH7_EEP CH[7].EEP
|
||||
#define CH7_TEP CH[7].TEP
|
||||
#define CH8_EEP CH[8].EEP
|
||||
#define CH8_TEP CH[8].TEP
|
||||
#define CH9_EEP CH[9].EEP
|
||||
#define CH9_TEP CH[9].TEP
|
||||
#define CH10_EEP CH[10].EEP
|
||||
#define CH10_TEP CH[10].TEP
|
||||
#define CH11_EEP CH[11].EEP
|
||||
#define CH11_TEP CH[11].TEP
|
||||
#define CH12_EEP CH[12].EEP
|
||||
#define CH12_TEP CH[12].TEP
|
||||
#define CH13_EEP CH[13].EEP
|
||||
#define CH13_TEP CH[13].TEP
|
||||
#define CH14_EEP CH[14].EEP
|
||||
#define CH14_TEP CH[14].TEP
|
||||
#define CH15_EEP CH[15].EEP
|
||||
#define CH15_TEP CH[15].TEP
|
||||
|
||||
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
|
||||
#define CHG0 CHG[0]
|
||||
#define CHG1 CHG[1]
|
||||
#define CHG2 CHG[2]
|
||||
#define CHG3 CHG[3]
|
||||
|
||||
/* All bitfield macros for the CHGx registers therefore changed name. */
|
||||
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_TO_NRF52_H */
|
||||
|
||||
578
lib/sdk/components/device/nrf51_to_nrf52840.h
Normal file
578
lib/sdk/components/device/nrf51_to_nrf52840.h
Normal file
@ -0,0 +1,578 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef NRF51_TO_NRF52840_H
|
||||
#define NRF51_TO_NRF52840_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices.
|
||||
* It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
|
||||
* from the nrf51_deprecated.h file. */
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
|
||||
#define UART0_IRQHandler UARTE0_UART0_IRQHandler
|
||||
#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
#define ADC_IRQHandler SAADC_IRQHandler
|
||||
#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define SWI0_IRQHandler SWI0_EGU0_IRQHandler
|
||||
#define SWI1_IRQHandler SWI1_EGU1_IRQHandler
|
||||
#define SWI2_IRQHandler SWI2_EGU2_IRQHandler
|
||||
#define SWI3_IRQHandler SWI3_EGU3_IRQHandler
|
||||
#define SWI4_IRQHandler SWI4_EGU4_IRQHandler
|
||||
#define SWI5_IRQHandler SWI5_EGU5_IRQHandler
|
||||
|
||||
#define UART0_IRQn UARTE0_UART0_IRQn
|
||||
#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
|
||||
#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
|
||||
#define ADC_IRQn SAADC_IRQn
|
||||
#define LPCOMP_IRQn COMP_LPCOMP_IRQn
|
||||
#define SWI0_IRQn SWI0_EGU0_IRQn
|
||||
#define SWI1_IRQn SWI1_EGU1_IRQn
|
||||
#define SWI2_IRQn SWI2_EGU2_IRQn
|
||||
#define SWI3_IRQn SWI3_EGU3_IRQn
|
||||
#define SWI4_IRQn SWI4_EGU4_IRQn
|
||||
#define SWI5_IRQn SWI5_EGU5_IRQn
|
||||
|
||||
|
||||
/* UICR */
|
||||
/* Register RBPCONF was renamed to APPROTECT. */
|
||||
#define RBPCONF APPROTECT
|
||||
|
||||
#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos
|
||||
#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk
|
||||
#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled
|
||||
#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled
|
||||
|
||||
|
||||
/* GPIO */
|
||||
/* GPIO port was renamed to P0. */
|
||||
#define NRF_GPIO NRF_P0
|
||||
#define NRF_GPIO_BASE NRF_P0_BASE
|
||||
|
||||
|
||||
/* QDEC */
|
||||
/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
|
||||
#define PSELLED PSEL.LED
|
||||
#define PSELA PSEL.A
|
||||
#define PSELB PSEL.B
|
||||
|
||||
|
||||
/* SPIS */
|
||||
/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
|
||||
#define PSELSCK PSEL.SCK
|
||||
#define PSELMISO PSEL.MISO
|
||||
#define PSELMOSI PSEL.MOSI
|
||||
#define PSELCSN PSEL.CSN
|
||||
|
||||
/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
|
||||
#define RXDPTR RXD.PTR
|
||||
#define MAXRX RXD.MAXCNT
|
||||
#define AMOUNTRX RXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
|
||||
#define TXDPTR TXD.PTR
|
||||
#define MAXTX TXD.MAXCNT
|
||||
#define AMOUNTTX TXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
|
||||
/* UART */
|
||||
/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
|
||||
#define PSELRTS PSEL.RTS
|
||||
#define PSELTXD PSEL.TXD
|
||||
#define PSELCTS PSEL.CTS
|
||||
#define PSELRXD PSEL.RXD
|
||||
|
||||
/* TWI */
|
||||
/* The registers PSELSCL, PSELSDA were restructured into a struct. */
|
||||
#define PSELSCL PSEL.SCL
|
||||
#define PSELSDA PSEL.SDA
|
||||
|
||||
|
||||
|
||||
/* From nrf51_deprecated.h */
|
||||
|
||||
/* NVMC */
|
||||
/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
|
||||
#define ERASEPROTECTEDPAGE ERASEPCR0
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* COMP module was eliminated. Adapted to nrf52840 headers. */
|
||||
#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn
|
||||
|
||||
|
||||
/* REFSEL register redefined enumerated values and added some more. */
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
|
||||
|
||||
|
||||
/* RADIO */
|
||||
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
|
||||
|
||||
|
||||
/* FICR */
|
||||
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
|
||||
#define DEVICEID0 DEVICEID[0]
|
||||
#define DEVICEID1 DEVICEID[1]
|
||||
|
||||
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
|
||||
#define ER0 ER[0]
|
||||
#define ER1 ER[1]
|
||||
#define ER2 ER[2]
|
||||
#define ER3 ER[3]
|
||||
|
||||
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
|
||||
#define IR0 IR[0]
|
||||
#define IR1 IR[1]
|
||||
#define IR2 IR[2]
|
||||
#define IR3 IR[3]
|
||||
|
||||
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
|
||||
#define DEVICEADDR0 DEVICEADDR[0]
|
||||
#define DEVICEADDR1 DEVICEADDR[1]
|
||||
|
||||
|
||||
/* PPI */
|
||||
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
|
||||
#define TASKS_CHG0EN TASKS_CHG[0].EN
|
||||
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
|
||||
#define TASKS_CHG1EN TASKS_CHG[1].EN
|
||||
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
|
||||
#define TASKS_CHG2EN TASKS_CHG[2].EN
|
||||
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
|
||||
#define TASKS_CHG3EN TASKS_CHG[3].EN
|
||||
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
|
||||
|
||||
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
|
||||
#define CH0_EEP CH[0].EEP
|
||||
#define CH0_TEP CH[0].TEP
|
||||
#define CH1_EEP CH[1].EEP
|
||||
#define CH1_TEP CH[1].TEP
|
||||
#define CH2_EEP CH[2].EEP
|
||||
#define CH2_TEP CH[2].TEP
|
||||
#define CH3_EEP CH[3].EEP
|
||||
#define CH3_TEP CH[3].TEP
|
||||
#define CH4_EEP CH[4].EEP
|
||||
#define CH4_TEP CH[4].TEP
|
||||
#define CH5_EEP CH[5].EEP
|
||||
#define CH5_TEP CH[5].TEP
|
||||
#define CH6_EEP CH[6].EEP
|
||||
#define CH6_TEP CH[6].TEP
|
||||
#define CH7_EEP CH[7].EEP
|
||||
#define CH7_TEP CH[7].TEP
|
||||
#define CH8_EEP CH[8].EEP
|
||||
#define CH8_TEP CH[8].TEP
|
||||
#define CH9_EEP CH[9].EEP
|
||||
#define CH9_TEP CH[9].TEP
|
||||
#define CH10_EEP CH[10].EEP
|
||||
#define CH10_TEP CH[10].TEP
|
||||
#define CH11_EEP CH[11].EEP
|
||||
#define CH11_TEP CH[11].TEP
|
||||
#define CH12_EEP CH[12].EEP
|
||||
#define CH12_TEP CH[12].TEP
|
||||
#define CH13_EEP CH[13].EEP
|
||||
#define CH13_TEP CH[13].TEP
|
||||
#define CH14_EEP CH[14].EEP
|
||||
#define CH14_TEP CH[14].TEP
|
||||
#define CH15_EEP CH[15].EEP
|
||||
#define CH15_TEP CH[15].TEP
|
||||
|
||||
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
|
||||
#define CHG0 CHG[0]
|
||||
#define CHG1 CHG[1]
|
||||
#define CHG2 CHG[2]
|
||||
#define CHG3 CHG[3]
|
||||
|
||||
/* All bitfield macros for the CHGx registers therefore changed name. */
|
||||
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_TO_NRF52840_H */
|
||||
|
||||
2100
lib/sdk/components/device/nrf52.h
Normal file
2100
lib/sdk/components/device/nrf52.h
Normal file
File diff suppressed because it is too large
Load Diff
275
lib/sdk/components/device/nrf52832_peripherals.h
Normal file
275
lib/sdk/components/device/nrf52832_peripherals.h
Normal file
@ -0,0 +1,275 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF52832_PERIPHERALS_H
|
||||
#define _NRF52832_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 8
|
||||
|
||||
/* Floating Point Unit */
|
||||
#define FPU_PRESENT
|
||||
#define FPU_COUNT 1
|
||||
|
||||
/* Systick timer */
|
||||
#define SYSTICK_PRESENT
|
||||
#define SYSTICK_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* Memory Watch Unit */
|
||||
#define MWU_PRESENT
|
||||
#define MWU_COUNT 1
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 128
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 16
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* NFC Tag */
|
||||
#define NFCT_PRESENT
|
||||
#define NFCT_COUNT 1
|
||||
|
||||
#define NFCT_EASYDMA_MAXCNT_SIZE 9
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 20
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 6
|
||||
#define PPI_FEATURE_FORKS_PRESENT
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
#define EGU_COUNT 6
|
||||
|
||||
#define EGU0_CH_NUM 16
|
||||
#define EGU1_CH_NUM 16
|
||||
#define EGU2_CH_NUM 16
|
||||
#define EGU3_CH_NUM 16
|
||||
#define EGU4_CH_NUM 16
|
||||
#define EGU5_CH_NUM 16
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 5
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 32
|
||||
#define TIMER2_MAX_SIZE 32
|
||||
#define TIMER3_MAX_SIZE 32
|
||||
#define TIMER4_MAX_SIZE 32
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
#define TIMER3_CC_NUM 6
|
||||
#define TIMER4_CC_NUM 6
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 3
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
#define RTC2_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 3
|
||||
|
||||
/* Serial Peripheral Interface Master with DMA */
|
||||
#define SPIM_PRESENT
|
||||
#define SPIM_COUNT 3
|
||||
|
||||
#define SPIM0_MAX_DATARATE 8
|
||||
#define SPIM1_MAX_DATARATE 8
|
||||
#define SPIM2_MAX_DATARATE 8
|
||||
|
||||
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
|
||||
#define SPIM0_EASYDMA_MAXCNT_SIZE 8
|
||||
#define SPIM1_EASYDMA_MAXCNT_SIZE 8
|
||||
#define SPIM2_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA*/
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 3
|
||||
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE 8
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
#define SPIS2_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Two Wire Interface Master with DMA */
|
||||
#define TWIM_PRESENT
|
||||
#define TWIM_COUNT 2
|
||||
|
||||
#define TWIM0_EASYDMA_MAXCNT_SIZE 8
|
||||
#define TWIM1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Slave with DMA */
|
||||
#define TWIS_PRESENT
|
||||
#define TWIS_COUNT 2
|
||||
|
||||
#define TWIS0_EASYDMA_MAXCNT_SIZE 8
|
||||
#define TWIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||
#define UARTE_PRESENT
|
||||
#define UARTE_COUNT 1
|
||||
|
||||
#define UARTE0_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Successive Approximation Analog to Digital Converter */
|
||||
#define SAADC_PRESENT
|
||||
#define SAADC_COUNT 1
|
||||
|
||||
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 8
|
||||
|
||||
#define GPIOTE_FEATURE_SET_PRESENT
|
||||
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 16
|
||||
|
||||
#define LPCOMP_FEATURE_HYST_PRESENT
|
||||
|
||||
/* Comparator */
|
||||
#define COMP_PRESENT
|
||||
#define COMP_COUNT 1
|
||||
|
||||
/* Pulse Width Modulator */
|
||||
#define PWM_PRESENT
|
||||
#define PWM_COUNT 3
|
||||
|
||||
#define PWM0_CH_NUM 4
|
||||
#define PWM1_CH_NUM 4
|
||||
#define PWM2_CH_NUM 4
|
||||
|
||||
#define PWM0_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM1_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM2_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Pulse Density Modulator */
|
||||
#define PDM_PRESENT
|
||||
#define PDM_COUNT 1
|
||||
|
||||
#define PDM_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Inter-IC Sound Interface */
|
||||
#define I2S_PRESENT
|
||||
#define I2S_COUNT 1
|
||||
|
||||
#define I2S_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
|
||||
#endif // _NRF52832_PERIPHERALS_H
|
||||
2442
lib/sdk/components/device/nrf52840.h
Normal file
2442
lib/sdk/components/device/nrf52840.h
Normal file
File diff suppressed because it is too large
Load Diff
14790
lib/sdk/components/device/nrf52840_bitfields.h
Normal file
14790
lib/sdk/components/device/nrf52840_bitfields.h
Normal file
File diff suppressed because it is too large
Load Diff
298
lib/sdk/components/device/nrf52840_peripherals.h
Normal file
298
lib/sdk/components/device/nrf52840_peripherals.h
Normal file
@ -0,0 +1,298 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF52840_PERIPHERALS_H
|
||||
#define _NRF52840_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 9
|
||||
|
||||
#define POWER_FEATURE_VDDH_PRESENT
|
||||
|
||||
/* Floating Point Unit */
|
||||
#define FPU_PRESENT
|
||||
#define FPU_COUNT 1
|
||||
|
||||
/* Systick timer */
|
||||
#define SYSTICK_PRESENT
|
||||
#define SYSTICK_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* Memory Watch Unit */
|
||||
#define MWU_PRESENT
|
||||
#define MWU_COUNT 1
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 2
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
#define P1_PIN_NUM 16
|
||||
|
||||
/* ACL */
|
||||
#define ACL_PRESENT
|
||||
|
||||
#define ACL_REGIONS_COUNT 8
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 16
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* NFC Tag */
|
||||
#define NFCT_PRESENT
|
||||
#define NFCT_COUNT 1
|
||||
|
||||
#define NFCT_EASYDMA_MAXCNT_SIZE 9
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 20
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 6
|
||||
#define PPI_FEATURE_FORKS_PRESENT
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
#define EGU_COUNT 6
|
||||
|
||||
#define EGU0_CH_NUM 16
|
||||
#define EGU1_CH_NUM 16
|
||||
#define EGU2_CH_NUM 16
|
||||
#define EGU3_CH_NUM 16
|
||||
#define EGU4_CH_NUM 16
|
||||
#define EGU5_CH_NUM 16
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 5
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 32
|
||||
#define TIMER2_MAX_SIZE 32
|
||||
#define TIMER3_MAX_SIZE 32
|
||||
#define TIMER4_MAX_SIZE 32
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
#define TIMER3_CC_NUM 6
|
||||
#define TIMER4_CC_NUM 6
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 3
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
#define RTC2_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 3
|
||||
|
||||
/* Serial Peripheral Interface Master with DMA */
|
||||
#define SPIM_PRESENT
|
||||
#define SPIM_COUNT 4
|
||||
|
||||
#define SPIM0_MAX_DATARATE 8
|
||||
#define SPIM1_MAX_DATARATE 8
|
||||
#define SPIM2_MAX_DATARATE 8
|
||||
#define SPIM3_MAX_DATARATE 32
|
||||
|
||||
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1
|
||||
|
||||
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIM1_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIM2_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIM3_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA*/
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 3
|
||||
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIS2_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Two Wire Interface Master with DMA */
|
||||
#define TWIM_PRESENT
|
||||
#define TWIM_COUNT 2
|
||||
|
||||
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define TWIM1_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Two Wire Interface Slave with DMA */
|
||||
#define TWIS_PRESENT
|
||||
#define TWIS_COUNT 2
|
||||
|
||||
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define TWIS1_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||
#define UARTE_PRESENT
|
||||
#define UARTE_COUNT 2
|
||||
|
||||
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define UARTE1_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Successive Approximation Analog to Digital Converter */
|
||||
#define SAADC_PRESENT
|
||||
#define SAADC_COUNT 1
|
||||
|
||||
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 8
|
||||
|
||||
#define GPIOTE_FEATURE_SET_PRESENT
|
||||
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 16
|
||||
|
||||
#define LPCOMP_FEATURE_HYST_PRESENT
|
||||
|
||||
/* Comparator */
|
||||
#define COMP_PRESENT
|
||||
#define COMP_COUNT 1
|
||||
|
||||
/* Pulse Width Modulator */
|
||||
#define PWM_PRESENT
|
||||
#define PWM_COUNT 4
|
||||
|
||||
#define PWM0_CH_NUM 4
|
||||
#define PWM1_CH_NUM 4
|
||||
#define PWM2_CH_NUM 4
|
||||
#define PWM3_CH_NUM 4
|
||||
|
||||
#define PWM0_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM1_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM2_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM3_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Pulse Density Modulator */
|
||||
#define PDM_PRESENT
|
||||
#define PDM_COUNT 1
|
||||
|
||||
#define PDM_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Inter-IC Sound Interface */
|
||||
#define I2S_PRESENT
|
||||
#define I2S_COUNT 1
|
||||
|
||||
#define I2S_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Universal Serial Bus Device */
|
||||
#define USBD_PRESENT
|
||||
#define USBD_COUNT 1
|
||||
|
||||
#define USBD_EASYDMA_MAXCNT_SIZE 7
|
||||
|
||||
/* ARM TrustZone Cryptocell 310 */
|
||||
#define CRYPTOCELL_PRESENT
|
||||
#define CRYPTOCELL_COUNT 1
|
||||
|
||||
/* Quad SPI */
|
||||
#define QSPI_PRESENT
|
||||
#define QSPI_COUNT 1
|
||||
|
||||
#define QSPI_EASYDMA_MAXCNT_SIZE 20
|
||||
|
||||
#endif // _NRF52840_PERIPHERALS_H
|
||||
12657
lib/sdk/components/device/nrf52_bitfields.h
Normal file
12657
lib/sdk/components/device/nrf52_bitfields.h
Normal file
File diff suppressed because it is too large
Load Diff
81
lib/sdk/components/device/nrf52_name_change.h
Normal file
81
lib/sdk/components/device/nrf52_name_change.h
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef NRF52_NAME_CHANGE_H
|
||||
#define NRF52_NAME_CHANGE_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and
|
||||
* nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
|
||||
* macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
|
||||
*/
|
||||
|
||||
/* I2S */
|
||||
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
|
||||
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
|
||||
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
|
||||
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
|
||||
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
|
||||
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
|
||||
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
|
||||
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
|
||||
|
||||
/* LPCOMP */
|
||||
/* Corrected typo in RESULT register. */
|
||||
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF52_NAME_CHANGE_H */
|
||||
|
||||
105
lib/sdk/components/device/nrf52_to_nrf52840.h
Normal file
105
lib/sdk/components/device/nrf52_to_nrf52840.h
Normal file
@ -0,0 +1,105 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef NRF52_TO_NRF52840_H
|
||||
#define NRF52_TO_NRF52840_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices.
|
||||
* It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
|
||||
* from the nrf52_namechange.h file. */
|
||||
|
||||
/* Differences between latest nRF52 headers and nRF52840 headers. */
|
||||
|
||||
/* UART */
|
||||
/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
|
||||
#define PSELRTS PSEL.RTS
|
||||
#define PSELTXD PSEL.TXD
|
||||
#define PSELCTS PSEL.CTS
|
||||
#define PSELRXD PSEL.RXD
|
||||
|
||||
/* TWI */
|
||||
/* The registers PSELSCL, PSELSDA were restructured into a struct. */
|
||||
#define PSELSCL PSEL.SCL
|
||||
#define PSELSDA PSEL.SDA
|
||||
|
||||
|
||||
/* LPCOMP */
|
||||
/* The hysteresis control enumerated values has changed name for nRF52840 devices. */
|
||||
#define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled
|
||||
#define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled
|
||||
|
||||
|
||||
/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
|
||||
|
||||
/* I2S */
|
||||
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
|
||||
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
|
||||
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
|
||||
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
|
||||
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
|
||||
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
|
||||
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
|
||||
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
|
||||
|
||||
/* LPCOMP */
|
||||
/* Corrected typo in RESULT register. */
|
||||
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_TO_NRF52840_H */
|
||||
|
||||
297
lib/sdk/components/drivers_nrf/common/nrf_drv_common.c
Normal file
297
lib/sdk/components/drivers_nrf/common/nrf_drv_common.c
Normal file
@ -0,0 +1,297 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include <stddef.h>
|
||||
#include "nrf_drv_common.h"
|
||||
#include "nrf_assert.h"
|
||||
#include "app_util_platform.h"
|
||||
#include "nrf_peripherals.h"
|
||||
|
||||
#if NRF_DRV_COMMON_POWER_CLOCK_ISR
|
||||
#include "nrf_drv_power.h"
|
||||
#include "nrf_drv_clock.h"
|
||||
#endif
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
#include "nrf_soc.h"
|
||||
#endif
|
||||
|
||||
#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
|
||||
|
||||
#define NRF_LOG_MODULE_NAME common
|
||||
|
||||
#if COMMON_CONFIG_LOG_ENABLED
|
||||
#define NRF_LOG_LEVEL COMMON_CONFIG_LOG_LEVEL
|
||||
#define NRF_LOG_INFO_COLOR COMMON_CONFIG_INFO_COLOR
|
||||
#define NRF_LOG_DEBUG_COLOR COMMON_CONFIG_DEBUG_COLOR
|
||||
#else //COMMON_CONFIG_LOG_ENABLED
|
||||
#define NRF_LOG_LEVEL 0
|
||||
#endif //COMMON_CONFIG_LOG_ENABLED
|
||||
#include "nrf_log.h"
|
||||
NRF_LOG_MODULE_REGISTER();
|
||||
|
||||
|
||||
typedef struct {
|
||||
nrf_drv_irq_handler_t handler;
|
||||
bool acquired;
|
||||
} shared_resource_t;
|
||||
|
||||
// SPIM0, SPIS0, SPI0, TWIM0, TWIS0, TWI0
|
||||
#if (NRF_MODULE_ENABLED(SPI0) || NRF_MODULE_ENABLED(SPIS0) || NRF_MODULE_ENABLED(TWI0) || NRF_MODULE_ENABLED(TWIS0))
|
||||
#define SERIAL_BOX_0_IN_USE
|
||||
// [this checking may need a different form in unit tests, hence macro]
|
||||
#ifndef IS_SERIAL_BOX_0
|
||||
#define IS_SERIAL_BOX_0(p_per_base) (p_per_base == NRF_SPI0)
|
||||
#endif
|
||||
|
||||
static shared_resource_t m_serial_box_0 = { .acquired = false };
|
||||
void SPI0_TWI0_IRQHandler(void)
|
||||
{
|
||||
ASSERT(m_serial_box_0.handler);
|
||||
m_serial_box_0.handler();
|
||||
}
|
||||
#endif // (NRF_MODULE_ENABLED(SPI0) || NRF_MODULE_ENABLED(SPIS0) || NRF_MODULE_ENABLED(TWI0) || NRF_MODULE_ENABLED(TWIS0))
|
||||
|
||||
// SPIM1, SPIS1, SPI1, TWIM1, TWIS1, TWI1
|
||||
#if (NRF_MODULE_ENABLED(SPI1) || NRF_MODULE_ENABLED(SPIS1) || NRF_MODULE_ENABLED(TWI1) || NRF_MODULE_ENABLED(TWIS1))
|
||||
#define SERIAL_BOX_1_IN_USE
|
||||
// [this checking may need a different form in unit tests, hence macro]
|
||||
#ifndef IS_SERIAL_BOX_1
|
||||
#define IS_SERIAL_BOX_1(p_per_base) (p_per_base == NRF_SPI1)
|
||||
#endif
|
||||
|
||||
static shared_resource_t m_serial_box_1 = { .acquired = false };
|
||||
#ifdef TWIM_PRESENT
|
||||
void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler(void)
|
||||
#else
|
||||
void SPI1_TWI1_IRQHandler(void)
|
||||
#endif
|
||||
{
|
||||
ASSERT(m_serial_box_1.handler);
|
||||
m_serial_box_1.handler();
|
||||
}
|
||||
#endif // (NRF_MODULE_ENABLED(SPI1) || NRF_MODULE_ENABLED(SPIS1) || NRF_MODULE_ENABLED(TWI1) || NRF_MODULE_ENABLED(TWIS1))
|
||||
|
||||
// SPIM2, SPIS2, SPI2
|
||||
#if (NRF_MODULE_ENABLED(SPI2) || NRF_MODULE_ENABLED(SPIS2))
|
||||
#define SERIAL_BOX_2_IN_USE
|
||||
// [this checking may need a different form in unit tests, hence macro]
|
||||
#ifndef IS_SERIAL_BOX_2
|
||||
#define IS_SERIAL_BOX_2(p_per_base) (p_per_base == NRF_SPI2)
|
||||
#endif
|
||||
|
||||
static shared_resource_t m_serial_box_2 = { .acquired = false };
|
||||
void SPIM2_SPIS2_SPI2_IRQHandler(void)
|
||||
{
|
||||
ASSERT(m_serial_box_2.handler);
|
||||
m_serial_box_2.handler();
|
||||
}
|
||||
#endif // (NRF_MODULE_ENABLED(SPI2) || NRF_MODULE_ENABLED(SPIS2))
|
||||
|
||||
// COMP, LPCOMP
|
||||
#if (NRF_MODULE_ENABLED(COMP) || NRF_MODULE_ENABLED(LPCOMP))
|
||||
#define COMP_LPCOMP_IN_USE
|
||||
|
||||
#ifndef IS_COMP_LPCOMP
|
||||
#define IS_COMP_LPCOMP(p_per_base) ((p_per_base) == NRF_LPCOMP)
|
||||
#endif
|
||||
|
||||
static shared_resource_t m_comp_lpcomp = { .acquired = false };
|
||||
void LPCOMP_IRQHandler(void)
|
||||
{
|
||||
ASSERT(m_comp_lpcomp.handler);
|
||||
m_comp_lpcomp.handler();
|
||||
}
|
||||
#endif // (NRF_MODULE_ENABLED(COMP) || NRF_MODULE_ENABLED(LPCOMP))
|
||||
|
||||
#if defined(SERIAL_BOX_0_IN_USE) || \
|
||||
defined(SERIAL_BOX_1_IN_USE) || \
|
||||
defined(SERIAL_BOX_2_IN_USE) || \
|
||||
defined(COMP_LPCOMP_IN_USE)
|
||||
static ret_code_t acquire_shared_resource(shared_resource_t * p_resource,
|
||||
nrf_drv_irq_handler_t handler)
|
||||
{
|
||||
ret_code_t err_code;
|
||||
|
||||
bool busy = false;
|
||||
|
||||
CRITICAL_REGION_ENTER();
|
||||
if (p_resource->acquired)
|
||||
{
|
||||
busy = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
p_resource->acquired = true;
|
||||
}
|
||||
CRITICAL_REGION_EXIT();
|
||||
|
||||
if (busy)
|
||||
{
|
||||
err_code = NRF_ERROR_BUSY;
|
||||
NRF_LOG_WARNING("Function: %s, error code: %s.", (uint32_t)__func__, (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code));
|
||||
return err_code;
|
||||
}
|
||||
|
||||
p_resource->handler = handler;
|
||||
err_code = NRF_SUCCESS;
|
||||
NRF_LOG_INFO("Function: %s, error code: %s.", (uint32_t)__func__, (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code));
|
||||
return err_code;
|
||||
}
|
||||
#endif
|
||||
|
||||
ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base,
|
||||
nrf_drv_irq_handler_t handler)
|
||||
{
|
||||
#ifdef SERIAL_BOX_0_IN_USE
|
||||
if (IS_SERIAL_BOX_0(p_per_base))
|
||||
{
|
||||
return acquire_shared_resource(&m_serial_box_0, handler);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef SERIAL_BOX_1_IN_USE
|
||||
if (IS_SERIAL_BOX_1(p_per_base))
|
||||
{
|
||||
return acquire_shared_resource(&m_serial_box_1, handler);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef SERIAL_BOX_2_IN_USE
|
||||
if (IS_SERIAL_BOX_2(p_per_base))
|
||||
{
|
||||
return acquire_shared_resource(&m_serial_box_2, handler);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef COMP_LPCOMP_IN_USE
|
||||
if (IS_COMP_LPCOMP(p_per_base))
|
||||
{
|
||||
return acquire_shared_resource(&m_comp_lpcomp, handler);
|
||||
}
|
||||
#endif
|
||||
ret_code_t err_code;
|
||||
|
||||
err_code = NRF_ERROR_INVALID_PARAM;
|
||||
NRF_LOG_WARNING("Function: %s, error code: %s.", (uint32_t)__func__, (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code));
|
||||
return err_code;
|
||||
}
|
||||
|
||||
void nrf_drv_common_per_res_release(void const * p_per_base)
|
||||
{
|
||||
#ifdef SERIAL_BOX_0_IN_USE
|
||||
if (IS_SERIAL_BOX_0(p_per_base))
|
||||
{
|
||||
m_serial_box_0.acquired = false;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
#ifdef SERIAL_BOX_1_IN_USE
|
||||
if (IS_SERIAL_BOX_1(p_per_base))
|
||||
{
|
||||
m_serial_box_1.acquired = false;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
#ifdef SERIAL_BOX_2_IN_USE
|
||||
if (IS_SERIAL_BOX_2(p_per_base))
|
||||
{
|
||||
m_serial_box_2.acquired = false;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
#ifdef COMP_LPCOMP_IN_USE
|
||||
if (IS_COMP_LPCOMP(p_per_base))
|
||||
{
|
||||
m_comp_lpcomp.acquired = false;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
{}
|
||||
}
|
||||
|
||||
#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
|
||||
|
||||
#if NRF_MODULE_ENABLED(POWER)
|
||||
void nrf_drv_common_power_irq_disable(void)
|
||||
{
|
||||
#if NRF_DRV_COMMON_POWER_CLOCK_ISR
|
||||
if (!nrf_drv_clock_init_check())
|
||||
#endif
|
||||
{
|
||||
nrf_drv_common_irq_disable(POWER_CLOCK_IRQn);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if NRF_MODULE_ENABLED(CLOCK)
|
||||
void nrf_drv_common_clock_irq_disable(void)
|
||||
{
|
||||
#if NRF_DRV_COMMON_POWER_CLOCK_ISR
|
||||
if (!nrf_drv_power_init_check())
|
||||
#endif
|
||||
{
|
||||
nrf_drv_common_irq_disable(POWER_CLOCK_IRQn);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if NRF_DRV_COMMON_POWER_CLOCK_ISR
|
||||
void POWER_CLOCK_IRQHandler(void)
|
||||
{
|
||||
extern void nrf_drv_clock_onIRQ(void);
|
||||
extern void nrf_drv_power_onIRQ(void);
|
||||
|
||||
nrf_drv_clock_onIRQ();
|
||||
nrf_drv_power_onIRQ();
|
||||
}
|
||||
#endif // NRF_DRV_COMMON_POWER_CLOCK_ISR
|
||||
|
||||
|
||||
void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority)
|
||||
{
|
||||
INTERRUPT_PRIORITY_ASSERT(priority);
|
||||
|
||||
NVIC_SetPriority(IRQn, priority);
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
358
lib/sdk/components/drivers_nrf/common/nrf_drv_common.h
Normal file
358
lib/sdk/components/drivers_nrf/common/nrf_drv_common.h
Normal file
@ -0,0 +1,358 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_DRV_COMMON_H__
|
||||
#define NRF_DRV_COMMON_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "sdk_errors.h"
|
||||
#include "sdk_common.h"
|
||||
#include "nrf_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef NRF51
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
#define INTERRUPT_PRIORITY_IS_VALID(pri) (((pri) == 1) || ((pri) == 3))
|
||||
#else
|
||||
#define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 4)
|
||||
#endif //SOFTDEVICE_PRESENT
|
||||
#else
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
#define INTERRUPT_PRIORITY_IS_VALID(pri) ((((pri) > 1) && ((pri) < 4)) || \
|
||||
(((pri) > 4) && ((pri) < 8)))
|
||||
#else
|
||||
#define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 8)
|
||||
#endif //SOFTDEVICE_PRESENT
|
||||
#endif //NRF52
|
||||
|
||||
#define INTERRUPT_PRIORITY_VALIDATION(pri) STATIC_ASSERT(INTERRUPT_PRIORITY_IS_VALID((pri)))
|
||||
#define INTERRUPT_PRIORITY_ASSERT(pri) ASSERT(INTERRUPT_PRIORITY_IS_VALID((pri)))
|
||||
|
||||
/**
|
||||
* @defgroup nrf_drv_common Peripheral drivers common module
|
||||
* @{
|
||||
* @ingroup nrf_drivers
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Offset of event registers in every peripheral instance.
|
||||
*
|
||||
* This is the offset where event registers start in every peripheral.
|
||||
*/
|
||||
#define NRF_DRV_COMMON_EVREGS_OFFSET 0x100U
|
||||
|
||||
/**
|
||||
* @brief The flag that is set when POWER_CLOCK ISR is implemented in common module
|
||||
*
|
||||
* This flag means that the function POWER_CLOCK_IRQHandler is implemented in
|
||||
* nrf_drv_common.c file. In the @c clock and @c power modules functions
|
||||
* nrf_drv_clock_onIRQ nrf_drv_power_onIRQ should be implemented
|
||||
* and they would be called from common implementation.
|
||||
*
|
||||
* None of the checking is done here.
|
||||
* The implementation functions in @c clock and @c power are required to handle
|
||||
* correctly the case when they are called without any event bit set.
|
||||
*/
|
||||
#define NRF_DRV_COMMON_POWER_CLOCK_ISR (NRF_MODULE_ENABLED(CLOCK) && NRF_MODULE_ENABLED(POWER))
|
||||
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_DRV_STATE_UNINITIALIZED, /**< Uninitialized. */
|
||||
NRF_DRV_STATE_INITIALIZED, /**< Initialized but powered off. */
|
||||
NRF_DRV_STATE_POWERED_ON
|
||||
} nrf_drv_state_t;
|
||||
|
||||
/**
|
||||
* @brief Driver power state selection.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_DRV_PWR_CTRL_ON, /**< Power on request. */
|
||||
NRF_DRV_PWR_CTRL_OFF /**< Power off request. */
|
||||
} nrf_drv_pwr_ctrl_t;
|
||||
|
||||
/**
|
||||
* @brief IRQ handler type.
|
||||
*/
|
||||
typedef void (*nrf_drv_irq_handler_t)(void);
|
||||
|
||||
|
||||
#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
|
||||
|
||||
/**
|
||||
* @brief Function for acquiring shared peripheral resources associated with
|
||||
* the specified peripheral.
|
||||
*
|
||||
* Certain resources and registers are shared among peripherals that have
|
||||
* the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0).
|
||||
* Only one of them can be utilized at a given time. This function reserves
|
||||
* proper resources to be used by the specified peripheral.
|
||||
* If PERIPHERAL_RESOURCE_SHARING_ENABLED is set to a non-zero value, IRQ
|
||||
* handlers for peripherals that are sharing resources with others are
|
||||
* implemented by the nrf_drv_common module instead of individual drivers.
|
||||
* The drivers must then specify their interrupt handling routines and
|
||||
* register them by using this function.
|
||||
*
|
||||
* @param[in] p_per_base Requested peripheral base pointer.
|
||||
* @param[in] handler Interrupt handler to register. May be NULL
|
||||
* if interrupts are not used for the peripheral.
|
||||
*
|
||||
* @retval NRF_SUCCESS If resources were acquired successfully.
|
||||
* @retval NRF_ERROR_BUSY If resources were already acquired.
|
||||
* @retval NRF_ERROR_INVALID_PARAM If the specified peripheral is not enabled
|
||||
* or the peripheral does not share resources
|
||||
* with other peripherals.
|
||||
*/
|
||||
ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base,
|
||||
nrf_drv_irq_handler_t handler);
|
||||
|
||||
/**
|
||||
* @brief Function for releasing shared resources reserved previously by
|
||||
* @ref nrf_drv_common_per_res_acquire() for the specified peripheral.
|
||||
*
|
||||
* @param[in] p_per_base Requested peripheral base pointer.
|
||||
*/
|
||||
void nrf_drv_common_per_res_release(void const * p_per_base);
|
||||
|
||||
#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function sets priority and enables NVIC interrupt
|
||||
*
|
||||
* @note Function checks if correct priority is used when softdevice is present
|
||||
*
|
||||
* @param[in] IRQn Interrupt id
|
||||
* @param[in] priority Interrupt priority
|
||||
*/
|
||||
void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority);
|
||||
|
||||
#if NRF_MODULE_ENABLED(POWER)
|
||||
/**
|
||||
* @brief Disable power IRQ
|
||||
*
|
||||
* Power and clock peripheral uses the same IRQ.
|
||||
* This function disables POWER_CLOCK IRQ only if CLOCK driver
|
||||
* is uninitialized.
|
||||
*
|
||||
* @sa nrf_drv_common_power_clock_irq_init
|
||||
*/
|
||||
void nrf_drv_common_power_irq_disable(void);
|
||||
#endif
|
||||
|
||||
#if NRF_MODULE_ENABLED(CLOCK)
|
||||
/**
|
||||
* @brief Disable clock IRQ
|
||||
*
|
||||
* Power and clock peripheral uses the same IRQ.
|
||||
* This function disables POWER_CLOCK IRQ only if POWER driver
|
||||
* is uninitialized.
|
||||
*
|
||||
* @sa nrf_drv_common_power_clock_irq_init
|
||||
*/
|
||||
void nrf_drv_common_clock_irq_disable(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Check if interrupt is enabled
|
||||
*
|
||||
* Function that checks if selected interrupt is enabled.
|
||||
*
|
||||
* @param[in] IRQn Interrupt id
|
||||
*
|
||||
* @retval true Selected IRQ is enabled.
|
||||
* @retval false Selected IRQ is disabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_drv_common_irq_enable_check(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
* @brief Function disables NVIC interrupt
|
||||
*
|
||||
* @param[in] IRQn Interrupt id
|
||||
*/
|
||||
__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
* @brief Convert bit position to event code
|
||||
*
|
||||
* Function for converting the bit position in INTEN register to event code
|
||||
* that is equivalent to the offset of the event register from the beginning
|
||||
* of peripheral instance.
|
||||
*
|
||||
* For example the result of this function can be casted directly to
|
||||
* the types like @ref nrf_twis_event_t or @ref nrf_rng_event_t
|
||||
*
|
||||
* @param bit Bit position in INTEN register
|
||||
* @return Event code to be casted to the right enum type or to be used in functions like
|
||||
* @ref nrf_rng_event_get
|
||||
*
|
||||
* @sa nrf_drv_event_to_bitpos
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit);
|
||||
|
||||
/**
|
||||
* @brief Convert event code to bit position
|
||||
*
|
||||
* This function can be used to get bit position in INTEN register from event code.
|
||||
*
|
||||
* @param event Event code that may be casted from enum values from types like
|
||||
* @ref nrf_twis_event_t or @ref nrf_rng_event_t
|
||||
* @return Bit position in INTEN register that corresponds to the given code.
|
||||
*
|
||||
* @sa nrf_drv_bitpos_to_event
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event);
|
||||
|
||||
/**
|
||||
* @brief Get interrupt number connected with given instance
|
||||
*
|
||||
* Function returns interrupt number for a given instance of any peripheral.
|
||||
* @param[in] pinst Pointer to peripheral registry
|
||||
* @return Interrupt number
|
||||
*/
|
||||
__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst);
|
||||
|
||||
#if NRF_MODULE_ENABLED(CLOCK) || NRF_MODULE_ENABLED(POWER)
|
||||
/**
|
||||
* @brief Enable and setup power clock IRQ
|
||||
*
|
||||
* This function would be called from @ref nrf_drv_clock and @ref nrf_drv_power
|
||||
* to enable related interrupt.
|
||||
* This function avoids multiple interrupt configuration.
|
||||
*
|
||||
* @note
|
||||
* This function is aviable only if @ref nrf_drv_clock or @ref nrf_drv_power
|
||||
* module is enabled.
|
||||
*
|
||||
* @note
|
||||
* If both @ref nrf_drv_clock and @ref nrf_drv_power modules are enabled,
|
||||
* during the compilation the check is made that
|
||||
* @ref CLOCK_CONFIG_IRQ_PRIORITY equals @ref POWER_CONFIG_IRQ_PRIORITY.
|
||||
*
|
||||
* @sa nrf_drv_common_power_irq_disable
|
||||
* @sa nrf_drv_common_clock_irq_disable
|
||||
*/
|
||||
__STATIC_INLINE void nrf_drv_common_power_clock_irq_init(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Check if given object is in RAM
|
||||
*
|
||||
* Function for analyzing if given location is placed in RAM.
|
||||
* This function is used to determine if we have address that can be supported by EasyDMA.
|
||||
* @param[in] ptr Pointer to the object
|
||||
* @retval true Object is located in RAM
|
||||
* @retval false Object is not located in RAM
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr);
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE bool nrf_drv_common_irq_enable_check(IRQn_Type IRQn)
|
||||
{
|
||||
return 0 != (NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] &
|
||||
(uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit)
|
||||
{
|
||||
return NRF_DRV_COMMON_EVREGS_OFFSET + bit * sizeof(uint32_t);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event)
|
||||
{
|
||||
return (event - NRF_DRV_COMMON_EVREGS_OFFSET) / sizeof(uint32_t);
|
||||
}
|
||||
|
||||
__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst)
|
||||
{
|
||||
uint8_t ret = (uint8_t)((uint32_t)pinst>>12U);
|
||||
return (IRQn_Type) ret;
|
||||
}
|
||||
|
||||
#if NRF_MODULE_ENABLED(CLOCK) || NRF_MODULE_ENABLED(POWER)
|
||||
__STATIC_INLINE void nrf_drv_common_power_clock_irq_init(void)
|
||||
{
|
||||
if (!nrf_drv_common_irq_enable_check(POWER_CLOCK_IRQn))
|
||||
{
|
||||
nrf_drv_common_irq_enable(
|
||||
POWER_CLOCK_IRQn,
|
||||
#if NRF_DRV_COMMON_POWER_CLOCK_ISR
|
||||
#if CLOCK_CONFIG_IRQ_PRIORITY != POWER_CONFIG_IRQ_PRIORITY
|
||||
#error CLOCK_CONFIG_IRQ_PRIORITY and POWER_CONFIG_IRQ_PRIORITY have to be the same.
|
||||
#endif
|
||||
CLOCK_CONFIG_IRQ_PRIORITY
|
||||
#elif NRF_MODULE_ENABLED(CLOCK)
|
||||
CLOCK_CONFIG_IRQ_PRIORITY
|
||||
#elif NRF_MODULE_ENABLED(POWER)
|
||||
POWER_CONFIG_IRQ_PRIORITY
|
||||
#endif
|
||||
);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr)
|
||||
{
|
||||
return ((((uintptr_t)ptr) & 0xE0000000u) == 0x20000000u);
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_DRV_COMMON_H__
|
||||
|
||||
/** @} */
|
||||
269
lib/sdk/components/drivers_nrf/delay/nrf_delay.h
Normal file
269
lib/sdk/components/drivers_nrf/delay/nrf_delay.h
Normal file
@ -0,0 +1,269 @@
|
||||
/**
|
||||
* Copyright (c) 2011 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _NRF_DELAY_H
|
||||
#define _NRF_DELAY_H
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CLOCK_FREQ_16MHz (16000000UL)
|
||||
|
||||
#ifdef NRF52_SERIES
|
||||
#define CPU_FREQ_64MHz
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Function for delaying execution for number of microseconds.
|
||||
*
|
||||
* @note NRF52 has instruction cache and because of that delay is not precise.
|
||||
*
|
||||
* @param number_of_us
|
||||
*
|
||||
*/
|
||||
/*lint -e{438, 522, 40, 10, 563} */
|
||||
__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for delaying execution for number of miliseconds.
|
||||
*
|
||||
* @note NRF52 has instruction cache and because of that delay is not precise.
|
||||
*
|
||||
* @note Function internally calls @ref nrf_delay_us so the maximum delay is the
|
||||
* same as in case of @ref nrf_delay_us, approx. 71 minutes.
|
||||
*
|
||||
* @param number_of_ms
|
||||
*
|
||||
*/
|
||||
|
||||
/*lint -e{438, 522, 40, 10, 563} */
|
||||
__STATIC_INLINE void nrf_delay_ms(uint32_t number_of_ms);
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us)
|
||||
{
|
||||
if (!number_of_us)
|
||||
return;
|
||||
__asm
|
||||
{
|
||||
loop:
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
CMP SystemCoreClock, CLOCK_FREQ_16MHz
|
||||
BEQ cond
|
||||
NOP
|
||||
#ifdef CPU_FREQ_64MHz
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
#endif //CPU_FREQ_64MHz
|
||||
cond:
|
||||
SUBS number_of_us, #1
|
||||
BNE loop
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined ( _WIN32 ) || defined ( __unix ) || defined( __APPLE__ )
|
||||
|
||||
|
||||
#ifndef CUSTOM_NRF_DELAY_US
|
||||
__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us)
|
||||
{}
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ ) || ( __ICCARM__ )
|
||||
|
||||
__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us)
|
||||
{
|
||||
const uint32_t clock16MHz = CLOCK_FREQ_16MHz;
|
||||
if (number_of_us)
|
||||
{
|
||||
__ASM volatile (
|
||||
#if ( defined(__GNUC__) && (__CORTEX_M == (0x00U) ) )
|
||||
".syntax unified\n"
|
||||
#endif
|
||||
"1:\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" CMP %[SystemCoreClock], %[clock16MHz]\n"
|
||||
" BEQ.N 2f\n"
|
||||
" NOP\n"
|
||||
#ifdef CPU_FREQ_64MHz
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
" NOP\n"
|
||||
#endif //CPU_FREQ_64MHz
|
||||
"2:\n"
|
||||
" SUBS %[number_of_us], %[number_of_us], #1\n"
|
||||
" BNE.N 1b\n"
|
||||
#if ( defined(__GNUC__) && (__CORTEX_M == (0x00U) ) )
|
||||
".syntax divided\n"
|
||||
#endif
|
||||
#if ( __CORTEX_M == (0x00U) )
|
||||
// The SUBS instruction in Cortex-M0 is available only in 16-bit encoding,
|
||||
// hence it requires a "lo" register (r0-r7) as an operand.
|
||||
: [number_of_us] "=l" (number_of_us)
|
||||
#else
|
||||
: [number_of_us] "=r" (number_of_us)
|
||||
#endif
|
||||
: [SystemCoreClock] "r" (SystemCoreClock),
|
||||
[clock16MHz] "r" (clock16MHz),
|
||||
"[number_of_us]" (number_of_us)
|
||||
: "cc"
|
||||
);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
__STATIC_INLINE void nrf_delay_ms(uint32_t number_of_ms)
|
||||
{
|
||||
nrf_delay_us(1000*number_of_ms);
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
401
lib/sdk/components/drivers_nrf/hal/nrf_clock.h
Normal file
401
lib/sdk/components/drivers_nrf/hal/nrf_clock.h
Normal file
@ -0,0 +1,401 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_CLOCK_H__
|
||||
#define NRF_CLOCK_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup nrf_clock_hal Clock HAL
|
||||
* @{
|
||||
* @ingroup nrf_clock
|
||||
* @brief Hardware access layer for managing the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK).
|
||||
*/
|
||||
|
||||
#define NRF_CLOCK_TASK_TRIGGER (1UL)
|
||||
#define NRF_CLOCK_EVENT_CLEAR (0UL)
|
||||
|
||||
/**
|
||||
* @brief Low-frequency clock sources.
|
||||
* @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */
|
||||
NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
|
||||
NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth /**< Internal 32 kHz synthesizer from HFCLK system clock. */
|
||||
} nrf_clock_lfclk_t;
|
||||
|
||||
/**
|
||||
* @brief High-frequency clock sources.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_RC, /**< Internal 16 MHz RC oscillator. */
|
||||
NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */
|
||||
} nrf_clock_hfclk_t;
|
||||
|
||||
/**
|
||||
* @brief Trigger status of task LFCLKSTART/HFCLKSTART.
|
||||
* @details Used by LFCLKRUN and HFCLKRUN registers.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_CLOCK_START_TASK_NOT_TRIGGERED = CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */
|
||||
NRF_CLOCK_START_TASK_TRIGGERED = CLOCK_LFCLKRUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */
|
||||
} nrf_clock_start_task_status_t;
|
||||
|
||||
/**
|
||||
* @brief Interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */
|
||||
NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */
|
||||
NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */
|
||||
NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk /**< Interrupt on CTTO event. */
|
||||
} nrf_clock_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief Tasks.
|
||||
*
|
||||
* @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running.
|
||||
* The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/
|
||||
NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source.*/
|
||||
NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source.*/
|
||||
NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source.*/
|
||||
NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator.*/
|
||||
NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer.*/
|
||||
NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer.*/
|
||||
} nrf_clock_task_t; /*lint -restore */
|
||||
|
||||
/**
|
||||
* @brief Events.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/
|
||||
NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/
|
||||
NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed.*/
|
||||
NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO) /**< Calibration timer time-out.*/
|
||||
} nrf_clock_event_t; /*lint -restore */
|
||||
|
||||
/**
|
||||
* @brief Function for enabling a specific interrupt.
|
||||
*
|
||||
* @param[in] int_mask Interrupt.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling a specific interrupt.
|
||||
*
|
||||
* @param[in] int_mask Interrupt.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a specific interrupt.
|
||||
*
|
||||
* @param[in] int_mask Interrupt.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the address of a specific task.
|
||||
* @details This function can be used by the PPI module.
|
||||
*
|
||||
* @param[in] task Task.
|
||||
*
|
||||
* @return Address of the requested task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for setting a specific task.
|
||||
*
|
||||
* @param[in] task Task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the address of a specific event.
|
||||
* @details This function can be used by the PPI module.
|
||||
*
|
||||
* @param[in] event Event.
|
||||
*
|
||||
* @return Address of the requested event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific event.
|
||||
*
|
||||
* @param[in] event Event.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a specific event.
|
||||
*
|
||||
* @param[in] event Event.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for changing the low-frequency clock source.
|
||||
* @details This function cannot be called when the low-frequency clock is running.
|
||||
*
|
||||
* @param[in] source New low-frequency clock source.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the selected source for the low-frequency clock.
|
||||
*
|
||||
* @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the selected source for the low-frequency clock.
|
||||
* @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the selected source for the low-frequency clock.
|
||||
* @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the selected source for the low-frequency clock.
|
||||
*/
|
||||
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the active source of the low-frequency clock.
|
||||
*
|
||||
* @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the active source of the low-frequency clock.
|
||||
* @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the active source of the low-frequency clock.
|
||||
* @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the active source of the low-frequency clock.
|
||||
*/
|
||||
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the clock source for the LFCLK clock when the task LKCLKSTART is triggered.
|
||||
*
|
||||
* @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is running and generating the LFCLK clock.
|
||||
* @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is running and generating the LFCLK clock.
|
||||
* @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is running and generating the LFCLK clock.
|
||||
*/
|
||||
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of the LFCLK clock.
|
||||
*
|
||||
* @retval false If the LFCLK clock is not running.
|
||||
* @retval true If the LFCLK clock is running.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_clock_lf_is_running(void);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the trigger status of the task LFCLKSTART.
|
||||
*
|
||||
* @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task LFCLKSTART has not been triggered.
|
||||
* @retval NRF_CLOCK_START_TASK_TRIGGERED If the task LFCLKSTART has been triggered.
|
||||
*/
|
||||
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the active source of the high-frequency clock.
|
||||
*
|
||||
* @retval NRF_CLOCK_HFCLK_LOW_ACCURACY If the internal 16 MHz RC oscillator is the active source of the high-frequency clock.
|
||||
* @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY If an external 16 MHz/32 MHz crystal oscillator is the active source of the high-frequency clock.
|
||||
*/
|
||||
__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of the HFCLK clock.
|
||||
*
|
||||
* @param[in] clk_src Clock source to be checked.
|
||||
*
|
||||
* @retval false If the HFCLK clock is not running.
|
||||
* @retval true If the HFCLK clock is running.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the trigger status of the task HFCLKSTART.
|
||||
*
|
||||
* @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task HFCLKSTART has not been triggered.
|
||||
* @retval NRF_CLOCK_START_TASK_TRIGGERED If the task HFCLKSTART has been triggered.
|
||||
*/
|
||||
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void);
|
||||
|
||||
/**
|
||||
* @brief Function for changing the calibration timer interval.
|
||||
*
|
||||
* @param[in] interval New calibration timer interval in 0.25 s resolution (range: 0.25 seconds to 31.75 seconds).
|
||||
*/
|
||||
__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval);
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask)
|
||||
{
|
||||
NRF_CLOCK->INTENSET = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask)
|
||||
{
|
||||
NRF_CLOCK->INTENCLR = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask)
|
||||
{
|
||||
return (bool)(NRF_CLOCK->INTENCLR & int_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task)
|
||||
{
|
||||
return ((uint32_t )NRF_CLOCK + task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = NRF_CLOCK_TASK_TRIGGER;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event)
|
||||
{
|
||||
return ((uint32_t)NRF_CLOCK + event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = NRF_CLOCK_EVENT_CLEAR;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event)
|
||||
{
|
||||
return (bool)*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event));
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source)
|
||||
{
|
||||
NRF_CLOCK->LFCLKSRC =
|
||||
(uint32_t)((source << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void)
|
||||
{
|
||||
return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRC &
|
||||
CLOCK_LFCLKSRC_SRC_Msk) >> CLOCK_LFCLKSRC_SRC_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void)
|
||||
{
|
||||
return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSTAT &
|
||||
CLOCK_LFCLKSTAT_SRC_Msk) >> CLOCK_LFCLKSTAT_SRC_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void)
|
||||
{
|
||||
return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRCCOPY &
|
||||
CLOCK_LFCLKSRCCOPY_SRC_Msk) >> CLOCK_LFCLKSRCCOPY_SRC_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_clock_lf_is_running(void)
|
||||
{
|
||||
return ((NRF_CLOCK->LFCLKSTAT &
|
||||
CLOCK_LFCLKSTAT_STATE_Msk) >> CLOCK_LFCLKSTAT_STATE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void)
|
||||
{
|
||||
return (nrf_clock_start_task_status_t)((NRF_CLOCK->LFCLKRUN &
|
||||
CLOCK_LFCLKRUN_STATUS_Msk) >>
|
||||
CLOCK_LFCLKRUN_STATUS_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void)
|
||||
{
|
||||
return (nrf_clock_hfclk_t)((NRF_CLOCK->HFCLKSTAT &
|
||||
CLOCK_HFCLKSTAT_SRC_Msk) >> CLOCK_HFCLKSTAT_SRC_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src)
|
||||
{
|
||||
return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) ==
|
||||
(CLOCK_HFCLKSTAT_STATE_Msk | (clk_src << CLOCK_HFCLKSTAT_SRC_Pos));
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void)
|
||||
{
|
||||
return (nrf_clock_start_task_status_t)((NRF_CLOCK->HFCLKRUN &
|
||||
CLOCK_HFCLKRUN_STATUS_Msk) >>
|
||||
CLOCK_HFCLKRUN_STATUS_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval)
|
||||
{
|
||||
NRF_CLOCK->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk);
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_CLOCK_H__
|
||||
518
lib/sdk/components/drivers_nrf/hal/nrf_comp.h
Normal file
518
lib/sdk/components/drivers_nrf/hal/nrf_comp.h
Normal file
@ -0,0 +1,518 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief COMP HAL API.
|
||||
*/
|
||||
|
||||
#ifndef NRF_COMP_H_
|
||||
#define NRF_COMP_H_
|
||||
|
||||
/**
|
||||
* @defgroup nrf_comp_hal COMP HAL
|
||||
* @{
|
||||
* @ingroup nrf_comp
|
||||
* @brief @tagAPI52 Hardware access layer for managing the Comparator (COMP).
|
||||
*/
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @enum nrf_comp_input_t
|
||||
* @brief COMP analog pin selection.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */
|
||||
NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */
|
||||
NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */
|
||||
NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */
|
||||
NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */
|
||||
NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */
|
||||
NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */
|
||||
#if defined (COMP_PSEL_PSEL_AnalogInput7) || defined (__SDK_DOXYGEN__)
|
||||
NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7, /*!< AIN7 selected as analog input. */
|
||||
#endif
|
||||
#if defined (COMP_PSEL_PSEL_VddDiv2) || defined (__SDK_DOXYGEN__)
|
||||
NRF_COMP_VDD_DIV2 = COMP_PSEL_PSEL_VddDiv2, /*!< VDD/2 selected as analog input. */
|
||||
#endif
|
||||
}nrf_comp_input_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_comp_ref_t
|
||||
* @brief COMP reference selection.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_COMP_REF_Int1V2 = COMP_REFSEL_REFSEL_Int1V2, /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V). */
|
||||
NRF_COMP_REF_Int1V8 = COMP_REFSEL_REFSEL_Int1V8, /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V). */
|
||||
NRF_COMP_REF_Int2V4 = COMP_REFSEL_REFSEL_Int2V4, /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V). */
|
||||
NRF_COMP_REF_VDD = COMP_REFSEL_REFSEL_VDD, /*!< VREF = VDD. */
|
||||
NRF_COMP_REF_ARef = COMP_REFSEL_REFSEL_ARef /*!< VREF = AREF (VDD >= VREF >= AREFMIN). */
|
||||
}nrf_comp_ref_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_comp_ext_ref_t
|
||||
* @brief COMP external analog reference selection.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_COMP_EXT_REF_0 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference0, /*!< Use AIN0 as external analog reference. */
|
||||
NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 /*!< Use AIN1 as external analog reference. */
|
||||
}nrf_comp_ext_ref_t;
|
||||
|
||||
/**
|
||||
* @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t th_down; /*!< THDOWN value. */
|
||||
uint8_t th_up; /*!< THUP value. */
|
||||
}nrf_comp_th_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_comp_main_mode_t
|
||||
* @brief COMP main operation mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_COMP_MAIN_MODE_SE = COMP_MODE_MAIN_SE, /*!< Single ended mode. */
|
||||
NRF_COMP_MAIN_MODE_Diff = COMP_MODE_MAIN_Diff /*!< Differential mode. */
|
||||
}nrf_comp_main_mode_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_comp_sp_mode_t
|
||||
* @brief COMP speed and power mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_COMP_SP_MODE_Low = COMP_MODE_SP_Low, /*!< Low power mode. */
|
||||
NRF_COMP_SP_MODE_Normal = COMP_MODE_SP_Normal, /*!< Normal mode. */
|
||||
NRF_COMP_SP_MODE_High = COMP_MODE_SP_High /*!< High speed mode. */
|
||||
}nrf_comp_sp_mode_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_comp_hyst_t
|
||||
* @brief COMP comparator hysteresis.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_COMP_HYST_NoHyst = COMP_HYST_HYST_NoHyst, /*!< Comparator hysteresis disabled. */
|
||||
NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV /*!< Comparator hysteresis enabled. */
|
||||
}nrf_comp_hyst_t;
|
||||
|
||||
#if defined (COMP_ISOURCE_ISOURCE_Msk)
|
||||
/**
|
||||
* @brief COMP current source selection on analog input.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_COMP_ISOURCE_Off = COMP_ISOURCE_ISOURCE_Off, /*!< Current source disabled. */
|
||||
NRF_COMP_ISOURCE_Ien2uA5 = COMP_ISOURCE_ISOURCE_Ien2mA5, /*!< Current source enabled (+/- 2.5 uA). */
|
||||
NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA, /*!< Current source enabled (+/- 5 uA). */
|
||||
NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA /*!< Current source enabled (+/- 10 uA). */
|
||||
}nrf_isource_t;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @enum nrf_comp_task_t
|
||||
* @brief COMP tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_COMP_TASK_START = offsetof(NRF_COMP_Type, TASKS_START), /*!< COMP start sampling task. */
|
||||
NRF_COMP_TASK_STOP = offsetof(NRF_COMP_Type, TASKS_STOP), /*!< COMP stop sampling task. */
|
||||
NRF_COMP_TASK_SAMPLE = offsetof(NRF_COMP_Type, TASKS_SAMPLE) /*!< Sample comparator value. */
|
||||
/*lint -restore*/
|
||||
}nrf_comp_task_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_comp_event_t
|
||||
* @brief COMP events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_COMP_EVENT_READY = offsetof(NRF_COMP_Type, EVENTS_READY), /*!< COMP is ready and output is valid. */
|
||||
NRF_COMP_EVENT_DOWN = offsetof(NRF_COMP_Type, EVENTS_DOWN), /*!< Input voltage crossed the threshold going down. */
|
||||
NRF_COMP_EVENT_UP = offsetof(NRF_COMP_Type, EVENTS_UP), /*!< Input voltage crossed the threshold going up. */
|
||||
NRF_COMP_EVENT_CROSS = offsetof(NRF_COMP_Type, EVENTS_CROSS) /*!< Input voltage crossed the threshold in any direction. */
|
||||
/*lint -restore*/
|
||||
}nrf_comp_event_t;
|
||||
|
||||
/**
|
||||
* @brief COMP reference configuration.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
nrf_comp_ref_t reference; /*!< COMP reference selection. */
|
||||
nrf_comp_ext_ref_t external; /*!< COMP external analog reference selection. */
|
||||
}nrf_comp_ref_conf_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the COMP peripheral.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_enable(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the COMP peripheral.
|
||||
*/
|
||||
|
||||
__STATIC_INLINE void nrf_comp_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Function for checking if the COMP peripheral is enabled.
|
||||
*
|
||||
* @retval true If the COMP peripheral is enabled.
|
||||
* @retval false If the COMP peripheral is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_comp_enable_check(void);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the reference source.
|
||||
*
|
||||
* @param[in] reference COMP reference selection.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the external analog reference source.
|
||||
*
|
||||
* @param[in] ext_ref COMP external analog reference selection.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting threshold voltages.
|
||||
*
|
||||
* @param[in] threshold COMP VDOWN and VUP thresholds.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the main mode.
|
||||
*
|
||||
* @param[in] main_mode COMP main operation mode.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the speed mode.
|
||||
*
|
||||
* @param[in] speed_mode COMP speed and power mode.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the hysteresis.
|
||||
*
|
||||
* @param[in] hyst COMP comparator hysteresis.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst);
|
||||
|
||||
#if defined (COMP_ISOURCE_ISOURCE_Msk)
|
||||
/**
|
||||
* @brief Function for setting the current source on the analog input.
|
||||
*
|
||||
* @param[in] isource COMP current source selection on analog input.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Function for selecting the active input of the COMP.
|
||||
*
|
||||
* @param[in] input Input to be selected.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the last COMP compare result.
|
||||
*
|
||||
* @return The last compare result. If 0, then VIN+ < VIN-. If 1, then VIN+ > VIN-.
|
||||
*
|
||||
* @note If VIN+ == VIN-, the return value depends on the previous result.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_comp_result_get(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling interrupts from COMP.
|
||||
*
|
||||
* @param[in] comp_int_mask Mask of interrupts to be enabled.
|
||||
*
|
||||
* @sa nrf_comp_int_enable_check()
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling interrupts from COMP.
|
||||
*
|
||||
* @param[in] comp_int_mask Mask of interrupts to be disabled.
|
||||
*
|
||||
* @sa nrf_comp_int_enable_check()
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the enabled interrupts of COMP.
|
||||
*
|
||||
* @param[in] comp_int_mask Mask of interrupts to be checked.
|
||||
*
|
||||
* @retval true If any interrupts of the specified mask are enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific COMP task register.
|
||||
*
|
||||
* @param[in] comp_task COMP task.
|
||||
*
|
||||
* @return Address of the specified COMP task.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific COMP event register.
|
||||
*
|
||||
* @param[in] comp_event COMP event.
|
||||
*
|
||||
* @return Address of the specified COMP event.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting COMP shorts.
|
||||
*
|
||||
* @param[in] comp_short_mask COMP shorts by mask.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing COMP shorts by mask.
|
||||
*
|
||||
* @param[in] comp_short_mask COMP shorts to be cleared.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting a specific COMP task.
|
||||
*
|
||||
* @param[in] comp_task COMP task to be set.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific COMP event.
|
||||
*
|
||||
* @param[in] comp_event COMP event to be cleared.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the state of a specific COMP event.
|
||||
*
|
||||
* @retval true If the specified COMP event is active.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event);
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_comp_enable(void)
|
||||
{
|
||||
NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Enabled << COMP_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_disable(void)
|
||||
{
|
||||
NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Disabled << COMP_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_comp_enable_check(void)
|
||||
{
|
||||
return ((NRF_COMP->ENABLE) & COMP_ENABLE_ENABLE_Enabled);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference)
|
||||
{
|
||||
NRF_COMP->REFSEL = (reference << COMP_REFSEL_REFSEL_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref)
|
||||
{
|
||||
NRF_COMP->EXTREFSEL = (ext_ref << COMP_EXTREFSEL_EXTREFSEL_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold)
|
||||
{
|
||||
NRF_COMP->TH =
|
||||
((threshold.th_down << COMP_TH_THDOWN_Pos) & COMP_TH_THDOWN_Msk) |
|
||||
((threshold.th_up << COMP_TH_THUP_Pos) & COMP_TH_THUP_Msk);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode)
|
||||
{
|
||||
NRF_COMP->MODE |= (main_mode << COMP_MODE_MAIN_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode)
|
||||
{
|
||||
NRF_COMP->MODE |= (speed_mode << COMP_MODE_SP_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst)
|
||||
{
|
||||
NRF_COMP->HYST = (hyst << COMP_HYST_HYST_Pos) & COMP_HYST_HYST_Msk;
|
||||
}
|
||||
|
||||
#if defined (COMP_ISOURCE_ISOURCE_Msk)
|
||||
__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource)
|
||||
{
|
||||
NRF_COMP->ISOURCE = (isource << COMP_ISOURCE_ISOURCE_Pos) & COMP_ISOURCE_ISOURCE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input)
|
||||
{
|
||||
NRF_COMP->PSEL = ((uint32_t)input << COMP_PSEL_PSEL_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_comp_result_get(void)
|
||||
{
|
||||
return (uint32_t)NRF_COMP->RESULT;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask)
|
||||
{
|
||||
NRF_COMP->INTENSET = comp_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask)
|
||||
{
|
||||
NRF_COMP->INTENCLR = comp_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask)
|
||||
{
|
||||
return (NRF_COMP->INTENSET & comp_int_mask); // when read this register will return the value of INTEN.
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask)
|
||||
{
|
||||
NRF_COMP->SHORTS |= comp_short_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask)
|
||||
{
|
||||
NRF_COMP->SHORTS &= ~comp_short_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task)
|
||||
{
|
||||
*( (volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_task) ) = 1;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event)
|
||||
{
|
||||
*( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)comp_event) ) = 0;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event)
|
||||
{
|
||||
return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_event));
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_COMP_H_
|
||||
100
lib/sdk/components/drivers_nrf/hal/nrf_ecb.c
Normal file
100
lib/sdk/components/drivers_nrf/hal/nrf_ecb.c
Normal file
@ -0,0 +1,100 @@
|
||||
/**
|
||||
* Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief Implementation of AES ECB driver
|
||||
*/
|
||||
|
||||
|
||||
//lint -e438
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_ecb.h"
|
||||
|
||||
static uint8_t ecb_data[48]; ///< ECB data structure for RNG peripheral to access.
|
||||
static uint8_t* ecb_key; ///< Key: Starts at ecb_data
|
||||
static uint8_t* ecb_cleartext; ///< Cleartext: Starts at ecb_data + 16 bytes.
|
||||
static uint8_t* ecb_ciphertext; ///< Ciphertext: Starts at ecb_data + 32 bytes.
|
||||
|
||||
bool nrf_ecb_init(void)
|
||||
{
|
||||
ecb_key = ecb_data;
|
||||
ecb_cleartext = ecb_data + 16;
|
||||
ecb_ciphertext = ecb_data + 32;
|
||||
|
||||
NRF_ECB->ECBDATAPTR = (uint32_t)ecb_data;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
bool nrf_ecb_crypt(uint8_t * dest_buf, const uint8_t * src_buf)
|
||||
{
|
||||
uint32_t counter = 0x1000000;
|
||||
if (src_buf != ecb_cleartext)
|
||||
{
|
||||
memcpy(ecb_cleartext,src_buf,16);
|
||||
}
|
||||
NRF_ECB->EVENTS_ENDECB = 0;
|
||||
NRF_ECB->TASKS_STARTECB = 1;
|
||||
while (NRF_ECB->EVENTS_ENDECB == 0)
|
||||
{
|
||||
counter--;
|
||||
if (counter == 0)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
NRF_ECB->EVENTS_ENDECB = 0;
|
||||
if (dest_buf != ecb_ciphertext)
|
||||
{
|
||||
memcpy(dest_buf,ecb_ciphertext,16);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void nrf_ecb_set_key(const uint8_t * key)
|
||||
{
|
||||
memcpy(ecb_key,key,16);
|
||||
}
|
||||
|
||||
|
||||
101
lib/sdk/components/drivers_nrf/hal/nrf_ecb.h
Normal file
101
lib/sdk/components/drivers_nrf/hal/nrf_ecb.h
Normal file
@ -0,0 +1,101 @@
|
||||
/**
|
||||
* Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief ECB driver API.
|
||||
*/
|
||||
|
||||
#ifndef NRF_ECB_H__
|
||||
#define NRF_ECB_H__
|
||||
|
||||
/**
|
||||
* @defgroup nrf_ecb AES ECB encryption
|
||||
* @{
|
||||
* @ingroup nrf_drivers
|
||||
* @brief Driver for the AES Electronic Code Book (ECB) peripheral.
|
||||
*
|
||||
* To encrypt data, the peripheral must first be powered on
|
||||
* using @ref nrf_ecb_init. Next, the key must be set using @ref nrf_ecb_set_key.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Function for initializing and powering on the ECB peripheral.
|
||||
*
|
||||
* This function allocates memory for the ECBDATAPTR.
|
||||
* @retval true If initialization was successful.
|
||||
* @retval false If powering on failed.
|
||||
*/
|
||||
bool nrf_ecb_init(void);
|
||||
|
||||
/**
|
||||
* @brief Function for encrypting 16-byte data using current key.
|
||||
*
|
||||
* This function avoids unnecessary copying of data if the parameters point to the
|
||||
* correct locations in the ECB data structure.
|
||||
*
|
||||
* @param dst Result of encryption, 16 bytes will be written.
|
||||
* @param src Source with 16-byte data to be encrypted.
|
||||
*
|
||||
* @retval true If the encryption operation completed.
|
||||
* @retval false If the encryption operation did not complete.
|
||||
*/
|
||||
bool nrf_ecb_crypt(uint8_t * dst, const uint8_t * src);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the key to be used for encryption.
|
||||
*
|
||||
* @param key Pointer to the key. 16 bytes will be read.
|
||||
*/
|
||||
void nrf_ecb_set_key(const uint8_t * key);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_ECB_H__
|
||||
|
||||
/** @} */
|
||||
367
lib/sdk/components/drivers_nrf/hal/nrf_egu.h
Normal file
367
lib/sdk/components/drivers_nrf/hal/nrf_egu.h
Normal file
@ -0,0 +1,367 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_EGU_H__
|
||||
#define NRF_EGU_H__
|
||||
|
||||
/**
|
||||
* @defgroup nrf_egu EGU (Event Generator Unit) abstraction
|
||||
* @{
|
||||
* @ingroup nrf_drivers
|
||||
* @brief @tagAPI52 EGU (Event Generator Unit) module functions.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "nrf_assert.h"
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @enum nrf_egu_task_t
|
||||
* @brief EGU tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30 -esym(628,__INTADDR__)*/
|
||||
NRF_EGU_TASK_TRIGGER0 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]), /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */
|
||||
NRF_EGU_TASK_TRIGGER1 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]), /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */
|
||||
NRF_EGU_TASK_TRIGGER2 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]), /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */
|
||||
NRF_EGU_TASK_TRIGGER3 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[3]), /**< Trigger 3 for triggering the corresponding TRIGGERED[3] event. */
|
||||
NRF_EGU_TASK_TRIGGER4 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[4]), /**< Trigger 4 for triggering the corresponding TRIGGERED[4] event. */
|
||||
NRF_EGU_TASK_TRIGGER5 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[5]), /**< Trigger 5 for triggering the corresponding TRIGGERED[5] event. */
|
||||
NRF_EGU_TASK_TRIGGER6 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[6]), /**< Trigger 6 for triggering the corresponding TRIGGERED[6] event. */
|
||||
NRF_EGU_TASK_TRIGGER7 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[7]), /**< Trigger 7 for triggering the corresponding TRIGGERED[7] event. */
|
||||
NRF_EGU_TASK_TRIGGER8 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[8]), /**< Trigger 8 for triggering the corresponding TRIGGERED[8] event. */
|
||||
NRF_EGU_TASK_TRIGGER9 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[9]), /**< Trigger 9 for triggering the corresponding TRIGGERED[9] event. */
|
||||
NRF_EGU_TASK_TRIGGER10 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[10]), /**< Trigger 10 for triggering the corresponding TRIGGERED[10] event. */
|
||||
NRF_EGU_TASK_TRIGGER11 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[11]), /**< Trigger 11 for triggering the corresponding TRIGGERED[11] event. */
|
||||
NRF_EGU_TASK_TRIGGER12 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[12]), /**< Trigger 12 for triggering the corresponding TRIGGERED[12] event. */
|
||||
NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */
|
||||
NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */
|
||||
NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15]) /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */
|
||||
/*lint -restore*/
|
||||
} nrf_egu_task_t;
|
||||
|
||||
|
||||
/**
|
||||
* @enum nrf_egu_event_t
|
||||
* @brief EGU events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30 -esym(628,__INTADDR__)*/
|
||||
NRF_EGU_EVENT_TRIGGERED0 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]), /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED1 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]), /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED2 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]), /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED3 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[3]), /**< Event number 3 generated by triggering the corresponding TRIGGER[3] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED4 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[4]), /**< Event number 4 generated by triggering the corresponding TRIGGER[4] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED5 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[5]), /**< Event number 5 generated by triggering the corresponding TRIGGER[5] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED6 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[6]), /**< Event number 6 generated by triggering the corresponding TRIGGER[6] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED7 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[7]), /**< Event number 7 generated by triggering the corresponding TRIGGER[7] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED8 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[8]), /**< Event number 8 generated by triggering the corresponding TRIGGER[8] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED9 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[9]), /**< Event number 9 generated by triggering the corresponding TRIGGER[9] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED10 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[10]), /**< Event number 10 generated by triggering the corresponding TRIGGER[10] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED11 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[11]), /**< Event number 11 generated by triggering the corresponding TRIGGER[11] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED12 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[12]), /**< Event number 12 generated by triggering the corresponding TRIGGER[12] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */
|
||||
NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15]) /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */
|
||||
/*lint -restore*/
|
||||
} nrf_egu_event_t;
|
||||
|
||||
|
||||
/**
|
||||
* @enum nrf_egu_int_mask_t
|
||||
* @brief EGU interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_EGU_INT_TRIGGERED0 = EGU_INTENSET_TRIGGERED0_Msk, /**< Interrupt on EVENTS_TRIGGERED[0] event. */
|
||||
NRF_EGU_INT_TRIGGERED1 = EGU_INTENSET_TRIGGERED1_Msk, /**< Interrupt on EVENTS_TRIGGERED[1] event. */
|
||||
NRF_EGU_INT_TRIGGERED2 = EGU_INTENSET_TRIGGERED2_Msk, /**< Interrupt on EVENTS_TRIGGERED[2] event. */
|
||||
NRF_EGU_INT_TRIGGERED3 = EGU_INTENSET_TRIGGERED3_Msk, /**< Interrupt on EVENTS_TRIGGERED[3] event. */
|
||||
NRF_EGU_INT_TRIGGERED4 = EGU_INTENSET_TRIGGERED4_Msk, /**< Interrupt on EVENTS_TRIGGERED[4] event. */
|
||||
NRF_EGU_INT_TRIGGERED5 = EGU_INTENSET_TRIGGERED5_Msk, /**< Interrupt on EVENTS_TRIGGERED[5] event. */
|
||||
NRF_EGU_INT_TRIGGERED6 = EGU_INTENSET_TRIGGERED6_Msk, /**< Interrupt on EVENTS_TRIGGERED[6] event. */
|
||||
NRF_EGU_INT_TRIGGERED7 = EGU_INTENSET_TRIGGERED7_Msk, /**< Interrupt on EVENTS_TRIGGERED[7] event. */
|
||||
NRF_EGU_INT_TRIGGERED8 = EGU_INTENSET_TRIGGERED8_Msk, /**< Interrupt on EVENTS_TRIGGERED[8] event. */
|
||||
NRF_EGU_INT_TRIGGERED9 = EGU_INTENSET_TRIGGERED9_Msk, /**< Interrupt on EVENTS_TRIGGERED[9] event. */
|
||||
NRF_EGU_INT_TRIGGERED10 = EGU_INTENSET_TRIGGERED10_Msk, /**< Interrupt on EVENTS_TRIGGERED[10] event. */
|
||||
NRF_EGU_INT_TRIGGERED11 = EGU_INTENSET_TRIGGERED11_Msk, /**< Interrupt on EVENTS_TRIGGERED[11] event. */
|
||||
NRF_EGU_INT_TRIGGERED12 = EGU_INTENSET_TRIGGERED12_Msk, /**< Interrupt on EVENTS_TRIGGERED[12] event. */
|
||||
NRF_EGU_INT_TRIGGERED13 = EGU_INTENSET_TRIGGERED13_Msk, /**< Interrupt on EVENTS_TRIGGERED[13] event. */
|
||||
NRF_EGU_INT_TRIGGERED14 = EGU_INTENSET_TRIGGERED14_Msk, /**< Interrupt on EVENTS_TRIGGERED[14] event. */
|
||||
NRF_EGU_INT_TRIGGERED15 = EGU_INTENSET_TRIGGERED15_Msk, /**< Interrupt on EVENTS_TRIGGERED[15] event. */
|
||||
NRF_EGU_INT_ALL = 0xFFFFuL
|
||||
} nrf_egu_int_mask_t;
|
||||
|
||||
/**@brief Function for getting max channel number of given EGU.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
*
|
||||
* @returns number of available channels.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx)
|
||||
{
|
||||
if (NRF_EGUx == NRF_EGU0){
|
||||
return EGU0_CH_NUM;
|
||||
}
|
||||
if (NRF_EGUx == NRF_EGU1){
|
||||
return EGU1_CH_NUM;
|
||||
}
|
||||
#if EGU_COUNT > 2
|
||||
if (NRF_EGUx == NRF_EGU2){
|
||||
return EGU2_CH_NUM;
|
||||
}
|
||||
if (NRF_EGUx == NRF_EGU3){
|
||||
return EGU3_CH_NUM;
|
||||
}
|
||||
if (NRF_EGUx == NRF_EGU4){
|
||||
return EGU4_CH_NUM;
|
||||
}
|
||||
if (NRF_EGUx == NRF_EGU5){
|
||||
return EGU5_CH_NUM;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for triggering a specific EGU task.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param egu_task EGU task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task)) = 0x1UL;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific EGU task register.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param egu_task EGU task.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx,
|
||||
nrf_egu_task_t egu_task)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific EGU TRIGGER task register.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param channel Channel number.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_egu_task_trigger_address_get(NRF_EGU_Type * NRF_EGUx,
|
||||
uint8_t channel)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
|
||||
return (uint32_t*)&NRF_EGUx->TASKS_TRIGGER[channel];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the specific EGU TRIGGER task.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param channel Channel number.
|
||||
*/
|
||||
__STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
|
||||
return (nrf_egu_task_t)((uint32_t) NRF_EGU_TASK_TRIGGER0 + (channel * sizeof(uint32_t)));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the state of a specific EGU event.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param egu_event EGU event to check.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx,
|
||||
nrf_egu_event_t egu_event)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific EGU event.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param egu_event EGU event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx,
|
||||
nrf_egu_event_t egu_event)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific EGU event register.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param egu_event EGU event.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx,
|
||||
nrf_egu_event_t egu_event)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific EGU TRIGGERED event register.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param channel Channel number.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_egu_event_triggered_address_get(NRF_EGU_Type * NRF_EGUx,
|
||||
uint8_t channel)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
|
||||
return (uint32_t*)&NRF_EGUx->EVENTS_TRIGGERED[channel];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the specific EGU TRIGGERED event.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param channel Channel number.
|
||||
*/
|
||||
__STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx,
|
||||
uint8_t channel)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
|
||||
return (nrf_egu_event_t)((uint32_t) NRF_EGU_EVENT_TRIGGERED0 + (channel * sizeof(uint32_t)));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling one or more specific EGU interrupts.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param egu_int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
NRF_EGUx->INTENSET = egu_int_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of one or more EGU interrupts.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param egu_int_mask Interrupts to check.
|
||||
*
|
||||
* @retval true If all of the specified interrupts are enabled.
|
||||
* @retval false If at least one of the specified interrupts is disabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
return (bool)(NRF_EGUx->INTENSET & egu_int_mask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling one or more specific EGU interrupts.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param egu_int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
NRF_EGUx->INTENCLR = egu_int_mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving one or more specific EGU interrupts.
|
||||
*
|
||||
* @param NRF_EGUx EGU instance.
|
||||
* @param channel Channel number.
|
||||
*
|
||||
* @returns EGU interrupt mask.
|
||||
*/
|
||||
__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel)
|
||||
{
|
||||
ASSERT(NRF_EGUx);
|
||||
ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
|
||||
return (nrf_egu_int_mask_t)((uint32_t) (EGU_INTENSET_TRIGGERED0_Msk << channel));
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
795
lib/sdk/components/drivers_nrf/hal/nrf_gpio.h
Normal file
795
lib/sdk/components/drivers_nrf/hal/nrf_gpio.h
Normal file
@ -0,0 +1,795 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_GPIO_H__
|
||||
#define NRF_GPIO_H__
|
||||
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
#include "nrf_assert.h"
|
||||
#include <stdbool.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup nrf_gpio GPIO abstraction
|
||||
* @{
|
||||
* @ingroup nrf_drivers
|
||||
* @brief GPIO pin abstraction and port abstraction for reading and writing byte-wise to GPIO ports.
|
||||
*/
|
||||
|
||||
#if (GPIO_COUNT == 1)
|
||||
#define NUMBER_OF_PINS (P0_PIN_NUM)
|
||||
#define GPIO_REG_LIST {NRF_GPIO}
|
||||
#elif (GPIO_COUNT == 2)
|
||||
#define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM)
|
||||
#define GPIO_REG_LIST {NRF_P0, NRF_P1}
|
||||
#else
|
||||
#error "Not supported."
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions.
|
||||
*/
|
||||
#define NRF_GPIO_PIN_MAP(port, pin) ((port << 5) | (pin & 0x1F))
|
||||
|
||||
/**
|
||||
* @brief Pin direction definitions.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input.
|
||||
NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
|
||||
} nrf_gpio_pin_dir_t;
|
||||
|
||||
/**
|
||||
* @brief Connection of input buffer.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer.
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer.
|
||||
} nrf_gpio_pin_input_t;
|
||||
|
||||
/**
|
||||
* @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled.
|
||||
NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled.
|
||||
NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled.
|
||||
} nrf_gpio_pin_pull_t;
|
||||
|
||||
/**
|
||||
* @brief Enumerator used for selecting output drive mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'.
|
||||
NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'.
|
||||
NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'.
|
||||
NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'.
|
||||
NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'.
|
||||
NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'.
|
||||
NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'.
|
||||
NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'.
|
||||
} nrf_gpio_pin_drive_t;
|
||||
|
||||
/**
|
||||
* @brief Enumerator used for selecting the pin to sense high or low level on the pin input.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
|
||||
NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level.
|
||||
NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
|
||||
} nrf_gpio_pin_sense_t;
|
||||
|
||||
|
||||
#if (__LINT__ != 1)
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
|
||||
* This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
|
||||
*
|
||||
* @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
|
||||
*
|
||||
* @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
|
||||
*
|
||||
* @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
|
||||
* Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
|
||||
* This function can be used to configure pin range as simple input.
|
||||
*
|
||||
* @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
|
||||
*
|
||||
* @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
|
||||
*
|
||||
* @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
|
||||
*
|
||||
* @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
|
||||
* Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
|
||||
uint32_t pin_range_end,
|
||||
nrf_gpio_pin_pull_t pull_config);
|
||||
|
||||
/**
|
||||
* @brief Pin configuration function.
|
||||
*
|
||||
* The main pin configuration function.
|
||||
* This function allows to set any aspect in PIN_CNF register.
|
||||
* @param pin_number Specifies the pin number.
|
||||
* @param dir Pin direction.
|
||||
* @param input Connect or disconnect the input buffer.
|
||||
* @param pull Pull configuration.
|
||||
* @param drive Drive configuration.
|
||||
* @param sense Pin sensing mechanism.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_cfg(
|
||||
uint32_t pin_number,
|
||||
nrf_gpio_pin_dir_t dir,
|
||||
nrf_gpio_pin_input_t input,
|
||||
nrf_gpio_pin_pull_t pull,
|
||||
nrf_gpio_pin_drive_t drive,
|
||||
nrf_gpio_pin_sense_t sense);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the given GPIO pin number as output, hiding inner details.
|
||||
* This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
|
||||
*
|
||||
* @param pin_number Specifies the pin number.
|
||||
*
|
||||
* @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the given GPIO pin number as input, hiding inner details.
|
||||
* This function can be used to configure a pin as simple input.
|
||||
*
|
||||
* @param pin_number Specifies the pin number.
|
||||
* @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
|
||||
*
|
||||
* @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
|
||||
|
||||
/**
|
||||
* @brief Function for resetting pin configuration to its default state.
|
||||
*
|
||||
* @param pin_number Specifies the pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
|
||||
*
|
||||
* @param pin_number Specifies the pin number.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for disconnecting input for the given GPIO.
|
||||
*
|
||||
* @param pin_number Specifies the pin number.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the given GPIO pin number as input, hiding inner details.
|
||||
* This function can be used to configure pin range as simple input.
|
||||
* Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable.
|
||||
*
|
||||
* @param pin_number Specifies the pin number.
|
||||
* @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high).
|
||||
* @param sense_config Sense level of the pin (no sense, sense low, or sense high).
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
|
||||
nrf_gpio_pin_pull_t pull_config,
|
||||
nrf_gpio_pin_sense_t sense_config);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring sense level for the given GPIO.
|
||||
*
|
||||
* @param pin_number Specifies the pin number.
|
||||
* @param sense_config Sense configuration.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the direction for a GPIO pin.
|
||||
*
|
||||
* @param pin_number Specifies the pin number for which to set the direction.
|
||||
*
|
||||
* @param direction Specifies the direction.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
|
||||
|
||||
/**
|
||||
* @brief Function for setting a GPIO pin.
|
||||
*
|
||||
* Note that the pin must be configured as an output for this function to have any effect.
|
||||
*
|
||||
* @param pin_number Specifies the pin number to set.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a GPIO pin.
|
||||
*
|
||||
* Note that the pin must be configured as an output for this
|
||||
* function to have any effect.
|
||||
*
|
||||
* @param pin_number Specifies the pin number to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for toggling a GPIO pin.
|
||||
*
|
||||
* Note that the pin must be configured as an output for this
|
||||
* function to have any effect.
|
||||
*
|
||||
* @param pin_number Specifies the pin number to toggle.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for writing a value to a GPIO pin.
|
||||
*
|
||||
* Note that the pin must be configured as an output for this
|
||||
* function to have any effect.
|
||||
*
|
||||
* @param pin_number Specifies the pin number to write.
|
||||
*
|
||||
* @param value Specifies the value to be written to the pin.
|
||||
* @arg 0 Clears the pin.
|
||||
* @arg >=1 Sets the pin.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
|
||||
|
||||
/**
|
||||
* @brief Function for reading the input level of a GPIO pin.
|
||||
*
|
||||
* Note that the pin must have input connected for the value
|
||||
* returned from this function to be valid.
|
||||
*
|
||||
* @param pin_number Specifies the pin number to read.
|
||||
*
|
||||
* @return 0 if the pin input level is low. Positive value if the pin is high.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for reading the output level of a GPIO pin.
|
||||
*
|
||||
* @param pin_number Specifies the pin number to read.
|
||||
*
|
||||
* @return 0 if the pin output level is low. Positive value if pin output is high.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for reading the sense configuration of a GPIO pin.
|
||||
*
|
||||
* @param pin_number Specifies the pin number to read.
|
||||
*
|
||||
* @retval Sense configuration.
|
||||
*/
|
||||
__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for setting output direction on selected pins on a given port.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param out_mask Mask specifying the pins to set as output.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for setting input direction on selected pins on a given port.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param in_mask Mask specifying the pins to set as input.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for writing the direction configuration of GPIO pins in a given port.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param dir_mask Mask specifying the direction of pins. Bit set means that the given pin is configured as output.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for reading the direction configuration of a GPIO port.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @retval Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for reading the input signals of GPIO pins on a given port.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @retval Port input values.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for reading the output signals of GPIO pins of a given port.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @retval Port output values.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for writing the GPIO pins output on a given port.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param value Output port mask.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
|
||||
|
||||
/**
|
||||
* @brief Function for setting high level on selected GPIO pins of a given port.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param set_mask Mask with pins to set as logical high level.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for setting low level on selected GPIO pins of a given port.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param clr_mask Mask with pins to set as logical low level.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for reading pins state of multiple consecutive ports.
|
||||
*
|
||||
* @param start_port Index of the first port to read.
|
||||
* @param length Number of ports to read.
|
||||
* @param p_masks Pointer to output array where port states will be stored.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks);
|
||||
|
||||
#ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT
|
||||
/**
|
||||
* @brief Function for reading latch state of multiple consecutive ports.
|
||||
*
|
||||
* @param start_port Index of the first port to read.
|
||||
* @param length Number of ports to read.
|
||||
* @param p_masks Pointer to output array where latch states will be stored.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length,
|
||||
uint32_t * p_masks);
|
||||
|
||||
/**
|
||||
* @brief Function for reading latch state of single pin.
|
||||
*
|
||||
* @param pin_number Pin number.
|
||||
* @return 0 if latch is not set. Positive value otherwise.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing latch state of a single pin.
|
||||
*
|
||||
* @param pin_number Pin number.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
|
||||
#endif
|
||||
|
||||
|
||||
#endif // #ifndef (__LINT__ != 1)
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
/**
|
||||
* @brief Function for extracting port and relative pin number from absolute pin number.
|
||||
*
|
||||
* @param[inout] Pointer to absolute pin number which is overriden by relative to port pin number.
|
||||
*
|
||||
* @return Pointer to port register set.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
|
||||
{
|
||||
ASSERT(*p_pin < NUMBER_OF_PINS);
|
||||
#if (GPIO_COUNT == 1)
|
||||
// The oldest definition case
|
||||
return NRF_GPIO;
|
||||
#else
|
||||
if (*p_pin < P0_PIN_NUM)
|
||||
{
|
||||
return NRF_P0;
|
||||
}
|
||||
else
|
||||
{
|
||||
*p_pin = *p_pin & (P0_PIN_NUM - 1);
|
||||
return NRF_P1;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
|
||||
{
|
||||
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
|
||||
for (; pin_range_start <= pin_range_end; pin_range_start++)
|
||||
{
|
||||
nrf_gpio_cfg_output(pin_range_start);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
|
||||
uint32_t pin_range_end,
|
||||
nrf_gpio_pin_pull_t pull_config)
|
||||
{
|
||||
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
|
||||
for (; pin_range_start <= pin_range_end; pin_range_start++)
|
||||
{
|
||||
nrf_gpio_cfg_input(pin_range_start, pull_config);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_cfg(
|
||||
uint32_t pin_number,
|
||||
nrf_gpio_pin_dir_t dir,
|
||||
nrf_gpio_pin_input_t input,
|
||||
nrf_gpio_pin_pull_t pull,
|
||||
nrf_gpio_pin_drive_t drive,
|
||||
nrf_gpio_pin_sense_t sense)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
|
||||
reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
|
||||
| ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)
|
||||
| ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
|
||||
{
|
||||
nrf_gpio_cfg(
|
||||
pin_number,
|
||||
NRF_GPIO_PIN_DIR_OUTPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT,
|
||||
NRF_GPIO_PIN_NOPULL,
|
||||
NRF_GPIO_PIN_S0S1,
|
||||
NRF_GPIO_PIN_NOSENSE);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
|
||||
{
|
||||
nrf_gpio_cfg(
|
||||
pin_number,
|
||||
NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_CONNECT,
|
||||
pull_config,
|
||||
NRF_GPIO_PIN_S0S1,
|
||||
NRF_GPIO_PIN_NOSENSE);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
|
||||
{
|
||||
nrf_gpio_cfg(
|
||||
pin_number,
|
||||
NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT,
|
||||
NRF_GPIO_PIN_NOPULL,
|
||||
NRF_GPIO_PIN_S0S1,
|
||||
NRF_GPIO_PIN_NOSENSE);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
|
||||
uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
|
||||
|
||||
reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
|
||||
uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
|
||||
|
||||
reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
|
||||
nrf_gpio_pin_pull_t pull_config,
|
||||
nrf_gpio_pin_sense_t sense_config)
|
||||
{
|
||||
nrf_gpio_cfg(
|
||||
pin_number,
|
||||
NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_CONNECT,
|
||||
pull_config,
|
||||
NRF_GPIO_PIN_S0S1,
|
||||
sense_config);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
|
||||
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
|
||||
reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk;
|
||||
reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
|
||||
{
|
||||
if (direction == NRF_GPIO_PIN_DIR_INPUT)
|
||||
{
|
||||
nrf_gpio_cfg(
|
||||
pin_number,
|
||||
NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_CONNECT,
|
||||
NRF_GPIO_PIN_NOPULL,
|
||||
NRF_GPIO_PIN_S0S1,
|
||||
NRF_GPIO_PIN_NOSENSE);
|
||||
}
|
||||
else
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
reg->DIRSET = (1UL << pin_number);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
|
||||
nrf_gpio_port_out_set(reg, 1UL << pin_number);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
|
||||
nrf_gpio_port_out_clear(reg, 1UL << pin_number);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
uint32_t pins_state = reg->OUT;
|
||||
|
||||
reg->OUTSET = (~pins_state & (1UL << pin_number));
|
||||
reg->OUTCLR = (pins_state & (1UL << pin_number));
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
|
||||
{
|
||||
if (value == 0)
|
||||
{
|
||||
nrf_gpio_pin_clear(pin_number);
|
||||
}
|
||||
else
|
||||
{
|
||||
nrf_gpio_pin_set(pin_number);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
|
||||
return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
|
||||
return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
|
||||
return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
|
||||
GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
|
||||
{
|
||||
p_reg->DIRSET = out_mask;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask)
|
||||
{
|
||||
p_reg->DIRCLR = in_mask;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value)
|
||||
{
|
||||
p_reg->DIR = value;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)
|
||||
{
|
||||
return p_reg->DIR;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)
|
||||
{
|
||||
return p_reg->IN;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)
|
||||
{
|
||||
return p_reg->OUT;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value)
|
||||
{
|
||||
p_reg->OUT = value;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
|
||||
{
|
||||
p_reg->OUTSET = set_mask;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask)
|
||||
{
|
||||
p_reg->OUTCLR = clr_mask;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks)
|
||||
{
|
||||
NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
|
||||
|
||||
ASSERT(start_port + length <= GPIO_COUNT);
|
||||
uint32_t i;
|
||||
|
||||
for (i = start_port; i < (start_port + length); i++)
|
||||
{
|
||||
*p_masks = nrf_gpio_port_in_read(gpio_regs[i]);
|
||||
p_masks++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT
|
||||
__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, uint32_t * p_masks)
|
||||
{
|
||||
NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
|
||||
uint32_t i;
|
||||
|
||||
for (i = start_port; i < (start_port + length); i++)
|
||||
{
|
||||
*p_masks = gpio_regs[i]->LATCH;
|
||||
p_masks++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
|
||||
return (reg->LATCH & (1 << pin_number)) ? 1 : 0;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
|
||||
{
|
||||
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
|
||||
|
||||
reg->LATCH = (1 << pin_number);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
430
lib/sdk/components/drivers_nrf/hal/nrf_gpiote.h
Normal file
430
lib/sdk/components/drivers_nrf/hal/nrf_gpiote.h
Normal file
@ -0,0 +1,430 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_GPIOTE_H__
|
||||
#define NRF_GPIOTE_H__
|
||||
|
||||
#include "nrf_peripherals.h"
|
||||
#include "nrf.h"
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef GPIOTE_CONFIG_PORT_Msk
|
||||
#define GPIOTE_CONFIG_PORT_PIN_Msk (GPIOTE_CONFIG_PORT_Msk | GPIOTE_CONFIG_PSEL_Msk)
|
||||
#else
|
||||
#define GPIOTE_CONFIG_PORT_PIN_Msk GPIOTE_CONFIG_PSEL_Msk
|
||||
#endif
|
||||
/**
|
||||
* @defgroup nrf_gpiote_abs GPIOTE abstraction
|
||||
* @{
|
||||
* @ingroup nrf_gpiote
|
||||
* @brief GPIOTE abstraction for configuration of channels.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @enum nrf_gpiote_polarity_t
|
||||
* @brief Polarity for the GPIOTE channel.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high.
|
||||
NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low.
|
||||
NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle ///< Toggle.
|
||||
} nrf_gpiote_polarity_t;
|
||||
|
||||
|
||||
/**
|
||||
* @enum nrf_gpiote_outinit_t
|
||||
* @brief Initial output value for the GPIOTE channel.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high.
|
||||
NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High ///< High to low.
|
||||
} nrf_gpiote_outinit_t;
|
||||
|
||||
/**
|
||||
* @brief Tasks.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_GPIOTE_TASKS_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/
|
||||
NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/
|
||||
NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/
|
||||
NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/
|
||||
#if (GPIOTE_CH_NUM > 4) || defined(__SDK_DOXYGEN__)
|
||||
NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/
|
||||
NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/
|
||||
NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/
|
||||
NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/
|
||||
#endif
|
||||
#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__SDK_DOXYGEN__)
|
||||
NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/
|
||||
NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/
|
||||
NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/
|
||||
NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/
|
||||
NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/
|
||||
NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/
|
||||
NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/
|
||||
NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/
|
||||
#endif
|
||||
#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__SDK_DOXYGEN__)
|
||||
NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/
|
||||
NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/
|
||||
NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/
|
||||
NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/
|
||||
NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/
|
||||
NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/
|
||||
NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/
|
||||
NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/
|
||||
#endif
|
||||
/*lint -restore*/
|
||||
} nrf_gpiote_tasks_t;
|
||||
|
||||
/**
|
||||
* @brief Events.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_GPIOTE_EVENTS_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/
|
||||
NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/
|
||||
NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/
|
||||
NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/
|
||||
#if (GPIOTE_CH_NUM > 4) || defined(__SDK_DOXYGEN__)
|
||||
NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/
|
||||
NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/
|
||||
NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/
|
||||
NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/
|
||||
#endif
|
||||
NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event.*/
|
||||
/*lint -restore*/
|
||||
} nrf_gpiote_events_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_gpiote_int_t
|
||||
* @brief GPIOTE interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_GPIOTE_INT_IN0_MASK = GPIOTE_INTENSET_IN0_Msk, /**< GPIOTE interrupt from IN0. */
|
||||
NRF_GPIOTE_INT_IN1_MASK = GPIOTE_INTENSET_IN1_Msk, /**< GPIOTE interrupt from IN1. */
|
||||
NRF_GPIOTE_INT_IN2_MASK = GPIOTE_INTENSET_IN2_Msk, /**< GPIOTE interrupt from IN2. */
|
||||
NRF_GPIOTE_INT_IN3_MASK = GPIOTE_INTENSET_IN3_Msk, /**< GPIOTE interrupt from IN3. */
|
||||
#if (GPIOTE_CH_NUM > 4) || defined(__SDK_DOXYGEN__)
|
||||
NRF_GPIOTE_INT_IN4_MASK = GPIOTE_INTENSET_IN4_Msk, /**< GPIOTE interrupt from IN4. */
|
||||
NRF_GPIOTE_INT_IN5_MASK = GPIOTE_INTENSET_IN5_Msk, /**< GPIOTE interrupt from IN5. */
|
||||
NRF_GPIOTE_INT_IN6_MASK = GPIOTE_INTENSET_IN6_Msk, /**< GPIOTE interrupt from IN6. */
|
||||
NRF_GPIOTE_INT_IN7_MASK = GPIOTE_INTENSET_IN7_Msk, /**< GPIOTE interrupt from IN7. */
|
||||
#endif
|
||||
NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */
|
||||
} nrf_gpiote_int_t;
|
||||
|
||||
#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
|
||||
NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK)
|
||||
#if (GPIOTE_CH_NUM > 4)
|
||||
#undef NRF_GPIOTE_INT_IN_MASK
|
||||
#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
|
||||
NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\
|
||||
NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\
|
||||
NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific GPIOTE task.
|
||||
*
|
||||
* @param[in] task Task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific GPIOTE task.
|
||||
*
|
||||
* @param[in] task Task.
|
||||
*
|
||||
* @returns Address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the state of a specific GPIOTE event.
|
||||
*
|
||||
* @param[in] event Event.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific GPIOTE event.
|
||||
*
|
||||
* @param[in] event Event.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific GPIOTE event.
|
||||
*
|
||||
* @param[in] event Event.
|
||||
*
|
||||
* @return Address
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event);
|
||||
|
||||
/**@brief Function for enabling interrupts.
|
||||
*
|
||||
* @param[in] mask Interrupt mask to be enabled.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask);
|
||||
|
||||
/**@brief Function for disabling interrupts.
|
||||
*
|
||||
* @param[in] mask Interrupt mask to be disabled.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask);
|
||||
|
||||
/**@brief Function for checking if interrupts are enabled.
|
||||
*
|
||||
* @param[in] mask Mask of interrupt flags to check.
|
||||
*
|
||||
* @return Mask with enabled interrupts.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask);
|
||||
|
||||
/**@brief Function for enabling a GPIOTE event.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx);
|
||||
|
||||
/**@brief Function for disabling a GPIOTE event.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx);
|
||||
|
||||
/**@brief Function for configuring a GPIOTE event.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
* @param[in] pin Pin associated with event.
|
||||
* @param[in] polarity Transition that should generate an event.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin,
|
||||
nrf_gpiote_polarity_t polarity);
|
||||
|
||||
/**@brief Function for getting the pin associated with a GPIOTE event.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
*
|
||||
* @return Pin number.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx);
|
||||
|
||||
/**@brief Function for getting the polarity associated with a GPIOTE event.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
*
|
||||
* @return Polarity.
|
||||
*/
|
||||
__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx);
|
||||
|
||||
/**@brief Function for enabling a GPIOTE task.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx);
|
||||
|
||||
/**@brief Function for disabling a GPIOTE task.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx);
|
||||
|
||||
/**@brief Function for configuring a GPIOTE task.
|
||||
* @note Function is not configuring mode field so task is disabled after this function is called.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
* @param[in] pin Pin associated with event.
|
||||
* @param[in] polarity Transition that should generate an event.
|
||||
* @param[in] init_val Initial value of the pin.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
|
||||
nrf_gpiote_polarity_t polarity,
|
||||
nrf_gpiote_outinit_t init_val);
|
||||
|
||||
/**@brief Function for forcing a specific state on the pin connected to GPIOTE.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
* @param[in] init_val Pin state.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val);
|
||||
|
||||
/**@brief Function for resetting a GPIOTE task event configuration to the default state.
|
||||
*
|
||||
* @param[in] idx Task-Event index.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx);
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task)
|
||||
{
|
||||
*(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task)
|
||||
{
|
||||
return ((uint32_t)NRF_GPIOTE + task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event)
|
||||
{
|
||||
return (*(uint32_t *)nrf_gpiote_event_addr_get(event) == 0x1UL) ? true : false;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event)
|
||||
{
|
||||
*(uint32_t *)nrf_gpiote_event_addr_get(event) = 0;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_addr_get(event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event)
|
||||
{
|
||||
return ((uint32_t)NRF_GPIOTE + event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask)
|
||||
{
|
||||
NRF_GPIOTE->INTENSET = mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask)
|
||||
{
|
||||
NRF_GPIOTE->INTENCLR = mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask)
|
||||
{
|
||||
return (NRF_GPIOTE->INTENSET & mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx)
|
||||
{
|
||||
NRF_GPIOTE->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx)
|
||||
{
|
||||
NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, nrf_gpiote_polarity_t polarity)
|
||||
{
|
||||
NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
|
||||
NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
|
||||
((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx)
|
||||
{
|
||||
return ((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx)
|
||||
{
|
||||
return (nrf_gpiote_polarity_t)((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx)
|
||||
{
|
||||
uint32_t final_config = NRF_GPIOTE->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task;
|
||||
#ifdef NRF51
|
||||
/* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
|
||||
on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
|
||||
correct state in GPIOTE but not in the OUT register. */
|
||||
/* Configure channel to not existing, not connected to the pin, and configure as a tasks that will set it to proper level */
|
||||
NRF_GPIOTE->CONFIG[idx] = final_config | (((31) << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk);
|
||||
__NOP();
|
||||
__NOP();
|
||||
__NOP();
|
||||
#endif
|
||||
NRF_GPIOTE->CONFIG[idx] = final_config;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx)
|
||||
{
|
||||
NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
|
||||
nrf_gpiote_polarity_t polarity,
|
||||
nrf_gpiote_outinit_t init_val)
|
||||
{
|
||||
NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
|
||||
GPIOTE_CONFIG_POLARITY_Msk |
|
||||
GPIOTE_CONFIG_OUTINIT_Msk);
|
||||
|
||||
NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
|
||||
((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
|
||||
((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val)
|
||||
{
|
||||
NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk)
|
||||
| ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx)
|
||||
{
|
||||
NRF_GPIOTE->CONFIG[idx] = 0;
|
||||
}
|
||||
#endif //SUPPRESS_INLINE_IMPLEMENTATION
|
||||
/** @} */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
563
lib/sdk/components/drivers_nrf/hal/nrf_i2s.h
Normal file
563
lib/sdk/components/drivers_nrf/hal/nrf_i2s.h
Normal file
@ -0,0 +1,563 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @defgroup nrf_i2s_hal I2S HAL
|
||||
* @{
|
||||
* @ingroup nrf_i2s
|
||||
*
|
||||
* @brief @tagAPI52 Hardware access layer for managing the Inter-IC Sound (I2S) peripheral.
|
||||
*/
|
||||
|
||||
#ifndef NRF_I2S_H__
|
||||
#define NRF_I2S_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set
|
||||
* function call to specify that a given I2S signal (SDOUT, SDIN, or MCK)
|
||||
* shall not be connected to a physical pin.
|
||||
*/
|
||||
#define NRF_I2S_PIN_NOT_CONNECTED 0xFFFFFFFF
|
||||
|
||||
|
||||
/**
|
||||
* @brief I2S tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled.
|
||||
NRF_I2S_TASK_STOP = offsetof(NRF_I2S_Type, TASKS_STOP) ///< Stops I2S transfer. Also stops the MCK generator.
|
||||
/*lint -restore*/
|
||||
} nrf_i2s_task_t;
|
||||
|
||||
/**
|
||||
* @brief I2S events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double-buffers.
|
||||
NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double-buffers.
|
||||
NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED) ///< I2S transfer stopped.
|
||||
/*lint -restore*/
|
||||
} nrf_i2s_event_t;
|
||||
|
||||
/**
|
||||
* @brief I2S interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
|
||||
NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event.
|
||||
NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk ///< Interrupt on STOPPED event.
|
||||
} nrf_i2s_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief I2S modes of operation.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode.
|
||||
NRF_I2S_MODE_SLAVE = I2S_CONFIG_MODE_MODE_Slave ///< Slave mode.
|
||||
} nrf_i2s_mode_t;
|
||||
|
||||
/**
|
||||
* @brief I2S master clock generator settings.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_I2S_MCK_DISABLED = 0, ///< MCK disabled.
|
||||
// [conversion to 'int' needed to prevent compilers from complaining
|
||||
// that the provided value (0x80000000UL) is out of range of "int"]
|
||||
NRF_I2S_MCK_32MDIV2 = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz.
|
||||
NRF_I2S_MCK_32MDIV3 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3, ///< 32 MHz / 3 = 10.6666667 MHz.
|
||||
NRF_I2S_MCK_32MDIV4 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4, ///< 32 MHz / 4 = 8.0 MHz.
|
||||
NRF_I2S_MCK_32MDIV5 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5, ///< 32 MHz / 5 = 6.4 MHz.
|
||||
NRF_I2S_MCK_32MDIV6 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6, ///< 32 MHz / 6 = 5.3333333 MHz.
|
||||
NRF_I2S_MCK_32MDIV8 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, ///< 32 MHz / 8 = 4.0 MHz.
|
||||
NRF_I2S_MCK_32MDIV10 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, ///< 32 MHz / 10 = 3.2 MHz.
|
||||
NRF_I2S_MCK_32MDIV11 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11, ///< 32 MHz / 11 = 2.9090909 MHz.
|
||||
NRF_I2S_MCK_32MDIV15 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15, ///< 32 MHz / 15 = 2.1333333 MHz.
|
||||
NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz.
|
||||
NRF_I2S_MCK_32MDIV21 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21, ///< 32 MHz / 21 = 1.5238095 MHz.
|
||||
NRF_I2S_MCK_32MDIV23 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23, ///< 32 MHz / 23 = 1.3913043 MHz.
|
||||
NRF_I2S_MCK_32MDIV31 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31, ///< 32 MHz / 31 = 1.0322581 MHz.
|
||||
NRF_I2S_MCK_32MDIV42 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42, ///< 32 MHz / 42 = 0.7619048 MHz.
|
||||
NRF_I2S_MCK_32MDIV63 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63, ///< 32 MHz / 63 = 0.5079365 MHz.
|
||||
NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 ///< 32 MHz / 125 = 0.256 MHz.
|
||||
} nrf_i2s_mck_t;
|
||||
|
||||
/**
|
||||
* @brief I2S MCK/LRCK ratios.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_I2S_RATIO_32X = I2S_CONFIG_RATIO_RATIO_32X, ///< LRCK = MCK / 32.
|
||||
NRF_I2S_RATIO_48X = I2S_CONFIG_RATIO_RATIO_48X, ///< LRCK = MCK / 48.
|
||||
NRF_I2S_RATIO_64X = I2S_CONFIG_RATIO_RATIO_64X, ///< LRCK = MCK / 64.
|
||||
NRF_I2S_RATIO_96X = I2S_CONFIG_RATIO_RATIO_96X, ///< LRCK = MCK / 96.
|
||||
NRF_I2S_RATIO_128X = I2S_CONFIG_RATIO_RATIO_128X, ///< LRCK = MCK / 128.
|
||||
NRF_I2S_RATIO_192X = I2S_CONFIG_RATIO_RATIO_192X, ///< LRCK = MCK / 192.
|
||||
NRF_I2S_RATIO_256X = I2S_CONFIG_RATIO_RATIO_256X, ///< LRCK = MCK / 256.
|
||||
NRF_I2S_RATIO_384X = I2S_CONFIG_RATIO_RATIO_384X, ///< LRCK = MCK / 384.
|
||||
NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X ///< LRCK = MCK / 512.
|
||||
} nrf_i2s_ratio_t;
|
||||
|
||||
/**
|
||||
* @brief I2S sample widths.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit.
|
||||
NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
|
||||
NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit ///< 24 bit.
|
||||
} nrf_i2s_swidth_t;
|
||||
|
||||
/**
|
||||
* @brief I2S alignments of sample within a frame.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_I2S_ALIGN_LEFT = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned.
|
||||
NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned.
|
||||
} nrf_i2s_align_t;
|
||||
|
||||
/**
|
||||
* @brief I2S frame formats.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_I2S_FORMAT_I2S = I2S_CONFIG_FORMAT_FORMAT_I2S, ///< Original I2S format.
|
||||
NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left- or right-aligned) format.
|
||||
} nrf_i2s_format_t;
|
||||
|
||||
/**
|
||||
* @brief I2S enabled channels.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo.
|
||||
NRF_I2S_CHANNELS_LEFT = I2S_CONFIG_CHANNELS_CHANNELS_Left, ///< Left only.
|
||||
NRF_I2S_CHANNELS_RIGHT = I2S_CONFIG_CHANNELS_CHANNELS_Right ///< Right only.
|
||||
} nrf_i2s_channels_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific I2S task.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] task Task to activate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s,
|
||||
nrf_i2s_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific I2S task register.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] task Requested task.
|
||||
*
|
||||
* @return Address of the specified task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s,
|
||||
nrf_i2s_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific I2S event.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s,
|
||||
nrf_i2s_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific I2S event.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] event Event to check.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s,
|
||||
nrf_i2s_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific I2S event register.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] event Requested event.
|
||||
*
|
||||
* @return Address of the specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s,
|
||||
nrf_i2s_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] i2s_int Interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s,
|
||||
nrf_i2s_int_mask_t i2s_int);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the I2S peripheral.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the I2S peripheral.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring I2S pins.
|
||||
*
|
||||
* Usage of the SDOUT, SDIN, and MCK signals is optional.
|
||||
* If a given signal is not needed, pass the @ref NRF_I2S_PIN_NOT_CONNECTED
|
||||
* value instead of its pin number.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] sck_pin SCK pin number.
|
||||
* @param[in] lrck_pin LRCK pin number.
|
||||
* @param[in] mck_pin MCK pin number.
|
||||
* @param[in] sdout_pin SDOUT pin number.
|
||||
* @param[in] sdin_pin SDIN pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s,
|
||||
uint32_t sck_pin,
|
||||
uint32_t lrck_pin,
|
||||
uint32_t mck_pin,
|
||||
uint32_t sdout_pin,
|
||||
uint32_t sdin_pin);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the I2S peripheral configuration.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] mode Mode of operation (master or slave).
|
||||
* @param[in] format I2S frame format.
|
||||
* @param[in] alignment Alignment of sample within a frame.
|
||||
* @param[in] sample_width Sample width.
|
||||
* @param[in] channels Enabled channels.
|
||||
* @param[in] mck_setup Master clock generator setup.
|
||||
* @param[in] ratio MCK/LRCK ratio.
|
||||
*
|
||||
* @retval true If the configuration has been set successfully.
|
||||
* @retval false If the requested configuration is not allowed.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s,
|
||||
nrf_i2s_mode_t mode,
|
||||
nrf_i2s_format_t format,
|
||||
nrf_i2s_align_t alignment,
|
||||
nrf_i2s_swidth_t sample_width,
|
||||
nrf_i2s_channels_t channels,
|
||||
nrf_i2s_mck_t mck_setup,
|
||||
nrf_i2s_ratio_t ratio);
|
||||
|
||||
/**
|
||||
* @brief Function for setting up the I2S transfer.
|
||||
*
|
||||
* This function sets up the RX and TX buffers and enables reception and/or
|
||||
* transmission accordingly. If the transfer in a given direction is not
|
||||
* required, pass NULL instead of the pointer to the corresponding buffer.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] size Size of the buffers (in 32-bit words).
|
||||
* @param[in] p_rx_buffer Pointer to the receive buffer.
|
||||
* Pass NULL to disable reception.
|
||||
* @param[in] p_tx_buffer Pointer to the transmit buffer.
|
||||
* Pass NULL to disable transmission.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s,
|
||||
uint16_t size,
|
||||
uint32_t * p_rx_buffer,
|
||||
uint32_t const * p_tx_buffer);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the pointer to the receive buffer.
|
||||
*
|
||||
* @note The size of the buffer can be set only by calling
|
||||
* @ref nrf_i2s_transfer_set.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] p_buffer Pointer to the receive buffer.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s,
|
||||
uint32_t * p_buffer);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the pointer to the receive buffer.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
*
|
||||
* @return Pointer to the receive buffer.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the pointer to the transmit buffer.
|
||||
*
|
||||
* @note The size of the buffer can be set only by calling
|
||||
* @ref nrf_i2s_transfer_set.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
* @param[in] p_buffer Pointer to the transmit buffer.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s,
|
||||
uint32_t const * p_buffer);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the pointer to the transmit buffer.
|
||||
*
|
||||
* @param[in] p_i2s I2S instance.
|
||||
*
|
||||
* @return Pointer to the transmit buffer.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s);
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s,
|
||||
nrf_i2s_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s,
|
||||
nrf_i2s_task_t task)
|
||||
{
|
||||
return ((uint32_t)p_i2s + (uint32_t)task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s,
|
||||
nrf_i2s_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s,
|
||||
nrf_i2s_event_t event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s,
|
||||
nrf_i2s_event_t event)
|
||||
{
|
||||
return ((uint32_t)p_i2s + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask)
|
||||
{
|
||||
p_i2s->INTENSET = mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask)
|
||||
{
|
||||
p_i2s->INTENCLR = mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s,
|
||||
nrf_i2s_int_mask_t i2s_int)
|
||||
{
|
||||
return (bool)(p_i2s->INTENSET & i2s_int);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s)
|
||||
{
|
||||
p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Enabled << I2S_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s)
|
||||
{
|
||||
p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Disabled << I2S_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s,
|
||||
uint32_t sck_pin,
|
||||
uint32_t lrck_pin,
|
||||
uint32_t mck_pin,
|
||||
uint32_t sdout_pin,
|
||||
uint32_t sdin_pin)
|
||||
{
|
||||
p_i2s->PSEL.SCK = sck_pin;
|
||||
p_i2s->PSEL.LRCK = lrck_pin;
|
||||
p_i2s->PSEL.MCK = mck_pin;
|
||||
p_i2s->PSEL.SDOUT = sdout_pin;
|
||||
p_i2s->PSEL.SDIN = sdin_pin;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s,
|
||||
nrf_i2s_mode_t mode,
|
||||
nrf_i2s_format_t format,
|
||||
nrf_i2s_align_t alignment,
|
||||
nrf_i2s_swidth_t sample_width,
|
||||
nrf_i2s_channels_t channels,
|
||||
nrf_i2s_mck_t mck_setup,
|
||||
nrf_i2s_ratio_t ratio)
|
||||
{
|
||||
if (mode == NRF_I2S_MODE_MASTER)
|
||||
{
|
||||
// The MCK/LRCK ratio shall be a multiple of 2 * sample width.
|
||||
if (((sample_width == NRF_I2S_SWIDTH_16BIT) &&
|
||||
(ratio == NRF_I2S_RATIO_48X))
|
||||
||
|
||||
((sample_width == NRF_I2S_SWIDTH_24BIT) &&
|
||||
((ratio == NRF_I2S_RATIO_32X) ||
|
||||
(ratio == NRF_I2S_RATIO_64X) ||
|
||||
(ratio == NRF_I2S_RATIO_128X) ||
|
||||
(ratio == NRF_I2S_RATIO_256X) ||
|
||||
(ratio == NRF_I2S_RATIO_512X))))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
p_i2s->CONFIG.MODE = mode;
|
||||
p_i2s->CONFIG.FORMAT = format;
|
||||
p_i2s->CONFIG.ALIGN = alignment;
|
||||
p_i2s->CONFIG.SWIDTH = sample_width;
|
||||
p_i2s->CONFIG.CHANNELS = channels;
|
||||
p_i2s->CONFIG.RATIO = ratio;
|
||||
|
||||
if (mck_setup == NRF_I2S_MCK_DISABLED)
|
||||
{
|
||||
p_i2s->CONFIG.MCKEN =
|
||||
(I2S_CONFIG_MCKEN_MCKEN_Disabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
p_i2s->CONFIG.MCKFREQ = mck_setup;
|
||||
p_i2s->CONFIG.MCKEN =
|
||||
(I2S_CONFIG_MCKEN_MCKEN_Enabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s,
|
||||
uint16_t size,
|
||||
uint32_t * p_buffer_rx,
|
||||
uint32_t const * p_buffer_tx)
|
||||
{
|
||||
p_i2s->RXTXD.MAXCNT = size;
|
||||
|
||||
nrf_i2s_rx_buffer_set(p_i2s, p_buffer_rx);
|
||||
p_i2s->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0;
|
||||
|
||||
nrf_i2s_tx_buffer_set(p_i2s, p_buffer_tx);
|
||||
p_i2s->CONFIG.TXEN = (p_buffer_tx != NULL) ? 1 : 0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s,
|
||||
uint32_t * p_buffer)
|
||||
{
|
||||
p_i2s->RXD.PTR = (uint32_t)p_buffer;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s)
|
||||
{
|
||||
return (uint32_t *)(p_i2s->RXD.PTR);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s,
|
||||
uint32_t const * p_buffer)
|
||||
{
|
||||
p_i2s->TXD.PTR = (uint32_t)p_buffer;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s)
|
||||
{
|
||||
return (uint32_t *)(p_i2s->TXD.PTR);
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_I2S_H__
|
||||
|
||||
/** @} */
|
||||
425
lib/sdk/components/drivers_nrf/hal/nrf_lpcomp.h
Normal file
425
lib/sdk/components/drivers_nrf/hal/nrf_lpcomp.h
Normal file
@ -0,0 +1,425 @@
|
||||
/**
|
||||
* Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief LPCOMP HAL API.
|
||||
*/
|
||||
|
||||
#ifndef NRF_LPCOMP_H_
|
||||
#define NRF_LPCOMP_H_
|
||||
|
||||
/**
|
||||
* @defgroup nrf_lpcomp_hal LPCOMP HAL
|
||||
* @{
|
||||
* @ingroup nrf_lpcomp
|
||||
* @brief Hardware access layer for managing the Low Power Comparator (LPCOMP).
|
||||
*/
|
||||
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @enum nrf_lpcomp_ref_t
|
||||
* @brief LPCOMP reference selection.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
#if (LPCOMP_REFSEL_RESOLUTION == 8) || defined(__SDK_DOXYGEN__)
|
||||
NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling, /**< Use supply with a 1/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling, /**< Use supply with a 2/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling, /**< Use supply with a 3/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling, /**< Use supply with a 4/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling, /**< Use supply with a 5/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling, /**< Use supply with a 6/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling, /**< Use supply with a 7/8 prescaler as reference. */
|
||||
#elif (LPCOMP_REFSEL_RESOLUTION == 16) || defined(__SDK_DOXYGEN__)
|
||||
NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, /**< Use supply with a 1/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, /**< Use supply with a 2/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, /**< Use supply with a 3/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, /**< Use supply with a 4/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, /**< Use supply with a 5/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, /**< Use supply with a 6/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, /**< Use supply with a 7/8 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_1_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 1/16 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_3_16 = LPCOMP_REFSEL_REFSEL_Ref3_16Vdd, /**< Use supply with a 3/16 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_5_16 = LPCOMP_REFSEL_REFSEL_Ref5_16Vdd, /**< Use supply with a 5/16 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_7_16 = LPCOMP_REFSEL_REFSEL_Ref7_16Vdd, /**< Use supply with a 7/16 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_9_16 = LPCOMP_REFSEL_REFSEL_Ref9_16Vdd, /**< Use supply with a 9/16 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_11_16 = LPCOMP_REFSEL_REFSEL_Ref11_16Vdd, /**< Use supply with a 11/16 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_13_16 = LPCOMP_REFSEL_REFSEL_Ref13_16Vdd, /**< Use supply with a 13/16 prescaler as reference. */
|
||||
NRF_LPCOMP_REF_SUPPLY_15_16 = LPCOMP_REFSEL_REFSEL_Ref15_16Vdd, /**< Use supply with a 15/16 prescaler as reference. */
|
||||
#endif
|
||||
NRF_LPCOMP_REF_EXT_REF0 = LPCOMP_REFSEL_REFSEL_ARef |
|
||||
(LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), /**< External reference 0. */
|
||||
NRF_LPCOMP_CONFIG_REF_EXT_REF1 = LPCOMP_REFSEL_REFSEL_ARef |
|
||||
(LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 << 16), /**< External reference 1. */
|
||||
} nrf_lpcomp_ref_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_lpcomp_input_t
|
||||
* @brief LPCOMP input selection.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_LPCOMP_INPUT_0 = LPCOMP_PSEL_PSEL_AnalogInput0, /**< Input 0. */
|
||||
NRF_LPCOMP_INPUT_1 = LPCOMP_PSEL_PSEL_AnalogInput1, /**< Input 1. */
|
||||
NRF_LPCOMP_INPUT_2 = LPCOMP_PSEL_PSEL_AnalogInput2, /**< Input 2. */
|
||||
NRF_LPCOMP_INPUT_3 = LPCOMP_PSEL_PSEL_AnalogInput3, /**< Input 3. */
|
||||
NRF_LPCOMP_INPUT_4 = LPCOMP_PSEL_PSEL_AnalogInput4, /**< Input 4. */
|
||||
NRF_LPCOMP_INPUT_5 = LPCOMP_PSEL_PSEL_AnalogInput5, /**< Input 5. */
|
||||
NRF_LPCOMP_INPUT_6 = LPCOMP_PSEL_PSEL_AnalogInput6, /**< Input 6. */
|
||||
NRF_LPCOMP_INPUT_7 = LPCOMP_PSEL_PSEL_AnalogInput7 /**< Input 7. */
|
||||
} nrf_lpcomp_input_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_lpcomp_detect_t
|
||||
* @brief LPCOMP detection type selection.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, /**< Generate ANADETEC on crossing, both upwards and downwards crossing. */
|
||||
NRF_LPCOMP_DETECT_UP = LPCOMP_ANADETECT_ANADETECT_Up, /**< Generate ANADETEC on upwards crossing only. */
|
||||
NRF_LPCOMP_DETECT_DOWN = LPCOMP_ANADETECT_ANADETECT_Down /**< Generate ANADETEC on downwards crossing only. */
|
||||
} nrf_lpcomp_detect_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_lpcomp_task_t
|
||||
* @brief LPCOMP tasks.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_LPCOMP_TASK_START = offsetof(NRF_LPCOMP_Type, TASKS_START), /**< LPCOMP start sampling task. */
|
||||
NRF_LPCOMP_TASK_STOP = offsetof(NRF_LPCOMP_Type, TASKS_STOP), /**< LPCOMP stop sampling task. */
|
||||
NRF_LPCOMP_TASK_SAMPLE = offsetof(NRF_LPCOMP_Type, TASKS_SAMPLE) /**< Sample comparator value. */
|
||||
} nrf_lpcomp_task_t; /*lint -restore*/
|
||||
|
||||
|
||||
/**
|
||||
* @enum nrf_lpcomp_event_t
|
||||
* @brief LPCOMP events.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_LPCOMP_EVENT_READY = offsetof(NRF_LPCOMP_Type, EVENTS_READY), /**< LPCOMP is ready and output is valid. */
|
||||
NRF_LPCOMP_EVENT_DOWN = offsetof(NRF_LPCOMP_Type, EVENTS_DOWN), /**< Input voltage crossed the threshold going down. */
|
||||
NRF_LPCOMP_EVENT_UP = offsetof(NRF_LPCOMP_Type, EVENTS_UP), /**< Input voltage crossed the threshold going up. */
|
||||
NRF_LPCOMP_EVENT_CROSS = offsetof(NRF_LPCOMP_Type, EVENTS_CROSS) /**< Input voltage crossed the threshold in any direction. */
|
||||
} nrf_lpcomp_event_t; /*lint -restore*/
|
||||
|
||||
/**
|
||||
* @enum nrf_lpcomp_short_mask_t
|
||||
* @brief LPCOMP shorts masks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_LPCOMP_SHORT_CROSS_STOP_MASK = LPCOMP_SHORTS_CROSS_STOP_Msk, /*!< Short between CROSS event and STOP task. */
|
||||
NRF_LPCOMP_SHORT_UP_STOP_MASK = LPCOMP_SHORTS_UP_STOP_Msk, /*!< Short between UP event and STOP task. */
|
||||
NRF_LPCOMP_SHORT_DOWN_STOP_MASK = LPCOMP_SHORTS_DOWN_STOP_Msk, /*!< Short between DOWN event and STOP task. */
|
||||
NRF_LPCOMP_SHORT_READY_STOP_MASK = LPCOMP_SHORTS_READY_STOP_Msk, /*!< Short between READY event and STOP task. */
|
||||
NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Short between READY event and SAMPLE task. */
|
||||
} nrf_lpcomp_short_mask_t;
|
||||
|
||||
#ifdef LPCOMP_FEATURE_HYST_PRESENT
|
||||
/**
|
||||
* @enum nrf_lpcomp_hysteresis_t
|
||||
* @brief LPCOMP hysteresis.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_LPCOMP_HYST_NOHYST = LPCOMP_HYST_HYST_NoHyst, /**< Comparator hysteresis disabled. */
|
||||
NRF_LPCOMP_HYST_50mV = LPCOMP_HYST_HYST_Hyst50mV /**< Comparator hysteresis enabled (typ. 50 mV). */
|
||||
}nrf_lpcomp_hysteresis_t;
|
||||
#endif // LPCOMP_FEATURE_HYST_PRESENT
|
||||
|
||||
/** @brief LPCOMP configuration. */
|
||||
typedef struct
|
||||
{
|
||||
nrf_lpcomp_ref_t reference; /**< LPCOMP reference. */
|
||||
nrf_lpcomp_detect_t detection; /**< LPCOMP detection type. */
|
||||
#ifdef LPCOMP_FEATURE_HYST_PRESENT
|
||||
nrf_lpcomp_hysteresis_t hyst; /**< LPCOMP hysteresis. */
|
||||
#endif // LPCOMP_FEATURE_HYST_PRESENT
|
||||
} nrf_lpcomp_config_t;
|
||||
|
||||
/** Default LPCOMP configuration. */
|
||||
#define NRF_LPCOMP_CONFIG_DEFAULT { NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT, NRF_LPCOMP_DETECT_DOWN }
|
||||
|
||||
/**
|
||||
* @brief Function for configuring LPCOMP.
|
||||
*
|
||||
* This function powers on LPCOMP and configures it. LPCOMP is in DISABLE state after configuration,
|
||||
* so it must be enabled before using it. All shorts are inactive, events are cleared, and LPCOMP is stopped.
|
||||
*
|
||||
* @param[in] p_config Configuration.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config)
|
||||
{
|
||||
NRF_LPCOMP->TASKS_STOP = 1;
|
||||
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
|
||||
NRF_LPCOMP->REFSEL =
|
||||
(p_config->reference << LPCOMP_REFSEL_REFSEL_Pos) & LPCOMP_REFSEL_REFSEL_Msk;
|
||||
|
||||
//If external source is choosen extract analog reference index.
|
||||
if ((p_config->reference & LPCOMP_REFSEL_REFSEL_ARef)==LPCOMP_REFSEL_REFSEL_ARef)
|
||||
{
|
||||
uint32_t extref = p_config->reference >> 16;
|
||||
NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) & LPCOMP_EXTREFSEL_EXTREFSEL_Msk;
|
||||
}
|
||||
|
||||
NRF_LPCOMP->ANADETECT =
|
||||
(p_config->detection << LPCOMP_ANADETECT_ANADETECT_Pos) & LPCOMP_ANADETECT_ANADETECT_Msk;
|
||||
#ifdef LPCOMP_FEATURE_HYST_PRESENT
|
||||
NRF_LPCOMP->HYST = ((p_config->hyst) << LPCOMP_HYST_HYST_Pos) & LPCOMP_HYST_HYST_Msk;
|
||||
#endif //LPCOMP_FEATURE_HYST_PRESENT
|
||||
NRF_LPCOMP->SHORTS = 0;
|
||||
NRF_LPCOMP->INTENCLR = LPCOMP_INTENCLR_CROSS_Msk | LPCOMP_INTENCLR_UP_Msk |
|
||||
LPCOMP_INTENCLR_DOWN_Msk | LPCOMP_INTENCLR_READY_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for selecting the LPCOMP input.
|
||||
*
|
||||
* This function selects the active input of LPCOMP.
|
||||
*
|
||||
* @param[in] input Input to be selected.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input)
|
||||
{
|
||||
uint32_t lpcomp_enable_state = NRF_LPCOMP->ENABLE;
|
||||
|
||||
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
|
||||
NRF_LPCOMP->PSEL =
|
||||
((uint32_t)input << LPCOMP_PSEL_PSEL_Pos) | (NRF_LPCOMP->PSEL & ~LPCOMP_PSEL_PSEL_Msk);
|
||||
NRF_LPCOMP->ENABLE = lpcomp_enable_state;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the Low Power Comparator.
|
||||
*
|
||||
* This function enables LPCOMP.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_enable(void)
|
||||
{
|
||||
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos;
|
||||
NRF_LPCOMP->EVENTS_READY = 0;
|
||||
NRF_LPCOMP->EVENTS_DOWN = 0;
|
||||
NRF_LPCOMP->EVENTS_UP = 0;
|
||||
NRF_LPCOMP->EVENTS_CROSS = 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the Low Power Comparator.
|
||||
*
|
||||
* This function disables LPCOMP.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_disable(void)
|
||||
{
|
||||
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the last LPCOMP compare result.
|
||||
*
|
||||
* @return The last compare result. If 0 then VIN+ < VIN-, if 1 then the opposite.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_lpcomp_result_get(void)
|
||||
{
|
||||
return (uint32_t)NRF_LPCOMP->RESULT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling interrupts from LPCOMP.
|
||||
*
|
||||
* @param[in] lpcomp_int_mask Mask of interrupts to be enabled.
|
||||
*
|
||||
* @sa nrf_lpcomp_int_disable()
|
||||
* @sa nrf_lpcomp_int_enable_check()
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t lpcomp_int_mask)
|
||||
{
|
||||
NRF_LPCOMP->INTENSET = lpcomp_int_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling interrupts from LPCOMP.
|
||||
*
|
||||
* @param[in] lpcomp_int_mask Mask of interrupts to be disabled.
|
||||
*
|
||||
* @sa nrf_lpcomp_int_enable()
|
||||
* @sa nrf_lpcomp_int_enable_check()
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask)
|
||||
{
|
||||
NRF_LPCOMP->INTENCLR = lpcomp_int_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the enabled interrupts of LPCOMP.
|
||||
*
|
||||
* @param[in] lpcomp_int_mask Mask of interrupts to be checked.
|
||||
*
|
||||
* @retval true If any of interrupts of the specified mask are enabled.
|
||||
*
|
||||
* @sa nrf_lpcomp_int_enable()
|
||||
* @sa nrf_lpcomp_int_disable()
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t lpcomp_int_mask)
|
||||
{
|
||||
return (NRF_LPCOMP->INTENSET & lpcomp_int_mask); // when read this register will return the value of INTEN.
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific LPCOMP task register.
|
||||
*
|
||||
* @param[in] lpcomp_task LPCOMP task.
|
||||
*
|
||||
* @return The address of the specified LPCOMP task.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t lpcomp_task)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_task);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific LPCOMP event register.
|
||||
*
|
||||
* @param[in] lpcomp_event LPCOMP event.
|
||||
*
|
||||
* @return The address of the specified LPCOMP event.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t lpcomp_event)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting LPCOMP shorts.
|
||||
*
|
||||
* @param[in] lpcomp_short_mask LPCOMP shorts by mask.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t lpcomp_short_mask)
|
||||
{
|
||||
NRF_LPCOMP->SHORTS |= lpcomp_short_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing LPCOMP shorts by mask.
|
||||
*
|
||||
* @param[in] lpcomp_short_mask LPCOMP shorts to be cleared.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t lpcomp_short_mask)
|
||||
{
|
||||
NRF_LPCOMP->SHORTS &= ~lpcomp_short_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting a specific LPCOMP task.
|
||||
*
|
||||
* @param[in] lpcomp_task LPCOMP task to be set.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t lpcomp_task)
|
||||
{
|
||||
*( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_task) ) = 1;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific LPCOMP event.
|
||||
*
|
||||
* @param[in] lpcomp_event LPCOMP event to be cleared.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t lpcomp_event)
|
||||
{
|
||||
*( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event) ) = 0;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the state of a specific LPCOMP event.
|
||||
*
|
||||
* @retval true If the specified LPCOMP event is active.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t lpcomp_event)
|
||||
{
|
||||
return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* NRF_LPCOMP_H_ */
|
||||
136
lib/sdk/components/drivers_nrf/hal/nrf_nvmc.c
Normal file
136
lib/sdk/components/drivers_nrf/hal/nrf_nvmc.c
Normal file
@ -0,0 +1,136 @@
|
||||
/**
|
||||
* Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
*@file
|
||||
*@brief NMVC driver implementation
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_nvmc.h"
|
||||
|
||||
|
||||
static inline void wait_for_flash_ready(void)
|
||||
{
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {;}
|
||||
}
|
||||
|
||||
|
||||
void nrf_nvmc_page_erase(uint32_t address)
|
||||
{
|
||||
// Enable erase.
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
|
||||
__ISB();
|
||||
__DSB();
|
||||
|
||||
// Erase the page
|
||||
NRF_NVMC->ERASEPAGE = address;
|
||||
wait_for_flash_ready();
|
||||
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
|
||||
__ISB();
|
||||
__DSB();
|
||||
}
|
||||
|
||||
|
||||
void nrf_nvmc_write_byte(uint32_t address, uint8_t value)
|
||||
{
|
||||
uint32_t byte_shift = address & (uint32_t)0x03;
|
||||
uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in.
|
||||
uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3)));
|
||||
value32 = value32 + ((uint32_t)value << (byte_shift << 3));
|
||||
|
||||
// Enable write.
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
|
||||
__ISB();
|
||||
__DSB();
|
||||
|
||||
*(uint32_t*)address32 = value32;
|
||||
wait_for_flash_ready();
|
||||
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
|
||||
__ISB();
|
||||
__DSB();
|
||||
}
|
||||
|
||||
|
||||
void nrf_nvmc_write_word(uint32_t address, uint32_t value)
|
||||
{
|
||||
// Enable write.
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
|
||||
__ISB();
|
||||
__DSB();
|
||||
|
||||
*(uint32_t*)address = value;
|
||||
wait_for_flash_ready();
|
||||
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
|
||||
__ISB();
|
||||
__DSB();
|
||||
}
|
||||
|
||||
|
||||
void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes)
|
||||
{
|
||||
for (uint32_t i = 0; i < num_bytes; i++)
|
||||
{
|
||||
nrf_nvmc_write_byte(address + i, src[i]);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words)
|
||||
{
|
||||
// Enable write.
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
|
||||
__ISB();
|
||||
__DSB();
|
||||
|
||||
for (uint32_t i = 0; i < num_words; i++)
|
||||
{
|
||||
((uint32_t*)address)[i] = src[i];
|
||||
wait_for_flash_ready();
|
||||
}
|
||||
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
|
||||
__ISB();
|
||||
__DSB();
|
||||
}
|
||||
|
||||
125
lib/sdk/components/drivers_nrf/hal/nrf_nvmc.h
Normal file
125
lib/sdk/components/drivers_nrf/hal/nrf_nvmc.h
Normal file
@ -0,0 +1,125 @@
|
||||
/**
|
||||
* Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief NMVC driver API.
|
||||
*/
|
||||
|
||||
#ifndef NRF_NVMC_H__
|
||||
#define NRF_NVMC_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup nrf_nvmc Non-volatile memory controller
|
||||
* @{
|
||||
* @ingroup nrf_drivers
|
||||
* @brief Driver for the NVMC peripheral.
|
||||
*
|
||||
* This driver allows writing to the non-volatile memory (NVM) regions
|
||||
* of the chip. In order to write to NVM the controller must be powered
|
||||
* on and the relevant page must be erased.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Erase a page in flash. This is required before writing to any
|
||||
* address in the page.
|
||||
*
|
||||
* @param address Start address of the page.
|
||||
*/
|
||||
void nrf_nvmc_page_erase(uint32_t address);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write a single byte to flash.
|
||||
*
|
||||
* The function reads the word containing the byte, and then
|
||||
* rewrites the entire word.
|
||||
*
|
||||
* @param address Address to write to.
|
||||
* @param value Value to write.
|
||||
*/
|
||||
void nrf_nvmc_write_byte(uint32_t address , uint8_t value);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write a 32-bit word to flash.
|
||||
* @param address Address to write to.
|
||||
* @param value Value to write.
|
||||
*/
|
||||
void nrf_nvmc_write_word(uint32_t address, uint32_t value);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write consecutive bytes to flash.
|
||||
*
|
||||
* @param address Address to write to.
|
||||
* @param src Pointer to data to copy from.
|
||||
* @param num_bytes Number of bytes in src to write.
|
||||
*/
|
||||
void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write consecutive words to flash.
|
||||
*
|
||||
* @param address Address to write to.
|
||||
* @param src Pointer to data to copy from.
|
||||
* @param num_words Number of words in src to write.
|
||||
*/
|
||||
void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_NVMC_H__
|
||||
/** @} */
|
||||
|
||||
|
||||
396
lib/sdk/components/drivers_nrf/hal/nrf_pdm.h
Normal file
396
lib/sdk/components/drivers_nrf/hal/nrf_pdm.h
Normal file
@ -0,0 +1,396 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_PDM_H_
|
||||
#define NRF_PDM_H_
|
||||
|
||||
/**
|
||||
* @defgroup nrf_pdm_hal PDM HAL
|
||||
* @{
|
||||
* @ingroup nrf_pdm
|
||||
*
|
||||
* @brief @tagAPI52 Hardware abstraction layer for accessing the pulse density modulation (PDM) peripheral.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define NRF_PDM_GAIN_MINIMUM 0x00
|
||||
#define NRF_PDM_GAIN_DEFAULT 0x28
|
||||
#define NRF_PDM_GAIN_MAXIMUM 0x50
|
||||
|
||||
typedef uint8_t nrf_pdm_gain_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PDM tasks.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_PDM_TASK_START = offsetof(NRF_PDM_Type, TASKS_START), ///< Starts continuous PDM transfer.
|
||||
NRF_PDM_TASK_STOP = offsetof(NRF_PDM_Type, TASKS_STOP) ///< Stops PDM transfer.
|
||||
} nrf_pdm_task_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PDM events.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_PDM_EVENT_STARTED = offsetof(NRF_PDM_Type, EVENTS_STARTED), ///< PDM transfer has started.
|
||||
NRF_PDM_EVENT_STOPPED = offsetof(NRF_PDM_Type, EVENTS_STOPPED), ///< PDM transfer has finished.
|
||||
NRF_PDM_EVENT_END = offsetof(NRF_PDM_Type, EVENTS_END) ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM.
|
||||
} nrf_pdm_event_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PDM interrupt masks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
|
||||
NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
|
||||
NRF_PDM_INT_END = PDM_INTENSET_END_Msk ///< Interrupt on EVENTS_END event.
|
||||
} nrf_pdm_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief PDM clock frequency.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K, ///< PDM_CLK = 1.000 MHz.
|
||||
NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default, ///< PDM_CLK = 1.032 MHz.
|
||||
NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K ///< PDM_CLK = 1.067 MHz.
|
||||
} nrf_pdm_freq_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PDM operation mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PDM_MODE_STEREO = PDM_MODE_OPERATION_Stereo, ///< Sample and store one pair (Left + Right) of 16-bit samples per RAM word.
|
||||
NRF_PDM_MODE_MONO = PDM_MODE_OPERATION_Mono ///< Sample and store two successive Left samples (16 bit each) per RAM word.
|
||||
} nrf_pdm_mode_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PDM sampling mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PDM_EDGE_LEFTFALLING = PDM_MODE_EDGE_LeftFalling, ///< Left (or mono) is sampled on falling edge of PDM_CLK.
|
||||
NRF_PDM_EDGE_LEFTRISING = PDM_MODE_EDGE_LeftRising ///< Left (or mono) is sampled on rising edge of PDM_CLK.
|
||||
} nrf_pdm_edge_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for triggering a PDM task.
|
||||
*
|
||||
* @param[in] pdm_task PDM task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t pdm_task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_task)) = 0x1UL;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a PDM task register.
|
||||
*
|
||||
* @param[in] pdm_task PDM task.
|
||||
*
|
||||
* @return Address of the specified PDM task.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t pdm_task)
|
||||
{
|
||||
return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)pdm_task);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the state of a PDM event.
|
||||
*
|
||||
* @param[in] pdm_event PDM event.
|
||||
*
|
||||
* @return State of the specified PDM event.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t pdm_event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a PDM event.
|
||||
*
|
||||
* @param[in] pdm_event PDM event.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t pdm_event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a PDM event register.
|
||||
*
|
||||
* @param[in] pdm_event PDM event.
|
||||
*
|
||||
* @return Address of the specified PDM event.
|
||||
*/
|
||||
__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t pdm_event)
|
||||
{
|
||||
return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling PDM interrupts.
|
||||
*
|
||||
* @param[in] pdm_int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_int_enable(uint32_t pdm_int_mask)
|
||||
{
|
||||
NRF_PDM->INTENSET = pdm_int_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of PDM interrupts.
|
||||
*
|
||||
* @param[in] pdm_int_mask Interrupts to check.
|
||||
*
|
||||
* @retval true If all specified interrupts are enabled.
|
||||
* @retval false If at least one of the given interrupts is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t pdm_int_mask)
|
||||
{
|
||||
return (bool)(NRF_PDM->INTENSET & pdm_int_mask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling interrupts.
|
||||
*
|
||||
* @param pdm_int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_int_disable(uint32_t pdm_int_mask)
|
||||
{
|
||||
NRF_PDM->INTENCLR = pdm_int_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the PDM peripheral.
|
||||
*
|
||||
* The PDM peripheral must be enabled before use.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_enable(void)
|
||||
{
|
||||
NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the PDM peripheral.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_disable(void)
|
||||
{
|
||||
NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Disabled << PDM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for checking if the PDM peripheral is enabled.
|
||||
*
|
||||
* @retval true If the PDM peripheral is enabled.
|
||||
* @retval false If the PDM peripheral is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_pdm_enable_check(void)
|
||||
{
|
||||
return (NRF_PDM->ENABLE == (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the PDM operation mode.
|
||||
*
|
||||
* @param[in] pdm_mode PDM operation mode.
|
||||
* @param[in] pdm_edge PDM sampling mode.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_mode_set(nrf_pdm_mode_t pdm_mode, nrf_pdm_edge_t pdm_edge)
|
||||
{
|
||||
NRF_PDM->MODE = ((pdm_mode << PDM_MODE_OPERATION_Pos) & PDM_MODE_OPERATION_Msk)
|
||||
| ((pdm_edge << PDM_MODE_EDGE_Pos) & PDM_MODE_EDGE_Msk);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the PDM operation mode.
|
||||
*
|
||||
* @param[out] p_pdm_mode PDM operation mode.
|
||||
* @param[out] p_pdm_edge PDM sampling mode.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_mode_get(nrf_pdm_mode_t * p_pdm_mode, nrf_pdm_edge_t * p_pdm_edge)
|
||||
{
|
||||
uint32_t mode = NRF_PDM->MODE;
|
||||
*p_pdm_mode = (nrf_pdm_mode_t)((mode & PDM_MODE_OPERATION_Msk ) >> PDM_MODE_OPERATION_Pos);
|
||||
*p_pdm_edge = (nrf_pdm_edge_t)((mode & PDM_MODE_EDGE_Msk ) >> PDM_MODE_EDGE_Pos);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the PDM clock frequency.
|
||||
*
|
||||
* @param[in] pdm_freq PDM clock frequency.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq)
|
||||
{
|
||||
NRF_PDM->PDMCLKCTRL = ((pdm_freq << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the PDM clock frequency.
|
||||
*/
|
||||
__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void)
|
||||
{
|
||||
return (nrf_pdm_freq_t) ((NRF_PDM->PDMCLKCTRL << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting up the PDM pins.
|
||||
*
|
||||
* @param[in] psel_clk CLK pin number.
|
||||
* @param[in] psel_din DIN pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din)
|
||||
{
|
||||
NRF_PDM->PSEL.CLK = psel_clk;
|
||||
NRF_PDM->PSEL.DIN = psel_din;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for disconnecting the PDM pins.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_psel_disconnect()
|
||||
{
|
||||
NRF_PDM->PSEL.CLK = ((PDM_PSEL_CLK_CONNECT_Disconnected << PDM_PSEL_CLK_CONNECT_Pos)
|
||||
& PDM_PSEL_CLK_CONNECT_Msk);
|
||||
NRF_PDM->PSEL.DIN = ((PDM_PSEL_DIN_CONNECT_Disconnected << PDM_PSEL_DIN_CONNECT_Pos)
|
||||
& PDM_PSEL_DIN_CONNECT_Msk);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the PDM gain.
|
||||
*
|
||||
* @param[in] gain_l Left channel gain.
|
||||
* @param[in] gain_r Right channel gain.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_gain_set(nrf_pdm_gain_t gain_l, nrf_pdm_gain_t gain_r)
|
||||
{
|
||||
NRF_PDM->GAINL = gain_l;
|
||||
NRF_PDM->GAINR = gain_r;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the PDM gain.
|
||||
*
|
||||
* @param[out] p_gain_l Left channel gain.
|
||||
* @param[out] p_gain_r Right channel gain.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t * p_gain_r)
|
||||
{
|
||||
*p_gain_l = NRF_PDM->GAINL;
|
||||
*p_gain_r = NRF_PDM->GAINR;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the PDM sample buffer.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to the RAM address where samples should be written with EasyDMA.
|
||||
* @param[in] num Number of samples to allocate memory for in EasyDMA mode.
|
||||
*
|
||||
* The amount of allocated RAM depends on the operation mode.
|
||||
* - For stereo mode: N 32-bit words.
|
||||
* - For mono mode: Ceil(N/2) 32-bit words.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num)
|
||||
{
|
||||
NRF_PDM->SAMPLE.PTR = (uint32_t)p_buffer;
|
||||
NRF_PDM->SAMPLE.MAXCNT = num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for getting the current PDM sample buffer address.
|
||||
*
|
||||
* @return Pointer to the current sample buffer.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_pdm_buffer_get()
|
||||
{
|
||||
return (uint32_t *)NRF_PDM->SAMPLE.PTR;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* NRF_PDM_H_ */
|
||||
73
lib/sdk/components/drivers_nrf/hal/nrf_peripherals.h
Normal file
73
lib/sdk/components/drivers_nrf/hal/nrf_peripherals.h
Normal file
@ -0,0 +1,73 @@
|
||||
/**
|
||||
* Copyright (c) 2016 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_PERIPHERALS_H
|
||||
#define NRF_PERIPHERALS_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
#ifdef NRF51422
|
||||
#include "nrf51422_peripherals.h"
|
||||
#endif
|
||||
|
||||
#ifdef NRF51802
|
||||
#include "nrf51802_peripherals.h"
|
||||
#endif
|
||||
|
||||
#ifdef NRF51822
|
||||
#include "nrf51822_peripherals.h"
|
||||
#endif
|
||||
|
||||
#ifdef NRF52810_XXAA
|
||||
#include "nrf52810_peripherals.h"
|
||||
#endif
|
||||
|
||||
#ifdef NRF52832_XXAA
|
||||
#include "nrf52832_peripherals.h"
|
||||
#endif
|
||||
|
||||
#ifdef NRF52840_XXAA
|
||||
#include "nrf52840_peripherals.h"
|
||||
#endif
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF_PERIPHERALS_H */
|
||||
|
||||
1065
lib/sdk/components/drivers_nrf/hal/nrf_power.h
Normal file
1065
lib/sdk/components/drivers_nrf/hal/nrf_power.h
Normal file
File diff suppressed because it is too large
Load Diff
439
lib/sdk/components/drivers_nrf/hal/nrf_ppi.h
Normal file
439
lib/sdk/components/drivers_nrf/hal/nrf_ppi.h
Normal file
@ -0,0 +1,439 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_PPI_H__
|
||||
#define NRF_PPI_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup nrf_ppi_hal PPI HAL
|
||||
* @{
|
||||
* @ingroup nrf_ppi
|
||||
* @brief Hardware access layer for setting up Programmable Peripheral Interconnect (PPI) channels.
|
||||
*/
|
||||
|
||||
#define NRF_PPI_TASK_SET (1UL)
|
||||
|
||||
/**
|
||||
* @enum nrf_ppi_channel_t
|
||||
* @brief PPI channels.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */
|
||||
NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */
|
||||
NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */
|
||||
NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */
|
||||
NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */
|
||||
NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */
|
||||
NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */
|
||||
NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */
|
||||
NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */
|
||||
NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */
|
||||
NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */
|
||||
NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */
|
||||
NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */
|
||||
NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
|
||||
NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
|
||||
NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
|
||||
#if (PPI_CH_NUM > 16) || defined(__SDK_DOXYGEN__)
|
||||
NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
|
||||
NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
|
||||
NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */
|
||||
NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */
|
||||
#endif
|
||||
NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */
|
||||
NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */
|
||||
NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */
|
||||
NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */
|
||||
NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */
|
||||
NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */
|
||||
NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */
|
||||
NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */
|
||||
NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */
|
||||
NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */
|
||||
NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */
|
||||
NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */
|
||||
} nrf_ppi_channel_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_ppi_channel_group_t
|
||||
* @brief PPI channel groups.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
|
||||
NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
|
||||
NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
|
||||
NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
|
||||
#if (PPI_GROUP_NUM > 4) || defined(__SDK_DOXYGEN__)
|
||||
NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
|
||||
NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
|
||||
#endif
|
||||
} nrf_ppi_channel_group_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_ppi_channel_include_t
|
||||
* @brief Definition of which PPI channels belong to a group.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */
|
||||
NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */
|
||||
} nrf_ppi_channel_include_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_ppi_channel_enable_t
|
||||
* @brief Definition if a PPI channel is enabled.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */
|
||||
NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */
|
||||
} nrf_ppi_channel_enable_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_ppi_task_t
|
||||
* @brief PPI tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30 -esym(628,__INTADDR__)*/
|
||||
NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0 */
|
||||
NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */
|
||||
NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1 */
|
||||
NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */
|
||||
NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2 */
|
||||
NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */
|
||||
NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3 */
|
||||
NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */
|
||||
#if (PPI_GROUP_NUM > 4) || defined(__SDK_DOXYGEN__)
|
||||
NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4 */
|
||||
NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */
|
||||
NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5 */
|
||||
NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5 */
|
||||
#endif
|
||||
/*lint -restore*/
|
||||
} nrf_ppi_task_t;
|
||||
|
||||
/**
|
||||
* @brief Function for enabling a given PPI channel.
|
||||
*
|
||||
* @details This function enables only one channel.
|
||||
*
|
||||
* @param[in] channel Channel to enable.
|
||||
*
|
||||
* */
|
||||
__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel)
|
||||
{
|
||||
NRF_PPI->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling a given PPI channel.
|
||||
*
|
||||
* @details This function disables only one channel.
|
||||
*
|
||||
* @param[in] channel Channel to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel)
|
||||
{
|
||||
NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for checking if a given PPI channel is enabled.
|
||||
*
|
||||
* @details This function checks only one channel.
|
||||
*
|
||||
* @param[in] channel Channel to check.
|
||||
*
|
||||
* @retval NRF_PPI_CHANNEL_ENABLED If the channel is enabled.
|
||||
* @retval NRF_PPI_CHANNEL_DISABLED If the channel is not enabled.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel)
|
||||
{
|
||||
if (NRF_PPI->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel)))
|
||||
{
|
||||
return NRF_PPI_CHANNEL_ENABLED;
|
||||
}
|
||||
else
|
||||
{
|
||||
return NRF_PPI_CHANNEL_DISABLED;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling all PPI channels.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channel_disable_all(void)
|
||||
{
|
||||
NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for disabling multiple PPI channels.
|
||||
*
|
||||
* @param[in] mask Channel mask.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask)
|
||||
{
|
||||
NRF_PPI->CHENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for setting up event and task endpoints for a given PPI channel.
|
||||
*
|
||||
* @param[in] eep Event register address.
|
||||
*
|
||||
* @param[in] tep Task register address.
|
||||
*
|
||||
* @param[in] channel Channel to which the given endpoints are assigned.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
|
||||
uint32_t eep,
|
||||
uint32_t tep)
|
||||
{
|
||||
NRF_PPI->CH[(uint32_t) channel].EEP = eep;
|
||||
NRF_PPI->CH[(uint32_t) channel].TEP = tep;
|
||||
}
|
||||
|
||||
#if defined(PPI_FEATURE_FORKS_PRESENT) || defined(__SDK_DOXYGEN__)
|
||||
/**
|
||||
* @brief Function for setting up task endpoint for a given PPI fork.
|
||||
*
|
||||
* @param[in] fork_tep Task register address.
|
||||
*
|
||||
* @param[in] channel Channel to which the given fork endpoint is assigned.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
|
||||
uint32_t fork_tep)
|
||||
{
|
||||
NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for setting up event and task endpoints for a given PPI channel and fork.
|
||||
*
|
||||
* @param[in] eep Event register address.
|
||||
*
|
||||
* @param[in] tep Task register address.
|
||||
*
|
||||
* @param[in] fork_tep Fork task register address (register value).
|
||||
*
|
||||
* @param[in] channel Channel to which the given endpoints are assigned.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,
|
||||
uint32_t eep,
|
||||
uint32_t tep,
|
||||
uint32_t fork_tep)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(channel, eep, tep);
|
||||
nrf_ppi_fork_endpoint_setup(channel, fork_tep);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Function for including a PPI channel in a channel group.
|
||||
*
|
||||
* @details This function adds only one channel to the group.
|
||||
*
|
||||
* @param[in] channel Channel to be included in the group.
|
||||
*
|
||||
* @param[in] channel_group Channel group.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel,
|
||||
nrf_ppi_channel_group_t channel_group)
|
||||
{
|
||||
NRF_PPI->CHG[(uint32_t) channel_group] =
|
||||
NRF_PPI->CHG[(uint32_t) channel_group] | (PPI_CHG_CH0_Included << ((uint32_t) channel));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for including multiple PPI channels in a channel group.
|
||||
*
|
||||
* @details This function adds all specified channels to the group.
|
||||
*
|
||||
* @param[in] channel_mask Channels to be included in the group.
|
||||
*
|
||||
* @param[in] channel_group Channel group.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask,
|
||||
nrf_ppi_channel_group_t channel_group)
|
||||
{
|
||||
NRF_PPI->CHG[(uint32_t) channel_group] =
|
||||
NRF_PPI->CHG[(uint32_t) channel_group] | (channel_mask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for removing a PPI channel from a channel group.
|
||||
*
|
||||
* @details This function removes only one channel from the group.
|
||||
*
|
||||
* @param[in] channel Channel to be removed from the group.
|
||||
*
|
||||
* @param[in] channel_group Channel group.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel,
|
||||
nrf_ppi_channel_group_t channel_group)
|
||||
{
|
||||
NRF_PPI->CHG[(uint32_t) channel_group] =
|
||||
NRF_PPI->CHG[(uint32_t) channel_group] & ~(PPI_CHG_CH0_Included << ((uint32_t) channel));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for removing multiple PPI channels from a channel group.
|
||||
*
|
||||
* @details This function removes all specified channels from the group.
|
||||
*
|
||||
* @param[in] channel_mask Channels to be removed from the group.
|
||||
*
|
||||
* @param[in] channel_group Channel group.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask,
|
||||
nrf_ppi_channel_group_t channel_group)
|
||||
{
|
||||
NRF_PPI->CHG[(uint32_t) channel_group] =
|
||||
NRF_PPI->CHG[(uint32_t) channel_group] & ~(channel_mask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for removing all PPI channels from a channel group.
|
||||
*
|
||||
* @param[in] group Channel group.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group)
|
||||
{
|
||||
NRF_PPI->CHG[(uint32_t) group] = 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling a channel group.
|
||||
*
|
||||
* @param[in] group Channel group.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group)
|
||||
{
|
||||
NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling a channel group.
|
||||
*
|
||||
* @param[in] group Channel group.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group)
|
||||
{
|
||||
NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting a PPI task.
|
||||
*
|
||||
* @param[in] ppi_task PPI task to set.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task)
|
||||
{
|
||||
*((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific PPI task register.
|
||||
*
|
||||
* @param[in] ppi_task PPI task.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task)
|
||||
{
|
||||
return (uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for returning the PPI enable task address of a specific group.
|
||||
*
|
||||
* @param[in] group PPI group.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group)
|
||||
{
|
||||
return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].EN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for returning the PPI disable task address of a specific group.
|
||||
*
|
||||
* @param[in] group PPI group.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group)
|
||||
{
|
||||
return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_PPI_H__
|
||||
701
lib/sdk/components/drivers_nrf/hal/nrf_pwm.h
Normal file
701
lib/sdk/components/drivers_nrf/hal/nrf_pwm.h
Normal file
@ -0,0 +1,701 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @defgroup nrf_pwm_hal PWM HAL
|
||||
* @{
|
||||
* @ingroup nrf_pwm
|
||||
*
|
||||
* @brief @tagAPI52 Hardware access layer for managing the Pulse Width Modulation (PWM)
|
||||
* peripheral.
|
||||
*/
|
||||
|
||||
#ifndef NRF_PWM_H__
|
||||
#define NRF_PWM_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf.h"
|
||||
#include "nrf_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
|
||||
* function call to specify that a given output channel shall not be
|
||||
* connected to a physical pin.
|
||||
*/
|
||||
#define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
|
||||
|
||||
/**
|
||||
* @brief Number of channels in each Pointer to the peripheral registers structure.
|
||||
*/
|
||||
#define NRF_PWM_CHANNEL_COUNT 4
|
||||
|
||||
|
||||
/**
|
||||
* @brief PWM tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
|
||||
NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
|
||||
NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
|
||||
NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
|
||||
/*lint -restore*/
|
||||
} nrf_pwm_task_t;
|
||||
|
||||
/**
|
||||
* @brief PWM events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
|
||||
NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
|
||||
NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
|
||||
NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
|
||||
NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
|
||||
NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
|
||||
NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the requested number of times.
|
||||
/*lint -restore*/
|
||||
} nrf_pwm_event_t;
|
||||
|
||||
/**
|
||||
* @brief PWM interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
|
||||
NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event.
|
||||
NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event.
|
||||
NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event.
|
||||
NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event.
|
||||
NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
|
||||
NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
|
||||
} nrf_pwm_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief PWM shortcuts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
|
||||
NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task.
|
||||
NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
|
||||
NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
|
||||
NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
|
||||
} nrf_pwm_short_mask_t;
|
||||
|
||||
/**
|
||||
* @brief PWM modes of operation.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
|
||||
NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
|
||||
} nrf_pwm_mode_t;
|
||||
|
||||
/**
|
||||
* @brief PWM base clock frequencies.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
|
||||
NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz.
|
||||
NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz.
|
||||
NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz.
|
||||
NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
|
||||
NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
|
||||
NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
|
||||
NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
|
||||
} nrf_pwm_clk_t;
|
||||
|
||||
/**
|
||||
* @brief PWM decoder load modes.
|
||||
*
|
||||
* The selected mode determines how the sequence data is read from RAM and
|
||||
* spread to the compare registers.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3).
|
||||
NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
|
||||
NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
|
||||
NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
|
||||
} nrf_pwm_dec_load_t;
|
||||
|
||||
/**
|
||||
* @brief PWM decoder next step modes.
|
||||
*
|
||||
* The selected mode determines when the next value from the active sequence
|
||||
* is loaded.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
|
||||
NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
|
||||
} nrf_pwm_dec_step_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Type used for defining duty cycle values for a sequence
|
||||
* loaded in @ref NRF_PWM_LOAD_COMMON mode.
|
||||
*/
|
||||
typedef uint16_t nrf_pwm_values_common_t;
|
||||
|
||||
/**
|
||||
* @brief Structure for defining duty cycle values for a sequence
|
||||
* loaded in @ref NRF_PWM_LOAD_GROUPED mode.
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
|
||||
uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
|
||||
} nrf_pwm_values_grouped_t;
|
||||
|
||||
/**
|
||||
* @brief Structure for defining duty cycle values for a sequence
|
||||
* loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t channel_0; ///< Duty cycle value for channel 0.
|
||||
uint16_t channel_1; ///< Duty cycle value for channel 1.
|
||||
uint16_t channel_2; ///< Duty cycle value for channel 2.
|
||||
uint16_t channel_3; ///< Duty cycle value for channel 3.
|
||||
} nrf_pwm_values_individual_t;
|
||||
|
||||
/**
|
||||
* @brief Structure for defining duty cycle values for a sequence
|
||||
* loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t channel_0; ///< Duty cycle value for channel 0.
|
||||
uint16_t channel_1; ///< Duty cycle value for channel 1.
|
||||
uint16_t channel_2; ///< Duty cycle value for channel 2.
|
||||
uint16_t counter_top; ///< Top value for the pulse generator counter.
|
||||
} nrf_pwm_values_wave_form_t;
|
||||
|
||||
/**
|
||||
* @brief Union grouping pointers to arrays of duty cycle values applicable to
|
||||
* various loading modes.
|
||||
*/
|
||||
typedef union {
|
||||
nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
|
||||
nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
|
||||
nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
|
||||
nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
|
||||
uint16_t const * p_raw; ///< Pointer providing raw access to the values.
|
||||
} nrf_pwm_values_t;
|
||||
|
||||
/**
|
||||
* @brief Structure for defining a sequence of PWM duty cycles.
|
||||
*
|
||||
* When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
|
||||
* provided duty cycle values are not copied. The @p values pointer is stored
|
||||
* in the peripheral's internal register, and the values are loaded from RAM
|
||||
* during the sequence playback. Therefore, you must ensure that the values
|
||||
* do not change before and during the sequence playback (for example,
|
||||
* the values cannot be placed in a local variable that is allocated on stack).
|
||||
* If the sequence is played in a loop and the values should be updated
|
||||
* before the next iteration, it is safe to modify them when the corresponding
|
||||
* event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
|
||||
* or @ref NRF_PWM_EVENT_SEQEND1, respectively).
|
||||
*
|
||||
* @note The @p repeats and @p end_delay values (which are written to the
|
||||
* SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
|
||||
* respectively) are ignored at the end of a complex sequence
|
||||
* playback, indicated by the LOOPSDONE event.
|
||||
* See the @linkProductSpecification52 for more information.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
|
||||
/**< This field is defined as an union of pointers
|
||||
* to provide a convenient way to define duty
|
||||
* cycle values in various loading modes
|
||||
* (see @ref nrf_pwm_dec_load_t).
|
||||
* In each value, the most significant bit (15)
|
||||
* determines the polarity of the output and the
|
||||
* others (14-0) compose the 15-bit value to be
|
||||
* compared with the pulse generator counter. */
|
||||
uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
|
||||
uint32_t repeats; ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
|
||||
uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
|
||||
} nrf_pwm_sequence_t;
|
||||
|
||||
/**
|
||||
* @brief Helper macro for calculating the number of 16-bit values in specified
|
||||
* array of duty cycle values.
|
||||
*/
|
||||
#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific PWM task.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] task Task to activate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
|
||||
nrf_pwm_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific PWM task register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] task Requested task.
|
||||
*
|
||||
* @return Address of the specified task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
|
||||
nrf_pwm_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific PWM event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
|
||||
nrf_pwm_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific PWM event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to check.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
|
||||
nrf_pwm_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific PWM event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Requested event.
|
||||
*
|
||||
* @return Address of the specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
|
||||
nrf_pwm_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] pwm_shorts_mask Shortcuts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] pwm_shorts_mask Shortcuts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the configuration of PWM shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] pwm_shorts_mask Shortcuts configuration to set.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] pwm_int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] pwm_int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the configuration of PWM interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] pwm_int_mask Interrupts configuration to set.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] pwm_int Interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
|
||||
nrf_pwm_int_mask_t pwm_int);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the PWM peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the PWM peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for assigning pins to PWM output channels.
|
||||
*
|
||||
* Usage of all PWM output channels is optional. If a given channel is not
|
||||
* needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
|
||||
* number.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] out_pins Array with pin numbers for individual PWM output channels.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
|
||||
uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the PWM peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] base_clock Base clock frequency.
|
||||
* @param[in] mode Operating mode of the pulse generator counter.
|
||||
* @param[in] top_value Value up to which the pulse generator counter counts.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
|
||||
nrf_pwm_clk_t base_clock,
|
||||
nrf_pwm_mode_t mode,
|
||||
uint16_t top_value);
|
||||
|
||||
/**
|
||||
* @brief Function for defining a sequence of PWM duty cycles.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] seq_id Identifier of the sequence (0 or 1).
|
||||
* @param[in] p_seq Pointer to the sequence definition.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
nrf_pwm_sequence_t const * p_seq);
|
||||
|
||||
/**
|
||||
* @brief Function for modifying the pointer to the duty cycle values
|
||||
* in the specified sequence.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] seq_id Identifier of the sequence (0 or 1).
|
||||
* @param[in] p_values Pointer to an array with duty cycle values.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
uint16_t const * p_values);
|
||||
|
||||
/**
|
||||
* @brief Function for modifying the total number of duty cycle values
|
||||
* in the specified sequence.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] seq_id Identifier of the sequence (0 or 1).
|
||||
* @param[in] length Number of duty cycle values.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
uint16_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for modifying the additional number of PWM periods spent
|
||||
* on each duty cycle value in the specified sequence.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] seq_id Identifier of the sequence (0 or 1).
|
||||
* @param[in] refresh Number of additional PWM periods for each duty cycle value.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
uint32_t refresh);
|
||||
|
||||
/**
|
||||
* @brief Function for modifying the additional time added after the sequence
|
||||
* is played.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] seq_id Identifier of the sequence (0 or 1).
|
||||
* @param[in] end_delay Number of PWM periods added at the end of the sequence.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
uint32_t end_delay);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the mode of loading sequence data from RAM
|
||||
* and advancing the sequence.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] dec_load Mode of loading sequence data from RAM.
|
||||
* @param[in] dec_step Mode of advancing the active sequence.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
|
||||
nrf_pwm_dec_load_t dec_load,
|
||||
nrf_pwm_dec_step_t dec_step);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the number of times the sequence playback
|
||||
* should be performed.
|
||||
*
|
||||
* This function applies to two-sequence playback (concatenated sequence 0 and 1).
|
||||
* A single sequence can be played back only once.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] loop_count Number of times to perform the sequence playback.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
|
||||
uint16_t loop_count);
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
|
||||
nrf_pwm_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
|
||||
nrf_pwm_task_t task)
|
||||
{
|
||||
return ((uint32_t)p_reg + (uint32_t)task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
|
||||
nrf_pwm_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
|
||||
nrf_pwm_event_t event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
|
||||
nrf_pwm_event_t event)
|
||||
{
|
||||
return ((uint32_t)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS |= pwm_shorts_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS &= ~(pwm_shorts_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS = pwm_shorts_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_int_mask)
|
||||
{
|
||||
p_reg->INTENSET = pwm_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = pwm_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
|
||||
uint32_t pwm_int_mask)
|
||||
{
|
||||
p_reg->INTEN = pwm_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
|
||||
nrf_pwm_int_mask_t pwm_int)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & pwm_int);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
|
||||
uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
|
||||
{
|
||||
p_reg->PSEL.OUT[i] = out_pins[i];
|
||||
}
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
|
||||
nrf_pwm_clk_t base_clock,
|
||||
nrf_pwm_mode_t mode,
|
||||
uint16_t top_value)
|
||||
{
|
||||
ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
|
||||
|
||||
p_reg->PRESCALER = base_clock;
|
||||
p_reg->MODE = mode;
|
||||
p_reg->COUNTERTOP = top_value;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
nrf_pwm_sequence_t const * p_seq)
|
||||
{
|
||||
ASSERT(p_seq != NULL);
|
||||
|
||||
nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw);
|
||||
nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length);
|
||||
nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats);
|
||||
nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
uint16_t const * p_values)
|
||||
{
|
||||
ASSERT(seq_id <= 1);
|
||||
ASSERT(p_values != NULL);
|
||||
p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
uint16_t length)
|
||||
{
|
||||
ASSERT(seq_id <= 1);
|
||||
ASSERT(length != 0);
|
||||
ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
|
||||
p_reg->SEQ[seq_id].CNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
uint32_t refresh)
|
||||
{
|
||||
ASSERT(seq_id <= 1);
|
||||
ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
|
||||
p_reg->SEQ[seq_id].REFRESH = refresh;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
|
||||
uint8_t seq_id,
|
||||
uint32_t end_delay)
|
||||
{
|
||||
ASSERT(seq_id <= 1);
|
||||
ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
|
||||
p_reg->SEQ[seq_id].ENDDELAY = end_delay;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
|
||||
nrf_pwm_dec_load_t dec_load,
|
||||
nrf_pwm_dec_step_t dec_step)
|
||||
{
|
||||
p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
|
||||
((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
|
||||
uint16_t loop_count)
|
||||
{
|
||||
p_reg->LOOP = loop_count;
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_PWM_H__
|
||||
|
||||
/** @} */
|
||||
504
lib/sdk/components/drivers_nrf/hal/nrf_qdec.h
Normal file
504
lib/sdk/components/drivers_nrf/hal/nrf_qdec.h
Normal file
@ -0,0 +1,504 @@
|
||||
/**
|
||||
* Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_QDEC_H__
|
||||
#define NRF_QDEC_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include "nrf_error.h"
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
/**
|
||||
* @defgroup nrf_qdec_hal QDEC HAL
|
||||
* @{
|
||||
* @ingroup nrf_qdec
|
||||
* @brief Hardware access layer for accessing the quadrature decoder (QDEC) peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @enum nrf_qdec_task_t
|
||||
* @brief QDEC tasks.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_QDEC_TASK_START = offsetof(NRF_QDEC_Type, TASKS_START), /**< Starting the quadrature decoder. */
|
||||
NRF_QDEC_TASK_STOP = offsetof(NRF_QDEC_Type, TASKS_STOP), /**< Stopping the quadrature decoder. */
|
||||
NRF_QDEC_TASK_READCLRACC = offsetof(NRF_QDEC_Type, TASKS_READCLRACC) /**< Reading and clearing ACC and ACCDBL registers. */
|
||||
} nrf_qdec_task_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_qdec_event_t
|
||||
* @brief QDEC events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QDEC_EVENT_SAMPLERDY = offsetof(NRF_QDEC_Type, EVENTS_SAMPLERDY), /**< Event generated for every new sample. */
|
||||
NRF_QDEC_EVENT_REPORTRDY = offsetof(NRF_QDEC_Type, EVENTS_REPORTRDY), /**< Event generated for every new report. */
|
||||
NRF_QDEC_EVENT_ACCOF = offsetof(NRF_QDEC_Type, EVENTS_ACCOF) /**< Event generated for every accumulator overflow. */
|
||||
} nrf_qdec_event_t; /*lint -restore */
|
||||
|
||||
/**
|
||||
* @enum nrf_qdec_short_mask_t
|
||||
* @brief QDEC shortcuts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK = QDEC_SHORTS_REPORTRDY_READCLRACC_Msk, /**< Shortcut between REPORTRDY event and READCLRACC task. */
|
||||
NRF_QDEC_SHORT_SAMPLERDY_STOP_MASK = QDEC_SHORTS_SAMPLERDY_STOP_Msk /**< Shortcut between SAMPLERDY event and STOP task. */
|
||||
} nrf_qdec_short_mask_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_qdec_int_mask_t
|
||||
* @brief QDEC interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QDEC_INT_SAMPLERDY_MASK = QDEC_INTENSET_SAMPLERDY_Msk, /**< Mask for enabling or disabling an interrupt on SAMPLERDY event. */
|
||||
NRF_QDEC_INT_REPORTRDY_MASK = QDEC_INTENSET_REPORTRDY_Msk, /**< Mask for enabling or disabling an interrupt on REPORTRDY event. */
|
||||
NRF_QDEC_INT_ACCOF_MASK = QDEC_INTENSET_ACCOF_Msk /**< Mask for enabling or disabling an interrupt on ACCOF event. */
|
||||
} nrf_qdec_int_mask_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_qdec_enable_t
|
||||
* @brief States of the enable bit.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QDEC_DISABLE = QDEC_ENABLE_ENABLE_Disabled, /**< Mask for disabling the QDEC periperal. When disabled, the QDEC decoder pins are not active. */
|
||||
NRF_QDEC_ENABLE = QDEC_ENABLE_ENABLE_Enabled /**< Mask for enabling the QDEC periperal. When enabled, the QDEC pins are active. */
|
||||
} nrf_qdec_enable_t;
|
||||
|
||||
|
||||
/**
|
||||
* @enum nrf_qdec_dbfen_t
|
||||
* @brief States of the debounce filter enable bit.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QDEC_DBFEN_DISABLE = QDEC_DBFEN_DBFEN_Disabled, /**< Mask for disabling the debounce filter. */
|
||||
NRF_QDEC_DBFEN_ENABLE = QDEC_DBFEN_DBFEN_Enabled /**< Mask for enabling the debounce filter. */
|
||||
} nrf_qdec_dbfen_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_qdec_ledpol_t
|
||||
* @brief Active LED polarity.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QDEC_LEPOL_ACTIVE_LOW = QDEC_LEDPOL_LEDPOL_ActiveLow, /**< QDEC LED active on output pin low. */
|
||||
NRF_QDEC_LEPOL_ACTIVE_HIGH = QDEC_LEDPOL_LEDPOL_ActiveHigh /**< QDEC LED active on output pin high. */
|
||||
} nrf_qdec_ledpol_t;
|
||||
|
||||
|
||||
/**
|
||||
* @enum nrf_qdec_sampleper_t
|
||||
* @brief Available sampling periods.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QDEC_SAMPLEPER_128us = QDEC_SAMPLEPER_SAMPLEPER_128us, /**< QDEC sampling period 128 microseconds. */
|
||||
NRF_QDEC_SAMPLEPER_256us = QDEC_SAMPLEPER_SAMPLEPER_256us, /**< QDEC sampling period 256 microseconds. */
|
||||
NRF_QDEC_SAMPLEPER_512us = QDEC_SAMPLEPER_SAMPLEPER_512us, /**< QDEC sampling period 512 microseconds. */
|
||||
NRF_QDEC_SAMPLEPER_1024us = QDEC_SAMPLEPER_SAMPLEPER_1024us, /**< QDEC sampling period 1024 microseconds. */
|
||||
NRF_QDEC_SAMPLEPER_2048us = QDEC_SAMPLEPER_SAMPLEPER_2048us, /**< QDEC sampling period 2048 microseconds. */
|
||||
NRF_QDEC_SAMPLEPER_4096us = QDEC_SAMPLEPER_SAMPLEPER_4096us, /**< QDEC sampling period 4096 microseconds. */
|
||||
NRF_QDEC_SAMPLEPER_8192us = QDEC_SAMPLEPER_SAMPLEPER_8192us, /**< QDEC sampling period 8192 microseconds. */
|
||||
NRF_QDEC_SAMPLEPER_16384us = QDEC_SAMPLEPER_SAMPLEPER_16384us /**< QDEC sampling period 16384 microseconds. */
|
||||
} nrf_qdec_sampleper_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_qdec_reportper_t
|
||||
* @brief Available report periods.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QDEC_REPORTPER_10 = QDEC_REPORTPER_REPORTPER_10Smpl, /**< QDEC report period 10 samples. */
|
||||
NRF_QDEC_REPORTPER_40 = QDEC_REPORTPER_REPORTPER_40Smpl, /**< QDEC report period 40 samples. */
|
||||
NRF_QDEC_REPORTPER_80 = QDEC_REPORTPER_REPORTPER_80Smpl, /**< QDEC report period 80 samples. */
|
||||
NRF_QDEC_REPORTPER_120 = QDEC_REPORTPER_REPORTPER_120Smpl, /**< QDEC report period 120 samples. */
|
||||
NRF_QDEC_REPORTPER_160 = QDEC_REPORTPER_REPORTPER_160Smpl, /**< QDEC report period 160 samples. */
|
||||
NRF_QDEC_REPORTPER_200 = QDEC_REPORTPER_REPORTPER_200Smpl, /**< QDEC report period 200 samples. */
|
||||
NRF_QDEC_REPORTPER_240 = QDEC_REPORTPER_REPORTPER_240Smpl, /**< QDEC report period 240 samples. */
|
||||
NRF_QDEC_REPORTPER_280 = QDEC_REPORTPER_REPORTPER_280Smpl, /**< QDEC report period 280 samples. */
|
||||
NRF_QDEC_REPORTPER_DISABLED /**< QDEC reporting disabled. */
|
||||
} nrf_qdec_reportper_t;
|
||||
|
||||
/**
|
||||
* @brief Function for enabling QDEC.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_enable(void)
|
||||
{
|
||||
NRF_QDEC->ENABLE = NRF_QDEC_ENABLE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling QDEC.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_disable(void)
|
||||
{
|
||||
NRF_QDEC->ENABLE = NRF_QDEC_DISABLE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the enable state of QDEC.
|
||||
* @return State of the register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_enable_get(void)
|
||||
{
|
||||
return NRF_QDEC->ENABLE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling QDEC interrupts by mask.
|
||||
* @param[in] qdec_int_mask Sources of the interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_int_enable(uint32_t qdec_int_mask)
|
||||
{
|
||||
NRF_QDEC->INTENSET = qdec_int_mask; // writing 0 has no effect
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling QDEC interrupts by mask.
|
||||
* @param[in] qdec_int_mask Sources of the interrupts to disable.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_int_disable(uint32_t qdec_int_mask)
|
||||
{
|
||||
NRF_QDEC->INTENCLR = qdec_int_mask; // writing 0 has no effect
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the enabled interrupts of the QDEC.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t qdec_int_mask)
|
||||
{
|
||||
return NRF_QDEC->INTENSET & qdec_int_mask; // when read this register will return the value of INTEN.
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the debouncing filter of the QED.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_dbfen_enable(void)
|
||||
{
|
||||
NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_ENABLE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the debouncing filter of the QED.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_dbfen_disable(void)
|
||||
{
|
||||
NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_DISABLE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the state of the QDEC's debouncing filter.
|
||||
* @retval NRF_QDEC_DBFEN_DISABLE If the debouncing filter is disabled.
|
||||
* @retval NRF_QDEC_DBFEN_ENABLE If the debouncing filter is enabled.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void)
|
||||
{
|
||||
return NRF_QDEC->DBFEN;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for assigning QDEC pins.
|
||||
* @param[in] psela Pin number.
|
||||
* @param[in] pselb Pin number.
|
||||
* @param[in] pselled Pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled)
|
||||
{
|
||||
NRF_QDEC->PSELA = psela;
|
||||
NRF_QDEC->PSELB = pselb;
|
||||
NRF_QDEC->PSELLED = pselled;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for setting a specific QDEC task.
|
||||
* @param[in] qdec_task QDEC task to be set.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task)
|
||||
{
|
||||
*( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task) ) = 1;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the address of a QDEC task register.
|
||||
* @param[in] qdec_task QDEC task.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t qdec_task)
|
||||
{
|
||||
return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific QDEC event.
|
||||
* @param[in] qdec_event QDEC event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t qdec_event)
|
||||
{
|
||||
*( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event) ) = 0;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_QDEC + qdec_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a specific QDEC event.
|
||||
* @return State of the QDEC event.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t qdec_event)
|
||||
{
|
||||
return *(volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the address of a specific QDEC event register.
|
||||
* @param[in] qdec_event QDEC event.
|
||||
* @return Address of the specified QDEC event.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t qdec_event)
|
||||
{
|
||||
return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting QDEC shortcuts.
|
||||
* @param[in] qdec_short_mask QDEC shortcut by mask.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t qdec_short_mask)
|
||||
{
|
||||
NRF_QDEC->SHORTS |= qdec_short_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing shortcuts of the QDEC by mask.
|
||||
* @param[in] qdec_short_mask QDEC shortcute to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t qdec_short_mask)
|
||||
{
|
||||
NRF_QDEC->SHORTS &= ~qdec_short_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the value of QDEC's SAMPLEPER register.
|
||||
* @return Value of the SAMPLEPER register.
|
||||
*/
|
||||
__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void)
|
||||
{
|
||||
return NRF_QDEC->SAMPLEPER;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for converting the value of QDEC's SAMPLE PERIOD to microseconds.
|
||||
* @retval sampling period in microseconds.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_sampleper_to_value(uint32_t sampleper)
|
||||
{
|
||||
return (1 << (7 + sampleper));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for setting the value of QDEC's SAMPLEPER register.
|
||||
* @param[in] sample_per Sampling period.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_sampleper_set(nrf_qdec_sampleper_t sample_per)
|
||||
{
|
||||
NRF_QDEC->SAMPLEPER = sample_per;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the value of QDEC's SAMPLE register.
|
||||
* @return Value of the SAMPLE register.
|
||||
*/
|
||||
__STATIC_INLINE int32_t nrf_qdec_sample_get(void)
|
||||
{
|
||||
return NRF_QDEC->SAMPLE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the value of QDEC's ACC register.
|
||||
* @return Value of the ACC register.
|
||||
*/
|
||||
__STATIC_INLINE int32_t nrf_qdec_acc_get(void)
|
||||
{
|
||||
return NRF_QDEC->ACC;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the value of QDEC's ACCREAD register.
|
||||
* @return Value of the ACCREAD register.
|
||||
*/
|
||||
__STATIC_INLINE int32_t nrf_qdec_accread_get(void)
|
||||
{
|
||||
return NRF_QDEC->ACCREAD;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the value of QDEC's ACCDBL register.
|
||||
* @return Value of the ACCDBL register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_accdbl_get(void)
|
||||
{
|
||||
return NRF_QDEC->ACCDBL;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the value of QDEC's ACCDBLREAD register.
|
||||
* @return Value of the ACCDBLREAD register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_accdblread_get(void)
|
||||
{
|
||||
return NRF_QDEC->ACCDBLREAD;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting how long the LED is switched on before sampling.
|
||||
* @param[in] time_us Time (in microseconds) how long the LED is switched on before sampling.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_ledpre_set(uint32_t time_us)
|
||||
{
|
||||
NRF_QDEC->LEDPRE = time_us;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving how long the LED is switched on before sampling.
|
||||
* @retval time_us Time (in microseconds) how long the LED is switched on before sampling.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_ledpre_get(void)
|
||||
{
|
||||
return NRF_QDEC->LEDPRE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the report period (in samples).
|
||||
* @param[in] reportper Number of samples.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_reportper_set(nrf_qdec_reportper_t reportper)
|
||||
{
|
||||
NRF_QDEC->REPORTPER = reportper;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the report period.
|
||||
* @retval reportper Number of samples as encoded in the register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_reportper_reg_get(void)
|
||||
{
|
||||
return NRF_QDEC->REPORTPER;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the value of QDEC's SAMPLEPER register.
|
||||
* @param [in] reportper Reportper to be converted to amount of samples per report.
|
||||
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_reportper_to_value(uint32_t reportper)
|
||||
{
|
||||
return (reportper == NRF_QDEC_REPORTPER_10) ? 10 : reportper * 40;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the active level for the LED.
|
||||
* @param[in] pol Active level for the LED.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qdec_ledpol_set(nrf_qdec_ledpol_t pol)
|
||||
{
|
||||
NRF_QDEC->LEDPOL = pol;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the active level for the LED.
|
||||
* @return Active level for the LED.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void)
|
||||
{
|
||||
return NRF_QDEC->LEDPOL;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
765
lib/sdk/components/drivers_nrf/hal/nrf_qspi.h
Normal file
765
lib/sdk/components/drivers_nrf/hal/nrf_qspi.h
Normal file
@ -0,0 +1,765 @@
|
||||
/**
|
||||
* Copyright (c) 2016 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @defgroup nrf_qspi_hal QSPI HAL
|
||||
* @{
|
||||
* @ingroup nrf_qspi
|
||||
*
|
||||
* @brief Hardware access layer for accessing the QSPI peripheral.
|
||||
*/
|
||||
|
||||
#ifndef NRF_QSPI_H__
|
||||
#define NRF_QSPI_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include "boards.h"
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set
|
||||
* function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3)
|
||||
* will not be connected to a physical pin.
|
||||
*/
|
||||
#define NRF_QSPI_PIN_NOT_CONNECTED 0xFF
|
||||
|
||||
/**
|
||||
* @brief Macro for setting proper values to pin registers.
|
||||
*/
|
||||
|
||||
#define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin)
|
||||
|
||||
/**
|
||||
* @brief QSPI tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */
|
||||
NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */
|
||||
NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */
|
||||
NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */
|
||||
/*lint -restore*/
|
||||
} nrf_qspi_task_t;
|
||||
|
||||
/**
|
||||
* @brief QSPI events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */
|
||||
/*lint -restore*/
|
||||
} nrf_qspi_event_t;
|
||||
|
||||
/**
|
||||
* @brief QSPI interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */
|
||||
} nrf_qspi_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief QSPI frequency divider values.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QSPI_FREQ_32MDIV1, /**< 32.0 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV2, /**< 16.0 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV3, /**< 10.6 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV4, /**< 8.00 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV5, /**< 6.40 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV6, /**< 5.33 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV7, /**< 4.57 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV8, /**< 4.00 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV9, /**< 3.55 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV10, /**< 3.20 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV11, /**< 2.90 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV12, /**< 2.66 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV13, /**< 2.46 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV14, /**< 2.29 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV15, /**< 2.13 MHz. */
|
||||
NRF_QSPI_FREQ_32MDIV16, /**< 2.00 MHz. */
|
||||
} nrf_qspi_frequency_t;
|
||||
|
||||
/**
|
||||
* @brief Interface configuration for a read operation.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */
|
||||
NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O, /**< Dual data line SPI. READ2O (opcode 0x3B). */
|
||||
NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO, /**< Dual data line SPI. READ2IO (opcode 0xBB). */
|
||||
NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O, /**< Quad data line SPI. READ4O (opcode 0x6B). */
|
||||
NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */
|
||||
} nrf_qspi_readoc_t;
|
||||
|
||||
/**
|
||||
* @brief Interface configuration for a write operation.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */
|
||||
NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O, /**< Dual data line SPI. PP2O (opcode 0xA2). */
|
||||
NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O, /**< Quad data line SPI. PP4O (opcode 0x32). */
|
||||
NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */
|
||||
} nrf_qspi_writeoc_t;
|
||||
|
||||
/**
|
||||
* @brief Interface configuration for addressing mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */
|
||||
NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */
|
||||
} nrf_qspi_addrmode_t;
|
||||
|
||||
/**
|
||||
* @brief QSPI SPI mode. Polarization and phase configuration.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */
|
||||
NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */
|
||||
} nrf_qspi_spi_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Addressing configuration mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */
|
||||
NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode, /**< Send opcode. */
|
||||
NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0, /**< Send opcode, byte0. */
|
||||
NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */
|
||||
} nrf_qspi_addrconfig_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Erasing data length.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */
|
||||
NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB, /**< Erase 64 kB block (flash command 0xD8). */
|
||||
NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */
|
||||
} nrf_qspi_erase_len_t;
|
||||
|
||||
/**
|
||||
* @brief Custom instruction length.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */
|
||||
NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B, /**< Send opcode, CINSTRDAT0.BYTE0. */
|
||||
NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */
|
||||
NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */
|
||||
NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */
|
||||
NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */
|
||||
NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */
|
||||
NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */
|
||||
NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */
|
||||
} nrf_qspi_cinstr_len_t;
|
||||
|
||||
/**
|
||||
* @brief Pins configuration.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t sck_pin; /**< SCK pin number. */
|
||||
uint8_t csn_pin; /**< Chip select pin number. */
|
||||
uint8_t io0_pin; /**< IO0/MOSI pin number. */
|
||||
uint8_t io1_pin; /**< IO1/MISO pin number. */
|
||||
uint8_t io2_pin; /**< IO2 pin number (optional).
|
||||
* Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
|
||||
*/
|
||||
uint8_t io3_pin; /**< IO3 pin number (optional).
|
||||
* Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
|
||||
*/
|
||||
} nrf_qspi_pins_t;
|
||||
|
||||
/**
|
||||
* @brief Custom instruction configuration.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t opcode; /**< Opcode used in custom instruction transmission. */
|
||||
nrf_qspi_cinstr_len_t length; /**< Length of the custom instruction data. */
|
||||
bool io2_level; /**< I/O line level during transmission. */
|
||||
bool io3_level; /**< I/O line level during transmission. */
|
||||
bool wipwait; /**< Wait if a Wait in Progress bit is set in the memory status byte. */
|
||||
bool wren; /**< Send write enable before instruction. */
|
||||
} nrf_qspi_cinstr_conf_t;
|
||||
|
||||
/**
|
||||
* @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t opcode; /**< Opcode used to enter proper addressing mode. */
|
||||
uint8_t byte0; /**< Byte following the opcode. */
|
||||
uint8_t byte1; /**< Byte following byte0. */
|
||||
nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */
|
||||
bool wipwait; /**< Enable/disable waiting for complete operation execution. */
|
||||
bool wren; /**< Send write enable before instruction. */
|
||||
} nrf_qspi_addrconfig_conf_t;
|
||||
|
||||
/**
|
||||
* @brief Structure with QSPI protocol interface configuration.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
nrf_qspi_readoc_t readoc; /**< Read operation code. */
|
||||
nrf_qspi_writeoc_t writeoc; /**< Write operation code. */
|
||||
nrf_qspi_addrmode_t addrmode; /**< Addresing mode (24-bit or 32-bit). */
|
||||
bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */
|
||||
} nrf_qspi_prot_conf_t;
|
||||
|
||||
/**
|
||||
* @brief QSPI physical interface configuration.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */
|
||||
bool dpmen; /**< Enable the DPM feature. */
|
||||
nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */
|
||||
nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as enum @ref nrf_qspi_frequency_t. */
|
||||
} nrf_qspi_phy_conf_t;
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific QSPI task.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] task Task to activate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific QSPI task register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] task Requested task.
|
||||
*
|
||||
* @return Address of the specified task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
|
||||
nrf_qspi_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific QSPI event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] qspi_event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific SPI event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] qspi_event Event to check.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific QSPI event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] qspi_event Requested event.
|
||||
*
|
||||
* @return Address of the specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
|
||||
nrf_qspi_event_t qspi_event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] qspi_int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] qspi_int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] qspi_int Interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
|
||||
nrf_qspi_int_mask_t qspi_int);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the QSPI peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the QSPI peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring QSPI pins.
|
||||
*
|
||||
* If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED
|
||||
* value instead of its pin number.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
|
||||
const nrf_qspi_pins_t * p_pins);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the QSPI IFCONFIG0 register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] p_config Pointer to the QSPI protocol interface configuration structure. See @ref nrf_qspi_prot_conf_t.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
|
||||
const nrf_qspi_prot_conf_t * p_config);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the QSPI IFCONFIG1 register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] p_config Pointer to the QSPI physical interface configuration structure. See @ref nrf_qspi_phy_conf_t.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
|
||||
const nrf_qspi_phy_conf_t * p_config);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the QSPI ADDRCONF register.
|
||||
*
|
||||
* Function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure
|
||||
* is sent during the start of the peripheral. Remember that the reset instruction can set
|
||||
* addressing mode to default in the memory device. If memory reset is necessary before configuring
|
||||
* the addressing mode, use custom instruction feature instead of this function.
|
||||
* Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions
|
||||
* using a custom instruction feature (reset enable and then reset), set proper addressing mode
|
||||
* using the custom instruction feature.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] p_config Pointer to the addressing mode configuration structure. See @ref nrf_qspi_addrconfig_conf_t.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
|
||||
const nrf_qspi_addrconfig_conf_t * p_config);
|
||||
|
||||
/**
|
||||
* @brief Function for setting write data into the peripheral register (without starting the process).
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] p_buffer Pointer to the writing buffer.
|
||||
* @param[in] length Lenght of the writing data.
|
||||
* @param[in] dest_addr Address in memory to write to.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
|
||||
void const * p_buffer,
|
||||
uint32_t length,
|
||||
uint32_t dest_addr);
|
||||
|
||||
/**
|
||||
* @brief Function for setting read data into the peripheral register (without starting the process).
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[out] p_buffer Pointer to the reading buffer.
|
||||
* @param[in] length Length of the read data.
|
||||
* @param[in] src_addr Address in memory to read from.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
|
||||
void * p_buffer,
|
||||
uint32_t length,
|
||||
uint32_t src_addr);
|
||||
|
||||
/**
|
||||
* @brief Function for setting erase data into the peripheral register (without starting the process).
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes.
|
||||
* @param[in] len Size of erasing area.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
|
||||
uint32_t erase_addr,
|
||||
nrf_qspi_erase_len_t len);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the peripheral status register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
*
|
||||
* @return Peripheral status register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the device status register stored in the peripheral status register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
*
|
||||
* @return Device status register (lower byte).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for checking if the peripheral is busy or not.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
*
|
||||
* @retval true If QSPI is busy.
|
||||
* @retval false If QSPI is ready.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting registers sending with custom instruction transmission.
|
||||
*
|
||||
* This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument
|
||||
* (sending only opcode without data).
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] length Length of the custom instruction data.
|
||||
* @param[in] p_tx_data Pointer to the data to send with the custom instruction.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
|
||||
nrf_qspi_cinstr_len_t length,
|
||||
void const * p_tx_data);
|
||||
|
||||
/**
|
||||
* @brief Function for getting data from register after custom instruction transmission.
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] length Length of the custom instruction data.
|
||||
* @param[in] p_rx_data Pointer to the reading buffer.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
|
||||
nrf_qspi_cinstr_len_t length,
|
||||
void * p_rx_data);
|
||||
|
||||
/**
|
||||
* @brief Function for sending custom instruction to external memory.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral register structure.
|
||||
* @param[in] p_config Pointer to the custom instruction configuration structure. See @ref nrf_qspi_cinstr_conf_t.
|
||||
*/
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
|
||||
const nrf_qspi_cinstr_conf_t * p_config);
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
|
||||
nrf_qspi_task_t task)
|
||||
{
|
||||
return ((uint32_t)p_reg + (uint32_t)task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event)) = 0x0UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
|
||||
nrf_qspi_event_t qspi_event)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask)
|
||||
{
|
||||
p_reg->INTENSET = qspi_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = qspi_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
|
||||
nrf_qspi_int_mask_t qspi_int)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & qspi_int);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, const nrf_qspi_pins_t * p_pins)
|
||||
{
|
||||
p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin);
|
||||
p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin);
|
||||
p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin);
|
||||
p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin);
|
||||
p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin);
|
||||
p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
|
||||
const nrf_qspi_prot_conf_t * p_config)
|
||||
{
|
||||
uint32_t config = p_config->readoc;
|
||||
config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos;
|
||||
config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos;
|
||||
config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos;
|
||||
|
||||
p_reg->IFCONFIG0 = config;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
|
||||
const nrf_qspi_phy_conf_t * p_config)
|
||||
{
|
||||
// IFCONFIG1 mask for reserved fields in the register.
|
||||
uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
|
||||
config |= p_config->sck_delay;
|
||||
config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos;
|
||||
config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos;
|
||||
config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos;
|
||||
|
||||
p_reg->IFCONFIG1 = config;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
|
||||
const nrf_qspi_addrconfig_conf_t * p_config)
|
||||
{
|
||||
uint32_t config = p_config->opcode;
|
||||
config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos;
|
||||
config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos;
|
||||
config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos;
|
||||
config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos;
|
||||
config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos;
|
||||
|
||||
p_reg->ADDRCONF = config;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
|
||||
void const * p_buffer,
|
||||
uint32_t length,
|
||||
uint32_t dest_addr)
|
||||
{
|
||||
p_reg->WRITE.DST = dest_addr;
|
||||
p_reg->WRITE.SRC = (uint32_t) p_buffer;
|
||||
p_reg->WRITE.CNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
|
||||
void * p_buffer,
|
||||
uint32_t length,
|
||||
uint32_t src_addr)
|
||||
{
|
||||
p_reg->READ.SRC = src_addr;
|
||||
p_reg->READ.DST = (uint32_t) p_buffer;
|
||||
p_reg->READ.CNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
|
||||
uint32_t erase_addr,
|
||||
nrf_qspi_erase_len_t len)
|
||||
{
|
||||
p_reg->ERASE.PTR = erase_addr;
|
||||
p_reg->ERASE.LEN = len;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)
|
||||
{
|
||||
return p_reg->STATUS;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)
|
||||
{
|
||||
return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)
|
||||
{
|
||||
return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >>
|
||||
QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
|
||||
nrf_qspi_cinstr_len_t length,
|
||||
void const * p_tx_data)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data;
|
||||
|
||||
// Load custom instruction.
|
||||
switch (length)
|
||||
{
|
||||
case NRF_QSPI_CINSTR_LEN_9B:
|
||||
reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos;
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_8B:
|
||||
reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos;
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_7B:
|
||||
reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos;
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_6B:
|
||||
reg |= ((uint32_t)p_tx_data_8[4]);
|
||||
p_reg->CINSTRDAT1 = reg;
|
||||
reg = 0;
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_5B:
|
||||
reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos;
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_4B:
|
||||
reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos;
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_3B:
|
||||
reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos;
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_2B:
|
||||
reg |= ((uint32_t)p_tx_data_8[0]);
|
||||
p_reg->CINSTRDAT0 = reg;
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_1B:
|
||||
/* Send only opcode. Case to avoid compiler warnings. */
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
|
||||
nrf_qspi_cinstr_len_t length,
|
||||
void * p_rx_data)
|
||||
{
|
||||
uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data;
|
||||
|
||||
uint32_t reg = p_reg->CINSTRDAT1;
|
||||
switch (length)
|
||||
{
|
||||
case NRF_QSPI_CINSTR_LEN_9B:
|
||||
p_rx_data_8[7] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE7_Pos);
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_8B:
|
||||
p_rx_data_8[6] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE6_Pos);
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_7B:
|
||||
p_rx_data_8[5] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE5_Pos);
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_6B:
|
||||
p_rx_data_8[4] = (uint8_t)(reg);
|
||||
/* fall-through */
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
reg = p_reg->CINSTRDAT0;
|
||||
switch (length)
|
||||
{
|
||||
case NRF_QSPI_CINSTR_LEN_5B:
|
||||
p_rx_data_8[3] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE3_Pos);
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_4B:
|
||||
p_rx_data_8[2] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE2_Pos);
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_3B:
|
||||
p_rx_data_8[1] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE1_Pos);
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_2B:
|
||||
p_rx_data_8[0] = (uint8_t)(reg);
|
||||
/* fall-through */
|
||||
case NRF_QSPI_CINSTR_LEN_1B:
|
||||
/* Send only opcode. Case to avoid compiler warnings. */
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
|
||||
const nrf_qspi_cinstr_conf_t * p_config)
|
||||
{
|
||||
p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
|
||||
((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
|
||||
((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
|
||||
((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
|
||||
((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
|
||||
((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos));
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_QSPI_H__
|
||||
|
||||
/** @} */
|
||||
282
lib/sdk/components/drivers_nrf/hal/nrf_rng.h
Normal file
282
lib/sdk/components/drivers_nrf/hal/nrf_rng.h
Normal file
@ -0,0 +1,282 @@
|
||||
/**
|
||||
* Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief RNG HAL API.
|
||||
*/
|
||||
|
||||
#ifndef NRF_RNG_H__
|
||||
#define NRF_RNG_H__
|
||||
/**
|
||||
* @defgroup nrf_rng_hal RNG HAL
|
||||
* @{
|
||||
* @ingroup nrf_rng
|
||||
* @brief Hardware access layer for managing the random number generator (RNG).
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NRF_RNG_TASK_SET (1UL)
|
||||
#define NRF_RNG_EVENT_CLEAR (0UL)
|
||||
/**
|
||||
* @enum nrf_rng_task_t
|
||||
* @brief RNG tasks.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_RNG_TASK_START = offsetof(NRF_RNG_Type, TASKS_START), /**< Start the random number generator. */
|
||||
NRF_RNG_TASK_STOP = offsetof(NRF_RNG_Type, TASKS_STOP) /**< Stop the random number generator. */
|
||||
} nrf_rng_task_t; /*lint -restore */
|
||||
|
||||
/**
|
||||
* @enum nrf_rng_event_t
|
||||
* @brief RNG events.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_RNG_EVENT_VALRDY = offsetof(NRF_RNG_Type, EVENTS_VALRDY) /**< New random number generated event. */
|
||||
} nrf_rng_event_t; /*lint -restore */
|
||||
|
||||
/**
|
||||
* @enum nrf_rng_int_mask_t
|
||||
* @brief RNG interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_RNG_INT_VALRDY_MASK = RNG_INTENSET_VALRDY_Msk /**< Mask for enabling or disabling an interrupt on VALRDY event. */
|
||||
} nrf_rng_int_mask_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_rng_short_mask_t
|
||||
* @brief Types of RNG shortcuts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_RNG_SHORT_VALRDY_STOP_MASK = RNG_SHORTS_VALRDY_STOP_Msk /**< Mask for setting shortcut between EVENT_VALRDY and TASK_STOP. */
|
||||
} nrf_rng_short_mask_t;
|
||||
|
||||
/**
|
||||
* @brief Function for enabling interrupts.
|
||||
*
|
||||
* @param[in] rng_int_mask Mask of interrupts.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling interrupts.
|
||||
*
|
||||
* @param[in] rng_int_mask Mask of interrupts.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the state of a specific interrupt.
|
||||
*
|
||||
* @param[in] rng_int_mask Interrupt.
|
||||
*
|
||||
* @retval true If the interrupt is not enabled.
|
||||
* @retval false If the interrupt is enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific task.
|
||||
*
|
||||
* This function can be used by the PPI module.
|
||||
*
|
||||
* @param[in] rng_task Task.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task);
|
||||
|
||||
/**
|
||||
* @brief Function for setting a specific task.
|
||||
*
|
||||
* @param[in] rng_task Task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting address of a specific event.
|
||||
*
|
||||
* This function can be used by the PPI module.
|
||||
*
|
||||
* @param[in] rng_event Event.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific event.
|
||||
*
|
||||
* @param[in] rng_event Event.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the state of a specific event.
|
||||
*
|
||||
* @param[in] rng_event Event.
|
||||
*
|
||||
* @retval true If the event is not set.
|
||||
* @retval false If the event is set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event);
|
||||
|
||||
/**
|
||||
* @brief Function for setting shortcuts.
|
||||
*
|
||||
* @param[in] rng_short_mask Mask of shortcuts.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing shortcuts.
|
||||
*
|
||||
* @param[in] rng_short_mask Mask of shortcuts.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the previously generated random value.
|
||||
*
|
||||
* @return Previously generated random value.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t nrf_rng_random_value_get(void);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling digital error correction.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rng_error_correction_enable(void);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling digital error correction.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rng_error_correction_disable(void);
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask)
|
||||
{
|
||||
NRF_RNG->INTENSET = rng_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask)
|
||||
{
|
||||
NRF_RNG->INTENCLR = rng_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask)
|
||||
{
|
||||
return (bool)(NRF_RNG->INTENCLR & rng_int_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)NRF_RNG + rng_task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_task)) = NRF_RNG_TASK_SET;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)NRF_RNG + rng_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)) = NRF_RNG_EVENT_CLEAR;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event)
|
||||
{
|
||||
return (bool) * ((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event));
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask)
|
||||
{
|
||||
NRF_RNG->SHORTS |= rng_short_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask)
|
||||
{
|
||||
NRF_RNG->SHORTS &= ~rng_short_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint8_t nrf_rng_random_value_get(void)
|
||||
{
|
||||
return (uint8_t)(NRF_RNG->VALUE & RNG_VALUE_VALUE_Msk);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rng_error_correction_enable(void)
|
||||
{
|
||||
NRF_RNG->CONFIG |= RNG_CONFIG_DERCEN_Msk;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rng_error_correction_disable(void)
|
||||
{
|
||||
NRF_RNG->CONFIG &= ~RNG_CONFIG_DERCEN_Msk;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* NRF_RNG_H__ */
|
||||
343
lib/sdk/components/drivers_nrf/hal/nrf_rtc.h
Normal file
343
lib/sdk/components/drivers_nrf/hal/nrf_rtc.h
Normal file
@ -0,0 +1,343 @@
|
||||
/**
|
||||
* Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief RTC HAL API.
|
||||
*/
|
||||
|
||||
#ifndef NRF_RTC_H
|
||||
#define NRF_RTC_H
|
||||
|
||||
/**
|
||||
* @defgroup nrf_rtc_hal RTC HAL
|
||||
* @{
|
||||
* @ingroup nrf_rtc
|
||||
* @brief Hardware access layer for managing the real time counter (RTC).
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_assert.h"
|
||||
#include "nrf_peripherals.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Macro for getting the number of compare channels available
|
||||
* in a given RTC instance.
|
||||
*/
|
||||
|
||||
#define NRF_RTC_CC_CHANNEL_COUNT(id) CONCAT_3(RTC, id, _CC_NUM)
|
||||
|
||||
#define RTC_INPUT_FREQ 32768 /**< Input frequency of the RTC instance. */
|
||||
|
||||
/**
|
||||
* @brief Macro for converting expected frequency to prescaler setting.
|
||||
*/
|
||||
#define RTC_FREQ_TO_PRESCALER(FREQ) (uint16_t)(((RTC_INPUT_FREQ) / (FREQ)) - 1)
|
||||
|
||||
/**< Macro for wrapping values to RTC capacity. */
|
||||
#define RTC_WRAP(val) ((val) & RTC_COUNTER_COUNTER_Msk)
|
||||
|
||||
#define RTC_CHANNEL_INT_MASK(ch) ((uint32_t)(NRF_RTC_INT_COMPARE0_MASK) << (ch))
|
||||
#define RTC_CHANNEL_EVENT_ADDR(ch) (nrf_rtc_event_t)((NRF_RTC_EVENT_COMPARE_0) + (ch) * sizeof(uint32_t))
|
||||
/**
|
||||
* @enum nrf_rtc_task_t
|
||||
* @brief RTC tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_RTC_TASK_START = offsetof(NRF_RTC_Type,TASKS_START), /**< Start. */
|
||||
NRF_RTC_TASK_STOP = offsetof(NRF_RTC_Type,TASKS_STOP), /**< Stop. */
|
||||
NRF_RTC_TASK_CLEAR = offsetof(NRF_RTC_Type,TASKS_CLEAR), /**< Clear. */
|
||||
NRF_RTC_TASK_TRIGGER_OVERFLOW = offsetof(NRF_RTC_Type,TASKS_TRIGOVRFLW),/**< Trigger overflow. */
|
||||
/*lint -restore*/
|
||||
} nrf_rtc_task_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_rtc_event_t
|
||||
* @brief RTC events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_RTC_EVENT_TICK = offsetof(NRF_RTC_Type,EVENTS_TICK), /**< Tick event. */
|
||||
NRF_RTC_EVENT_OVERFLOW = offsetof(NRF_RTC_Type,EVENTS_OVRFLW), /**< Overflow event. */
|
||||
NRF_RTC_EVENT_COMPARE_0 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[0]), /**< Compare 0 event. */
|
||||
NRF_RTC_EVENT_COMPARE_1 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[1]), /**< Compare 1 event. */
|
||||
NRF_RTC_EVENT_COMPARE_2 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[2]), /**< Compare 2 event. */
|
||||
NRF_RTC_EVENT_COMPARE_3 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[3]) /**< Compare 3 event. */
|
||||
/*lint -restore*/
|
||||
} nrf_rtc_event_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_rtc_int_t
|
||||
* @brief RTC interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_RTC_INT_TICK_MASK = RTC_INTENSET_TICK_Msk, /**< RTC interrupt from tick event. */
|
||||
NRF_RTC_INT_OVERFLOW_MASK = RTC_INTENSET_OVRFLW_Msk, /**< RTC interrupt from overflow event. */
|
||||
NRF_RTC_INT_COMPARE0_MASK = RTC_INTENSET_COMPARE0_Msk, /**< RTC interrupt from compare event on channel 0. */
|
||||
NRF_RTC_INT_COMPARE1_MASK = RTC_INTENSET_COMPARE1_Msk, /**< RTC interrupt from compare event on channel 1. */
|
||||
NRF_RTC_INT_COMPARE2_MASK = RTC_INTENSET_COMPARE2_Msk, /**< RTC interrupt from compare event on channel 2. */
|
||||
NRF_RTC_INT_COMPARE3_MASK = RTC_INTENSET_COMPARE3_Msk /**< RTC interrupt from compare event on channel 3. */
|
||||
} nrf_rtc_int_t;
|
||||
|
||||
/**@brief Function for setting a compare value for a channel.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] ch Channel.
|
||||
* @param[in] cc_val Compare value to set.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val);
|
||||
|
||||
/**@brief Function for returning the compare value for a channel.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] ch Channel.
|
||||
*
|
||||
* @return COMPARE[ch] value.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch);
|
||||
|
||||
/**@brief Function for enabling interrupts.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] mask Interrupt mask to be enabled.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask);
|
||||
|
||||
/**@brief Function for disabling interrupts.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] mask Interrupt mask to be disabled.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask);
|
||||
|
||||
/**@brief Function for checking if interrupts are enabled.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] mask Mask of interrupt flags to check.
|
||||
*
|
||||
* @return Mask with enabled interrupts.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask);
|
||||
|
||||
/**@brief Function for returning the status of currently enabled interrupts.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Value in INTEN register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc);
|
||||
|
||||
/**@brief Function for checking if an event is pending.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] event Address of the event.
|
||||
*
|
||||
* @return Mask of pending events.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
|
||||
|
||||
/**@brief Function for clearing an event.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
|
||||
|
||||
/**@brief Function for returning a counter value.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Counter value.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc);
|
||||
|
||||
/**@brief Function for setting a prescaler value.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] val Value to set the prescaler to.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val);
|
||||
|
||||
/**@brief Function for returning the address of an event.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] event Requested event.
|
||||
*
|
||||
* @return Address of the requested event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
|
||||
|
||||
/**@brief Function for returning the address of a task.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] task Requested task.
|
||||
*
|
||||
* @return Address of the requested task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task);
|
||||
|
||||
/**@brief Function for starting a task.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] task Requested task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task);
|
||||
|
||||
/**@brief Function for enabling events.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] mask Mask of event flags to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask);
|
||||
|
||||
/**@brief Function for disabling an event.
|
||||
*
|
||||
* @param[in] p_rtc Pointer to the peripheral registers structure.
|
||||
* @param[in] event Requested event.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t event);
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val)
|
||||
{
|
||||
p_rtc->CC[ch] = cc_val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch)
|
||||
{
|
||||
return p_rtc->CC[ch];
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask)
|
||||
{
|
||||
p_rtc->INTENSET = mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask)
|
||||
{
|
||||
p_rtc->INTENCLR = mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask)
|
||||
{
|
||||
return (p_rtc->INTENSET & mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc)
|
||||
{
|
||||
return p_rtc->INTENSET;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
|
||||
{
|
||||
return *(volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)) = 0;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc)
|
||||
{
|
||||
return p_rtc->COUNTER;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val)
|
||||
{
|
||||
ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos));
|
||||
p_rtc->PRESCALER = val;
|
||||
}
|
||||
__STATIC_INLINE uint32_t rtc_prescaler_get(NRF_RTC_Type * p_rtc)
|
||||
{
|
||||
return p_rtc->PRESCALER;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
|
||||
{
|
||||
return (uint32_t)p_rtc + event;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task)
|
||||
{
|
||||
return (uint32_t)p_rtc + task;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task)
|
||||
{
|
||||
*(__IO uint32_t *)((uint32_t)p_rtc + task) = 1;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask)
|
||||
{
|
||||
p_rtc->EVTENSET = mask;
|
||||
}
|
||||
__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t mask)
|
||||
{
|
||||
p_rtc->EVTENCLR = mask;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* NRF_RTC_H */
|
||||
62
lib/sdk/components/drivers_nrf/hal/nrf_saadc.c
Normal file
62
lib/sdk/components/drivers_nrf/hal/nrf_saadc.c
Normal file
@ -0,0 +1,62 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief SAADC HAL implementation
|
||||
*/
|
||||
#include "sdk_config.h"
|
||||
#if SAADC_ENABLED
|
||||
#include "nrf_saadc.h"
|
||||
|
||||
void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config)
|
||||
{
|
||||
NRF_SAADC->CH[channel].CONFIG =
|
||||
((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk)
|
||||
| ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk)
|
||||
| ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk)
|
||||
| ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk)
|
||||
| ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk)
|
||||
| ((config->mode << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk)
|
||||
| ((config->burst << SAADC_CH_CONFIG_BURST_Pos) & SAADC_CH_CONFIG_BURST_Msk);
|
||||
nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n);
|
||||
return;
|
||||
}
|
||||
#endif //SAADC_ENABLED
|
||||
|
||||
609
lib/sdk/components/drivers_nrf/hal/nrf_saadc.h
Normal file
609
lib/sdk/components/drivers_nrf/hal/nrf_saadc.h
Normal file
@ -0,0 +1,609 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_SAADC_H_
|
||||
#define NRF_SAADC_H_
|
||||
|
||||
/**
|
||||
* @defgroup nrf_saadc_hal SAADC HAL
|
||||
* @{
|
||||
* @ingroup nrf_saadc
|
||||
*
|
||||
* @brief @tagAPI52 Hardware access layer for accessing the SAADC peripheral.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NRF_SAADC_CHANNEL_COUNT 8
|
||||
|
||||
/**
|
||||
* @brief Resolution of the analog-to-digital converter.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution.
|
||||
NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution.
|
||||
NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution.
|
||||
NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution.
|
||||
} nrf_saadc_resolution_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Input selection for the analog-to-digital converter.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected.
|
||||
NRF_SAADC_INPUT_AIN0 = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0).
|
||||
NRF_SAADC_INPUT_AIN1 = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1).
|
||||
NRF_SAADC_INPUT_AIN2 = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2).
|
||||
NRF_SAADC_INPUT_AIN3 = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3).
|
||||
NRF_SAADC_INPUT_AIN4 = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4).
|
||||
NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5).
|
||||
NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6).
|
||||
NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7).
|
||||
NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD ///< VDD as input.
|
||||
} nrf_saadc_input_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter oversampling mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling.
|
||||
NRF_SAADC_OVERSAMPLE_2X = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x, ///< Oversample 2x.
|
||||
NRF_SAADC_OVERSAMPLE_4X = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x, ///< Oversample 4x.
|
||||
NRF_SAADC_OVERSAMPLE_8X = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x, ///< Oversample 8x.
|
||||
NRF_SAADC_OVERSAMPLE_16X = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x, ///< Oversample 16x.
|
||||
NRF_SAADC_OVERSAMPLE_32X = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x, ///< Oversample 32x.
|
||||
NRF_SAADC_OVERSAMPLE_64X = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x, ///< Oversample 64x.
|
||||
NRF_SAADC_OVERSAMPLE_128X = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x.
|
||||
NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x.
|
||||
} nrf_saadc_oversample_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter channel resistor control.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder.
|
||||
NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND.
|
||||
NRF_SAADC_RESISTOR_PULLUP = SAADC_CH_CONFIG_RESP_Pullup, ///< Pull-up to VDD.
|
||||
NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2 ///< Set input at VDD/2.
|
||||
} nrf_saadc_resistor_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Gain factor of the analog-to-digital converter input.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6.
|
||||
NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5.
|
||||
NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4.
|
||||
NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3.
|
||||
NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2.
|
||||
NRF_SAADC_GAIN1 = SAADC_CH_CONFIG_GAIN_Gain1, ///< Gain factor 1.
|
||||
NRF_SAADC_GAIN2 = SAADC_CH_CONFIG_GAIN_Gain2, ///< Gain factor 2.
|
||||
NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4.
|
||||
} nrf_saadc_gain_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reference selection for the analog-to-digital converter.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference (0.6 V).
|
||||
NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference.
|
||||
} nrf_saadc_reference_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter acquisition time.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us.
|
||||
NRF_SAADC_ACQTIME_5US = SAADC_CH_CONFIG_TACQ_5us, ///< 5 us.
|
||||
NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us.
|
||||
NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us.
|
||||
NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us.
|
||||
NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us.
|
||||
} nrf_saadc_acqtime_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter channel mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single ended, PSELN will be ignored, negative input to ADC shorted to GND.
|
||||
NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode.
|
||||
} nrf_saadc_mode_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter channel burst mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_BURST_DISABLED = SAADC_CH_CONFIG_BURST_Disabled, ///< Burst mode is disabled (normal operation).
|
||||
NRF_SAADC_BURST_ENABLED = SAADC_CH_CONFIG_BURST_Enabled ///< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.
|
||||
} nrf_saadc_burst_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter tasks.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM.
|
||||
NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled.
|
||||
NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any on-going conversion.
|
||||
NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration.
|
||||
} nrf_saadc_task_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter events.
|
||||
*/
|
||||
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
|
||||
{
|
||||
NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started.
|
||||
NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer.
|
||||
NRF_SAADC_EVENT_DONE = offsetof(NRF_SAADC_Type, EVENTS_DONE), ///< A conversion task has been completed.
|
||||
NRF_SAADC_EVENT_RESULTDONE = offsetof(NRF_SAADC_Type, EVENTS_RESULTDONE), ///< A result is ready to get transferred to RAM.
|
||||
NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete.
|
||||
NRF_SAADC_EVENT_STOPPED = offsetof(NRF_SAADC_Type, EVENTS_STOPPED), ///< The ADC has stopped.
|
||||
NRF_SAADC_EVENT_CH0_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH), ///< Last result is equal or above CH[0].LIMIT.HIGH.
|
||||
NRF_SAADC_EVENT_CH0_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL), ///< Last result is equal or below CH[0].LIMIT.LOW.
|
||||
NRF_SAADC_EVENT_CH1_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH), ///< Last result is equal or above CH[1].LIMIT.HIGH.
|
||||
NRF_SAADC_EVENT_CH1_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL), ///< Last result is equal or below CH[1].LIMIT.LOW.
|
||||
NRF_SAADC_EVENT_CH2_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH), ///< Last result is equal or above CH[2].LIMIT.HIGH.
|
||||
NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW.
|
||||
NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH.
|
||||
NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW.
|
||||
NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH.
|
||||
NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW.
|
||||
NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH.
|
||||
NRF_SAADC_EVENT_CH5_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL), ///< Last result is equal or below CH[5].LIMIT.LOW.
|
||||
NRF_SAADC_EVENT_CH6_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH), ///< Last result is equal or above CH[6].LIMIT.HIGH.
|
||||
NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW.
|
||||
NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH.
|
||||
NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW.
|
||||
} nrf_saadc_event_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter interrupt masks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
|
||||
NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event.
|
||||
NRF_SAADC_INT_DONE = SAADC_INTENSET_DONE_Msk, ///< Interrupt on EVENTS_DONE event.
|
||||
NRF_SAADC_INT_RESULTDONE = SAADC_INTENSET_RESULTDONE_Msk, ///< Interrupt on EVENTS_RESULTDONE event.
|
||||
NRF_SAADC_INT_CALIBRATEDONE = SAADC_INTENSET_CALIBRATEDONE_Msk, ///< Interrupt on EVENTS_CALIBRATEDONE event.
|
||||
NRF_SAADC_INT_STOPPED = SAADC_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
|
||||
NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event.
|
||||
NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event.
|
||||
NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event.
|
||||
NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event.
|
||||
NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event.
|
||||
NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event.
|
||||
NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event.
|
||||
NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event.
|
||||
NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event.
|
||||
NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event.
|
||||
NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event.
|
||||
NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event.
|
||||
NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event.
|
||||
NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event.
|
||||
NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event.
|
||||
NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event.
|
||||
NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts.
|
||||
} nrf_saadc_int_mask_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter value limit type.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SAADC_LIMIT_LOW = 0,
|
||||
NRF_SAADC_LIMIT_HIGH = 1
|
||||
} nrf_saadc_limit_t;
|
||||
|
||||
|
||||
typedef int16_t nrf_saadc_value_t; ///< Type of a single ADC conversion result.
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter configuration structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
nrf_saadc_resolution_t resolution;
|
||||
nrf_saadc_oversample_t oversample;
|
||||
nrf_saadc_value_t * buffer;
|
||||
uint32_t buffer_size;
|
||||
} nrf_saadc_config_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Analog-to-digital converter channel configuration structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
nrf_saadc_resistor_t resistor_p;
|
||||
nrf_saadc_resistor_t resistor_n;
|
||||
nrf_saadc_gain_t gain;
|
||||
nrf_saadc_reference_t reference;
|
||||
nrf_saadc_acqtime_t acq_time;
|
||||
nrf_saadc_mode_t mode;
|
||||
nrf_saadc_burst_t burst;
|
||||
nrf_saadc_input_t pin_p;
|
||||
nrf_saadc_input_t pin_n;
|
||||
} nrf_saadc_channel_config_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for triggering a specific SAADC task.
|
||||
*
|
||||
* @param[in] saadc_task SAADC task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task)) = 0x1UL;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific SAADC task register.
|
||||
*
|
||||
* @param[in] saadc_task SAADC task.
|
||||
*
|
||||
* @return Address of the specified SAADC task.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task)
|
||||
{
|
||||
return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the state of a specific SAADC event.
|
||||
*
|
||||
* @param[in] saadc_event SAADC event.
|
||||
*
|
||||
* @return State of the specified SAADC event.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing the specific SAADC event.
|
||||
*
|
||||
* @param[in] saadc_event SAADC event.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific SAADC event register.
|
||||
*
|
||||
* @param[in] saadc_event SAADC event.
|
||||
*
|
||||
* @return Address of the specified SAADC event.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event)
|
||||
{
|
||||
return (uint32_t )((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific SAADC limit event register.
|
||||
*
|
||||
* @param[in] channel Channel number.
|
||||
* @param[in] limit_type Low limit or high limit.
|
||||
*
|
||||
* @return Address of the specified SAADC limit event.
|
||||
*/
|
||||
__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type)
|
||||
{
|
||||
ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
|
||||
if (limit_type == NRF_SAADC_LIMIT_HIGH)
|
||||
{
|
||||
return &NRF_SAADC->EVENTS_CH[channel].LIMITH;
|
||||
}
|
||||
else
|
||||
{
|
||||
return &NRF_SAADC->EVENTS_CH[channel].LIMITL;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting the SAADC channel monitoring limit events.
|
||||
*
|
||||
* @param[in] channel Channel number.
|
||||
* @param[in] limit_type Low limit or high limit.
|
||||
*/
|
||||
__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type)
|
||||
{
|
||||
if (limit_type == NRF_SAADC_LIMIT_HIGH)
|
||||
{
|
||||
return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITH +
|
||||
(uint32_t) (NRF_SAADC_EVENT_CH1_LIMITH - NRF_SAADC_EVENT_CH0_LIMITH)
|
||||
* (uint32_t) channel );
|
||||
}
|
||||
else
|
||||
{
|
||||
return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITL +
|
||||
(uint32_t) (NRF_SAADC_EVENT_CH1_LIMITL - NRF_SAADC_EVENT_CH0_LIMITL)
|
||||
* (uint32_t) channel );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the input pins for a specific SAADC channel.
|
||||
*
|
||||
* @param[in] channel Channel number.
|
||||
* @param[in] pselp Positive input.
|
||||
* @param[in] pseln Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
|
||||
nrf_saadc_input_t pselp,
|
||||
nrf_saadc_input_t pseln)
|
||||
{
|
||||
NRF_SAADC->CH[channel].PSELN = pseln;
|
||||
NRF_SAADC->CH[channel].PSELP = pselp;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the SAADC channel monitoring limits.
|
||||
*
|
||||
* @param[in] channel Channel number.
|
||||
* @param[in] low Low limit.
|
||||
* @param[in] high High limit.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low, int16_t high)
|
||||
{
|
||||
NRF_SAADC->CH[channel].LIMIT = (
|
||||
(((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk)
|
||||
| (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified SAADC interrupts.
|
||||
*
|
||||
* @param[in] saadc_int_mask Interrupt(s) to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask)
|
||||
{
|
||||
NRF_SAADC->INTENSET = saadc_int_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of specified SAADC interrupts.
|
||||
*
|
||||
* @param[in] saadc_int_mask Interrupt(s) to check.
|
||||
*
|
||||
* @retval true If all specified interrupts are enabled.
|
||||
* @retval false If at least one of the given interrupts is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask)
|
||||
{
|
||||
return (bool)(NRF_SAADC->INTENSET & saadc_int_mask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param saadc_int_mask Interrupt(s) to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask)
|
||||
{
|
||||
NRF_SAADC->INTENCLR = saadc_int_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for generating masks for SAADC channel limit interrupts.
|
||||
*
|
||||
* @param[in] channel SAADC channel number.
|
||||
* @param[in] limit_type Limit type.
|
||||
*
|
||||
* @returns Interrupt mask.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type)
|
||||
{
|
||||
ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
|
||||
uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ? NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
|
||||
return mask << (channel * 2);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for checking whether the SAADC is busy.
|
||||
*
|
||||
* This function checks whether the analog-to-digital converter is busy with a conversion.
|
||||
*
|
||||
* @retval true If the SAADC is busy.
|
||||
* @retval false If the SAADC is not busy.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_saadc_busy_check(void)
|
||||
{
|
||||
//return ((NRF_SAADC->STATUS & SAADC_STATUS_STATUS_Msk) == SAADC_STATUS_STATUS_Msk);
|
||||
//simplified for performance
|
||||
return NRF_SAADC->STATUS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the SAADC.
|
||||
*
|
||||
* The analog-to-digital converter must be enabled before use.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_enable(void)
|
||||
{
|
||||
NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the SAADC.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_disable(void)
|
||||
{
|
||||
NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for checking if the SAADC is enabled.
|
||||
*
|
||||
* @retval true If the SAADC is enabled.
|
||||
* @retval false If the SAADC is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_saadc_enable_check(void)
|
||||
{
|
||||
//simplified for performance
|
||||
return NRF_SAADC->ENABLE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for initializing the SAADC result buffer.
|
||||
*
|
||||
* @param[in] buffer Pointer to the result buffer.
|
||||
* @param[in] num Size of buffer in words.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * buffer, uint32_t num)
|
||||
{
|
||||
NRF_SAADC->RESULT.PTR = (uint32_t)buffer;
|
||||
NRF_SAADC->RESULT.MAXCNT = num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for getting the number of buffer words transferred since last START operation.
|
||||
*
|
||||
* @returns Number of words transferred.
|
||||
*/
|
||||
__STATIC_INLINE uint16_t nrf_saadc_amount_get(void)
|
||||
{
|
||||
return NRF_SAADC->RESULT.AMOUNT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the SAADC sample resolution.
|
||||
*
|
||||
* @param[in] resolution Bit resolution.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution)
|
||||
{
|
||||
NRF_SAADC->RESOLUTION = resolution;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the oversampling feature.
|
||||
*
|
||||
* @param[in] oversample Oversampling mode.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample)
|
||||
{
|
||||
NRF_SAADC->OVERSAMPLE = oversample;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for getting the oversampling feature configuration.
|
||||
*
|
||||
* @return Oversampling configuration.
|
||||
*/
|
||||
__STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void)
|
||||
{
|
||||
return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for initializing the SAADC channel.
|
||||
*
|
||||
* @param[in] channel Channel number.
|
||||
* @param[in] config Pointer to the channel configuration structure.
|
||||
*/
|
||||
void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config);
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* NRF_SAADC_H_ */
|
||||
375
lib/sdk/components/drivers_nrf/hal/nrf_spi.h
Normal file
375
lib/sdk/components/drivers_nrf/hal/nrf_spi.h
Normal file
@ -0,0 +1,375 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @defgroup nrf_spi_hal SPI HAL
|
||||
* @{
|
||||
* @ingroup nrf_spi
|
||||
*
|
||||
* @brief Hardware access layer for accessing the SPI peripheral.
|
||||
*/
|
||||
|
||||
#ifndef NRF_SPI_H__
|
||||
#define NRF_SPI_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief This value can be used as a parameter for the @ref nrf_spi_pins_set
|
||||
* function to specify that a given SPI signal (SCK, MOSI, or MISO)
|
||||
* shall not be connected to a physical pin.
|
||||
*/
|
||||
#define NRF_SPI_PIN_NOT_CONNECTED 0xFFFFFFFF
|
||||
|
||||
|
||||
/**
|
||||
* @brief SPI events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_SPI_EVENT_READY = offsetof(NRF_SPI_Type, EVENTS_READY) ///< TXD byte sent and RXD byte received.
|
||||
/*lint -restore*/
|
||||
} nrf_spi_event_t;
|
||||
|
||||
/**
|
||||
* @brief SPI interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPI_INT_READY_MASK = SPI_INTENSET_READY_Msk ///< Interrupt on READY event.
|
||||
} nrf_spi_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief SPI data rates.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPI_FREQ_125K = SPI_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
|
||||
NRF_SPI_FREQ_250K = SPI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
|
||||
NRF_SPI_FREQ_500K = SPI_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
|
||||
NRF_SPI_FREQ_1M = SPI_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
|
||||
NRF_SPI_FREQ_2M = SPI_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
|
||||
NRF_SPI_FREQ_4M = SPI_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
|
||||
// [conversion to 'int' needed to prevent compilers from complaining
|
||||
// that the provided value (0x80000000UL) is out of range of "int"]
|
||||
NRF_SPI_FREQ_8M = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
|
||||
} nrf_spi_frequency_t;
|
||||
|
||||
/**
|
||||
* @brief SPI modes.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock.
|
||||
NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock.
|
||||
NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock.
|
||||
NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock.
|
||||
} nrf_spi_mode_t;
|
||||
|
||||
/**
|
||||
* @brief SPI bit orders.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPI_BIT_ORDER_MSB_FIRST = SPI_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
|
||||
NRF_SPI_BIT_ORDER_LSB_FIRST = SPI_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
|
||||
} nrf_spi_bit_order_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific SPI event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spi_event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_event_t spi_event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific SPI event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spi_event Event to check.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_event_t spi_event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific SPI event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spi_event Requested event.
|
||||
*
|
||||
* @return Address of the specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_event_t spi_event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spi_int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg,
|
||||
uint32_t spi_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spi_int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg,
|
||||
uint32_t spi_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spi_int Interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_int_mask_t spi_int);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the SPI peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the SPI peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring SPI pins.
|
||||
*
|
||||
* If a given signal is not needed, pass the @ref NRF_SPI_PIN_NOT_CONNECTED
|
||||
* value instead of its pin number.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] sck_pin SCK pin number.
|
||||
* @param[in] mosi_pin MOSI pin number.
|
||||
* @param[in] miso_pin MISO pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg,
|
||||
uint32_t sck_pin,
|
||||
uint32_t mosi_pin,
|
||||
uint32_t miso_pin);
|
||||
|
||||
/**
|
||||
* @brief Function for writing data to the SPI transmitter register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] data TX data to send.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data);
|
||||
|
||||
/**
|
||||
* @brief Function for reading data from the SPI receiver register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return RX data received.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the SPI master data rate.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] frequency SPI frequency.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_frequency_t frequency);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the SPI configuration.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spi_mode SPI mode.
|
||||
* @param[in] spi_bit_order SPI bit order.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_mode_t spi_mode,
|
||||
nrf_spi_bit_order_t spi_bit_order);
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_event_t spi_event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_event_t spi_event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_event_t spi_event)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg,
|
||||
uint32_t spi_int_mask)
|
||||
{
|
||||
p_reg->INTENSET = spi_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg,
|
||||
uint32_t spi_int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = spi_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_int_mask_t spi_int)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & spi_int);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg,
|
||||
uint32_t sck_pin,
|
||||
uint32_t mosi_pin,
|
||||
uint32_t miso_pin)
|
||||
{
|
||||
p_reg->PSELSCK = sck_pin;
|
||||
p_reg->PSELMOSI = mosi_pin;
|
||||
p_reg->PSELMISO = miso_pin;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data)
|
||||
{
|
||||
p_reg->TXD = data;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg)
|
||||
{
|
||||
return p_reg->RXD;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_frequency_t frequency)
|
||||
{
|
||||
p_reg->FREQUENCY = frequency;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg,
|
||||
nrf_spi_mode_t spi_mode,
|
||||
nrf_spi_bit_order_t spi_bit_order)
|
||||
{
|
||||
uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ?
|
||||
SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst);
|
||||
switch (spi_mode)
|
||||
{
|
||||
default:
|
||||
case NRF_SPI_MODE_0:
|
||||
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
|
||||
(SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
|
||||
case NRF_SPI_MODE_1:
|
||||
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
|
||||
(SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
|
||||
case NRF_SPI_MODE_2:
|
||||
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) |
|
||||
(SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
|
||||
case NRF_SPI_MODE_3:
|
||||
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) |
|
||||
(SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
}
|
||||
p_reg->CONFIG = config;
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_SPI_H__
|
||||
|
||||
/** @} */
|
||||
571
lib/sdk/components/drivers_nrf/hal/nrf_spim.h
Normal file
571
lib/sdk/components/drivers_nrf/hal/nrf_spim.h
Normal file
@ -0,0 +1,571 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @defgroup nrf_spim_hal SPIM HAL
|
||||
* @{
|
||||
* @ingroup nrf_spi
|
||||
*
|
||||
* @brief Hardware access layer for accessing the SPIM peripheral.
|
||||
*/
|
||||
|
||||
#ifndef NRF_SPIM_H__
|
||||
#define NRF_SPIM_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief This value can be used as a parameter for the @ref nrf_spim_pins_set
|
||||
* function to specify that a given SPI signal (SCK, MOSI, or MISO)
|
||||
* shall not be connected to a physical pin.
|
||||
*/
|
||||
#define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF
|
||||
|
||||
|
||||
/**
|
||||
* @brief SPIM tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction.
|
||||
NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction.
|
||||
NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction.
|
||||
NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME) ///< Resume SPI transaction.
|
||||
/*lint -restore*/
|
||||
} nrf_spim_task_t;
|
||||
|
||||
/**
|
||||
* @brief SPIM events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped.
|
||||
NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached.
|
||||
NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END), ///< End of RXD buffer and TXD buffer reached.
|
||||
NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached.
|
||||
NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED) ///< Transaction started.
|
||||
/*lint -restore*/
|
||||
} nrf_spim_event_t;
|
||||
|
||||
/**
|
||||
* @brief SPIM shortcuts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk ///< Shortcut between END event and START task.
|
||||
} nrf_spim_short_mask_t;
|
||||
|
||||
/**
|
||||
* @brief SPIM interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
|
||||
NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
|
||||
NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event.
|
||||
NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
|
||||
NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk ///< Interrupt on STARTED event.
|
||||
} nrf_spim_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief SPI master data rates.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
|
||||
NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
|
||||
NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
|
||||
NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
|
||||
NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
|
||||
NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
|
||||
// [conversion to 'int' needed to prevent compilers from complaining
|
||||
// that the provided value (0x80000000UL) is out of range of "int"]
|
||||
NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8,///< 8 Mbps.
|
||||
#ifndef SPI_PRESENT
|
||||
NRF_SPI_FREQ_125K = NRF_SPIM_FREQ_125K,
|
||||
NRF_SPI_FREQ_250K = NRF_SPIM_FREQ_250K,
|
||||
NRF_SPI_FREQ_500K = NRF_SPIM_FREQ_500K,
|
||||
NRF_SPI_FREQ_1M = NRF_SPIM_FREQ_1M,
|
||||
NRF_SPI_FREQ_2M = NRF_SPIM_FREQ_2M,
|
||||
NRF_SPI_FREQ_4M = NRF_SPIM_FREQ_4M,
|
||||
NRF_SPI_FREQ_8M = NRF_SPIM_FREQ_8M,
|
||||
#endif
|
||||
} nrf_spim_frequency_t;
|
||||
|
||||
/**
|
||||
* @brief SPI modes.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
|
||||
NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
|
||||
NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock.
|
||||
NRF_SPIM_MODE_3, ///< SCK active low, sample on trailing edge of clock.
|
||||
#ifndef SPI_PRESENT
|
||||
NRF_SPI_MODE_0 = NRF_SPIM_MODE_0,
|
||||
NRF_SPI_MODE_1 = NRF_SPIM_MODE_1,
|
||||
NRF_SPI_MODE_2 = NRF_SPIM_MODE_2,
|
||||
NRF_SPI_MODE_3 = NRF_SPIM_MODE_3,
|
||||
#endif
|
||||
} nrf_spim_mode_t;
|
||||
|
||||
/**
|
||||
* @brief SPI bit orders.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
|
||||
NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst, ///< Least significant bit shifted out first.
|
||||
#ifndef SPI_PRESENT
|
||||
NRF_SPI_BIT_ORDER_MSB_FIRST = NRF_SPIM_BIT_ORDER_MSB_FIRST,
|
||||
NRF_SPI_BIT_ORDER_LSB_FIRST = NRF_SPIM_BIT_ORDER_LSB_FIRST,
|
||||
#endif
|
||||
} nrf_spim_bit_order_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific SPIM task.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_task Task to activate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_task_t spim_task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific SPIM task register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_task Requested task.
|
||||
*
|
||||
* @return Address of the specified task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_task_t spim_task);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific SPIM event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_event_t spim_event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific SPIM event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_event Event to check.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_event_t spim_event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific SPIM event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_event Requested event.
|
||||
*
|
||||
* @return Address of the specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_event_t spim_event);
|
||||
/**
|
||||
* @brief Function for enabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_shorts_mask Shortcuts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
|
||||
uint32_t spim_shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_shorts_mask Shortcuts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
|
||||
uint32_t spim_shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for getting shorts setting.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
|
||||
uint32_t spim_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
|
||||
uint32_t spim_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spim_int Interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_int_mask_t spim_int);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the SPIM peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the SPIM peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring SPIM pins.
|
||||
*
|
||||
* If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
|
||||
* value instead of its pin number.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] sck_pin SCK pin number.
|
||||
* @param[in] mosi_pin MOSI pin number.
|
||||
* @param[in] miso_pin MISO pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
|
||||
uint32_t sck_pin,
|
||||
uint32_t mosi_pin,
|
||||
uint32_t miso_pin);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the SPI master data rate.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] frequency SPI frequency.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_frequency_t frequency);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the transmit buffer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] p_buffer Pointer to the buffer with data to send.
|
||||
* @param[in] length Maximum number of data bytes to transmit.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
|
||||
uint8_t const * p_buffer,
|
||||
uint8_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the receive buffer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] p_buffer Pointer to the buffer for received data.
|
||||
* @param[in] length Maximum number of data bytes to receive.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
|
||||
uint8_t * p_buffer,
|
||||
uint8_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the SPI configuration.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spi_mode SPI mode.
|
||||
* @param[in] spi_bit_order SPI bit order.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_mode_t spi_mode,
|
||||
nrf_spim_bit_order_t spi_bit_order);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the over-read character.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] orc Over-read character that is clocked out in case of
|
||||
* an over-read of the TXD buffer.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
|
||||
uint8_t orc);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the TX list feature.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the TX list feature.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the RX list feature.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the RX list feature.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg);
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_task_t spim_task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_task_t spim_task)
|
||||
{
|
||||
return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_event_t spim_event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_event_t spim_event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_event_t spim_event)
|
||||
{
|
||||
return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
|
||||
uint32_t spim_shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS |= spim_shorts_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
|
||||
uint32_t spim_shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS &= ~(spim_shorts_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg)
|
||||
{
|
||||
return p_reg->SHORTS;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
|
||||
uint32_t spim_int_mask)
|
||||
{
|
||||
p_reg->INTENSET = spim_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
|
||||
uint32_t spim_int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = spim_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_int_mask_t spim_int)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & spim_int);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
|
||||
uint32_t sck_pin,
|
||||
uint32_t mosi_pin,
|
||||
uint32_t miso_pin)
|
||||
{
|
||||
p_reg->PSEL.SCK = sck_pin;
|
||||
p_reg->PSEL.MOSI = mosi_pin;
|
||||
p_reg->PSEL.MISO = miso_pin;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_frequency_t frequency)
|
||||
{
|
||||
p_reg->FREQUENCY = frequency;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
|
||||
uint8_t const * p_buffer,
|
||||
uint8_t length)
|
||||
{
|
||||
p_reg->TXD.PTR = (uint32_t)p_buffer;
|
||||
p_reg->TXD.MAXCNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
|
||||
uint8_t * p_buffer,
|
||||
uint8_t length)
|
||||
{
|
||||
p_reg->RXD.PTR = (uint32_t)p_buffer;
|
||||
p_reg->RXD.MAXCNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
|
||||
nrf_spim_mode_t spi_mode,
|
||||
nrf_spim_bit_order_t spi_bit_order)
|
||||
{
|
||||
uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
|
||||
SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
|
||||
switch (spi_mode)
|
||||
{
|
||||
default:
|
||||
case NRF_SPIM_MODE_0:
|
||||
config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
|
||||
(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
|
||||
case NRF_SPIM_MODE_1:
|
||||
config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
|
||||
(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
|
||||
case NRF_SPIM_MODE_2:
|
||||
config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
|
||||
(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
|
||||
case NRF_SPIM_MODE_3:
|
||||
config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
|
||||
(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
}
|
||||
p_reg->CONFIG = config;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
|
||||
uint8_t orc)
|
||||
{
|
||||
p_reg->ORC = orc;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
|
||||
{
|
||||
p_reg->TXD.LIST = 1;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
|
||||
{
|
||||
p_reg->TXD.LIST = 0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
|
||||
{
|
||||
p_reg->RXD.LIST = 1;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
|
||||
{
|
||||
p_reg->RXD.LIST = 0;
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_SPIM_H__
|
||||
|
||||
/** @} */
|
||||
553
lib/sdk/components/drivers_nrf/hal/nrf_spis.h
Normal file
553
lib/sdk/components/drivers_nrf/hal/nrf_spis.h
Normal file
@ -0,0 +1,553 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @defgroup nrf_spis_hal SPIS HAL
|
||||
* @{
|
||||
* @ingroup nrf_spis
|
||||
*
|
||||
* @brief Hardware access layer for accessing the SPIS peripheral.
|
||||
*/
|
||||
|
||||
#ifndef NRF_SPIS_H__
|
||||
#define NRF_SPIS_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief This value can be used as a parameter for the @ref nrf_spis_pins_set
|
||||
* function to specify that a given SPI signal (SCK, MOSI, or MISO)
|
||||
* shall not be connected to a physical pin.
|
||||
*/
|
||||
#define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF
|
||||
|
||||
|
||||
/**
|
||||
* @brief SPIS tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore.
|
||||
NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it.
|
||||
/*lint -restore*/
|
||||
} nrf_spis_task_t;
|
||||
|
||||
/**
|
||||
* @brief SPIS events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed.
|
||||
NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired.
|
||||
/*lint -restore*/
|
||||
} nrf_spis_event_t;
|
||||
|
||||
/**
|
||||
* @brief SPIS shortcuts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task.
|
||||
} nrf_spis_short_mask_t;
|
||||
|
||||
/**
|
||||
* @brief SPIS interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event.
|
||||
NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event.
|
||||
} nrf_spis_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief SPI modes.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock.
|
||||
NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock.
|
||||
NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock.
|
||||
NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock.
|
||||
} nrf_spis_mode_t;
|
||||
|
||||
/**
|
||||
* @brief SPI bit orders.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
|
||||
NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
|
||||
} nrf_spis_bit_order_t;
|
||||
|
||||
/**
|
||||
* @brief SPI semaphore status.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free.
|
||||
NRF_SPIS_SEMSTAT_CPU = 1, ///< Semaphore is assigned to the CPU.
|
||||
NRF_SPIS_SEMSTAT_SPIS = 2, ///< Semaphore is assigned to the SPI slave.
|
||||
NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending.
|
||||
} nrf_spis_semstat_t;
|
||||
|
||||
/**
|
||||
* @brief SPIS status.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented.
|
||||
NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented.
|
||||
} nrf_spis_status_mask_t;
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific SPIS task.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_task Task to activate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
|
||||
nrf_spis_task_t spis_task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific SPIS task register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_task Requested task.
|
||||
*
|
||||
* @return Address of the specified task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
|
||||
nrf_spis_task_t spis_task);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific SPIS event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
|
||||
nrf_spis_event_t spis_event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific SPIS event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_event Event to check.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
|
||||
nrf_spis_event_t spis_event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific SPIS event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_event Requested event.
|
||||
*
|
||||
* @return Address of the specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
|
||||
nrf_spis_event_t spis_event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_shorts_mask Shortcuts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
|
||||
uint32_t spis_shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_shorts_mask Shortcuts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
|
||||
uint32_t spis_shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
|
||||
uint32_t spis_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
|
||||
uint32_t spis_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spis_int Interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,
|
||||
nrf_spis_int_mask_t spis_int);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the SPIS peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the SPIS peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the SPIS semaphore status.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @returns Current semaphore status.
|
||||
*/
|
||||
__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the SPIS status.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @returns Current SPIS status.
|
||||
*/
|
||||
__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring SPIS pins.
|
||||
*
|
||||
* If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED
|
||||
* value instead of its pin number.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] sck_pin SCK pin number.
|
||||
* @param[in] mosi_pin MOSI pin number.
|
||||
* @param[in] miso_pin MISO pin number.
|
||||
* @param[in] csn_pin CSN pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
|
||||
uint32_t sck_pin,
|
||||
uint32_t mosi_pin,
|
||||
uint32_t miso_pin,
|
||||
uint32_t csn_pin);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the transmit buffer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] p_buffer Pointer to the buffer that contains the data to send.
|
||||
* @param[in] length Maximum number of data bytes to transmit.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
|
||||
uint8_t const * p_buffer,
|
||||
uint8_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the receive buffer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] p_buffer Pointer to the buffer for received data.
|
||||
* @param[in] length Maximum number of data bytes to receive.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
|
||||
uint8_t * p_buffer,
|
||||
uint8_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the number of bytes transmitted
|
||||
* in the last granted transaction.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @returns Number of bytes transmitted.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the number of bytes received
|
||||
* in the last granted transaction.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @returns Number of bytes received.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the SPI configuration.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] spi_mode SPI mode.
|
||||
* @param[in] spi_bit_order SPI bit order.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
|
||||
nrf_spis_mode_t spi_mode,
|
||||
nrf_spis_bit_order_t spi_bit_order);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the default character.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] def Default character that is clocked out in case of
|
||||
* an overflow of the RXD buffer.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
|
||||
uint8_t def);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the over-read character.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] orc Over-read character that is clocked out in case of
|
||||
* an over-read of the TXD buffer.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
|
||||
uint8_t orc);
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
|
||||
nrf_spis_task_t spis_task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
|
||||
nrf_spis_task_t spis_task)
|
||||
{
|
||||
return (uint32_t)p_reg + (uint32_t)spis_task;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
|
||||
nrf_spis_event_t spis_event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
|
||||
nrf_spis_event_t spis_event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
|
||||
nrf_spis_event_t spis_event)
|
||||
{
|
||||
return (uint32_t)p_reg + (uint32_t)spis_event;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
|
||||
uint32_t spis_shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS |= spis_shorts_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
|
||||
uint32_t spis_shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS &= ~(spis_shorts_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
|
||||
uint32_t spis_int_mask)
|
||||
{
|
||||
p_reg->INTENSET = spis_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
|
||||
uint32_t spis_int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = spis_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,
|
||||
nrf_spis_int_mask_t spis_int)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & spis_int);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg)
|
||||
{
|
||||
return (nrf_spis_semstat_t) ((p_reg->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk)
|
||||
>> SPIS_SEMSTAT_SEMSTAT_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg)
|
||||
{
|
||||
return (nrf_spis_status_mask_t) p_reg->STATUS;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
|
||||
uint32_t sck_pin,
|
||||
uint32_t mosi_pin,
|
||||
uint32_t miso_pin,
|
||||
uint32_t csn_pin)
|
||||
{
|
||||
p_reg->PSELSCK = sck_pin;
|
||||
p_reg->PSELMOSI = mosi_pin;
|
||||
p_reg->PSELMISO = miso_pin;
|
||||
p_reg->PSELCSN = csn_pin;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
|
||||
uint8_t const * p_buffer,
|
||||
uint8_t length)
|
||||
{
|
||||
p_reg->TXDPTR = (uint32_t)p_buffer;
|
||||
p_reg->MAXTX = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
|
||||
uint8_t * p_buffer,
|
||||
uint8_t length)
|
||||
{
|
||||
p_reg->RXDPTR = (uint32_t)p_buffer;
|
||||
p_reg->MAXRX = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg)
|
||||
{
|
||||
return (uint8_t) p_reg->AMOUNTTX;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)
|
||||
{
|
||||
return (uint8_t) p_reg->AMOUNTRX;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
|
||||
nrf_spis_mode_t spi_mode,
|
||||
nrf_spis_bit_order_t spi_bit_order)
|
||||
{
|
||||
uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ?
|
||||
SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst);
|
||||
|
||||
switch (spi_mode)
|
||||
{
|
||||
default:
|
||||
case NRF_SPIS_MODE_0:
|
||||
config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
|
||||
(SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
|
||||
case NRF_SPIS_MODE_1:
|
||||
config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
|
||||
(SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
|
||||
case NRF_SPIS_MODE_2:
|
||||
config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
|
||||
(SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
|
||||
case NRF_SPIS_MODE_3:
|
||||
config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
|
||||
(SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
|
||||
break;
|
||||
}
|
||||
p_reg->CONFIG = config;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
|
||||
uint8_t orc)
|
||||
{
|
||||
p_reg->ORC = orc;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
|
||||
uint8_t def)
|
||||
{
|
||||
p_reg->DEF = def;
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_SPIS_H__
|
||||
|
||||
/** @} */
|
||||
184
lib/sdk/components/drivers_nrf/hal/nrf_systick.h
Normal file
184
lib/sdk/components/drivers_nrf/hal/nrf_systick.h
Normal file
@ -0,0 +1,184 @@
|
||||
/**
|
||||
* Copyright (c) 2016 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_SYSTICK_H__
|
||||
#define NRF_SYSTICK_H__
|
||||
|
||||
#include "nrf.h"
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/**
|
||||
* @defgroup nrf_systick_hal SYSTICK HAL
|
||||
* @{
|
||||
* @ingroup nrf_systick
|
||||
*
|
||||
* @brief Hardware access layer for accessing the SYSTICK peripheral.
|
||||
*
|
||||
* SYSTICK is ARM peripheral, not Nordic design.
|
||||
* It means that it has no Nordic-typical interface with Tasks and Events.
|
||||
*
|
||||
* Its usage is limited here to implement simple delays.
|
||||
* Also keep in mind that this timer would be stopped when CPU is sleeping
|
||||
* (WFE/WFI instruction is successfully executed).
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Mask of usable bits in the SysTick value
|
||||
*/
|
||||
#define NRF_SYSTICK_VAL_MASK SysTick_VAL_CURRENT_Msk
|
||||
|
||||
/**
|
||||
* @brief Flags used by SysTick configuration.
|
||||
*
|
||||
* @sa nrf_systick_csr_set
|
||||
* @sa nrf_systick_csr_get
|
||||
*/
|
||||
typedef enum {
|
||||
NRF_SYSTICK_CSR_COUNTFLAG_MASK = SysTick_CTRL_COUNTFLAG_Msk, /**< Status flag: Returns 1 if timer counted to 0 since the last read of this register. */
|
||||
|
||||
NRF_SYSTICK_CSR_CLKSOURCE_MASK = SysTick_CTRL_CLKSOURCE_Msk, /**< Configuration bit: Select the SysTick clock source. */
|
||||
NRF_SYSTICK_CSR_CLKSOURCE_REF = 0U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select reference clock. */
|
||||
NRF_SYSTICK_CSR_CLKSOURCE_CPU = 1U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select CPU clock. */
|
||||
|
||||
NRF_SYSTICK_CSR_TICKINT_MASK = SysTick_CTRL_TICKINT_Msk, /**< Configuration bit: Enables SysTick exception request. */
|
||||
NRF_SYSTICK_CSR_TICKINT_ENABLE = 1U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero does not assert the SysTick exception request. */
|
||||
NRF_SYSTICK_CSR_TICKINT_DISABLE = 0U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero to asserts the SysTick exception request. */
|
||||
|
||||
NRF_SYSTICK_CSR_ENABLE_MASK = SysTick_CTRL_ENABLE_Msk, /**< Configuration bit: Enable the SysTick timer. */
|
||||
NRF_SYSTICK_CSR_ENABLE = 1U << SysTick_CTRL_ENABLE_Pos, /**< Configuration value: Counter enabled. */
|
||||
NRF_SYSTICK_CSR_DISABLE = 0U << SysTick_CTRL_ENABLE_Pos /**< Configuration value: Counter disabled. */
|
||||
} nrf_systick_csr_flags_t;
|
||||
|
||||
/**
|
||||
* @brief Get Configuration and Status Register
|
||||
*
|
||||
* @return Values composed by @ref nrf_systick_csr_flags_t.
|
||||
* @note The @ref NRF_SYSTICK_CSR_COUNTFLAG_MASK value is cleared when CSR register is read.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_systick_csr_get(void);
|
||||
|
||||
/**
|
||||
* @brief Set Configuration and Status Register
|
||||
*
|
||||
* @param[in] val The value composed from @ref nrf_systick_csr_flags_t.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_systick_csr_set(uint32_t val);
|
||||
|
||||
/**
|
||||
* @brief Get the current reload value.
|
||||
*
|
||||
* @return The reload register value.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_systick_load_get(void);
|
||||
|
||||
/**
|
||||
* @brief Configure the reload value.
|
||||
*
|
||||
* @param[in] val The value to set in the reload register.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_systick_load_set(uint32_t val);
|
||||
|
||||
/**
|
||||
* @brief Read the SysTick current value
|
||||
*
|
||||
* @return The current SysTick value
|
||||
* @sa NRF_SYSTICK_VAL_MASK
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_systick_val_get(void);
|
||||
|
||||
/**
|
||||
* @brief Clear the SysTick current value
|
||||
*
|
||||
* @note The SysTick does not allow setting current value.
|
||||
* Any write to VAL register would clear the timer.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_systick_val_clear(void);
|
||||
|
||||
/**
|
||||
* @brief Read the calibration register
|
||||
*
|
||||
* @return The calibration register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_systick_calib_get(void);
|
||||
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_systick_csr_get(void)
|
||||
{
|
||||
return SysTick->CTRL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_systick_csr_set(uint32_t val)
|
||||
{
|
||||
SysTick->CTRL = val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_systick_load_get(void)
|
||||
{
|
||||
return SysTick->LOAD;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_systick_load_set(uint32_t val)
|
||||
{
|
||||
SysTick->LOAD = val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_systick_val_get(void)
|
||||
{
|
||||
return SysTick->VAL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_systick_val_clear(void)
|
||||
{
|
||||
SysTick->VAL = 0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_systick_calib_get(void)
|
||||
{
|
||||
return SysTick->CALIB;
|
||||
}
|
||||
|
||||
#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
|
||||
|
||||
/** @} */
|
||||
#endif /* NRF_SYSTICK_H__ */
|
||||
91
lib/sdk/components/drivers_nrf/hal/nrf_temp.h
Normal file
91
lib/sdk/components/drivers_nrf/hal/nrf_temp.h
Normal file
@ -0,0 +1,91 @@
|
||||
/**
|
||||
* Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_TEMP_H__
|
||||
#define NRF_TEMP_H__
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup nrf_temperature TEMP (temperature) abstraction
|
||||
* @{
|
||||
* @ingroup nrf_drivers temperature_example
|
||||
* @brief Temperature module init and read functions.
|
||||
*
|
||||
*/
|
||||
|
||||
/**@cond NO_DOXYGEN */
|
||||
#define MASK_SIGN (0x00000200UL)
|
||||
#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
|
||||
|
||||
/**
|
||||
* @brief Function for preparing the temp module for temperature measurement.
|
||||
*
|
||||
* This function initializes the TEMP module and writes to the hidden configuration register.
|
||||
*/
|
||||
static __INLINE void nrf_temp_init(void)
|
||||
{
|
||||
/**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */
|
||||
*(uint32_t *) 0x4000C504 = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for reading temperature measurement.
|
||||
*
|
||||
* The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value.
|
||||
*/
|
||||
static __INLINE int32_t nrf_temp_read(void)
|
||||
{
|
||||
/**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */
|
||||
return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP);
|
||||
}
|
||||
/**@endcond */
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
630
lib/sdk/components/drivers_nrf/hal/nrf_timer.h
Normal file
630
lib/sdk/components/drivers_nrf/hal/nrf_timer.h
Normal file
@ -0,0 +1,630 @@
|
||||
/**
|
||||
* Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @defgroup nrf_timer_hal Timer HAL
|
||||
* @{
|
||||
* @ingroup nrf_timer
|
||||
*
|
||||
* @brief Hardware access layer for accessing the timer peripheral.
|
||||
*/
|
||||
|
||||
#ifndef NRF_TIMER_H__
|
||||
#define NRF_TIMER_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf_peripherals.h"
|
||||
#include "nrf.h"
|
||||
#include "nrf_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro for validating the correctness of the BIT_WIDTH setting.
|
||||
*/
|
||||
|
||||
#define TIMER_MAX_SIZE(id) CONCAT_3(TIMER, id, _MAX_SIZE)
|
||||
|
||||
#define TIMER_BIT_WIDTH_MAX(id, bit_width) \
|
||||
(TIMER_MAX_SIZE(id) == 8 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) : \
|
||||
(TIMER_MAX_SIZE(id) == 16 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \
|
||||
(bit_width == NRF_TIMER_BIT_WIDTH_16) : \
|
||||
(TIMER_MAX_SIZE(id) == 24 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \
|
||||
(bit_width == NRF_TIMER_BIT_WIDTH_16) || \
|
||||
(bit_width == NRF_TIMER_BIT_WIDTH_24) : \
|
||||
(TIMER_MAX_SIZE(id) == 32 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \
|
||||
(bit_width == NRF_TIMER_BIT_WIDTH_16) || \
|
||||
(bit_width == NRF_TIMER_BIT_WIDTH_24) || \
|
||||
(bit_width == NRF_TIMER_BIT_WIDTH_32) : \
|
||||
false))))
|
||||
|
||||
#if TIMER_COUNT > 3
|
||||
#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
|
||||
((p_reg == NRF_TIMER0) && (TIMER_BIT_WIDTH_MAX(0, bit_width))) \
|
||||
|| ((p_reg == NRF_TIMER1) && (TIMER_BIT_WIDTH_MAX(1, bit_width))) \
|
||||
|| ((p_reg == NRF_TIMER2) && (TIMER_BIT_WIDTH_MAX(2, bit_width))) \
|
||||
|| ((p_reg == NRF_TIMER3) && (TIMER_BIT_WIDTH_MAX(3, bit_width))) \
|
||||
|| ((p_reg == NRF_TIMER4) && (TIMER_BIT_WIDTH_MAX(4, bit_width))) )
|
||||
|
||||
#else
|
||||
#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
|
||||
((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
|
||||
|| ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
|
||||
|| ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) )
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Macro for getting the number of capture/compare channels available
|
||||
* in a given timer instance.
|
||||
*/
|
||||
#define NRF_TIMER_CC_CHANNEL_COUNT(id) CONCAT_3(TIMER, id, _CC_NUM)
|
||||
|
||||
/**
|
||||
* @brief Timer tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30 -esym(628,__INTADDR__)*/
|
||||
NRF_TIMER_TASK_START = offsetof(NRF_TIMER_Type, TASKS_START), ///< Task for starting the timer.
|
||||
NRF_TIMER_TASK_STOP = offsetof(NRF_TIMER_Type, TASKS_STOP), ///< Task for stopping the timer.
|
||||
NRF_TIMER_TASK_COUNT = offsetof(NRF_TIMER_Type, TASKS_COUNT), ///< Task for incrementing the timer (in counter mode).
|
||||
NRF_TIMER_TASK_CLEAR = offsetof(NRF_TIMER_Type, TASKS_CLEAR), ///< Task for resetting the timer value.
|
||||
NRF_TIMER_TASK_SHUTDOWN = offsetof(NRF_TIMER_Type, TASKS_SHUTDOWN), ///< Task for powering off the timer.
|
||||
NRF_TIMER_TASK_CAPTURE0 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[0]), ///< Task for capturing the timer value on channel 0.
|
||||
NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1.
|
||||
NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2.
|
||||
NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3.
|
||||
#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
|
||||
NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4.
|
||||
NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5.
|
||||
#endif
|
||||
/*lint -restore*/
|
||||
} nrf_timer_task_t;
|
||||
|
||||
/**
|
||||
* @brief Timer events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_TIMER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0.
|
||||
NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1.
|
||||
NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2.
|
||||
NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3.
|
||||
#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
|
||||
NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4.
|
||||
NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5.
|
||||
#endif
|
||||
/*lint -restore*/
|
||||
} nrf_timer_event_t;
|
||||
|
||||
/**
|
||||
* @brief Types of timer shortcuts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TIMER_SHORT_COMPARE0_STOP_MASK = TIMER_SHORTS_COMPARE0_STOP_Msk, ///< Shortcut for stopping the timer based on compare 0.
|
||||
NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk, ///< Shortcut for stopping the timer based on compare 1.
|
||||
NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk, ///< Shortcut for stopping the timer based on compare 2.
|
||||
NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk, ///< Shortcut for stopping the timer based on compare 3.
|
||||
#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
|
||||
NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk, ///< Shortcut for stopping the timer based on compare 4.
|
||||
NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk, ///< Shortcut for stopping the timer based on compare 5.
|
||||
#endif
|
||||
NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0.
|
||||
NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1.
|
||||
NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2.
|
||||
NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3.
|
||||
#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
|
||||
NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4.
|
||||
NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5.
|
||||
#endif
|
||||
} nrf_timer_short_mask_t;
|
||||
|
||||
/**
|
||||
* @brief Timer modes.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TIMER_MODE_TIMER = TIMER_MODE_MODE_Timer, ///< Timer mode: timer.
|
||||
NRF_TIMER_MODE_COUNTER = TIMER_MODE_MODE_Counter, ///< Timer mode: counter.
|
||||
#if defined(TIMER_MODE_MODE_LowPowerCounter) || defined(__SDK_DOXYGEN__)
|
||||
NRF_TIMER_MODE_LOW_POWER_COUNTER = TIMER_MODE_MODE_LowPowerCounter, ///< Timer mode: low-power counter.
|
||||
#endif
|
||||
} nrf_timer_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Timer bit width.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TIMER_BIT_WIDTH_8 = TIMER_BITMODE_BITMODE_08Bit, ///< Timer bit width 8 bit.
|
||||
NRF_TIMER_BIT_WIDTH_16 = TIMER_BITMODE_BITMODE_16Bit, ///< Timer bit width 16 bit.
|
||||
NRF_TIMER_BIT_WIDTH_24 = TIMER_BITMODE_BITMODE_24Bit, ///< Timer bit width 24 bit.
|
||||
NRF_TIMER_BIT_WIDTH_32 = TIMER_BITMODE_BITMODE_32Bit ///< Timer bit width 32 bit.
|
||||
} nrf_timer_bit_width_t;
|
||||
|
||||
/**
|
||||
* @brief Timer prescalers.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TIMER_FREQ_16MHz = 0, ///< Timer frequency 16 MHz.
|
||||
NRF_TIMER_FREQ_8MHz, ///< Timer frequency 8 MHz.
|
||||
NRF_TIMER_FREQ_4MHz, ///< Timer frequency 4 MHz.
|
||||
NRF_TIMER_FREQ_2MHz, ///< Timer frequency 2 MHz.
|
||||
NRF_TIMER_FREQ_1MHz, ///< Timer frequency 1 MHz.
|
||||
NRF_TIMER_FREQ_500kHz, ///< Timer frequency 500 kHz.
|
||||
NRF_TIMER_FREQ_250kHz, ///< Timer frequency 250 kHz.
|
||||
NRF_TIMER_FREQ_125kHz, ///< Timer frequency 125 kHz.
|
||||
NRF_TIMER_FREQ_62500Hz, ///< Timer frequency 62500 Hz.
|
||||
NRF_TIMER_FREQ_31250Hz ///< Timer frequency 31250 Hz.
|
||||
} nrf_timer_frequency_t;
|
||||
|
||||
/**
|
||||
* @brief Timer capture/compare channels.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TIMER_CC_CHANNEL0 = 0, ///< Timer capture/compare channel 0.
|
||||
NRF_TIMER_CC_CHANNEL1, ///< Timer capture/compare channel 1.
|
||||
NRF_TIMER_CC_CHANNEL2, ///< Timer capture/compare channel 2.
|
||||
NRF_TIMER_CC_CHANNEL3, ///< Timer capture/compare channel 3.
|
||||
#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
|
||||
NRF_TIMER_CC_CHANNEL4, ///< Timer capture/compare channel 4.
|
||||
NRF_TIMER_CC_CHANNEL5, ///< Timer capture/compare channel 5.
|
||||
#endif
|
||||
} nrf_timer_cc_channel_t;
|
||||
|
||||
/**
|
||||
* @brief Timer interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TIMER_INT_COMPARE0_MASK = TIMER_INTENSET_COMPARE0_Msk, ///< Timer interrupt from compare event on channel 0.
|
||||
NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1.
|
||||
NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2.
|
||||
NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3.
|
||||
#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
|
||||
NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4.
|
||||
NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5.
|
||||
#endif
|
||||
} nrf_timer_int_mask_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific timer task.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] task Task to activate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific timer task register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] task Requested task.
|
||||
*
|
||||
* @return Address of the specified task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific timer event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific timer event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to check.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific timer event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Requested event.
|
||||
*
|
||||
* @return Address of the specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] timer_shorts_mask Shortcuts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] timer_shorts_mask Shortcuts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] timer_int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] timer_int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] timer_int Interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_int);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the timer mode.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] mode Timer mode.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the timer mode.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Timer mode.
|
||||
*/
|
||||
__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the timer bit width.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] bit_width Timer bit width.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_bit_width_t bit_width);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the timer bit width.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Timer bit width.
|
||||
*/
|
||||
__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the timer frequency.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] frequency Timer frequency.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_frequency_t frequency);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the timer frequency.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Timer frequency.
|
||||
*/
|
||||
__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for writing the capture/compare register for a specified channel.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] cc_channel Requested capture/compare channel.
|
||||
* @param[in] cc_value Value to write to the capture/compare register.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_cc_channel_t cc_channel,
|
||||
uint32_t cc_value);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the capture/compare value for a specified channel.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] cc_channel Requested capture/compare channel.
|
||||
*
|
||||
* @return Value from the requested capture/compare register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_cc_channel_t cc_channel);
|
||||
|
||||
/**
|
||||
* @brief Function for getting a specific timer capture task.
|
||||
*
|
||||
* @param[in] channel Capture channel.
|
||||
*
|
||||
* @return Capture task.
|
||||
*/
|
||||
__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel);
|
||||
|
||||
/**
|
||||
* @brief Function for getting a specific timer compare event.
|
||||
*
|
||||
* @param[in] channel Compare channel.
|
||||
*
|
||||
* @return Compare event.
|
||||
*/
|
||||
__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel);
|
||||
|
||||
/**
|
||||
* @brief Function for getting a specific timer compare interrupt.
|
||||
*
|
||||
* @param[in] channel Compare channel.
|
||||
*
|
||||
* @return Compare interrupt.
|
||||
*/
|
||||
__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel);
|
||||
|
||||
/**
|
||||
* @brief Function for calculating the number of timer ticks for a given time
|
||||
* (in microseconds) and timer frequency.
|
||||
*
|
||||
* @param[in] time_us Time in microseconds.
|
||||
* @param[in] frequency Timer frequency.
|
||||
*
|
||||
* @return Number of timer ticks.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
|
||||
nrf_timer_frequency_t frequency);
|
||||
|
||||
/**
|
||||
* @brief Function for calculating the number of timer ticks for a given time
|
||||
* (in milliseconds) and timer frequency.
|
||||
*
|
||||
* @param[in] time_ms Time in milliseconds.
|
||||
* @param[in] frequency Timer frequency.
|
||||
*
|
||||
* @return Number of timer ticks.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
|
||||
nrf_timer_frequency_t frequency);
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_task_t task)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_event_t event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_event_t event)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS |= timer_shorts_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS &= ~(timer_shorts_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_int_mask)
|
||||
{
|
||||
p_reg->INTENSET = timer_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = timer_int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg,
|
||||
uint32_t timer_int)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & timer_int);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_mode_t mode)
|
||||
{
|
||||
p_reg->MODE = (p_reg->MODE & ~TIMER_MODE_MODE_Msk) |
|
||||
((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg)
|
||||
{
|
||||
return (nrf_timer_mode_t)(p_reg->MODE);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_bit_width_t bit_width)
|
||||
{
|
||||
p_reg->BITMODE = (p_reg->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) |
|
||||
((bit_width << TIMER_BITMODE_BITMODE_Pos) &
|
||||
TIMER_BITMODE_BITMODE_Msk);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg)
|
||||
{
|
||||
return (nrf_timer_bit_width_t)(p_reg->BITMODE);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_frequency_t frequency)
|
||||
{
|
||||
p_reg->PRESCALER = (p_reg->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) |
|
||||
((frequency << TIMER_PRESCALER_PRESCALER_Pos) &
|
||||
TIMER_PRESCALER_PRESCALER_Msk);
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg)
|
||||
{
|
||||
return (nrf_timer_frequency_t)(p_reg->PRESCALER);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_cc_channel_t cc_channel,
|
||||
uint32_t cc_value)
|
||||
{
|
||||
p_reg->CC[cc_channel] = cc_value;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg,
|
||||
nrf_timer_cc_channel_t cc_channel)
|
||||
{
|
||||
return (uint32_t)p_reg->CC[cc_channel];
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel)
|
||||
{
|
||||
return (nrf_timer_task_t)
|
||||
((uint32_t)NRF_TIMER_TASK_CAPTURE0 + (channel * sizeof(uint32_t)));
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel)
|
||||
{
|
||||
return (nrf_timer_event_t)
|
||||
((uint32_t)NRF_TIMER_EVENT_COMPARE0 + (channel * sizeof(uint32_t)));
|
||||
}
|
||||
|
||||
__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel)
|
||||
{
|
||||
return (nrf_timer_int_mask_t)
|
||||
((uint32_t)NRF_TIMER_INT_COMPARE0_MASK << channel);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
|
||||
nrf_timer_frequency_t frequency)
|
||||
{
|
||||
// The "frequency" parameter here is actually the prescaler value, and the
|
||||
// timer runs at the following frequency: f = 16 MHz / 2^prescaler.
|
||||
uint32_t prescaler = (uint32_t)frequency;
|
||||
ASSERT(time_us <= (UINT32_MAX / 16UL));
|
||||
return ((time_us * 16UL) >> prescaler);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
|
||||
nrf_timer_frequency_t frequency)
|
||||
{
|
||||
// The "frequency" parameter here is actually the prescaler value, and the
|
||||
// timer runs at the following frequency: f = 16000 kHz / 2^prescaler.
|
||||
uint32_t prescaler = (uint32_t)frequency;
|
||||
ASSERT(time_ms <= (UINT32_MAX / 16000UL));
|
||||
return ((time_ms * 16000UL) >> prescaler);
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_TIMER_H__
|
||||
|
||||
/** @} */
|
||||
452
lib/sdk/components/drivers_nrf/hal/nrf_twi.h
Normal file
452
lib/sdk/components/drivers_nrf/hal/nrf_twi.h
Normal file
@ -0,0 +1,452 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_TWI_H__
|
||||
#define NRF_TWI_H__
|
||||
|
||||
/**
|
||||
* @defgroup nrf_twi_hal TWI HAL
|
||||
* @{
|
||||
* @ingroup nrf_twi
|
||||
*
|
||||
* @brief Hardware access layer for managing the TWI peripheral.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "nrf_peripherals.h"
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TWI tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_TWI_TASK_STARTRX = offsetof(NRF_TWI_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
|
||||
NRF_TWI_TASK_STARTTX = offsetof(NRF_TWI_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
|
||||
NRF_TWI_TASK_STOP = offsetof(NRF_TWI_Type, TASKS_STOP), ///< Stop TWI transaction.
|
||||
NRF_TWI_TASK_SUSPEND = offsetof(NRF_TWI_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
|
||||
NRF_TWI_TASK_RESUME = offsetof(NRF_TWI_Type, TASKS_RESUME) ///< Resume TWI transaction.
|
||||
/*lint -restore*/
|
||||
} nrf_twi_task_t;
|
||||
|
||||
/**
|
||||
* @brief TWI events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_TWI_EVENT_STOPPED = offsetof(NRF_TWI_Type, EVENTS_STOPPED), ///< TWI stopped.
|
||||
NRF_TWI_EVENT_RXDREADY = offsetof(NRF_TWI_Type, EVENTS_RXDREADY), ///< TWI RXD byte received.
|
||||
NRF_TWI_EVENT_TXDSENT = offsetof(NRF_TWI_Type, EVENTS_TXDSENT), ///< TWI TXD byte sent.
|
||||
NRF_TWI_EVENT_ERROR = offsetof(NRF_TWI_Type, EVENTS_ERROR), ///< TWI error.
|
||||
NRF_TWI_EVENT_BB = offsetof(NRF_TWI_Type, EVENTS_BB), ///< TWI byte boundary, generated before each byte that is sent or received.
|
||||
NRF_TWI_EVENT_SUSPENDED = offsetof(NRF_TWI_Type, EVENTS_SUSPENDED) ///< TWI entered the suspended state.
|
||||
/*lint -restore*/
|
||||
} nrf_twi_event_t;
|
||||
|
||||
/**
|
||||
* @brief TWI shortcuts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWI_SHORT_BB_SUSPEND_MASK = TWI_SHORTS_BB_SUSPEND_Msk, ///< Shortcut between BB event and SUSPEND task.
|
||||
NRF_TWI_SHORT_BB_STOP_MASK = TWI_SHORTS_BB_STOP_Msk, ///< Shortcut between BB event and STOP task.
|
||||
} nrf_twi_short_mask_t;
|
||||
|
||||
/**
|
||||
* @brief TWI interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWI_INT_STOPPED_MASK = TWI_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
|
||||
NRF_TWI_INT_RXDREADY_MASK = TWI_INTENSET_RXDREADY_Msk, ///< Interrupt on RXDREADY event.
|
||||
NRF_TWI_INT_TXDSENT_MASK = TWI_INTENSET_TXDSENT_Msk, ///< Interrupt on TXDSENT event.
|
||||
NRF_TWI_INT_ERROR_MASK = TWI_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
|
||||
NRF_TWI_INT_BB_MASK = TWI_INTENSET_BB_Msk, ///< Interrupt on BB event.
|
||||
NRF_TWI_INT_SUSPENDED_MASK = TWI_INTENSET_SUSPENDED_Msk ///< Interrupt on SUSPENDED event.
|
||||
} nrf_twi_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief TWI error source.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWI_ERROR_ADDRESS_NACK = TWI_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
|
||||
NRF_TWI_ERROR_DATA_NACK = TWI_ERRORSRC_DNACK_Msk, ///< NACK received after sending a data byte.
|
||||
NRF_TWI_ERROR_OVERRUN = TWI_ERRORSRC_OVERRUN_Msk ///< Overrun error.
|
||||
/**< A new byte was received before the previous byte was read
|
||||
* from the RXD register (previous data is lost). */
|
||||
} nrf_twi_error_t;
|
||||
|
||||
/**
|
||||
* @brief TWI master clock frequency.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWI_FREQ_100K = TWI_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
|
||||
NRF_TWI_FREQ_250K = TWI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
|
||||
NRF_TWI_FREQ_400K = TWI_FREQUENCY_FREQUENCY_K400 ///< 400 kbps.
|
||||
} nrf_twi_frequency_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific TWI task.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] task Task to activate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific TWI task register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] task Requested task.
|
||||
*
|
||||
* @return Address of the specified task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific TWI event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to check.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific TWI event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Requested event.
|
||||
*
|
||||
* @return Address of the specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] shorts_mask Shortcuts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg,
|
||||
uint32_t shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] shorts_mask Shortcuts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg,
|
||||
uint32_t shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg,
|
||||
uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg,
|
||||
uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] int_mask Interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_int_mask_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the TWI peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the TWI peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring TWI pins.
|
||||
*
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] scl_pin SCL pin number.
|
||||
* @param[in] sda_pin SDA pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg,
|
||||
uint32_t scl_pin,
|
||||
uint32_t sda_pin);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the TWI master clock frequency.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] frequency TWI frequency.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_frequency_t frequency);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the TWI error source.
|
||||
*
|
||||
* The error flags are cleared after reading.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Mask with error source flags.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the address to be used in TWI transfers.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] address Address to be used in transfers.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address);
|
||||
|
||||
/**
|
||||
* @brief Function for reading data received by TWI.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Received data.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for writing data to be transmitted by TWI.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] data Data to be transmitted.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data);
|
||||
|
||||
__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg,
|
||||
uint32_t shorts_mask);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_task_t task)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_event_t event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_event_t event)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg,
|
||||
uint32_t shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS |= shorts_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg,
|
||||
uint32_t shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS &= ~(shorts_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg,
|
||||
uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENSET = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg,
|
||||
uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_int_mask_t int_mask)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & int_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg,
|
||||
uint32_t scl_pin,
|
||||
uint32_t sda_pin)
|
||||
{
|
||||
#if defined(TWI_PSEL_SCL_CONNECT_Pos)
|
||||
p_reg->PSEL.SCL = scl_pin;
|
||||
#else
|
||||
p_reg->PSELSCL = scl_pin;
|
||||
#endif
|
||||
|
||||
#if defined(TWI_PSEL_SDA_CONNECT_Pos)
|
||||
p_reg->PSEL.SDA = sda_pin;
|
||||
#else
|
||||
p_reg->PSELSDA = sda_pin;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg,
|
||||
nrf_twi_frequency_t frequency)
|
||||
{
|
||||
p_reg->FREQUENCY = frequency;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg)
|
||||
{
|
||||
uint32_t error_source = p_reg->ERRORSRC;
|
||||
|
||||
// [error flags are cleared by writing '1' on their position]
|
||||
p_reg->ERRORSRC = error_source;
|
||||
|
||||
return error_source;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address)
|
||||
{
|
||||
p_reg->ADDRESS = address;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg)
|
||||
{
|
||||
return (uint8_t)p_reg->RXD;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data)
|
||||
{
|
||||
p_reg->TXD = data;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg,
|
||||
uint32_t shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS = shorts_mask;
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_TWI_H__
|
||||
527
lib/sdk/components/drivers_nrf/hal/nrf_twim.h
Normal file
527
lib/sdk/components/drivers_nrf/hal/nrf_twim.h
Normal file
@ -0,0 +1,527 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_TWIM_H__
|
||||
#define NRF_TWIM_H__
|
||||
|
||||
/**
|
||||
* @defgroup nrf_twim_hal TWIM HAL
|
||||
* @{
|
||||
* @ingroup nrf_twi
|
||||
*
|
||||
* @brief Hardware access layer for managing the TWIM peripheral.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TWIM tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
|
||||
NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
|
||||
NRF_TWIM_TASK_STOP = offsetof(NRF_TWIM_Type, TASKS_STOP), ///< Stop TWI transaction.
|
||||
NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
|
||||
NRF_TWIM_TASK_RESUME = offsetof(NRF_TWIM_Type, TASKS_RESUME) ///< Resume TWI transaction.
|
||||
/*lint -restore*/
|
||||
} nrf_twim_task_t;
|
||||
|
||||
/**
|
||||
* @brief TWIM events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped.
|
||||
NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error.
|
||||
NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended.
|
||||
NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started.
|
||||
NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started.
|
||||
NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte.
|
||||
NRF_TWIM_EVENT_LASTTX = offsetof(NRF_TWIM_Type, EVENTS_LASTTX) ///< Byte boundary, starting to transmit the last byte.
|
||||
/*lint -restore*/
|
||||
} nrf_twim_event_t;
|
||||
|
||||
/**
|
||||
* @brief TWIM shortcuts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task.
|
||||
NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK = TWIM_SHORTS_LASTTX_SUSPEND_Msk, ///< Shortcut between LASTTX event and SUSPEND task.
|
||||
NRF_TWIM_SHORT_LASTTX_STOP_MASK = TWIM_SHORTS_LASTTX_STOP_Msk, ///< Shortcut between LASTTX event and STOP task.
|
||||
NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_STARTTX_Msk, ///< Shortcut between LASTRX event and STARTTX task.
|
||||
NRF_TWIM_SHORT_LASTRX_STOP_MASK = TWIM_SHORTS_LASTRX_STOP_Msk ///< Shortcut between LASTRX event and STOP task.
|
||||
} nrf_twim_short_mask_t;
|
||||
|
||||
/**
|
||||
* @brief TWIM interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWIM_INT_STOPPED_MASK = TWIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
|
||||
NRF_TWIM_INT_ERROR_MASK = TWIM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
|
||||
NRF_TWIM_INT_SUSPENDED_MASK = (1 << 18), ///< Interrupt on SUSPENDED event.
|
||||
NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
|
||||
NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
|
||||
NRF_TWIM_INT_LASTRX_MASK = TWIM_INTENSET_LASTRX_Msk, ///< Interrupt on LASTRX event.
|
||||
NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk ///< Interrupt on LASTTX event.
|
||||
} nrf_twim_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief TWIM master clock frequency.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
|
||||
NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
|
||||
NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400, ///< 400 kbps.
|
||||
#ifndef TWI_PRESENT
|
||||
NRF_TWI_FREQ_100K = NRF_TWIM_FREQ_100K,
|
||||
NRF_TWI_FREQ_250K = NRF_TWIM_FREQ_250K,
|
||||
NRF_TWI_FREQ_400K = NRF_TWIM_FREQ_400K,
|
||||
#endif
|
||||
} nrf_twim_frequency_t;
|
||||
|
||||
/**
|
||||
* @brief TWIM error source.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
|
||||
NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk, ///< NACK received after sending a data byte.
|
||||
#ifndef TWI_PRESENT
|
||||
NRF_TWI_ERROR_ADDRESS_NACK = NRF_TWIM_ERROR_ADDRESS_NACK,
|
||||
NRF_TWI_ERROR_DATA_NACK = NRF_TWIM_ERROR_DATA_NACK,
|
||||
#endif
|
||||
} nrf_twim_error_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific TWIM task.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] task Task to activate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific TWIM task register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] task Requested task.
|
||||
*
|
||||
* @return Address of the specified task register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific TWIM event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific TWIM event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to check.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific TWIM event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Requested event.
|
||||
*
|
||||
* @return Address of the specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] shorts_mask Shortcuts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
|
||||
uint32_t shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] shorts_mask Shortcuts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
|
||||
uint32_t shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
|
||||
uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specified interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
|
||||
uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a given interrupt.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] int_mask Interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_int_mask_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the TWIM peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the TWIM peripheral.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring TWI pins.
|
||||
*
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] scl_pin SCL pin number.
|
||||
* @param[in] sda_pin SDA pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
|
||||
uint32_t scl_pin,
|
||||
uint32_t sda_pin);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the TWI master clock frequency.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] frequency TWI frequency.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_frequency_t frequency);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the TWI error source.
|
||||
*
|
||||
* The error flags are cleared after reading.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Mask with error source flags.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the address to be used in TWI transfers.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] address Address to be used in transfers.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
|
||||
uint8_t address);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the transmit buffer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] p_buffer Pointer to the buffer with data to send.
|
||||
* @param[in] length Maximum number of data bytes to transmit.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
|
||||
uint8_t const * p_buffer,
|
||||
uint8_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the receive buffer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] p_buffer Pointer to the buffer for received data.
|
||||
* @param[in] length Maximum number of data bytes to receive.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
|
||||
uint8_t * p_buffer,
|
||||
uint8_t length);
|
||||
|
||||
__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
|
||||
uint32_t shorts_mask);
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg);
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the TX list feature.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the TX list feature.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the RX list feature.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the RX list feature.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_task_t task)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_event_t event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_event_t event)
|
||||
{
|
||||
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
|
||||
uint32_t shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS |= shorts_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
|
||||
uint32_t shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS &= ~(shorts_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
|
||||
uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENSET = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
|
||||
uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_int_mask_t int_mask)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & int_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
|
||||
uint32_t scl_pin,
|
||||
uint32_t sda_pin)
|
||||
{
|
||||
p_reg->PSEL.SCL = scl_pin;
|
||||
p_reg->PSEL.SDA = sda_pin;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
|
||||
nrf_twim_frequency_t frequency)
|
||||
{
|
||||
p_reg->FREQUENCY = frequency;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg)
|
||||
{
|
||||
uint32_t error_source = p_reg->ERRORSRC;
|
||||
|
||||
// [error flags are cleared by writing '1' on their position]
|
||||
p_reg->ERRORSRC = error_source;
|
||||
|
||||
return error_source;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
|
||||
uint8_t address)
|
||||
{
|
||||
p_reg->ADDRESS = address;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
|
||||
uint8_t const * p_buffer,
|
||||
uint8_t length)
|
||||
{
|
||||
p_reg->TXD.PTR = (uint32_t)p_buffer;
|
||||
p_reg->TXD.MAXCNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
|
||||
uint8_t * p_buffer,
|
||||
uint8_t length)
|
||||
{
|
||||
p_reg->RXD.PTR = (uint32_t)p_buffer;
|
||||
p_reg->RXD.MAXCNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
|
||||
uint32_t shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS = shorts_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg)
|
||||
{
|
||||
return p_reg->TXD.AMOUNT;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg)
|
||||
{
|
||||
return p_reg->RXD.AMOUNT;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg)
|
||||
{
|
||||
p_reg->TXD.LIST = 1;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg)
|
||||
{
|
||||
p_reg->TXD.LIST = 0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg)
|
||||
{
|
||||
p_reg->RXD.LIST = 1;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg)
|
||||
{
|
||||
p_reg->RXD.LIST = 0;
|
||||
}
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_TWIM_H__
|
||||
706
lib/sdk/components/drivers_nrf/hal/nrf_twis.h
Normal file
706
lib/sdk/components/drivers_nrf/hal/nrf_twis.h
Normal file
@ -0,0 +1,706 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @ingroup nrf_twis
|
||||
* @defgroup nrf_twis_hal TWIS HAL
|
||||
* @{
|
||||
*
|
||||
* @brief @tagAPI52 Hardware access layer for Two Wire Interface Slave with EasyDMA
|
||||
* (TWIS) peripheral.
|
||||
*/
|
||||
#ifndef NRF_TWIS_H__
|
||||
#define NRF_TWIS_H__
|
||||
|
||||
#include "nrf.h"
|
||||
#include "sdk_config.h"
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TWIS tasks
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_TWIS_TASK_STOP = offsetof(NRF_TWIS_Type, TASKS_STOP), /**< Stop TWIS transaction */
|
||||
NRF_TWIS_TASK_SUSPEND = offsetof(NRF_TWIS_Type, TASKS_SUSPEND), /**< Suspend TWIS transaction */
|
||||
NRF_TWIS_TASK_RESUME = offsetof(NRF_TWIS_Type, TASKS_RESUME), /**< Resume TWIS transaction */
|
||||
NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command */
|
||||
NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX) /**< Prepare the TWIS slave to respond to a read command */
|
||||
/*lint -restore*/
|
||||
} nrf_twis_task_t;
|
||||
|
||||
/**
|
||||
* @brief TWIS events
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_TWIS_EVENT_STOPPED = offsetof(NRF_TWIS_Type, EVENTS_STOPPED), /**< TWIS stopped */
|
||||
NRF_TWIS_EVENT_ERROR = offsetof(NRF_TWIS_Type, EVENTS_ERROR), /**< TWIS error */
|
||||
NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started */
|
||||
NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started */
|
||||
NRF_TWIS_EVENT_WRITE = offsetof(NRF_TWIS_Type, EVENTS_WRITE), /**< Write command received */
|
||||
NRF_TWIS_EVENT_READ = offsetof(NRF_TWIS_Type, EVENTS_READ) /**< Read command received */
|
||||
/*lint -restore*/
|
||||
} nrf_twis_event_t;
|
||||
|
||||
/**
|
||||
* @brief TWIS shortcuts
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWIS_SHORT_WRITE_SUSPEND_MASK = TWIS_SHORTS_WRITE_SUSPEND_Msk, /**< Shortcut between WRITE event and SUSPEND task */
|
||||
NRF_TWIS_SHORT_READ_SUSPEND_MASK = TWIS_SHORTS_READ_SUSPEND_Msk, /**< Shortcut between READ event and SUSPEND task */
|
||||
} nrf_twis_short_mask_t;
|
||||
|
||||
/**
|
||||
* @brief TWIS interrupts
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWIS_INT_STOPPED_MASK = TWIS_INTEN_STOPPED_Msk, /**< Interrupt on STOPPED event */
|
||||
NRF_TWIS_INT_ERROR_MASK = TWIS_INTEN_ERROR_Msk, /**< Interrupt on ERROR event */
|
||||
NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event */
|
||||
NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event */
|
||||
NRF_TWIS_INT_WRITE_MASK = TWIS_INTEN_WRITE_Msk, /**< Interrupt on WRITE event */
|
||||
NRF_TWIS_INT_READ_MASK = TWIS_INTEN_READ_Msk, /**< Interrupt on READ event */
|
||||
} nrf_twis_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief TWIS error source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWIS_ERROR_OVERFLOW = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented */
|
||||
NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk, /**< NACK sent after receiving a data byte */
|
||||
NRF_TWIS_ERROR_OVERREAD = TWIS_ERRORSRC_OVERREAD_Msk /**< TX buffer over-read detected, and prevented */
|
||||
} nrf_twis_error_t;
|
||||
|
||||
/**
|
||||
* @brief TWIS address matching configuration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_TWIS_CONFIG_ADDRESS0_MASK = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0] */
|
||||
NRF_TWIS_CONFIG_ADDRESS1_MASK = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1] */
|
||||
NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching */
|
||||
} nrf_twis_config_addr_mask_t;
|
||||
|
||||
/**
|
||||
* @brief Variable type to hold amount of data for EasyDMA
|
||||
*
|
||||
* Variable of the minimum size that can hold the amount of data to transfer.
|
||||
*
|
||||
* @note
|
||||
* Defined to make it simple to change if EasyDMA would be updated to support more data in
|
||||
* the future devices to.
|
||||
*/
|
||||
typedef uint8_t nrf_twis_amount_t;
|
||||
|
||||
/**
|
||||
* @brief Smallest variable type to hold TWI address
|
||||
*
|
||||
* Variable of the minimum size that can hold single TWI address.
|
||||
*
|
||||
* @note
|
||||
* Defined to make it simple to change if new TWI would support for example
|
||||
* 10 bit addressing mode.
|
||||
*/
|
||||
typedef uint8_t nrf_twis_address_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for activating a specific TWIS task.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param task Task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific TWIS task register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param task Task.
|
||||
*
|
||||
* @return Task address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_twis_task_address_get(
|
||||
NRF_TWIS_Type const * const p_reg,
|
||||
nrf_twis_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param event Event.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_event_clear(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
nrf_twis_event_t event);
|
||||
/**
|
||||
* @brief Function for returning the state of a specific event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param event Event.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_twis_event_check(
|
||||
NRF_TWIS_Type const * const p_reg,
|
||||
nrf_twis_event_t event);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for getting and clearing the state of specific event
|
||||
*
|
||||
* This function checks the state of the event and clears it.
|
||||
* @param[in,out] p_reg Pointer to the peripheral registers structure.
|
||||
* @param event Event.
|
||||
*
|
||||
* @retval true If the event was set.
|
||||
* @retval false If the event was not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_twis_event_get_and_clear(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
nrf_twis_event_t event);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific TWIS event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param event Event.
|
||||
*
|
||||
* @return Address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_twis_event_address_get(
|
||||
NRF_TWIS_Type const * const p_reg,
|
||||
nrf_twis_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for setting a shortcut.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param short_mask Shortcuts mask.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing shortcuts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param short_mask Shortcuts mask.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask);
|
||||
|
||||
/**
|
||||
* @brief Get the shorts mask
|
||||
*
|
||||
* Function returns shorts register.
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @return Flags of currently enabled shortcuts
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling selected interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param int_mask Interrupts mask.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of selected interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param int_mask Interrupts mask.
|
||||
*
|
||||
* @retval true If any of selected interrupts is enabled.
|
||||
* @retval false If none of selected interrupts is enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling selected interrupts.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param int_mask Interrupts mask.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving and clearing the TWIS error source.
|
||||
*
|
||||
* @attention Error sources are cleared after read.
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @return Error source mask with values from @ref nrf_twis_error_t.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg);
|
||||
|
||||
/**
|
||||
* @brief Get information which of addresses matched
|
||||
*
|
||||
* Function returns index in the address table
|
||||
* that points to the address that already matched.
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @return Index of matched address
|
||||
*/
|
||||
__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling TWIS.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * const p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling TWIS.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * const p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring TWIS pins.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param scl SCL pin number.
|
||||
* @param sda SDA pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the receive buffer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param p_buf Pointer to the buffer for received data.
|
||||
* @param length Maximum number of data bytes to receive.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_rx_buffer_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t * p_buf,
|
||||
nrf_twis_amount_t length);
|
||||
|
||||
/**
|
||||
* @brief Function that prepares TWIS for receiving
|
||||
*
|
||||
* This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task.
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param p_buf Pointer to the buffer for received data.
|
||||
* @param length Maximum number of data bytes to receive.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_rx_prepare(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t * p_buf,
|
||||
nrf_twis_amount_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for getting number of bytes received in the last transaction.
|
||||
*
|
||||
* @param[in] p_reg TWIS instance.
|
||||
* @return Amount of bytes received.
|
||||
* */
|
||||
__STATIC_INLINE nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the transmit buffer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param p_buf Pointer to the buffer with data to send.
|
||||
* @param length Maximum number of data bytes to transmit.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_tx_buffer_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t const * p_buf,
|
||||
nrf_twis_amount_t length);
|
||||
|
||||
/**
|
||||
* @brief Function that prepares TWIS for transmitting
|
||||
*
|
||||
* This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task.
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param p_buf Pointer to the buffer with data to send.
|
||||
* @param length Maximum number of data bytes to transmit.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_tx_prepare(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t const * p_buf,
|
||||
nrf_twis_amount_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for getting number of bytes transmitted in the last transaction.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @return Amount of bytes transmitted.
|
||||
*/
|
||||
__STATIC_INLINE nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting slave address
|
||||
*
|
||||
* Function sets the selected address for this TWI interface.
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param n Index of address to set
|
||||
* @param addr Addres to set
|
||||
* @sa nrf_twis_config_address_set
|
||||
* @sa nrf_twis_config_address_get
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_address_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint_fast8_t n,
|
||||
nrf_twis_address_t addr);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving configured slave address
|
||||
*
|
||||
* Function gets the selected address for this TWI interface.
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param n Index of address to get
|
||||
*/
|
||||
__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(
|
||||
NRF_TWIS_Type const * const p_reg,
|
||||
uint_fast8_t n);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the device address configuration.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param addr_mask Mask of address indexes of what device should answer to.
|
||||
*
|
||||
* @sa nrf_twis_address_set
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_config_address_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
nrf_twis_config_addr_mask_t addr_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the device address configuration.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Mask of address indexes of what device should answer to.
|
||||
*/
|
||||
__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(
|
||||
NRF_TWIS_Type const * const p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the over-read character.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] orc Over-read character. Character clocked out in case of
|
||||
* over-read of the TXD buffer.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_twis_orc_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t orc);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the over-read character.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @return Over-read character configured for selected instance.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg);
|
||||
|
||||
|
||||
/** @} */ /* End of nrf_twis_hal */
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
/* ------------------------------------------------------------------------------------------------
|
||||
* Internal functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* @internal
|
||||
* @brief Internal function for getting task/event register address
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @oaram offset Offset of the register from the instance beginning
|
||||
*
|
||||
* @attention offset has to be modulo 4 value. In other case we can get hardware fault.
|
||||
* @return Pointer to the register
|
||||
*/
|
||||
__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type * const p_reg, uint32_t offset)
|
||||
{
|
||||
return (volatile uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
|
||||
}
|
||||
|
||||
/**
|
||||
* @internal
|
||||
* @brief Internal function for getting task/event register address - constant version
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @oaram offset Offset of the register from the instance beginning
|
||||
*
|
||||
* @attention offset has to be modulo 4 value. In other case we can get hardware fault.
|
||||
* @return Pointer to the register
|
||||
*/
|
||||
__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * const p_reg, uint32_t offset)
|
||||
{
|
||||
return (volatile const uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------------------------------
|
||||
* Interface functions definitions
|
||||
*/
|
||||
|
||||
|
||||
void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task)
|
||||
{
|
||||
*(nrf_twis_getRegPtr(p_reg, (uint32_t)task)) = 1UL;
|
||||
}
|
||||
|
||||
uint32_t nrf_twis_task_address_get(
|
||||
NRF_TWIS_Type const * const p_reg,
|
||||
nrf_twis_task_t task)
|
||||
{
|
||||
return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)task);
|
||||
}
|
||||
|
||||
void nrf_twis_event_clear(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
nrf_twis_event_t event)
|
||||
{
|
||||
*(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
bool nrf_twis_event_check(
|
||||
NRF_TWIS_Type const * const p_reg,
|
||||
nrf_twis_event_t event)
|
||||
{
|
||||
return (bool)*nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
|
||||
}
|
||||
|
||||
bool nrf_twis_event_get_and_clear(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
nrf_twis_event_t event)
|
||||
{
|
||||
bool ret = nrf_twis_event_check(p_reg, event);
|
||||
if (ret)
|
||||
{
|
||||
nrf_twis_event_clear(p_reg, event);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint32_t nrf_twis_event_address_get(
|
||||
NRF_TWIS_Type const * const p_reg,
|
||||
nrf_twis_event_t event)
|
||||
{
|
||||
return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
|
||||
}
|
||||
|
||||
void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask)
|
||||
{
|
||||
p_reg->SHORTS |= short_mask;
|
||||
}
|
||||
|
||||
void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask)
|
||||
{
|
||||
if (~0U == short_mask)
|
||||
{
|
||||
/* Optimized version for "disable all" */
|
||||
p_reg->SHORTS = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
p_reg->SHORTS &= ~short_mask;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg)
|
||||
{
|
||||
return p_reg->SHORTS;
|
||||
}
|
||||
|
||||
void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENSET = int_mask;
|
||||
}
|
||||
|
||||
bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & int_mask);
|
||||
}
|
||||
|
||||
void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = int_mask;
|
||||
}
|
||||
|
||||
uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg)
|
||||
{
|
||||
uint32_t ret = p_reg->ERRORSRC;
|
||||
p_reg->ERRORSRC = ret;
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg)
|
||||
{
|
||||
return (uint_fast8_t)p_reg->MATCH;
|
||||
}
|
||||
|
||||
void nrf_twis_enable(NRF_TWIS_Type * const p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
void nrf_twis_disable(NRF_TWIS_Type * const p_reg)
|
||||
{
|
||||
p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda)
|
||||
{
|
||||
p_reg->PSEL.SCL = scl;
|
||||
p_reg->PSEL.SDA = sda;
|
||||
}
|
||||
|
||||
void nrf_twis_rx_buffer_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t * p_buf,
|
||||
nrf_twis_amount_t length)
|
||||
{
|
||||
p_reg->RXD.PTR = (uint32_t)p_buf;
|
||||
p_reg->RXD.MAXCNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twis_rx_prepare(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t * p_buf,
|
||||
nrf_twis_amount_t length)
|
||||
{
|
||||
nrf_twis_rx_buffer_set(p_reg, p_buf, length);
|
||||
nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARERX);
|
||||
}
|
||||
|
||||
nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg)
|
||||
{
|
||||
return (nrf_twis_amount_t)p_reg->RXD.AMOUNT;
|
||||
}
|
||||
|
||||
void nrf_twis_tx_buffer_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t const * p_buf,
|
||||
nrf_twis_amount_t length)
|
||||
{
|
||||
p_reg->TXD.PTR = (uint32_t)p_buf;
|
||||
p_reg->TXD.MAXCNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_twis_tx_prepare(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t const * p_buf,
|
||||
nrf_twis_amount_t length)
|
||||
{
|
||||
nrf_twis_tx_buffer_set(p_reg, p_buf, length);
|
||||
nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARETX);
|
||||
}
|
||||
|
||||
nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg)
|
||||
{
|
||||
return (nrf_twis_amount_t)p_reg->TXD.AMOUNT;
|
||||
}
|
||||
|
||||
void nrf_twis_address_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint_fast8_t n,
|
||||
nrf_twis_address_t addr)
|
||||
{
|
||||
p_reg->ADDRESS[n] = addr;
|
||||
}
|
||||
|
||||
nrf_twis_address_t nrf_twis_address_get(
|
||||
NRF_TWIS_Type const * const p_reg,
|
||||
uint_fast8_t n)
|
||||
{
|
||||
return (nrf_twis_address_t)p_reg->ADDRESS[n];
|
||||
}
|
||||
void nrf_twis_config_address_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
nrf_twis_config_addr_mask_t addr_mask)
|
||||
{
|
||||
/* This is the only configuration in TWIS - just write it without masking */
|
||||
p_reg->CONFIG = addr_mask;
|
||||
}
|
||||
|
||||
nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * const p_reg)
|
||||
{
|
||||
return (nrf_twis_config_addr_mask_t)(p_reg->CONFIG & TWIS_ADDRESS_ADDRESS_Msk);
|
||||
}
|
||||
|
||||
void nrf_twis_orc_set(
|
||||
NRF_TWIS_Type * const p_reg,
|
||||
uint8_t orc)
|
||||
{
|
||||
p_reg->ORC = orc;
|
||||
}
|
||||
|
||||
uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg)
|
||||
{
|
||||
return (uint8_t)p_reg->ORC;
|
||||
}
|
||||
|
||||
#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* NRF_TWIS_H__ */
|
||||
|
||||
549
lib/sdk/components/drivers_nrf/hal/nrf_uart.h
Normal file
549
lib/sdk/components/drivers_nrf/hal/nrf_uart.h
Normal file
@ -0,0 +1,549 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_UART_H__
|
||||
#define NRF_UART_H__
|
||||
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//Temporary defining legacy UART for instance 1
|
||||
#define NRF_UART1 (NRF_UART_Type *)NRF_UARTE1
|
||||
|
||||
/**
|
||||
* @defgroup nrf_uart_hal UART HAL
|
||||
* @{
|
||||
* @ingroup nrf_uart
|
||||
*
|
||||
* @brief Hardware access layer for accessing the UART peripheral.
|
||||
*/
|
||||
|
||||
#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF
|
||||
|
||||
/**
|
||||
* @enum nrf_uart_task_t
|
||||
* @brief UART tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30 -esym(628,__INTADDR__)*/
|
||||
NRF_UART_TASK_STARTRX = offsetof(NRF_UART_Type, TASKS_STARTRX), /**< Task for starting reception. */
|
||||
NRF_UART_TASK_STOPRX = offsetof(NRF_UART_Type, TASKS_STOPRX), /**< Task for stopping reception. */
|
||||
NRF_UART_TASK_STARTTX = offsetof(NRF_UART_Type, TASKS_STARTTX), /**< Task for starting transmission. */
|
||||
NRF_UART_TASK_STOPTX = offsetof(NRF_UART_Type, TASKS_STOPTX), /**< Task for stopping transmission. */
|
||||
NRF_UART_TASK_SUSPEND = offsetof(NRF_UART_Type, TASKS_SUSPEND), /**< Task for suspending UART. */
|
||||
/*lint -restore*/
|
||||
} nrf_uart_task_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uart_event_t
|
||||
* @brief UART events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_UART_EVENT_CTS = offsetof(NRF_UART_Type, EVENTS_CTS), /**< Event from CTS line activation. */
|
||||
NRF_UART_EVENT_NCTS = offsetof(NRF_UART_Type, EVENTS_NCTS), /**< Event from CTS line deactivation. */
|
||||
NRF_UART_EVENT_RXDRDY = offsetof(NRF_UART_Type, EVENTS_RXDRDY),/**< Event from data ready in RXD. */
|
||||
NRF_UART_EVENT_TXDRDY = offsetof(NRF_UART_Type, EVENTS_TXDRDY),/**< Event from data sent from TXD. */
|
||||
NRF_UART_EVENT_ERROR = offsetof(NRF_UART_Type, EVENTS_ERROR), /**< Event from error detection. */
|
||||
NRF_UART_EVENT_RXTO = offsetof(NRF_UART_Type, EVENTS_RXTO) /**< Event from receiver timeout. */
|
||||
/*lint -restore*/
|
||||
} nrf_uart_event_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uart_int_mask_t
|
||||
* @brief UART interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_UART_INT_MASK_CTS = UART_INTENCLR_CTS_Msk, /**< CTS line activation interrupt. */
|
||||
NRF_UART_INT_MASK_NCTS = UART_INTENCLR_NCTS_Msk, /**< CTS line deactivation interrupt. */
|
||||
NRF_UART_INT_MASK_RXDRDY = UART_INTENCLR_RXDRDY_Msk, /**< Data ready in RXD interrupt. */
|
||||
NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk, /**< Data sent from TXD interrupt. */
|
||||
NRF_UART_INT_MASK_ERROR = UART_INTENCLR_ERROR_Msk, /**< Error detection interrupt. */
|
||||
NRF_UART_INT_MASK_RXTO = UART_INTENCLR_RXTO_Msk /**< Receiver timeout interrupt. */
|
||||
/*lint -restore*/
|
||||
} nrf_uart_int_mask_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uart_baudrate_t
|
||||
* @brief Baudrates supported by UART.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
#ifdef UARTE_PRESENT
|
||||
NRF_UART_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
|
||||
NRF_UART_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
|
||||
NRF_UART_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
|
||||
NRF_UART_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
|
||||
NRF_UART_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
|
||||
NRF_UART_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
|
||||
NRF_UART_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
|
||||
NRF_UART_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
|
||||
NRF_UART_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
|
||||
NRF_UART_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
|
||||
NRF_UART_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
|
||||
NRF_UART_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
|
||||
NRF_UART_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
|
||||
NRF_UART_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
|
||||
NRF_UART_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
|
||||
NRF_UART_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
|
||||
#else
|
||||
NRF_UART_BAUDRATE_1200 = UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
|
||||
NRF_UART_BAUDRATE_2400 = UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
|
||||
NRF_UART_BAUDRATE_4800 = UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
|
||||
NRF_UART_BAUDRATE_9600 = UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
|
||||
NRF_UART_BAUDRATE_14400 = UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
|
||||
NRF_UART_BAUDRATE_19200 = UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
|
||||
NRF_UART_BAUDRATE_28800 = UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
|
||||
NRF_UART_BAUDRATE_38400 = UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
|
||||
NRF_UART_BAUDRATE_57600 = UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
|
||||
NRF_UART_BAUDRATE_76800 = UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
|
||||
NRF_UART_BAUDRATE_115200 = UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
|
||||
NRF_UART_BAUDRATE_230400 = UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
|
||||
NRF_UART_BAUDRATE_250000 = UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
|
||||
NRF_UART_BAUDRATE_460800 = UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
|
||||
NRF_UART_BAUDRATE_921600 = UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
|
||||
NRF_UART_BAUDRATE_1000000 = UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
|
||||
#endif
|
||||
} nrf_uart_baudrate_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uart_error_mask_t
|
||||
* @brief Types of UART error masks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_UART_ERROR_OVERRUN_MASK = UART_ERRORSRC_OVERRUN_Msk, /**< Overrun error. */
|
||||
NRF_UART_ERROR_PARITY_MASK = UART_ERRORSRC_PARITY_Msk, /**< Parity error. */
|
||||
NRF_UART_ERROR_FRAMING_MASK = UART_ERRORSRC_FRAMING_Msk, /**< Framing error. */
|
||||
NRF_UART_ERROR_BREAK_MASK = UART_ERRORSRC_BREAK_Msk, /**< Break error. */
|
||||
} nrf_uart_error_mask_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uart_parity_t
|
||||
* @brief Types of UART parity modes.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_UART_PARITY_EXCLUDED = UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos, /**< Parity excluded. */
|
||||
NRF_UART_PARITY_INCLUDED = UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos, /**< Parity included. */
|
||||
} nrf_uart_parity_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uart_hwfc_t
|
||||
* @brief Types of UART flow control modes.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< HW flow control disabled. */
|
||||
NRF_UART_HWFC_ENABLED = UART_CONFIG_HWFC_Enabled, /**< HW flow control enabled. */
|
||||
} nrf_uart_hwfc_t;
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific UART event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific UART event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to check.
|
||||
*
|
||||
* @retval True if event is set, False otherwise.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific UART event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Desired event.
|
||||
*
|
||||
* @retval Address of specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg,
|
||||
nrf_uart_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling a specific interrupt.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param int_mask Mask of interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specific interrupts.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for getting error source mask. Function is clearing error source flags after reading.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @return Mask with error source flags.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling UART.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling UART.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring TX/RX pins.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param pseltxd TXD pin number.
|
||||
* @param pselrxd RXD pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
|
||||
|
||||
/**
|
||||
* @brief Function for disconnecting TX/RX pins.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting TX pin.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting RX pin.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting RTS pin.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting CTS pin.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for configuring flow control pins.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param pselrts RTS pin number.
|
||||
* @param pselcts CTS pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg,
|
||||
uint32_t pselrts,
|
||||
uint32_t pselcts);
|
||||
|
||||
/**
|
||||
* @brief Function for disconnecting flow control pins.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for reading RX data.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @return Received byte.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting Tx data.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param txd Byte.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd);
|
||||
|
||||
/**
|
||||
* @brief Function for starting an UART task.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param task Task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific task register.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param task Task.
|
||||
*
|
||||
* @return Task address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring UART.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param hwfc Hardware flow control. Enabled if true.
|
||||
* @param parity Parity. Included if true.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg,
|
||||
nrf_uart_parity_t parity,
|
||||
nrf_uart_hwfc_t hwfc);
|
||||
|
||||
/**
|
||||
* @brief Function for setting UART baudrate.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param baudrate Baudrate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate);
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg,
|
||||
nrf_uart_event_t event)
|
||||
{
|
||||
return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENSET = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & int_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg)
|
||||
{
|
||||
uint32_t errsrc_mask = p_reg->ERRORSRC;
|
||||
p_reg->ERRORSRC = errsrc_mask;
|
||||
return errsrc_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd)
|
||||
{
|
||||
#if defined(UART_PSEL_RXD_CONNECT_Pos)
|
||||
p_reg->PSEL.RXD = pselrxd;
|
||||
#else
|
||||
p_reg->PSELRXD = pselrxd;
|
||||
#endif
|
||||
#if defined(UART_PSEL_TXD_CONNECT_Pos)
|
||||
p_reg->PSEL.TXD = pseltxd;
|
||||
#else
|
||||
p_reg->PSELTXD = pseltxd;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg)
|
||||
{
|
||||
nrf_uart_txrx_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg)
|
||||
{
|
||||
#if defined(UART_PSEL_TXD_CONNECT_Pos)
|
||||
return p_reg->PSEL.TXD;
|
||||
#else
|
||||
return p_reg->PSELTXD;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg)
|
||||
{
|
||||
#if defined(UART_PSEL_RXD_CONNECT_Pos)
|
||||
return p_reg->PSEL.RXD;
|
||||
#else
|
||||
return p_reg->PSELRXD;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg)
|
||||
{
|
||||
#if defined(UART_PSEL_RTS_CONNECT_Pos)
|
||||
return p_reg->PSEL.RTS;
|
||||
#else
|
||||
return p_reg->PSELRTS;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg)
|
||||
{
|
||||
#if defined(UART_PSEL_RTS_CONNECT_Pos)
|
||||
return p_reg->PSEL.CTS;
|
||||
#else
|
||||
return p_reg->PSELCTS;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, uint32_t pselrts, uint32_t pselcts)
|
||||
{
|
||||
#if defined(UART_PSEL_RTS_CONNECT_Pos)
|
||||
p_reg->PSEL.RTS = pselrts;
|
||||
#else
|
||||
p_reg->PSELRTS = pselrts;
|
||||
#endif
|
||||
|
||||
#if defined(UART_PSEL_RTS_CONNECT_Pos)
|
||||
p_reg->PSEL.CTS = pselcts;
|
||||
#else
|
||||
p_reg->PSELCTS = pselcts;
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg)
|
||||
{
|
||||
nrf_uart_hwfc_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg)
|
||||
{
|
||||
return p_reg->RXD;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd)
|
||||
{
|
||||
p_reg->TXD = txd;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task)
|
||||
{
|
||||
return (uint32_t)p_reg + (uint32_t)task;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg,
|
||||
nrf_uart_parity_t parity,
|
||||
nrf_uart_hwfc_t hwfc)
|
||||
{
|
||||
p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate)
|
||||
{
|
||||
p_reg->BAUDRATE = baudrate;
|
||||
}
|
||||
#endif //SUPPRESS_INLINE_IMPLEMENTATION
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //NRF_UART_H__
|
||||
609
lib/sdk/components/drivers_nrf/hal/nrf_uarte.h
Normal file
609
lib/sdk/components/drivers_nrf/hal/nrf_uarte.h
Normal file
@ -0,0 +1,609 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_UARTE_H__
|
||||
#define NRF_UARTE_H__
|
||||
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF
|
||||
|
||||
/**
|
||||
* @defgroup nrf_uarte_hal UARTE HAL
|
||||
* @{
|
||||
* @ingroup nrf_uart
|
||||
*
|
||||
* @brief Hardware access layer for accessing the UARTE peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @enum nrf_uarte_task_t
|
||||
* @brief UARTE tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX),///< Start UART receiver.
|
||||
NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
|
||||
NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX),///< Start UART transmitter.
|
||||
NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
|
||||
NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
|
||||
/*lint -restore*/
|
||||
} nrf_uarte_task_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uarte_event_t
|
||||
* @brief UARTE events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
|
||||
NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
|
||||
NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
|
||||
NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
|
||||
NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
|
||||
NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
|
||||
NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED),///< Receiver has started.
|
||||
NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED),///< Transmitter has started.
|
||||
NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped.
|
||||
/*lint -restore*/
|
||||
} nrf_uarte_event_t;
|
||||
|
||||
/**
|
||||
* @brief Types of UARTE shortcuts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk,///< Shortcut between ENDRX event and STARTRX task.
|
||||
NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk, ///< Shortcut between ENDRX event and STOPRX task.
|
||||
} nrf_uarte_short_t;
|
||||
|
||||
|
||||
/**
|
||||
* @enum nrf_uarte_int_mask_t
|
||||
* @brief UARTE interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
|
||||
NRF_UARTE_INT_NCTSRX_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
|
||||
NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
|
||||
NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
|
||||
NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
|
||||
NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
|
||||
NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk,///< Interrupt on RXSTARTED event.
|
||||
NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk,///< Interrupt on TXSTARTED event.
|
||||
NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event.
|
||||
} nrf_uarte_int_mask_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uarte_baudrate_t
|
||||
* @brief Baudrates supported by UARTE.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
|
||||
NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
|
||||
NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
|
||||
NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
|
||||
NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
|
||||
NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
|
||||
NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
|
||||
NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
|
||||
NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
|
||||
NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
|
||||
NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
|
||||
NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
|
||||
NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
|
||||
NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
|
||||
NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
|
||||
NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud.
|
||||
#ifndef UART_PRESENT
|
||||
NRF_UART_BAUDRATE_1200 = NRF_UARTE_BAUDRATE_1200,
|
||||
NRF_UART_BAUDRATE_2400 = NRF_UARTE_BAUDRATE_2400,
|
||||
NRF_UART_BAUDRATE_4800 = NRF_UARTE_BAUDRATE_4800,
|
||||
NRF_UART_BAUDRATE_9600 = NRF_UARTE_BAUDRATE_9600,
|
||||
NRF_UART_BAUDRATE_14400 = NRF_UARTE_BAUDRATE_14400,
|
||||
NRF_UART_BAUDRATE_19200 = NRF_UARTE_BAUDRATE_19200,
|
||||
NRF_UART_BAUDRATE_28800 = NRF_UARTE_BAUDRATE_28800,
|
||||
NRF_UART_BAUDRATE_38400 = NRF_UARTE_BAUDRATE_38400,
|
||||
NRF_UART_BAUDRATE_57600 = NRF_UARTE_BAUDRATE_57600,
|
||||
NRF_UART_BAUDRATE_76800 = NRF_UARTE_BAUDRATE_76800,
|
||||
NRF_UART_BAUDRATE_115200 = NRF_UARTE_BAUDRATE_115200,
|
||||
NRF_UART_BAUDRATE_230400 = NRF_UARTE_BAUDRATE_230400,
|
||||
NRF_UART_BAUDRATE_250000 = NRF_UARTE_BAUDRATE_250000,
|
||||
NRF_UART_BAUDRATE_460800 = NRF_UARTE_BAUDRATE_460800,
|
||||
NRF_UART_BAUDRATE_921600 = NRF_UARTE_BAUDRATE_921600,
|
||||
NRF_UART_BAUDRATE_1000000 = NRF_UARTE_BAUDRATE_1000000,
|
||||
#endif
|
||||
} nrf_uarte_baudrate_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uarte_error_mask_t
|
||||
* @brief Types of UARTE error masks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error.
|
||||
NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error.
|
||||
NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error.
|
||||
NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk, ///< Break error.
|
||||
#ifndef UART_PRESENT
|
||||
NRF_UART_ERROR_OVERRUN_MASK = NRF_UARTE_ERROR_OVERRUN_MASK,
|
||||
NRF_UART_ERROR_PARITY_MASK = NRF_UARTE_ERROR_PARITY_MASK,
|
||||
NRF_UART_ERROR_FRAMING_MASK = NRF_UARTE_ERROR_FRAMING_MASK,
|
||||
NRF_UART_ERROR_BREAK_MASK = NRF_UARTE_ERROR_BREAK_MASK,
|
||||
#endif
|
||||
} nrf_uarte_error_mask_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uarte_parity_t
|
||||
* @brief Types of UARTE parity modes.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
|
||||
NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos, ///< Parity included.
|
||||
#ifndef UART_PRESENT
|
||||
NRF_UART_PARITY_EXCLUDED = NRF_UARTE_PARITY_EXCLUDED,
|
||||
NRF_UART_PARITY_INCLUDED = NRF_UARTE_PARITY_INCLUDED,
|
||||
#endif
|
||||
} nrf_uarte_parity_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_uarte_hwfc_t
|
||||
* @brief Types of UARTE flow control modes.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control disabled.
|
||||
NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control enabled.
|
||||
#ifndef UART_PRESENT
|
||||
NRF_UART_HWFC_DISABLED = NRF_UARTE_HWFC_DISABLED,
|
||||
NRF_UART_HWFC_ENABLED = NRF_UARTE_HWFC_ENABLED,
|
||||
#endif
|
||||
} nrf_uarte_hwfc_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing a specific UARTE event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to clear.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for checking the state of a specific UARTE event.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Event to check.
|
||||
*
|
||||
* @retval True if event is set, False otherwise.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific UARTE event register.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] event Desired event.
|
||||
*
|
||||
* @retval Address of specified event register.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
|
||||
nrf_uarte_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling UARTE shortcuts.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param shorts_mask Shortcuts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling UARTE shortcuts.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param shorts_mask Shortcuts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling UARTE interrupts.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param int_mask Interrupts to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of a given interrupt.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param int_mask Mask of interrupt to check.
|
||||
*
|
||||
* @retval true If the interrupt is enabled.
|
||||
* @retval false If the interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling specific interrupts.
|
||||
*
|
||||
* @param p_reg Instance.
|
||||
* @param int_mask Interrupts to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
|
||||
|
||||
/**
|
||||
* @brief Function for getting error source mask. Function is clearing error source flags after reading.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @return Mask with error source flags.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling UARTE.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling UARTE.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring TX/RX pins.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param pseltxd TXD pin number.
|
||||
* @param pselrxd RXD pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
|
||||
|
||||
/**
|
||||
* @brief Function for disconnecting TX/RX pins.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting TX pin.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting RX pin.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting RTS pin.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for getting CTS pin.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for configuring flow control pins.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param pselrts RTS pin number.
|
||||
* @param pselcts CTS pin number.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
|
||||
uint32_t pselrts,
|
||||
uint32_t pselcts);
|
||||
|
||||
/**
|
||||
* @brief Function for disconnecting flow control pins.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for starting an UARTE task.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param task Task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific task register.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param task Task.
|
||||
*
|
||||
* @return Task address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for configuring UARTE.
|
||||
*
|
||||
* @param p_reg Pointer to the peripheral registers structure.
|
||||
* @param hwfc Hardware flow control. Enabled if true.
|
||||
* @param parity Parity. Included if true.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
|
||||
nrf_uarte_parity_t parity,
|
||||
nrf_uarte_hwfc_t hwfc);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting UARTE baudrate.
|
||||
*
|
||||
* @param p_reg Instance.
|
||||
* @param baudrate Baudrate.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the transmit buffer.
|
||||
*
|
||||
* @param[in] p_reg Instance.
|
||||
* @param[in] p_buffer Pointer to the buffer with data to send.
|
||||
* @param[in] length Maximum number of data bytes to transmit.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
|
||||
uint8_t const * p_buffer,
|
||||
uint8_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for getting number of bytes transmitted in the last transaction.
|
||||
*
|
||||
* @param[in] p_reg Instance.
|
||||
*
|
||||
* @retval Amount of bytes transmitted.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the receive buffer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
* @param[in] p_buffer Pointer to the buffer for received data.
|
||||
* @param[in] length Maximum number of data bytes to receive.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
|
||||
uint8_t * p_buffer,
|
||||
uint8_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for getting number of bytes received in the last transaction.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the peripheral registers structure.
|
||||
*
|
||||
* @retval Amount of bytes received.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg);
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
|
||||
{
|
||||
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
|
||||
nrf_uarte_event_t event)
|
||||
{
|
||||
return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS |= shorts_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
|
||||
{
|
||||
p_reg->SHORTS &= ~(shorts_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENSET = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask)
|
||||
{
|
||||
return (bool)(p_reg->INTENSET & int_mask);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
|
||||
{
|
||||
p_reg->INTENCLR = int_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
uint32_t errsrc_mask = p_reg->ERRORSRC;
|
||||
p_reg->ERRORSRC = errsrc_mask;
|
||||
return errsrc_mask;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd)
|
||||
{
|
||||
p_reg->PSEL.TXD = pseltxd;
|
||||
p_reg->PSEL.RXD = pselrxd;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
return p_reg->PSEL.TXD;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
return p_reg->PSEL.RXD;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
return p_reg->PSEL.RTS;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
return p_reg->PSEL.CTS;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, uint32_t pselrts, uint32_t pselcts)
|
||||
{
|
||||
p_reg->PSEL.RTS = pselrts;
|
||||
p_reg->PSEL.CTS = pselcts;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
|
||||
{
|
||||
return (uint32_t)p_reg + (uint32_t)task;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
|
||||
nrf_uarte_parity_t parity,
|
||||
nrf_uarte_hwfc_t hwfc)
|
||||
{
|
||||
p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
|
||||
{
|
||||
p_reg->BAUDRATE = baudrate;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
|
||||
uint8_t const * p_buffer,
|
||||
uint8_t length)
|
||||
{
|
||||
p_reg->TXD.PTR = (uint32_t)p_buffer;
|
||||
p_reg->TXD.MAXCNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
return p_reg->TXD.AMOUNT;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
|
||||
uint8_t * p_buffer,
|
||||
uint8_t length)
|
||||
{
|
||||
p_reg->RXD.PTR = (uint32_t)p_buffer;
|
||||
p_reg->RXD.MAXCNT = length;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg)
|
||||
{
|
||||
return p_reg->RXD.AMOUNT;
|
||||
}
|
||||
#endif //SUPPRESS_INLINE_IMPLEMENTATION
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //NRF_UARTE_H__
|
||||
|
||||
1435
lib/sdk/components/drivers_nrf/hal/nrf_usbd.h
Normal file
1435
lib/sdk/components/drivers_nrf/hal/nrf_usbd.h
Normal file
File diff suppressed because it is too large
Load Diff
339
lib/sdk/components/drivers_nrf/hal/nrf_wdt.h
Normal file
339
lib/sdk/components/drivers_nrf/hal/nrf_wdt.h
Normal file
@ -0,0 +1,339 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**
|
||||
* @defgroup nrf_wdt_hal WDT HAL
|
||||
* @{
|
||||
* @ingroup nrf_wdt
|
||||
*
|
||||
* @brief Hardware access layer for accessing the watchdog timer (WDT) peripheral.
|
||||
*/
|
||||
|
||||
#ifndef NRF_WDT_H__
|
||||
#define NRF_WDT_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NRF_WDT_CHANNEL_NUMBER 0x8UL
|
||||
#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, shouldn't be modified.*/
|
||||
|
||||
#define NRF_WDT_TASK_SET 1UL
|
||||
#define NRF_WDT_EVENT_CLEAR 0UL
|
||||
|
||||
/**
|
||||
* @enum nrf_wdt_task_t
|
||||
* @brief WDT tasks.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30 -esym(628,__INTADDR__)*/
|
||||
NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */
|
||||
/*lint -restore*/
|
||||
} nrf_wdt_task_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_wdt_event_t
|
||||
* @brief WDT events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*lint -save -e30*/
|
||||
NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */
|
||||
/*lint -restore*/
|
||||
} nrf_wdt_event_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_wdt_behaviour_t
|
||||
* @brief WDT behavior in CPU SLEEP or HALT mode.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_WDT_BEHAVIOUR_RUN_SLEEP = WDT_CONFIG_SLEEP_Msk, /**< WDT will run when CPU is in SLEEP mode. */
|
||||
NRF_WDT_BEHAVIOUR_RUN_HALT = WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in HALT mode. */
|
||||
NRF_WDT_BEHAVIOUR_RUN_SLEEP_HALT = WDT_CONFIG_SLEEP_Msk | WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in SLEEP or HALT mode. */
|
||||
NRF_WDT_BEHAVIOUR_PAUSE_SLEEP_HALT = 0, /**< WDT will be paused when CPU is in SLEEP or HALT mode. */
|
||||
} nrf_wdt_behaviour_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_wdt_rr_register_t
|
||||
* @brief WDT reload request registers.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_WDT_RR0 = 0, /**< Reload request register 0. */
|
||||
NRF_WDT_RR1, /**< Reload request register 1. */
|
||||
NRF_WDT_RR2, /**< Reload request register 2. */
|
||||
NRF_WDT_RR3, /**< Reload request register 3. */
|
||||
NRF_WDT_RR4, /**< Reload request register 4. */
|
||||
NRF_WDT_RR5, /**< Reload request register 5. */
|
||||
NRF_WDT_RR6, /**< Reload request register 6. */
|
||||
NRF_WDT_RR7 /**< Reload request register 7. */
|
||||
} nrf_wdt_rr_register_t;
|
||||
|
||||
/**
|
||||
* @enum nrf_wdt_int_mask_t
|
||||
* @brief WDT interrupts.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */
|
||||
} nrf_wdt_int_mask_t;
|
||||
|
||||
/**
|
||||
* @brief Function for configuring the watchdog behavior when the CPU is sleeping or halted.
|
||||
*
|
||||
* @param behaviour Watchdog behavior when CPU is in SLEEP or HALT mode.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour)
|
||||
{
|
||||
NRF_WDT->CONFIG = behaviour;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for starting the watchdog.
|
||||
*
|
||||
* @param[in] task Task.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_WDT + task)) = NRF_WDT_TASK_SET;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for clearing the WDT event.
|
||||
*
|
||||
* @param[in] event Event.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = NRF_WDT_EVENT_CLEAR;
|
||||
#if __CORTEX_M == 0x04
|
||||
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event));
|
||||
(void)dummy;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of the WDT event.
|
||||
*
|
||||
* @param[in] event Event.
|
||||
*
|
||||
* @retval true If the event is set.
|
||||
* @retval false If the event is not set.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event)
|
||||
{
|
||||
return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + event));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling a specific interrupt.
|
||||
*
|
||||
* @param[in] int_mask Interrupt.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask)
|
||||
{
|
||||
NRF_WDT->INTENSET = int_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the state of given interrupt.
|
||||
*
|
||||
* @param[in] int_mask Interrupt.
|
||||
*
|
||||
* @retval true Interrupt is enabled.
|
||||
* @retval false Interrupt is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask)
|
||||
{
|
||||
return (bool)(NRF_WDT->INTENSET & int_mask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling a specific interrupt.
|
||||
*
|
||||
* @param[in] int_mask Interrupt.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask)
|
||||
{
|
||||
NRF_WDT->INTENCLR = int_mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific WDT task register.
|
||||
*
|
||||
* @param[in] task Task.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task)
|
||||
{
|
||||
return ((uint32_t)NRF_WDT + task);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific WDT event register.
|
||||
*
|
||||
* @param[in] event Event.
|
||||
*
|
||||
* @retval address of requested event register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event)
|
||||
{
|
||||
return ((uint32_t)NRF_WDT + event);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the watchdog status.
|
||||
*
|
||||
* @retval true If the watchdog is started.
|
||||
* @retval false If the watchdog is not started.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_wdt_started(void)
|
||||
{
|
||||
return (bool)(NRF_WDT->RUNSTATUS);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the watchdog reload request status.
|
||||
*
|
||||
* @param[in] rr_register Reload request register to check.
|
||||
*
|
||||
* @retval true If a reload request is running.
|
||||
* @retval false If no reload request is running.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register)
|
||||
{
|
||||
return (bool)(((NRF_WDT->REQSTATUS) >> rr_register) & 0x1UL);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting the watchdog reload value.
|
||||
*
|
||||
* @param[in] reload_value Watchdog counter initial value.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value)
|
||||
{
|
||||
NRF_WDT->CRV = reload_value;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the watchdog reload value.
|
||||
*
|
||||
* @retval Reload value.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void)
|
||||
{
|
||||
return (uint32_t)NRF_WDT->CRV;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for enabling a specific reload request register.
|
||||
*
|
||||
* @param[in] rr_register Reload request register to enable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register)
|
||||
{
|
||||
NRF_WDT->RREN |= 0x1UL << rr_register;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for disabling a specific reload request register.
|
||||
*
|
||||
* @param[in] rr_register Reload request register to disable.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register)
|
||||
{
|
||||
NRF_WDT->RREN &= ~(0x1UL << rr_register);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for retrieving the status of a specific reload request register.
|
||||
*
|
||||
* @param[in] rr_register Reload request register to check.
|
||||
*
|
||||
* @retval true If the reload request register is enabled.
|
||||
* @retval false If the reload request register is not enabled.
|
||||
*/
|
||||
__STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register)
|
||||
{
|
||||
return (bool)(NRF_WDT->RREN & (0x1UL << rr_register));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for setting a specific reload request register.
|
||||
*
|
||||
* @param[in] rr_register Reload request register to set.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register)
|
||||
{
|
||||
NRF_WDT->RR[rr_register] = NRF_WDT_RR_VALUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
339
lib/sdk/components/drivers_nrf/timer/nrf_drv_timer.c
Normal file
339
lib/sdk/components/drivers_nrf/timer/nrf_drv_timer.c
Normal file
@ -0,0 +1,339 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_common.h"
|
||||
#if NRF_MODULE_ENABLED(TIMER)
|
||||
#define ENABLED_TIMER_COUNT (TIMER0_ENABLED+TIMER1_ENABLED+TIMER2_ENABLED+TIMER3_ENABLED+TIMER4_ENABLED)
|
||||
#if ENABLED_TIMER_COUNT
|
||||
#include "nrf_drv_timer.h"
|
||||
#include "nrf_drv_common.h"
|
||||
#include "app_util_platform.h"
|
||||
|
||||
#define NRF_LOG_MODULE_NAME timer
|
||||
|
||||
#if TIMER_CONFIG_LOG_ENABLED
|
||||
#define NRF_LOG_LEVEL TIMER_CONFIG_LOG_LEVEL
|
||||
#define NRF_LOG_INFO_COLOR TIMER_CONFIG_INFO_COLOR
|
||||
#define NRF_LOG_DEBUG_COLOR TIMER_CONFIG_DEBUG_COLOR
|
||||
#else //TIMER_CONFIG_LOG_ENABLED
|
||||
#define NRF_LOG_LEVEL 0
|
||||
#endif //TIMER_CONFIG_LOG_ENABLED
|
||||
#include "nrf_log.h"
|
||||
NRF_LOG_MODULE_REGISTER();
|
||||
|
||||
/**@brief Timer control block. */
|
||||
typedef struct
|
||||
{
|
||||
nrf_timer_event_handler_t handler;
|
||||
void * context;
|
||||
nrf_drv_state_t state;
|
||||
} timer_control_block_t;
|
||||
|
||||
static timer_control_block_t m_cb[ENABLED_TIMER_COUNT];
|
||||
|
||||
ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance,
|
||||
nrf_drv_timer_config_t const * p_config,
|
||||
nrf_timer_event_handler_t timer_event_handler)
|
||||
{
|
||||
timer_control_block_t * p_cb = &m_cb[p_instance->instance_id];
|
||||
ASSERT(((p_instance->p_reg == NRF_TIMER0) && TIMER0_ENABLED) || (p_instance->p_reg != NRF_TIMER0));
|
||||
ASSERT(((p_instance->p_reg == NRF_TIMER1) && TIMER1_ENABLED) || (p_instance->p_reg != NRF_TIMER1));
|
||||
ASSERT(((p_instance->p_reg == NRF_TIMER2) && TIMER2_ENABLED) || (p_instance->p_reg != NRF_TIMER2));
|
||||
#if defined (NRF_TIMER3)
|
||||
ASSERT(((p_instance->p_reg == NRF_TIMER3) && TIMER3_ENABLED) || (p_instance->p_reg != NRF_TIMER3));
|
||||
#endif
|
||||
#if defined (NRF_TIMER4)
|
||||
ASSERT(((p_instance->p_reg == NRF_TIMER4) && TIMER4_ENABLED) || (p_instance->p_reg != NRF_TIMER4));
|
||||
#endif
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
ASSERT(p_instance->p_reg != NRF_TIMER0);
|
||||
#endif
|
||||
ASSERT(p_config);
|
||||
|
||||
ret_code_t err_code;
|
||||
|
||||
if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
|
||||
{
|
||||
err_code = NRF_ERROR_INVALID_STATE;
|
||||
NRF_LOG_WARNING("Function: %s, error code: %s.", (uint32_t)__func__, (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code));
|
||||
return err_code;
|
||||
}
|
||||
|
||||
if (timer_event_handler == NULL)
|
||||
{
|
||||
err_code = NRF_ERROR_INVALID_PARAM;
|
||||
NRF_LOG_WARNING("Function: %s, error code: %s.", (uint32_t)__func__, (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code));
|
||||
return err_code;
|
||||
}
|
||||
|
||||
/* Warning 685: Relational operator '<=' always evaluates to 'true'"
|
||||
* Warning in NRF_TIMER_IS_BIT_WIDTH_VALID macro. Macro validate timers resolution.
|
||||
* Not necessary in nRF52 based systems. Obligatory in nRF51 based systems.
|
||||
*/
|
||||
|
||||
/*lint -save -e685 */
|
||||
|
||||
ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width));
|
||||
|
||||
//lint -restore
|
||||
|
||||
p_cb->handler = timer_event_handler;
|
||||
p_cb->context = p_config->p_context;
|
||||
|
||||
uint8_t i;
|
||||
for (i = 0; i < p_instance->cc_channel_count; ++i)
|
||||
{
|
||||
nrf_timer_event_clear(p_instance->p_reg,
|
||||
nrf_timer_compare_event_get(i));
|
||||
}
|
||||
|
||||
nrf_drv_common_irq_enable(nrf_drv_get_IRQn(p_instance->p_reg),
|
||||
p_config->interrupt_priority);
|
||||
|
||||
nrf_timer_mode_set(p_instance->p_reg, p_config->mode);
|
||||
nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width);
|
||||
nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency);
|
||||
|
||||
p_cb->state = NRF_DRV_STATE_INITIALIZED;
|
||||
|
||||
err_code = NRF_SUCCESS;
|
||||
NRF_LOG_INFO("Function: %s, error code: %s.", (uint32_t)__func__, (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code));
|
||||
return err_code;
|
||||
}
|
||||
|
||||
void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance)
|
||||
{
|
||||
nrf_drv_common_irq_disable(nrf_drv_get_IRQn(p_instance->p_reg));
|
||||
|
||||
#define DISABLE_ALL UINT32_MAX
|
||||
nrf_timer_shorts_disable(p_instance->p_reg, DISABLE_ALL);
|
||||
nrf_timer_int_disable(p_instance->p_reg, DISABLE_ALL);
|
||||
#undef DISABLE_ALL
|
||||
|
||||
if (m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON)
|
||||
{
|
||||
nrf_drv_timer_disable(p_instance);
|
||||
}
|
||||
|
||||
m_cb[p_instance->instance_id].state = NRF_DRV_STATE_UNINITIALIZED;
|
||||
NRF_LOG_INFO("Uninitialized instance: %d.", p_instance->instance_id);
|
||||
}
|
||||
|
||||
void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance)
|
||||
{
|
||||
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_INITIALIZED);
|
||||
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
|
||||
m_cb[p_instance->instance_id].state = NRF_DRV_STATE_POWERED_ON;
|
||||
NRF_LOG_INFO("Enabled instance: %d.", p_instance->instance_id);
|
||||
}
|
||||
|
||||
void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance)
|
||||
{
|
||||
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
|
||||
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_SHUTDOWN);
|
||||
m_cb[p_instance->instance_id].state = NRF_DRV_STATE_INITIALIZED;
|
||||
NRF_LOG_INFO("Disabled instance: %d.", p_instance->instance_id);
|
||||
}
|
||||
|
||||
void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance)
|
||||
{
|
||||
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
|
||||
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
|
||||
NRF_LOG_INFO("Resumed instance: %d.", p_instance->instance_id);
|
||||
}
|
||||
|
||||
void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance)
|
||||
{
|
||||
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
|
||||
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_STOP);
|
||||
NRF_LOG_INFO("Paused instance: %d.", p_instance->instance_id);
|
||||
}
|
||||
|
||||
void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance)
|
||||
{
|
||||
ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
|
||||
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_CLEAR);
|
||||
}
|
||||
|
||||
void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance)
|
||||
{
|
||||
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
|
||||
ASSERT(nrf_timer_mode_get(p_instance->p_reg) != NRF_TIMER_MODE_TIMER);
|
||||
|
||||
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_COUNT);
|
||||
}
|
||||
|
||||
uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_cc_channel_t cc_channel)
|
||||
{
|
||||
ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
|
||||
ASSERT(cc_channel < p_instance->cc_channel_count);
|
||||
|
||||
nrf_timer_task_trigger(p_instance->p_reg,
|
||||
nrf_timer_capture_task_get(cc_channel));
|
||||
return nrf_timer_cc_read(p_instance->p_reg, cc_channel);
|
||||
}
|
||||
|
||||
void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_cc_channel_t cc_channel,
|
||||
uint32_t cc_value,
|
||||
bool enable_int)
|
||||
{
|
||||
nrf_timer_int_mask_t timer_int = nrf_timer_compare_int_get(cc_channel);
|
||||
|
||||
if (enable_int)
|
||||
{
|
||||
nrf_timer_int_enable(p_instance->p_reg, timer_int);
|
||||
}
|
||||
else
|
||||
{
|
||||
nrf_timer_int_disable(p_instance->p_reg, timer_int);
|
||||
}
|
||||
|
||||
nrf_timer_cc_write(p_instance->p_reg, cc_channel, cc_value);
|
||||
NRF_LOG_INFO("Timer id: %d, capture value set: %d, channel: %d.", p_instance->instance_id, cc_value, cc_channel);
|
||||
}
|
||||
|
||||
void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_cc_channel_t cc_channel,
|
||||
uint32_t cc_value,
|
||||
nrf_timer_short_mask_t timer_short_mask,
|
||||
bool enable_int)
|
||||
{
|
||||
nrf_timer_shorts_disable(p_instance->p_reg,
|
||||
(TIMER_SHORTS_COMPARE0_STOP_Msk << cc_channel) |
|
||||
(TIMER_SHORTS_COMPARE0_CLEAR_Msk << cc_channel));
|
||||
|
||||
nrf_timer_shorts_enable(p_instance->p_reg, timer_short_mask);
|
||||
|
||||
(void)nrf_drv_timer_compare(p_instance,
|
||||
cc_channel,
|
||||
cc_value,
|
||||
enable_int);
|
||||
NRF_LOG_INFO("Timer id: %d, capture value set: %d, channel: %d.", p_instance->instance_id, cc_value, cc_channel);
|
||||
}
|
||||
|
||||
void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t channel)
|
||||
{
|
||||
ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
|
||||
ASSERT(channel < p_instance->cc_channel_count);
|
||||
|
||||
nrf_timer_event_clear(p_instance->p_reg,
|
||||
nrf_timer_compare_event_get(channel));
|
||||
nrf_timer_int_enable(p_instance->p_reg,
|
||||
nrf_timer_compare_int_get(channel));
|
||||
}
|
||||
|
||||
void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t channel)
|
||||
{
|
||||
ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
|
||||
ASSERT(channel < p_instance->cc_channel_count);
|
||||
|
||||
nrf_timer_int_disable(p_instance->p_reg,
|
||||
nrf_timer_compare_int_get(channel));
|
||||
}
|
||||
|
||||
static void irq_handler(NRF_TIMER_Type * p_reg,
|
||||
timer_control_block_t * p_cb,
|
||||
uint8_t channel_count)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < channel_count; ++i)
|
||||
{
|
||||
nrf_timer_event_t event = nrf_timer_compare_event_get(i);
|
||||
nrf_timer_int_mask_t int_mask = nrf_timer_compare_int_get(i);
|
||||
|
||||
if (nrf_timer_event_check(p_reg, event) &&
|
||||
nrf_timer_int_enable_check(p_reg, int_mask))
|
||||
{
|
||||
nrf_timer_event_clear(p_reg, event);
|
||||
NRF_LOG_DEBUG("Compare event, channel: %d.", i);
|
||||
p_cb->handler(event, p_cb->context);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if NRF_MODULE_ENABLED(TIMER0)
|
||||
void TIMER0_IRQHandler(void)
|
||||
{
|
||||
irq_handler(NRF_TIMER0, &m_cb[TIMER0_INSTANCE_INDEX],
|
||||
NRF_TIMER_CC_CHANNEL_COUNT(0));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if NRF_MODULE_ENABLED(TIMER1)
|
||||
void TIMER1_IRQHandler(void)
|
||||
{
|
||||
irq_handler(NRF_TIMER1, &m_cb[TIMER1_INSTANCE_INDEX],
|
||||
NRF_TIMER_CC_CHANNEL_COUNT(1));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if NRF_MODULE_ENABLED(TIMER2)
|
||||
void TIMER2_IRQHandler(void)
|
||||
{
|
||||
irq_handler(NRF_TIMER2, &m_cb[TIMER2_INSTANCE_INDEX],
|
||||
NRF_TIMER_CC_CHANNEL_COUNT(2));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (NRF_TIMER3)
|
||||
#if NRF_MODULE_ENABLED(TIMER3)
|
||||
void TIMER3_IRQHandler(void)
|
||||
{
|
||||
irq_handler(NRF_TIMER3, &m_cb[TIMER3_INSTANCE_INDEX],
|
||||
NRF_TIMER_CC_CHANNEL_COUNT(3));
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (NRF_TIMER4)
|
||||
#if NRF_MODULE_ENABLED(TIMER4)
|
||||
void TIMER4_IRQHandler(void)
|
||||
{
|
||||
irq_handler(NRF_TIMER4, &m_cb[TIMER4_INSTANCE_INDEX],
|
||||
NRF_TIMER_CC_CHANNEL_COUNT(4));
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif // ENABLED_TIMER_COUNT
|
||||
#endif // NRF_MODULE_ENABLED(TIMER)
|
||||
410
lib/sdk/components/drivers_nrf/timer/nrf_drv_timer.h
Normal file
410
lib/sdk/components/drivers_nrf/timer/nrf_drv_timer.h
Normal file
@ -0,0 +1,410 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**@file
|
||||
* @addtogroup nrf_timer Timer HAL and driver
|
||||
* @ingroup nrf_drivers
|
||||
* @brief Timer APIs.
|
||||
* @details The timer HAL provides basic APIs for accessing the registers
|
||||
* of the timer. The timer driver provides APIs on a higher level.
|
||||
*
|
||||
* @defgroup nrf_drv_timer Timer driver
|
||||
* @{
|
||||
* @ingroup nrf_timer
|
||||
* @brief Multi-instance timer driver.
|
||||
*/
|
||||
|
||||
#ifndef NRF_DRV_TIMER_H__
|
||||
#define NRF_DRV_TIMER_H__
|
||||
|
||||
#include "nordic_common.h"
|
||||
#include "sdk_config.h"
|
||||
#include "nrf_timer.h"
|
||||
#include "sdk_errors.h"
|
||||
#include "nrf_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Timer driver instance data structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
NRF_TIMER_Type * p_reg; ///< Pointer to the structure with TIMER peripheral instance registers.
|
||||
uint8_t instance_id; ///< Driver instance index.
|
||||
uint8_t cc_channel_count; ///< Number of capture/compare channels.
|
||||
} nrf_drv_timer_t;
|
||||
|
||||
#define ENABLED_TIMER_COUNT (TIMER0_ENABLED+TIMER1_ENABLED+TIMER2_ENABLED+TIMER3_ENABLED+TIMER4_ENABLED)
|
||||
|
||||
#define TIMER0_INSTANCE_INDEX 0
|
||||
#define TIMER1_INSTANCE_INDEX TIMER0_INSTANCE_INDEX+TIMER0_ENABLED
|
||||
#define TIMER2_INSTANCE_INDEX TIMER1_INSTANCE_INDEX+TIMER1_ENABLED
|
||||
#define TIMER3_INSTANCE_INDEX TIMER2_INSTANCE_INDEX+TIMER2_ENABLED
|
||||
#define TIMER4_INSTANCE_INDEX TIMER3_INSTANCE_INDEX+TIMER3_ENABLED
|
||||
|
||||
/**
|
||||
* @brief Macro for creating a timer driver instance.
|
||||
*/
|
||||
#define NRF_DRV_TIMER_INSTANCE(id) \
|
||||
{ \
|
||||
.p_reg = CONCAT_2(NRF_TIMER, id), \
|
||||
.instance_id = CONCAT_3(TIMER, id, _INSTANCE_INDEX), \
|
||||
.cc_channel_count = NRF_TIMER_CC_CHANNEL_COUNT(id), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Timer driver instance configuration structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
nrf_timer_frequency_t frequency; ///< Frequency.
|
||||
nrf_timer_mode_t mode; ///< Mode of operation.
|
||||
nrf_timer_bit_width_t bit_width; ///< Bit width.
|
||||
uint8_t interrupt_priority; ///< Interrupt priority.
|
||||
void * p_context; ///< Context passed to interrupt handler.
|
||||
} nrf_drv_timer_config_t;
|
||||
|
||||
/**
|
||||
* @brief Timer driver instance default configuration.
|
||||
*/
|
||||
#define NRF_DRV_TIMER_DEFAULT_CONFIG \
|
||||
{ \
|
||||
.frequency = (nrf_timer_frequency_t)TIMER_DEFAULT_CONFIG_FREQUENCY,\
|
||||
.mode = (nrf_timer_mode_t)TIMER_DEFAULT_CONFIG_MODE, \
|
||||
.bit_width = (nrf_timer_bit_width_t)TIMER_DEFAULT_CONFIG_BIT_WIDTH,\
|
||||
.interrupt_priority = TIMER_DEFAULT_CONFIG_IRQ_PRIORITY, \
|
||||
.p_context = NULL \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Timer driver event handler type.
|
||||
*
|
||||
* @param[in] event_type Timer event.
|
||||
* @param[in] p_context General purpose parameter set during initialization of
|
||||
* the timer. This parameter can be used to pass
|
||||
* additional information to the handler function, for
|
||||
* example, the timer ID.
|
||||
*/
|
||||
typedef void (* nrf_timer_event_handler_t)(nrf_timer_event_t event_type,
|
||||
void * p_context);
|
||||
|
||||
/**
|
||||
* @brief Function for initializing the timer.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] p_config Initial configuration. Must not be NULL.
|
||||
* @param[in] timer_event_handler Event handler provided by the user.
|
||||
* Must not be NULL.
|
||||
*
|
||||
* @retval NRF_SUCCESS If initialization was successful.
|
||||
* @retval NRF_ERROR_INVALID_STATE If the instance is already initialized.
|
||||
* @retval NRF_ERROR_INVALID_PARAM If no handler was provided.
|
||||
*/
|
||||
ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance,
|
||||
nrf_drv_timer_config_t const * p_config,
|
||||
nrf_timer_event_handler_t timer_event_handler);
|
||||
|
||||
/**
|
||||
* @brief Function for uninitializing the timer.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for turning on the timer.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for turning off the timer.
|
||||
*
|
||||
* Note that the timer will allow to enter the lowest possible SYSTEM_ON state
|
||||
* only after this function is called.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for pausing the timer.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for resuming the timer.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for clearing the timer.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for incrementing the timer.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific timer task.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] timer_task Timer task.
|
||||
*
|
||||
* @return Task address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_task_t timer_task);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific timer capture task.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] channel Capture channel number.
|
||||
*
|
||||
* @return Task address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t channel);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific timer event.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] timer_event Timer event.
|
||||
*
|
||||
* @return Event address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_event_t timer_event);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the address of a specific timer compare event.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] channel Compare channel number.
|
||||
*
|
||||
* @return Event address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t channel);
|
||||
|
||||
/**
|
||||
* @brief Function for capturing the timer value.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] cc_channel Capture channel number.
|
||||
*
|
||||
* @return Captured value.
|
||||
*/
|
||||
uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_cc_channel_t cc_channel);
|
||||
|
||||
/**
|
||||
* @brief Function for returning the capture value from a specific channel.
|
||||
*
|
||||
* Use this function to read channel values when PPI is used for capturing.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] cc_channel Capture channel number.
|
||||
*
|
||||
* @return Captured value.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_capture_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_cc_channel_t cc_channel);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the timer channel in compare mode.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] cc_channel Compare channel number.
|
||||
* @param[in] cc_value Compare value.
|
||||
* @param[in] enable_int Enable or disable the interrupt for the compare channel.
|
||||
*/
|
||||
void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_cc_channel_t cc_channel,
|
||||
uint32_t cc_value,
|
||||
bool enable_int);
|
||||
|
||||
/**
|
||||
* @brief Function for setting the timer channel in extended compare mode.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] cc_channel Compare channel number.
|
||||
* @param[in] cc_value Compare value.
|
||||
* @param[in] timer_short_mask Shortcut between the compare event on the channel
|
||||
* and the timer task (STOP or CLEAR).
|
||||
* @param[in] enable_int Enable or disable the interrupt for the compare
|
||||
* channel.
|
||||
*/
|
||||
void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_cc_channel_t cc_channel,
|
||||
uint32_t cc_value,
|
||||
nrf_timer_short_mask_t timer_short_mask,
|
||||
bool enable_int);
|
||||
|
||||
/**
|
||||
* @brief Function for converting time in microseconds to timer ticks.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] time_us Time in microseconds.
|
||||
*
|
||||
* @return Number of ticks.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t time_us);
|
||||
|
||||
/**
|
||||
* @brief Function for converting time in milliseconds to timer ticks.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] time_ms Time in milliseconds.
|
||||
*
|
||||
* @return Number of ticks.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t time_ms);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling timer compare interrupt.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] channel Compare channel.
|
||||
*/
|
||||
void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t channel);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling timer compare interrupt.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] channel Compare channel.
|
||||
*/
|
||||
void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t channel);
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_task_t timer_task)
|
||||
{
|
||||
return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, timer_task);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t channel)
|
||||
{
|
||||
ASSERT(channel < p_instance->cc_channel_count);
|
||||
return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg,
|
||||
nrf_timer_capture_task_get(channel));
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_event_t timer_event)
|
||||
{
|
||||
return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, timer_event);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t channel)
|
||||
{
|
||||
ASSERT(channel < p_instance->cc_channel_count);
|
||||
return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg,
|
||||
nrf_timer_compare_event_get(channel));
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_capture_get(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
nrf_timer_cc_channel_t cc_channel)
|
||||
{
|
||||
return nrf_timer_cc_read(p_instance->p_reg, cc_channel);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t timer_us)
|
||||
{
|
||||
return nrf_timer_us_to_ticks(timer_us,
|
||||
nrf_timer_frequency_get(p_instance->p_reg));
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks(
|
||||
nrf_drv_timer_t const * const p_instance,
|
||||
uint32_t timer_ms)
|
||||
{
|
||||
return nrf_timer_ms_to_ticks(timer_ms,
|
||||
nrf_timer_frequency_get(p_instance->p_reg));
|
||||
}
|
||||
|
||||
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRF_DRV_TIMER_H__
|
||||
|
||||
/** @} */
|
||||
990
lib/sdk/components/drivers_nrf/uart/nrf_drv_uart.c
Normal file
990
lib/sdk/components/drivers_nrf/uart/nrf_drv_uart.c
Normal file
@ -0,0 +1,990 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_common.h"
|
||||
#if NRF_MODULE_ENABLED(UART)
|
||||
#include "nrf_drv_uart.h"
|
||||
#include "nrf_assert.h"
|
||||
#include "nrf_drv_common.h"
|
||||
#include "nrf_gpio.h"
|
||||
#include "app_util_platform.h"
|
||||
|
||||
#define NRF_LOG_MODULE_NAME uart
|
||||
|
||||
#if UART_CONFIG_LOG_ENABLED
|
||||
#define NRF_LOG_LEVEL UART_CONFIG_LOG_LEVEL
|
||||
#define NRF_LOG_INFO_COLOR UART_CONFIG_INFO_COLOR
|
||||
#define NRF_LOG_DEBUG_COLOR UART_CONFIG_DEBUG_COLOR
|
||||
#define EVT_TO_STR(event) (event == NRF_UART_EVENT_ERROR ? "NRF_UART_EVENT_ERROR" : "UNKNOWN EVENT")
|
||||
#else //UART_CONFIG_LOG_ENABLED
|
||||
#define EVT_TO_STR(event) ""
|
||||
#define NRF_LOG_LEVEL 0
|
||||
#endif //UART_CONFIG_LOG_ENABLED
|
||||
#include "nrf_log.h"
|
||||
NRF_LOG_MODULE_REGISTER();
|
||||
|
||||
#if (defined(UARTE_IN_USE) && defined(UART_IN_USE))
|
||||
// UARTE and UART combined
|
||||
#define CODE_FOR_UARTE(code) if (m_cb[p_instance->drv_inst_idx].use_easy_dma) { code }
|
||||
#define CODE_FOR_UARTE_INT(idx, code) if (m_cb[idx].use_easy_dma) { code }
|
||||
#define CODE_FOR_UART(code) else { code }
|
||||
#elif (defined(UARTE_IN_USE) && !defined(UART_IN_USE))
|
||||
// UARTE only
|
||||
#define CODE_FOR_UARTE(code) { code }
|
||||
#define CODE_FOR_UARTE_INT(idx, code) { code }
|
||||
#define CODE_FOR_UART(code)
|
||||
#elif (!defined(UARTE_IN_USE) && defined(UART_IN_USE))
|
||||
// UART only
|
||||
#define CODE_FOR_UARTE(code)
|
||||
#define CODE_FOR_UARTE_INT(idx, code)
|
||||
#define CODE_FOR_UART(code) { code }
|
||||
#else
|
||||
#error "Wrong configuration."
|
||||
#endif
|
||||
|
||||
#define TX_COUNTER_ABORT_REQ_VALUE 256
|
||||
|
||||
typedef struct
|
||||
{
|
||||
void * p_context;
|
||||
nrf_uart_event_handler_t handler;
|
||||
uint8_t const * p_tx_buffer;
|
||||
uint8_t * p_rx_buffer;
|
||||
uint8_t * p_rx_secondary_buffer;
|
||||
volatile uint16_t tx_counter;
|
||||
uint8_t tx_buffer_length;
|
||||
uint8_t rx_buffer_length;
|
||||
uint8_t rx_secondary_buffer_length;
|
||||
volatile uint8_t rx_counter;
|
||||
bool rx_enabled;
|
||||
nrf_drv_state_t state;
|
||||
#if (defined(UARTE_IN_USE) && defined(UART_IN_USE))
|
||||
bool use_easy_dma;
|
||||
#endif
|
||||
} uart_control_block_t;
|
||||
|
||||
static uart_control_block_t m_cb[UART_ENABLED_COUNT];
|
||||
|
||||
#ifdef NRF52810_XXAA
|
||||
#define IRQ_HANDLER(n) void UARTE##n##_IRQHandler(void)
|
||||
#else
|
||||
#define IRQ_HANDLER(n) void UART##n##_IRQHandler(void)
|
||||
#endif
|
||||
|
||||
__STATIC_INLINE void apply_config(nrf_drv_uart_t const * p_instance, nrf_drv_uart_config_t const * p_config)
|
||||
{
|
||||
if (p_config->pseltxd != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_pin_set(p_config->pseltxd);
|
||||
nrf_gpio_cfg_output(p_config->pseltxd);
|
||||
}
|
||||
if (p_config->pselrxd != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL);
|
||||
}
|
||||
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
nrf_uarte_baudrate_set(p_instance->reg.p_uarte, (nrf_uarte_baudrate_t)p_config->baudrate);
|
||||
nrf_uarte_configure(p_instance->reg.p_uarte, (nrf_uarte_parity_t)p_config->parity,
|
||||
(nrf_uarte_hwfc_t)p_config->hwfc);
|
||||
nrf_uarte_txrx_pins_set(p_instance->reg.p_uarte, p_config->pseltxd, p_config->pselrxd);
|
||||
if (p_config->hwfc == NRF_UART_HWFC_ENABLED)
|
||||
{
|
||||
if (p_config->pselcts != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL);
|
||||
}
|
||||
if (p_config->pselrts != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_pin_set(p_config->pselrts);
|
||||
nrf_gpio_cfg_output(p_config->pselrts);
|
||||
}
|
||||
nrf_uarte_hwfc_pins_set(p_instance->reg.p_uarte, p_config->pselrts, p_config->pselcts);
|
||||
}
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
nrf_uart_baudrate_set(p_instance->reg.p_uart, p_config->baudrate);
|
||||
nrf_uart_configure(p_instance->reg.p_uart, p_config->parity, p_config->hwfc);
|
||||
nrf_uart_txrx_pins_set(p_instance->reg.p_uart, p_config->pseltxd, p_config->pselrxd);
|
||||
if (p_config->hwfc == NRF_UART_HWFC_ENABLED)
|
||||
{
|
||||
if (p_config->pselcts != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL);
|
||||
}
|
||||
if (p_config->pselrts != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_pin_set(p_config->pselrts);
|
||||
nrf_gpio_cfg_output(p_config->pselrts);
|
||||
}
|
||||
nrf_uart_hwfc_pins_set(p_instance->reg.p_uart, p_config->pselrts, p_config->pselcts);
|
||||
}
|
||||
)
|
||||
}
|
||||
|
||||
__STATIC_INLINE void interrupts_enable(const nrf_drv_uart_t * p_instance, uint8_t interrupt_priority)
|
||||
{
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ENDRX);
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ENDTX);
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ERROR);
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_RXTO);
|
||||
nrf_uarte_int_enable(p_instance->reg.p_uarte, NRF_UARTE_INT_ENDRX_MASK |
|
||||
NRF_UARTE_INT_ENDTX_MASK |
|
||||
NRF_UARTE_INT_ERROR_MASK |
|
||||
NRF_UARTE_INT_RXTO_MASK);
|
||||
nrf_drv_common_irq_enable(nrf_drv_get_IRQn((void *)p_instance->reg.p_uarte), interrupt_priority);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
nrf_uart_event_clear(p_instance->reg.p_uart, NRF_UART_EVENT_TXDRDY);
|
||||
nrf_uart_event_clear(p_instance->reg.p_uart, NRF_UART_EVENT_RXTO);
|
||||
nrf_uart_int_enable(p_instance->reg.p_uart, NRF_UART_INT_MASK_TXDRDY |
|
||||
NRF_UART_INT_MASK_RXTO);
|
||||
nrf_drv_common_irq_enable(nrf_drv_get_IRQn((void *)p_instance->reg.p_uart), interrupt_priority);
|
||||
)
|
||||
}
|
||||
|
||||
__STATIC_INLINE void interrupts_disable(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
nrf_uarte_int_disable(p_instance->reg.p_uarte, NRF_UARTE_INT_ENDRX_MASK |
|
||||
NRF_UARTE_INT_ENDTX_MASK |
|
||||
NRF_UARTE_INT_ERROR_MASK |
|
||||
NRF_UARTE_INT_RXTO_MASK);
|
||||
nrf_drv_common_irq_disable(nrf_drv_get_IRQn((void *)p_instance->reg.p_uarte));
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
nrf_uart_int_disable(p_instance->reg.p_uart, NRF_UART_INT_MASK_RXDRDY |
|
||||
NRF_UART_INT_MASK_TXDRDY |
|
||||
NRF_UART_INT_MASK_ERROR |
|
||||
NRF_UART_INT_MASK_RXTO);
|
||||
nrf_drv_common_irq_disable(nrf_drv_get_IRQn((void *)p_instance->reg.p_uart));
|
||||
)
|
||||
|
||||
}
|
||||
|
||||
__STATIC_INLINE void pins_to_default(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
/* Reset pins to default states */
|
||||
uint32_t txd;
|
||||
uint32_t rxd;
|
||||
uint32_t rts;
|
||||
uint32_t cts;
|
||||
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
txd = nrf_uarte_tx_pin_get(p_instance->reg.p_uarte);
|
||||
rxd = nrf_uarte_rx_pin_get(p_instance->reg.p_uarte);
|
||||
rts = nrf_uarte_rts_pin_get(p_instance->reg.p_uarte);
|
||||
cts = nrf_uarte_cts_pin_get(p_instance->reg.p_uarte);
|
||||
nrf_uarte_txrx_pins_disconnect(p_instance->reg.p_uarte);
|
||||
nrf_uarte_hwfc_pins_disconnect(p_instance->reg.p_uarte);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
txd = nrf_uart_tx_pin_get(p_instance->reg.p_uart);
|
||||
rxd = nrf_uart_rx_pin_get(p_instance->reg.p_uart);
|
||||
rts = nrf_uart_rts_pin_get(p_instance->reg.p_uart);
|
||||
cts = nrf_uart_cts_pin_get(p_instance->reg.p_uart);
|
||||
nrf_uart_txrx_pins_disconnect(p_instance->reg.p_uart);
|
||||
nrf_uart_hwfc_pins_disconnect(p_instance->reg.p_uart);
|
||||
)
|
||||
|
||||
if (txd != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_cfg_default(txd);
|
||||
}
|
||||
|
||||
if (rxd != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_cfg_default(rxd);
|
||||
}
|
||||
|
||||
if (cts != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_cfg_default(cts);
|
||||
}
|
||||
|
||||
if (rts != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_cfg_default(rts);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
__STATIC_INLINE void uart_enable(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
CODE_FOR_UARTE(nrf_uarte_enable(p_instance->reg.p_uarte);)
|
||||
CODE_FOR_UART(nrf_uart_enable(p_instance->reg.p_uart););
|
||||
}
|
||||
|
||||
__STATIC_INLINE void uart_disable(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
CODE_FOR_UARTE(nrf_uarte_disable(p_instance->reg.p_uarte);)
|
||||
CODE_FOR_UART(nrf_uart_disable(p_instance->reg.p_uart););
|
||||
}
|
||||
|
||||
ret_code_t nrf_drv_uart_init(const nrf_drv_uart_t * p_instance, nrf_drv_uart_config_t const * p_config,
|
||||
nrf_uart_event_handler_t event_handler)
|
||||
{
|
||||
ASSERT(p_config);
|
||||
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
|
||||
ret_code_t err_code = NRF_SUCCESS;
|
||||
|
||||
if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
|
||||
{
|
||||
err_code = NRF_ERROR_INVALID_STATE;
|
||||
NRF_LOG_ERROR("Init failed. id:%d in wrong state", nrf_drv_get_IRQn((void *)p_instance->reg.p_reg));
|
||||
return err_code;
|
||||
}
|
||||
|
||||
#if (defined(UARTE_IN_USE) && defined(UART_IN_USE))
|
||||
p_cb->use_easy_dma = p_config->use_easy_dma;
|
||||
#endif
|
||||
apply_config(p_instance, p_config);
|
||||
|
||||
p_cb->handler = event_handler;
|
||||
p_cb->p_context = p_config->p_context;
|
||||
|
||||
if (p_cb->handler)
|
||||
{
|
||||
interrupts_enable(p_instance, p_config->interrupt_priority);
|
||||
}
|
||||
|
||||
uart_enable(p_instance);
|
||||
p_cb->rx_buffer_length = 0;
|
||||
p_cb->rx_secondary_buffer_length = 0;
|
||||
p_cb->tx_buffer_length = 0;
|
||||
p_cb->state = NRF_DRV_STATE_INITIALIZED;
|
||||
p_cb->rx_enabled = false;
|
||||
return err_code;
|
||||
}
|
||||
|
||||
void nrf_drv_uart_uninit(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
|
||||
|
||||
uart_disable(p_instance);
|
||||
|
||||
if (p_cb->handler)
|
||||
{
|
||||
interrupts_disable(p_instance);
|
||||
}
|
||||
|
||||
pins_to_default(p_instance);
|
||||
|
||||
p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
|
||||
p_cb->handler = NULL;
|
||||
NRF_LOG_INFO("Uninit id: %d.", nrf_drv_get_IRQn((void *)p_instance->reg.p_reg));
|
||||
}
|
||||
|
||||
#if defined(UART_IN_USE)
|
||||
__STATIC_INLINE void tx_byte(NRF_UART_Type * p_uart, uart_control_block_t * p_cb)
|
||||
{
|
||||
nrf_uart_event_clear(p_uart, NRF_UART_EVENT_TXDRDY);
|
||||
uint8_t txd = p_cb->p_tx_buffer[p_cb->tx_counter];
|
||||
p_cb->tx_counter++;
|
||||
nrf_uart_txd_set(p_uart, txd);
|
||||
}
|
||||
|
||||
__STATIC_INLINE ret_code_t nrf_drv_uart_tx_for_uart(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
|
||||
ret_code_t err_code = NRF_SUCCESS;
|
||||
|
||||
nrf_uart_event_clear(p_instance->reg.p_uart, NRF_UART_EVENT_TXDRDY);
|
||||
nrf_uart_task_trigger(p_instance->reg.p_uart, NRF_UART_TASK_STARTTX);
|
||||
|
||||
tx_byte(p_instance->reg.p_uart, p_cb);
|
||||
|
||||
if (p_cb->handler == NULL)
|
||||
{
|
||||
while (p_cb->tx_counter < (uint16_t) p_cb->tx_buffer_length)
|
||||
{
|
||||
while (!nrf_uart_event_check(p_instance->reg.p_uart, NRF_UART_EVENT_TXDRDY) &&
|
||||
p_cb->tx_counter != TX_COUNTER_ABORT_REQ_VALUE)
|
||||
{
|
||||
}
|
||||
if (p_cb->tx_counter != TX_COUNTER_ABORT_REQ_VALUE)
|
||||
{
|
||||
tx_byte(p_instance->reg.p_uart, p_cb);
|
||||
}
|
||||
}
|
||||
|
||||
if (p_cb->tx_counter == TX_COUNTER_ABORT_REQ_VALUE)
|
||||
{
|
||||
err_code = NRF_ERROR_FORBIDDEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
while (!nrf_uart_event_check(p_instance->reg.p_uart, NRF_UART_EVENT_TXDRDY))
|
||||
{
|
||||
}
|
||||
nrf_uart_task_trigger(p_instance->reg.p_uart, NRF_UART_TASK_STOPTX);
|
||||
}
|
||||
p_cb->tx_buffer_length = 0;
|
||||
}
|
||||
return err_code;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(UARTE_IN_USE)
|
||||
__STATIC_INLINE ret_code_t nrf_drv_uart_tx_for_uarte(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
|
||||
ret_code_t err_code = NRF_SUCCESS;
|
||||
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ENDTX);
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_TXSTOPPED);
|
||||
nrf_uarte_tx_buffer_set(p_instance->reg.p_uarte, p_cb->p_tx_buffer, p_cb->tx_buffer_length);
|
||||
nrf_uarte_task_trigger(p_instance->reg.p_uarte, NRF_UARTE_TASK_STARTTX);
|
||||
|
||||
if (p_cb->handler == NULL)
|
||||
{
|
||||
bool endtx;
|
||||
bool txstopped;
|
||||
do
|
||||
{
|
||||
endtx = nrf_uarte_event_check(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ENDTX);
|
||||
txstopped = nrf_uarte_event_check(p_instance->reg.p_uarte, NRF_UARTE_EVENT_TXSTOPPED);
|
||||
}
|
||||
while ((!endtx) && (!txstopped));
|
||||
|
||||
if (txstopped)
|
||||
{
|
||||
err_code = NRF_ERROR_FORBIDDEN;
|
||||
}
|
||||
p_cb->tx_buffer_length = 0;
|
||||
}
|
||||
return err_code;
|
||||
}
|
||||
#endif
|
||||
|
||||
ret_code_t nrf_drv_uart_tx(const nrf_drv_uart_t * p_instance, uint8_t const * const p_data, uint8_t length)
|
||||
{
|
||||
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
|
||||
ASSERT(p_cb->state == NRF_DRV_STATE_INITIALIZED);
|
||||
ASSERT(length>0);
|
||||
ASSERT(p_data);
|
||||
|
||||
ret_code_t err_code;
|
||||
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
// EasyDMA requires that transfer buffers are placed in DataRAM,
|
||||
// signal error if the are not.
|
||||
if (!nrf_drv_is_in_RAM(p_data))
|
||||
{
|
||||
err_code = NRF_ERROR_INVALID_ADDR;
|
||||
NRF_LOG_ERROR("Id:%d, Easy-DMA buffer not in RAM: %08x",
|
||||
nrf_drv_get_IRQn((void *)p_instance->reg.p_reg), p_data);
|
||||
return err_code;
|
||||
}
|
||||
)
|
||||
|
||||
if (nrf_drv_uart_tx_in_progress(p_instance))
|
||||
{
|
||||
err_code = NRF_ERROR_BUSY;
|
||||
NRF_LOG_WARNING("Id:%d busy",nrf_drv_get_IRQn((void *)p_instance->reg.p_reg));
|
||||
return err_code;
|
||||
}
|
||||
p_cb->tx_buffer_length = length;
|
||||
p_cb->p_tx_buffer = p_data;
|
||||
p_cb->tx_counter = 0;
|
||||
|
||||
NRF_LOG_INFO("TX req id:%d length: %d.",
|
||||
nrf_drv_get_IRQn((void *)p_instance->reg.p_reg),
|
||||
p_cb->tx_buffer_length);
|
||||
NRF_LOG_DEBUG("Tx data:");
|
||||
NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_cb->p_tx_buffer,
|
||||
p_cb->tx_buffer_length * sizeof(p_cb->p_tx_buffer[0]));
|
||||
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
return nrf_drv_uart_tx_for_uarte(p_instance);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
return nrf_drv_uart_tx_for_uart(p_instance);
|
||||
)
|
||||
}
|
||||
|
||||
bool nrf_drv_uart_tx_in_progress(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
return (m_cb[p_instance->drv_inst_idx].tx_buffer_length != 0);
|
||||
}
|
||||
|
||||
#if defined(UART_IN_USE)
|
||||
__STATIC_INLINE void rx_enable(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
nrf_uart_event_clear(p_instance->reg.p_uart, NRF_UART_EVENT_ERROR);
|
||||
nrf_uart_event_clear(p_instance->reg.p_uart, NRF_UART_EVENT_RXDRDY);
|
||||
nrf_uart_task_trigger(p_instance->reg.p_uart, NRF_UART_TASK_STARTRX);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void rx_byte(NRF_UART_Type * p_uart, uart_control_block_t * p_cb)
|
||||
{
|
||||
if (!p_cb->rx_buffer_length)
|
||||
{
|
||||
nrf_uart_event_clear(p_uart, NRF_UART_EVENT_RXDRDY);
|
||||
// Byte received when buffer is not set - data lost.
|
||||
(void) nrf_uart_rxd_get(p_uart);
|
||||
return;
|
||||
}
|
||||
nrf_uart_event_clear(p_uart, NRF_UART_EVENT_RXDRDY);
|
||||
p_cb->p_rx_buffer[p_cb->rx_counter] = nrf_uart_rxd_get(p_uart);
|
||||
p_cb->rx_counter++;
|
||||
}
|
||||
|
||||
__STATIC_INLINE ret_code_t nrf_drv_uart_rx_for_uart(const nrf_drv_uart_t * p_instance, uint8_t * p_data, uint8_t length, bool second_buffer)
|
||||
{
|
||||
ret_code_t err_code;
|
||||
|
||||
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
|
||||
|
||||
if ((!p_cb->rx_enabled) && (!second_buffer))
|
||||
{
|
||||
rx_enable(p_instance);
|
||||
}
|
||||
|
||||
if (p_cb->handler == NULL)
|
||||
{
|
||||
nrf_uart_event_clear(p_instance->reg.p_uart, NRF_UART_EVENT_RXTO);
|
||||
|
||||
bool rxrdy;
|
||||
bool rxto;
|
||||
bool error;
|
||||
do
|
||||
{
|
||||
do
|
||||
{
|
||||
error = nrf_uart_event_check(p_instance->reg.p_uart, NRF_UART_EVENT_ERROR);
|
||||
rxrdy = nrf_uart_event_check(p_instance->reg.p_uart, NRF_UART_EVENT_RXDRDY);
|
||||
rxto = nrf_uart_event_check(p_instance->reg.p_uart, NRF_UART_EVENT_RXTO);
|
||||
} while ((!rxrdy) && (!rxto) && (!error));
|
||||
|
||||
if (error || rxto)
|
||||
{
|
||||
break;
|
||||
}
|
||||
rx_byte(p_instance->reg.p_uart, p_cb);
|
||||
} while (p_cb->rx_buffer_length > p_cb->rx_counter);
|
||||
|
||||
p_cb->rx_buffer_length = 0;
|
||||
if (error)
|
||||
{
|
||||
err_code = NRF_ERROR_INTERNAL;
|
||||
NRF_LOG_WARNING("RX Id: %d, transfer error.", nrf_drv_get_IRQn((void *)p_instance->reg.p_reg));
|
||||
return err_code;
|
||||
}
|
||||
|
||||
if (rxto)
|
||||
{
|
||||
NRF_LOG_WARNING("RX Id: %d, aborted.", nrf_drv_get_IRQn((void *)p_instance->reg.p_reg));
|
||||
err_code = NRF_ERROR_FORBIDDEN;
|
||||
return err_code;
|
||||
}
|
||||
|
||||
if (p_cb->rx_enabled)
|
||||
{
|
||||
nrf_uart_task_trigger(p_instance->reg.p_uart, NRF_UART_TASK_STARTRX);
|
||||
}
|
||||
else
|
||||
{
|
||||
// Skip stopping RX if driver is forced to be enabled.
|
||||
nrf_uart_task_trigger(p_instance->reg.p_uart, NRF_UART_TASK_STOPRX);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
nrf_uart_int_enable(p_instance->reg.p_uart, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
|
||||
}
|
||||
err_code = NRF_SUCCESS;
|
||||
return err_code;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(UARTE_IN_USE)
|
||||
__STATIC_INLINE ret_code_t nrf_drv_uart_rx_for_uarte(const nrf_drv_uart_t * p_instance, uint8_t * p_data, uint8_t length, bool second_buffer)
|
||||
{
|
||||
ret_code_t err_code = NRF_SUCCESS;
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ENDRX);
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_RXTO);
|
||||
nrf_uarte_rx_buffer_set(p_instance->reg.p_uarte, p_data, length);
|
||||
if (!second_buffer)
|
||||
{
|
||||
nrf_uarte_task_trigger(p_instance->reg.p_uarte, NRF_UARTE_TASK_STARTRX);
|
||||
}
|
||||
else
|
||||
{
|
||||
nrf_uarte_shorts_enable(p_instance->reg.p_uarte, NRF_UARTE_SHORT_ENDRX_STARTRX);
|
||||
}
|
||||
|
||||
if (m_cb[p_instance->drv_inst_idx].handler == NULL)
|
||||
{
|
||||
bool endrx;
|
||||
bool rxto;
|
||||
bool error;
|
||||
do {
|
||||
endrx = nrf_uarte_event_check(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ENDRX);
|
||||
rxto = nrf_uarte_event_check(p_instance->reg.p_uarte, NRF_UARTE_EVENT_RXTO);
|
||||
error = nrf_uarte_event_check(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ERROR);
|
||||
}while ((!endrx) && (!rxto) && (!error));
|
||||
|
||||
m_cb[p_instance->drv_inst_idx].rx_buffer_length = 0;
|
||||
|
||||
if (error)
|
||||
{
|
||||
err_code = NRF_ERROR_INTERNAL;
|
||||
}
|
||||
|
||||
if (rxto)
|
||||
{
|
||||
err_code = NRF_ERROR_FORBIDDEN;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
nrf_uarte_int_enable(p_instance->reg.p_uarte, NRF_UARTE_INT_ERROR_MASK | NRF_UARTE_INT_ENDRX_MASK);
|
||||
}
|
||||
return err_code;
|
||||
}
|
||||
#endif
|
||||
|
||||
ret_code_t nrf_drv_uart_rx(const nrf_drv_uart_t * p_instance, uint8_t * p_data, uint8_t length)
|
||||
{
|
||||
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
|
||||
|
||||
ASSERT(m_cb[p_instance->drv_inst_idx].state == NRF_DRV_STATE_INITIALIZED);
|
||||
ASSERT(length>0);
|
||||
|
||||
ret_code_t err_code;
|
||||
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
// EasyDMA requires that transfer buffers are placed in DataRAM,
|
||||
// signal error if the are not.
|
||||
if (!nrf_drv_is_in_RAM(p_data))
|
||||
{
|
||||
err_code = NRF_ERROR_INVALID_ADDR;
|
||||
NRF_LOG_ERROR("Id:%d, Easy-DMA buffer not in RAM: %08x",
|
||||
nrf_drv_get_IRQn((void *)p_instance->reg.p_reg), p_data);
|
||||
return err_code;
|
||||
}
|
||||
)
|
||||
|
||||
bool second_buffer = false;
|
||||
|
||||
if (p_cb->handler)
|
||||
{
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
nrf_uarte_int_disable(p_instance->reg.p_uarte, NRF_UARTE_INT_ERROR_MASK | NRF_UARTE_INT_ENDRX_MASK);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
nrf_uart_int_disable(p_instance->reg.p_uart, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
|
||||
)
|
||||
}
|
||||
if (p_cb->rx_buffer_length != 0)
|
||||
{
|
||||
if (p_cb->rx_secondary_buffer_length != 0)
|
||||
{
|
||||
if (p_cb->handler)
|
||||
{
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
nrf_uarte_int_enable(p_instance->reg.p_uarte, NRF_UARTE_INT_ERROR_MASK | NRF_UARTE_INT_ENDRX_MASK);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
nrf_uart_int_enable(p_instance->reg.p_uart, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
|
||||
)
|
||||
}
|
||||
err_code = NRF_ERROR_BUSY;
|
||||
NRF_LOG_WARNING("RX Id:%d, busy", nrf_drv_get_IRQn((void *)p_instance->reg.p_reg));
|
||||
return err_code;
|
||||
}
|
||||
second_buffer = true;
|
||||
}
|
||||
|
||||
if (!second_buffer)
|
||||
{
|
||||
p_cb->rx_buffer_length = length;
|
||||
p_cb->p_rx_buffer = p_data;
|
||||
p_cb->rx_counter = 0;
|
||||
p_cb->rx_secondary_buffer_length = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
p_cb->p_rx_secondary_buffer = p_data;
|
||||
p_cb->rx_secondary_buffer_length = length;
|
||||
}
|
||||
|
||||
NRF_LOG_INFO("RX Id:%d len:%d", nrf_drv_get_IRQn((void *)p_instance->reg.p_reg), length);
|
||||
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
return nrf_drv_uart_rx_for_uarte(p_instance, p_data, length, second_buffer);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
return nrf_drv_uart_rx_for_uart(p_instance, p_data, length, second_buffer);
|
||||
)
|
||||
}
|
||||
|
||||
bool nrf_drv_uart_rx_ready(nrf_drv_uart_t const * p_instance)
|
||||
{
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
return nrf_uarte_event_check(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ENDRX);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
return nrf_uart_event_check(p_instance->reg.p_uart, NRF_UART_EVENT_RXDRDY);
|
||||
)
|
||||
}
|
||||
|
||||
void nrf_drv_uart_rx_enable(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
//Easy dma mode does not support enabling receiver without setting up buffer.
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
ASSERT(false);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
if (!m_cb[p_instance->drv_inst_idx].rx_enabled)
|
||||
{
|
||||
rx_enable(p_instance);
|
||||
m_cb[p_instance->drv_inst_idx].rx_enabled = true;
|
||||
}
|
||||
)
|
||||
}
|
||||
|
||||
void nrf_drv_uart_rx_disable(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
//Easy dma mode does not support enabling receiver without setting up buffer.
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
ASSERT(false);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
nrf_uart_task_trigger(p_instance->reg.p_uart, NRF_UART_TASK_STOPRX);
|
||||
m_cb[p_instance->drv_inst_idx].rx_enabled = false;
|
||||
)
|
||||
}
|
||||
|
||||
uint32_t nrf_drv_uart_errorsrc_get(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
uint32_t errsrc;
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_ERROR);
|
||||
errsrc = nrf_uarte_errorsrc_get_and_clear(p_instance->reg.p_uarte);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
nrf_uart_event_clear(p_instance->reg.p_uart, NRF_UART_EVENT_ERROR);
|
||||
errsrc = nrf_uart_errorsrc_get_and_clear(p_instance->reg.p_uart);
|
||||
)
|
||||
return errsrc;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void rx_done_event(uart_control_block_t * p_cb, uint8_t bytes, uint8_t * p_data)
|
||||
{
|
||||
nrf_drv_uart_event_t event;
|
||||
|
||||
event.type = NRF_DRV_UART_EVT_RX_DONE;
|
||||
event.data.rxtx.bytes = bytes;
|
||||
event.data.rxtx.p_data = p_data;
|
||||
|
||||
p_cb->handler(&event, p_cb->p_context);
|
||||
}
|
||||
|
||||
__STATIC_INLINE void tx_done_event(uart_control_block_t * p_cb, uint8_t bytes)
|
||||
{
|
||||
nrf_drv_uart_event_t event;
|
||||
|
||||
event.type = NRF_DRV_UART_EVT_TX_DONE;
|
||||
event.data.rxtx.bytes = bytes;
|
||||
event.data.rxtx.p_data = (uint8_t *)p_cb->p_tx_buffer;
|
||||
|
||||
p_cb->tx_buffer_length = 0;
|
||||
|
||||
NRF_LOG_INFO("TX done len:%d", bytes);
|
||||
p_cb->handler(&event, p_cb->p_context);
|
||||
}
|
||||
|
||||
void nrf_drv_uart_tx_abort(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
|
||||
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
nrf_uarte_event_clear(p_instance->reg.p_uarte, NRF_UARTE_EVENT_TXSTOPPED);
|
||||
nrf_uarte_task_trigger(p_instance->reg.p_uarte, NRF_UARTE_TASK_STOPTX);
|
||||
if (p_cb->handler == NULL)
|
||||
{
|
||||
while (!nrf_uarte_event_check(p_instance->reg.p_uarte, NRF_UARTE_EVENT_TXSTOPPED));
|
||||
}
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
nrf_uart_task_trigger(p_instance->reg.p_uart, NRF_UART_TASK_STOPTX);
|
||||
if (p_cb->handler)
|
||||
{
|
||||
tx_done_event(p_cb, p_cb->tx_counter);
|
||||
}
|
||||
else
|
||||
{
|
||||
p_cb->tx_counter = TX_COUNTER_ABORT_REQ_VALUE;
|
||||
}
|
||||
)
|
||||
NRF_LOG_INFO("TX abort Id:%d", nrf_drv_get_IRQn((void *)p_instance->reg.p_reg));
|
||||
}
|
||||
|
||||
void nrf_drv_uart_rx_abort(const nrf_drv_uart_t * p_instance)
|
||||
{
|
||||
CODE_FOR_UARTE
|
||||
(
|
||||
nrf_uarte_task_trigger(p_instance->reg.p_uarte, NRF_UARTE_TASK_STOPRX);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
nrf_uart_int_disable(p_instance->reg.p_uart, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
|
||||
nrf_uart_task_trigger(p_instance->reg.p_uart, NRF_UART_TASK_STOPRX);
|
||||
)
|
||||
NRF_LOG_INFO("RX abort Id:%d", nrf_drv_get_IRQn((void *)p_instance->reg.p_reg));
|
||||
}
|
||||
|
||||
|
||||
#if defined(UART_IN_USE)
|
||||
__STATIC_INLINE void uart_irq_handler(NRF_UART_Type * p_uart, uart_control_block_t * p_cb)
|
||||
{
|
||||
if (nrf_uart_int_enable_check(p_uart, NRF_UART_INT_MASK_ERROR) &&
|
||||
nrf_uart_event_check(p_uart, NRF_UART_EVENT_ERROR))
|
||||
{
|
||||
nrf_drv_uart_event_t event;
|
||||
nrf_uart_event_clear(p_uart, NRF_UART_EVENT_ERROR);
|
||||
nrf_uart_int_disable(p_uart, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
|
||||
if (!p_cb->rx_enabled)
|
||||
{
|
||||
nrf_uart_task_trigger(p_uart, NRF_UART_TASK_STOPRX);
|
||||
}
|
||||
event.type = NRF_DRV_UART_EVT_ERROR;
|
||||
event.data.error.error_mask = nrf_uart_errorsrc_get_and_clear(p_uart);
|
||||
event.data.error.rxtx.bytes = p_cb->rx_buffer_length;
|
||||
event.data.error.rxtx.p_data = p_cb->p_rx_buffer;
|
||||
|
||||
//abort transfer
|
||||
p_cb->rx_buffer_length = 0;
|
||||
p_cb->rx_secondary_buffer_length = 0;
|
||||
|
||||
p_cb->handler(&event,p_cb->p_context);
|
||||
}
|
||||
else if (nrf_uart_int_enable_check(p_uart, NRF_UART_INT_MASK_RXDRDY) &&
|
||||
nrf_uart_event_check(p_uart, NRF_UART_EVENT_RXDRDY))
|
||||
{
|
||||
rx_byte(p_uart, p_cb);
|
||||
if (p_cb->rx_buffer_length == p_cb->rx_counter)
|
||||
{
|
||||
if (p_cb->rx_secondary_buffer_length)
|
||||
{
|
||||
uint8_t * p_data = p_cb->p_rx_buffer;
|
||||
uint8_t rx_counter = p_cb->rx_counter;
|
||||
|
||||
//Switch to secondary buffer.
|
||||
p_cb->rx_buffer_length = p_cb->rx_secondary_buffer_length;
|
||||
p_cb->p_rx_buffer = p_cb->p_rx_secondary_buffer;
|
||||
p_cb->rx_secondary_buffer_length = 0;
|
||||
p_cb->rx_counter = 0;
|
||||
rx_done_event(p_cb, rx_counter, p_data);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (!p_cb->rx_enabled)
|
||||
{
|
||||
nrf_uart_task_trigger(p_uart, NRF_UART_TASK_STOPRX);
|
||||
}
|
||||
nrf_uart_int_disable(p_uart, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
|
||||
p_cb->rx_buffer_length = 0;
|
||||
rx_done_event(p_cb, p_cb->rx_counter, p_cb->p_rx_buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (nrf_uart_event_check(p_uart, NRF_UART_EVENT_TXDRDY))
|
||||
{
|
||||
if (p_cb->tx_counter < (uint16_t) p_cb->tx_buffer_length)
|
||||
{
|
||||
tx_byte(p_uart, p_cb);
|
||||
}
|
||||
else
|
||||
{
|
||||
nrf_uart_event_clear(p_uart, NRF_UART_EVENT_TXDRDY);
|
||||
if (p_cb->tx_buffer_length)
|
||||
{
|
||||
tx_done_event(p_cb, p_cb->tx_buffer_length);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (nrf_uart_event_check(p_uart, NRF_UART_EVENT_RXTO))
|
||||
{
|
||||
nrf_uart_event_clear(p_uart, NRF_UART_EVENT_RXTO);
|
||||
|
||||
// RXTO event may be triggered as a result of abort call. In th
|
||||
if (p_cb->rx_enabled)
|
||||
{
|
||||
nrf_uart_task_trigger(p_uart, NRF_UART_TASK_STARTRX);
|
||||
}
|
||||
if (p_cb->rx_buffer_length)
|
||||
{
|
||||
p_cb->rx_buffer_length = 0;
|
||||
rx_done_event(p_cb, p_cb->rx_counter, p_cb->p_rx_buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(UARTE_IN_USE)
|
||||
__STATIC_INLINE void uarte_irq_handler(NRF_UARTE_Type * p_uarte, uart_control_block_t * p_cb)
|
||||
{
|
||||
if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ERROR))
|
||||
{
|
||||
nrf_drv_uart_event_t event;
|
||||
|
||||
nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ERROR);
|
||||
|
||||
event.type = NRF_DRV_UART_EVT_ERROR;
|
||||
event.data.error.error_mask = nrf_uarte_errorsrc_get_and_clear(p_uarte);
|
||||
event.data.error.rxtx.bytes = nrf_uarte_rx_amount_get(p_uarte);
|
||||
event.data.error.rxtx.p_data = p_cb->p_rx_buffer;
|
||||
|
||||
//abort transfer
|
||||
p_cb->rx_buffer_length = 0;
|
||||
p_cb->rx_secondary_buffer_length = 0;
|
||||
|
||||
p_cb->handler(&event, p_cb->p_context);
|
||||
}
|
||||
else if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDRX))
|
||||
{
|
||||
nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDRX);
|
||||
uint8_t amount = nrf_uarte_rx_amount_get(p_uarte);
|
||||
// If the transfer was stopped before completion, amount of transfered bytes
|
||||
// will not be equal to the buffer length. Interrupted trunsfer is ignored.
|
||||
if (amount == p_cb->rx_buffer_length)
|
||||
{
|
||||
if (p_cb->rx_secondary_buffer_length)
|
||||
{
|
||||
uint8_t * p_data = p_cb->p_rx_buffer;
|
||||
nrf_uarte_shorts_disable(p_uarte, NRF_UARTE_SHORT_ENDRX_STARTRX);
|
||||
p_cb->rx_buffer_length = p_cb->rx_secondary_buffer_length;
|
||||
p_cb->p_rx_buffer = p_cb->p_rx_secondary_buffer;
|
||||
p_cb->rx_secondary_buffer_length = 0;
|
||||
rx_done_event(p_cb, amount, p_data);
|
||||
}
|
||||
else
|
||||
{
|
||||
p_cb->rx_buffer_length = 0;
|
||||
rx_done_event(p_cb, amount, p_cb->p_rx_buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_RXTO))
|
||||
{
|
||||
nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_RXTO);
|
||||
if (p_cb->rx_buffer_length)
|
||||
{
|
||||
p_cb->rx_buffer_length = 0;
|
||||
rx_done_event(p_cb, nrf_uarte_rx_amount_get(p_uarte), p_cb->p_rx_buffer);
|
||||
}
|
||||
}
|
||||
|
||||
if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDTX))
|
||||
{
|
||||
nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDTX);
|
||||
if (p_cb->tx_buffer_length)
|
||||
{
|
||||
tx_done_event(p_cb, nrf_uarte_tx_amount_get(p_uarte));
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if UART0_ENABLED
|
||||
IRQ_HANDLER(0)
|
||||
{
|
||||
CODE_FOR_UARTE_INT
|
||||
(
|
||||
UART0_INSTANCE_INDEX,
|
||||
uarte_irq_handler(NRF_UARTE0, &m_cb[UART0_INSTANCE_INDEX]);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
uart_irq_handler(NRF_UART0, &m_cb[UART0_INSTANCE_INDEX]);
|
||||
)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if UART1_ENABLED
|
||||
void UARTE1_IRQHandler(void)
|
||||
{
|
||||
CODE_FOR_UARTE_INT
|
||||
(
|
||||
UART1_INSTANCE_INDEX,
|
||||
uarte_irq_handler(NRF_UARTE1, &m_cb[UART1_INSTANCE_INDEX]);
|
||||
)
|
||||
CODE_FOR_UART
|
||||
(
|
||||
uart_irq_handler(NRF_UART1, &m_cb[UART1_INSTANCE_INDEX]);
|
||||
)
|
||||
}
|
||||
#endif
|
||||
#endif //NRF_MODULE_ENABLED(UART)
|
||||
|
||||
465
lib/sdk/components/drivers_nrf/uart/nrf_drv_uart.h
Normal file
465
lib/sdk/components/drivers_nrf/uart/nrf_drv_uart.h
Normal file
@ -0,0 +1,465 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**@file
|
||||
* @addtogroup nrf_uart UART driver and HAL
|
||||
* @ingroup nrf_drivers
|
||||
* @brief UART API.
|
||||
* @details The UART driver provides APIs for utilizing the UART peripheral.
|
||||
*
|
||||
* @defgroup nrf_drv_uart UART driver
|
||||
* @{
|
||||
* @ingroup nrf_uart
|
||||
*
|
||||
* @brief UART driver.
|
||||
*/
|
||||
|
||||
#ifndef NRF_DRV_UART_H
|
||||
#define NRF_DRV_UART_H
|
||||
|
||||
#include "nrf_peripherals.h"
|
||||
|
||||
#ifdef UART_PRESENT
|
||||
#include "nrf_uart.h"
|
||||
#endif
|
||||
|
||||
#ifdef UARTE_PRESENT
|
||||
#include "nrf_uarte.h"
|
||||
#endif
|
||||
|
||||
#include "sdk_errors.h"
|
||||
#include "sdk_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef UART1_ENABLED
|
||||
#define UART1_ENABLED 0
|
||||
#endif
|
||||
|
||||
#ifndef UART0_ENABLED
|
||||
#define UART0_ENABLED 0
|
||||
#endif
|
||||
|
||||
#define UART0_INSTANCE_INDEX 0
|
||||
#define UART1_INSTANCE_INDEX UART0_ENABLED
|
||||
#define UART_ENABLED_COUNT UART0_ENABLED + UART1_ENABLED
|
||||
|
||||
#if defined(UARTE_PRESENT) && defined(UART_PRESENT)
|
||||
#define NRF_DRV_UART_PERIPHERAL(id) \
|
||||
(CONCAT_3(UART, id, _CONFIG_USE_EASY_DMA) == 1 ? \
|
||||
(void *)CONCAT_2(NRF_UARTE, id) \
|
||||
: (void *)CONCAT_2(NRF_UART, id))
|
||||
#elif defined(UART_PRESENT)
|
||||
#define NRF_DRV_UART_PERIPHERAL(id) (void *)CONCAT_2(NRF_UART, id)
|
||||
#else //UARTE_PRESENT !UART_PRESENT
|
||||
#define NRF_DRV_UART_PERIPHERAL(id) (void *)CONCAT_2(NRF_UARTE, id)
|
||||
#endif
|
||||
|
||||
// This set of macros makes it possible to exclude parts of code, when one type
|
||||
// of supported peripherals is not used.
|
||||
|
||||
#if defined(UARTE_PRESENT) && defined(UART_PRESENT)
|
||||
|
||||
#if (UART_EASY_DMA_SUPPORT == 1)
|
||||
#define UARTE_IN_USE
|
||||
#endif
|
||||
|
||||
#if (UART_LEGACY_SUPPORT == 1)
|
||||
#define UART_IN_USE
|
||||
#endif
|
||||
|
||||
#if (UART_ENABLED == 1) && ((!defined(UARTE_IN_USE) && !defined(UART_IN_USE)) || ((UART_EASY_DMA_SUPPORT == 0) && (UART_LEGACY_SUPPORT == 0)))
|
||||
#error "Illegal settings in uart module!"
|
||||
#endif
|
||||
|
||||
#elif defined(UART_PRESENT)
|
||||
#define UART_IN_USE
|
||||
#elif defined(UARTE_PRESENT)
|
||||
#define UARTE_IN_USE
|
||||
#endif
|
||||
|
||||
#if defined(UARTE_PRESENT) && !defined(UART_PRESENT)
|
||||
typedef nrf_uarte_hwfc_t nrf_uart_hwfc_t;
|
||||
typedef nrf_uarte_parity_t nrf_uart_parity_t;
|
||||
typedef nrf_uarte_baudrate_t nrf_uart_baudrate_t;
|
||||
typedef nrf_uarte_error_mask_t nrf_uart_error_mask_t;
|
||||
typedef nrf_uarte_task_t nrf_uart_task_t;
|
||||
typedef nrf_uarte_event_t nrf_uart_event_t;
|
||||
#ifndef NRF_UART_PSEL_DISCONNECTED
|
||||
#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Structure for the UART driver instance.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
#if (defined(UARTE_IN_USE))
|
||||
NRF_UARTE_Type * p_uarte; ///< Pointer to a structure with UARTE registers.
|
||||
#endif
|
||||
#if (defined(UART_IN_USE) || (UART_ENABLED == 0))
|
||||
NRF_UART_Type * p_uart; ///< Pointer to a structure with UART registers.
|
||||
#endif
|
||||
void * p_reg;
|
||||
} reg;
|
||||
uint8_t drv_inst_idx; ///< Driver instance index.
|
||||
} nrf_drv_uart_t;
|
||||
|
||||
/**
|
||||
* @brief Macro for creating an UART driver instance.
|
||||
*/
|
||||
#define NRF_DRV_UART_INSTANCE(id) \
|
||||
{ \
|
||||
.reg = {NRF_DRV_UART_PERIPHERAL(id)}, \
|
||||
.drv_inst_idx = CONCAT_3(UART, id, _INSTANCE_INDEX),\
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Types of UART driver events.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NRF_DRV_UART_EVT_TX_DONE, ///< Requested TX transfer completed.
|
||||
NRF_DRV_UART_EVT_RX_DONE, ///< Requested RX transfer completed.
|
||||
NRF_DRV_UART_EVT_ERROR, ///< Error reported by UART peripheral.
|
||||
} nrf_drv_uart_evt_type_t;
|
||||
|
||||
/**@brief Structure for UART configuration. */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t pseltxd; ///< TXD pin number.
|
||||
uint32_t pselrxd; ///< RXD pin number.
|
||||
uint32_t pselcts; ///< CTS pin number.
|
||||
uint32_t pselrts; ///< RTS pin number.
|
||||
void * p_context; ///< Context passed to interrupt handler.
|
||||
nrf_uart_hwfc_t hwfc; ///< Flow control configuration.
|
||||
nrf_uart_parity_t parity; ///< Parity configuration.
|
||||
nrf_uart_baudrate_t baudrate; ///< Baudrate.
|
||||
uint8_t interrupt_priority; ///< Interrupt priority.
|
||||
#ifdef UARTE_PRESENT
|
||||
bool use_easy_dma;
|
||||
#endif
|
||||
} nrf_drv_uart_config_t;
|
||||
|
||||
/**@brief UART default configuration. */
|
||||
#ifdef UARTE_PRESENT
|
||||
#if !UART_LEGACY_SUPPORT
|
||||
#define DEFAULT_CONFIG_USE_EASY_DMA true
|
||||
#elif !UART_EASY_DMA_SUPPORT
|
||||
#define DEFAULT_CONFIG_USE_EASY_DMA false
|
||||
#else
|
||||
#define DEFAULT_CONFIG_USE_EASY_DMA UART0_USE_EASY_DMA
|
||||
#endif
|
||||
#define NRF_DRV_UART_DEFAULT_CONFIG \
|
||||
{ \
|
||||
.pseltxd = NRF_UART_PSEL_DISCONNECTED, \
|
||||
.pselrxd = NRF_UART_PSEL_DISCONNECTED, \
|
||||
.pselcts = NRF_UART_PSEL_DISCONNECTED, \
|
||||
.pselrts = NRF_UART_PSEL_DISCONNECTED, \
|
||||
.p_context = NULL, \
|
||||
.hwfc = (nrf_uart_hwfc_t)UART_DEFAULT_CONFIG_HWFC, \
|
||||
.parity = (nrf_uart_parity_t)UART_DEFAULT_CONFIG_PARITY, \
|
||||
.baudrate = (nrf_uart_baudrate_t)UART_DEFAULT_CONFIG_BAUDRATE, \
|
||||
.interrupt_priority = UART_DEFAULT_CONFIG_IRQ_PRIORITY, \
|
||||
.use_easy_dma = true \
|
||||
}
|
||||
#else
|
||||
#define NRF_DRV_UART_DEFAULT_CONFIG \
|
||||
{ \
|
||||
.pseltxd = NRF_UART_PSEL_DISCONNECTED, \
|
||||
.pselrxd = NRF_UART_PSEL_DISCONNECTED, \
|
||||
.pselcts = NRF_UART_PSEL_DISCONNECTED, \
|
||||
.pselrts = NRF_UART_PSEL_DISCONNECTED, \
|
||||
.p_context = NULL, \
|
||||
.hwfc = (nrf_uart_hwfc_t)UART_DEFAULT_CONFIG_HWFC, \
|
||||
.parity = (nrf_uart_parity_t)UART_DEFAULT_CONFIG_PARITY, \
|
||||
.baudrate = (nrf_uart_baudrate_t)UART_DEFAULT_CONFIG_BAUDRATE, \
|
||||
.interrupt_priority = UART_DEFAULT_CONFIG_IRQ_PRIORITY, \
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@brief Structure for UART transfer completion event. */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t * p_data; ///< Pointer to memory used for transfer.
|
||||
uint8_t bytes; ///< Number of bytes transfered.
|
||||
} nrf_drv_uart_xfer_evt_t;
|
||||
|
||||
/**@brief Structure for UART error event. */
|
||||
typedef struct
|
||||
{
|
||||
nrf_drv_uart_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transfered.
|
||||
uint32_t error_mask;///< Mask of error flags that generated the event.
|
||||
} nrf_drv_uart_error_evt_t;
|
||||
|
||||
/**@brief Structure for UART event. */
|
||||
typedef struct
|
||||
{
|
||||
nrf_drv_uart_evt_type_t type; ///< Event type.
|
||||
union
|
||||
{
|
||||
nrf_drv_uart_xfer_evt_t rxtx; ///< Data provided for transfer completion events.
|
||||
nrf_drv_uart_error_evt_t error;///< Data provided for error event.
|
||||
} data;
|
||||
} nrf_drv_uart_event_t;
|
||||
|
||||
/**
|
||||
* @brief UART interrupt event handler.
|
||||
*
|
||||
* @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available
|
||||
* only within the context of the event handler.
|
||||
* @param[in] p_context Context passed to interrupt handler, set on initialization.
|
||||
*/
|
||||
typedef void (*nrf_uart_event_handler_t)(nrf_drv_uart_event_t * p_event, void * p_context);
|
||||
|
||||
/**
|
||||
* @brief Function for initializing the UART driver.
|
||||
*
|
||||
* This function configures and enables UART. After this function GPIO pins are controlled by UART.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] p_config Initial configuration.
|
||||
* @param[in] event_handler Event handler provided by the user. If not provided driver works in
|
||||
* blocking mode.
|
||||
*
|
||||
* @retval NRF_SUCCESS If initialization was successful.
|
||||
* @retval NRF_ERROR_INVALID_STATE If driver is already initialized.
|
||||
*/
|
||||
ret_code_t nrf_drv_uart_init(nrf_drv_uart_t const * p_instance,
|
||||
nrf_drv_uart_config_t const * p_config,
|
||||
nrf_uart_event_handler_t event_handler);
|
||||
|
||||
/**
|
||||
* @brief Function for uninitializing the UART driver.
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_uart_uninit(nrf_drv_uart_t const * p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific UART task.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] task Task.
|
||||
*
|
||||
* @return Task address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_uart_task_address_get(nrf_drv_uart_t const * p_instance,
|
||||
nrf_uart_task_t task);
|
||||
|
||||
/**
|
||||
* @brief Function for getting the address of a specific UART event.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] event Event.
|
||||
*
|
||||
* @return Event address.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_drv_uart_event_address_get(nrf_drv_uart_t const * p_instance,
|
||||
nrf_uart_event_t event);
|
||||
|
||||
/**
|
||||
* @brief Function for sending data over UART.
|
||||
*
|
||||
* If an event handler was provided in nrf_drv_uart_init() call, this function
|
||||
* returns immediately and the handler is called when the transfer is done.
|
||||
* Otherwise, the transfer is performed in blocking mode, i.e. this function
|
||||
* returns when the transfer is finished. Blocking mode is not using interrupt so
|
||||
* there is no context switching inside the function.
|
||||
*
|
||||
* @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers
|
||||
* are placed in the Data RAM region. If they are not and UARTE instance is
|
||||
* used, this function will fail with error code NRF_ERROR_INVALID_ADDR.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] p_data Pointer to data.
|
||||
* @param[in] length Number of bytes to send.
|
||||
*
|
||||
* @retval NRF_SUCCESS If initialization was successful.
|
||||
* @retval NRF_ERROR_BUSY If driver is already transferring.
|
||||
* @retval NRF_ERROR_FORBIDDEN If the transfer was aborted from a different context
|
||||
* (blocking mode only, also see @ref nrf_drv_uart_rx_disable).
|
||||
* @retval NRF_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only).
|
||||
*/
|
||||
ret_code_t nrf_drv_uart_tx(nrf_drv_uart_t const * p_instance,
|
||||
uint8_t const * const p_data, uint8_t length);
|
||||
|
||||
/**
|
||||
* @brief Function for checking if UART is currently transmitting.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*
|
||||
* @retval true If UART is transmitting.
|
||||
* @retval false If UART is not transmitting.
|
||||
*/
|
||||
bool nrf_drv_uart_tx_in_progress(nrf_drv_uart_t const * p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for aborting any ongoing transmission.
|
||||
* @note @ref NRF_DRV_UART_EVT_TX_DONE event will be generated in non-blocking mode. Event will
|
||||
* contain number of bytes sent until abort was called. If Easy DMA is not used event will be
|
||||
* called from the function context. If Easy DMA is used it will be called from UART interrupt
|
||||
* context.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_uart_tx_abort(nrf_drv_uart_t const * p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for receiving data over UART.
|
||||
*
|
||||
* If an event handler was provided in the nrf_drv_uart_init() call, this function
|
||||
* returns immediately and the handler is called when the transfer is done.
|
||||
* Otherwise, the transfer is performed in blocking mode, i.e. this function
|
||||
* returns when the transfer is finished. Blocking mode is not using interrupt so
|
||||
* there is no context switching inside the function.
|
||||
* The receive buffer pointer is double buffered in non-blocking mode. The secondary
|
||||
* buffer can be set immediately after starting the transfer and will be filled
|
||||
* when the primary buffer is full. The double buffering feature allows
|
||||
* receiving data continuously.
|
||||
*
|
||||
* @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers
|
||||
* are placed in the Data RAM region. If they are not and UARTE driver instance
|
||||
* is used, this function will fail with error code NRF_ERROR_INVALID_ADDR.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
* @param[in] p_data Pointer to data.
|
||||
* @param[in] length Number of bytes to receive.
|
||||
*
|
||||
* @retval NRF_SUCCESS If initialization was successful.
|
||||
* @retval NRF_ERROR_BUSY If the driver is already receiving
|
||||
* (and the secondary buffer has already been set
|
||||
* in non-blocking mode).
|
||||
* @retval NRF_ERROR_FORBIDDEN If the transfer was aborted from a different context
|
||||
* (blocking mode only, also see @ref nrf_drv_uart_rx_disable).
|
||||
* @retval NRF_ERROR_INTERNAL If UART peripheral reported an error.
|
||||
* @retval NRF_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only).
|
||||
*/
|
||||
ret_code_t nrf_drv_uart_rx(nrf_drv_uart_t const * p_instance,
|
||||
uint8_t * p_data, uint8_t length);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for testing the receiver state in blocking mode.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*
|
||||
* @retval true If the receiver has at least one byte of data to get.
|
||||
* @retval false If the receiver is empty.
|
||||
*/
|
||||
bool nrf_drv_uart_rx_ready(nrf_drv_uart_t const * p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for enabling the receiver.
|
||||
*
|
||||
* UART has a 6-byte-long RX FIFO and it is used to store incoming data. If a user does not call the
|
||||
* UART receive function before the FIFO is filled, an overrun error will appear. Enabling the receiver
|
||||
* without specifying an RX buffer is supported only in UART mode (without Easy DMA). The receiver must be
|
||||
* explicitly closed by the user @sa nrf_drv_uart_rx_disable. This function asserts if the mode is wrong.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_uart_rx_enable(nrf_drv_uart_t const * p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for disabling the receiver.
|
||||
*
|
||||
* This function must be called to close the receiver after it has been explicitly enabled by
|
||||
* @sa nrf_drv_uart_rx_enable. The feature is supported only in UART mode (without Easy DMA). The function
|
||||
* asserts if mode is wrong.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_uart_rx_disable(nrf_drv_uart_t const * p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for aborting any ongoing reception.
|
||||
* @note @ref NRF_DRV_UART_EVT_RX_DONE event will be generated in non-blocking mode. The event will
|
||||
* contain the number of bytes received until abort was called. The event is called from UART interrupt
|
||||
* context.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*/
|
||||
void nrf_drv_uart_rx_abort(nrf_drv_uart_t const * p_instance);
|
||||
|
||||
/**
|
||||
* @brief Function for reading error source mask. Mask contains values from @ref nrf_uart_error_mask_t.
|
||||
* @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is
|
||||
* generated. Function clears error sources after reading.
|
||||
*
|
||||
* @param[in] p_instance Pointer to the driver instance structure.
|
||||
*
|
||||
* @retval Mask of reported errors.
|
||||
*/
|
||||
uint32_t nrf_drv_uart_errorsrc_get(nrf_drv_uart_t const * p_instance);
|
||||
|
||||
|
||||
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
||||
__STATIC_INLINE uint32_t nrf_drv_uart_task_address_get(nrf_drv_uart_t const * p_instance,
|
||||
nrf_uart_task_t task)
|
||||
{
|
||||
#ifdef UART_IN_USE
|
||||
return nrf_uart_task_address_get(p_instance->reg.p_uart, task);
|
||||
#else
|
||||
return nrf_uarte_task_address_get(p_instance->reg.p_uarte, (nrf_uarte_task_t)task);
|
||||
#endif
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t nrf_drv_uart_event_address_get(nrf_drv_uart_t const * p_instance,
|
||||
nrf_uart_event_t event)
|
||||
{
|
||||
#ifdef UART_IN_USE
|
||||
return nrf_uart_event_address_get(p_instance->reg.p_uart, event);
|
||||
#else
|
||||
return nrf_uarte_event_address_get(p_instance->reg.p_uarte, (nrf_uarte_event_t)event);
|
||||
#endif
|
||||
}
|
||||
#endif //SUPPRESS_INLINE_IMPLEMENTATION
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //NRF_DRV_UART_H
|
||||
/** @} */
|
||||
141
lib/sdk/components/drivers_nrf/usbd/nrf_drv_usbd_errata.h
Normal file
141
lib/sdk/components/drivers_nrf/usbd/nrf_drv_usbd_errata.h
Normal file
@ -0,0 +1,141 @@
|
||||
/**
|
||||
* Copyright (c) 2017 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NRF_DRV_USBD_ERRATA_H__
|
||||
#define NRF_DRV_USBD_ERRATA_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
/**
|
||||
* @defgroup nrf_drv_usbd_errata Functions to check if selected PAN is present in current chip
|
||||
* @{
|
||||
* @ingroup nrf_drv_usbd
|
||||
*
|
||||
* Functions here are checking the presence of an error in current chip.
|
||||
* The checking is done at runtime based on the microcontroller version.
|
||||
* This file is subject to removal when nRF51840 prototype support is removed.
|
||||
*/
|
||||
|
||||
#ifndef NRF_DRV_USBD_ERRATA_ENABLE
|
||||
/**
|
||||
* @brief The constant that informs if errata should be enabled at all
|
||||
*
|
||||
* If this constant is set to 0, all the Errata bug fixes will be automatically disabled.
|
||||
*/
|
||||
#define NRF_DRV_USBD_ERRATA_ENABLE 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Internal auxiliary function to check if the program is running on NRF52840 chip
|
||||
* @retval true It is NRF52480 chip
|
||||
* @retval false It is other chip
|
||||
*/
|
||||
static inline bool nrf_drv_usbd_errata_type_52840(void)
|
||||
{
|
||||
return ((((*(uint32_t *)0xF0000FE0) & 0xFF) == 0x08) &&
|
||||
(((*(uint32_t *)0xF0000FE4) & 0x0F) == 0x0));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Internal auxiliary function to check if the program is running on first sample of
|
||||
* NRF52840 chip
|
||||
* @retval true It is NRF52480 chip and it is first sample version
|
||||
* @retval false It is other chip
|
||||
*/
|
||||
static inline bool nrf_drv_usbd_errata_type_52840_proto1(void)
|
||||
{
|
||||
return ( nrf_drv_usbd_errata_type_52840() &&
|
||||
( ((*(uint32_t *)0xF0000FE8) & 0xF0) == 0x00 ) &&
|
||||
( ((*(uint32_t *)0xF0000FEC) & 0xF0) == 0x00 ) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to check if chip requires errata 104
|
||||
*
|
||||
* Errata: USBD: EPDATA event is not always generated.
|
||||
*
|
||||
* @retval true Errata should be implemented
|
||||
* @retval false Errata should not be implemented
|
||||
*/
|
||||
static inline bool nrf_drv_usbd_errata_104(void)
|
||||
{
|
||||
return NRF_DRV_USBD_ERRATA_ENABLE && nrf_drv_usbd_errata_type_52840_proto1();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to check if chip requires errata 154
|
||||
*
|
||||
* Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task.
|
||||
*
|
||||
* @retval true Errata should be implemented
|
||||
* @retval false Errata should not be implemented
|
||||
*/
|
||||
static inline bool nrf_drv_usbd_errata_154(void)
|
||||
{
|
||||
return NRF_DRV_USBD_ERRATA_ENABLE && nrf_drv_usbd_errata_type_52840_proto1();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to check if chip requires errata 166
|
||||
*
|
||||
* Errata: ISO double buffering not functional
|
||||
*
|
||||
* @retval true Errata should be implemented
|
||||
* @retval false Errata should not be implemented
|
||||
*/
|
||||
static inline bool nrf_drv_usbd_errata_166(void)
|
||||
{
|
||||
return NRF_DRV_USBD_ERRATA_ENABLE && true;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to check if chip requires errata ???
|
||||
*
|
||||
* Errata: SIZE.EPOUT not writable
|
||||
*
|
||||
* @retval true Errata should be implemented
|
||||
* @retval false Errata should not be implemented
|
||||
*/
|
||||
static inline bool nrf_drv_usbd_errata_sizeepout_rw(void)
|
||||
{
|
||||
return NRF_DRV_USBD_ERRATA_ENABLE && nrf_drv_usbd_errata_type_52840_proto1();
|
||||
}
|
||||
|
||||
/** @} */
|
||||
#endif /* NRF_DRV_USBD_ERRATA_H__ */
|
||||
61
lib/sdk/components/libraries/crc16/crc16.c
Normal file
61
lib/sdk/components/libraries/crc16/crc16.c
Normal file
@ -0,0 +1,61 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_common.h"
|
||||
#if NRF_MODULE_ENABLED(CRC16)
|
||||
#include "crc16.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc)
|
||||
{
|
||||
uint16_t crc = (p_crc == NULL) ? 0xFFFF : *p_crc;
|
||||
|
||||
for (uint32_t i = 0; i < size; i++)
|
||||
{
|
||||
crc = (uint8_t)(crc >> 8) | (crc << 8);
|
||||
crc ^= p_data[i];
|
||||
crc ^= (uint8_t)(crc & 0xFF) >> 4;
|
||||
crc ^= (crc << 8) << 4;
|
||||
crc ^= ((crc & 0xFF) << 4) << 1;
|
||||
}
|
||||
|
||||
return crc;
|
||||
}
|
||||
#endif //NRF_MODULE_ENABLED(CRC16)
|
||||
80
lib/sdk/components/libraries/crc16/crc16.h
Normal file
80
lib/sdk/components/libraries/crc16/crc16.h
Normal file
@ -0,0 +1,80 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
*
|
||||
* @defgroup crc16 CRC16 compute
|
||||
* @{
|
||||
* @ingroup hci_transport
|
||||
*
|
||||
* @brief This module implements CRC-16-CCITT (polynomial 0x1021) with 0xFFFF initial value.
|
||||
* The data can be passed in multiple blocks.
|
||||
*/
|
||||
|
||||
#ifndef CRC16_H__
|
||||
#define CRC16_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**@brief Function for calculating CRC-16 in blocks.
|
||||
*
|
||||
* Feed each consecutive data block into this function, along with the current value of p_crc as
|
||||
* returned by the previous call of this function. The first call of this function should pass NULL
|
||||
* as the initial value of the crc in p_crc.
|
||||
*
|
||||
* @param[in] p_data The input data block for computation.
|
||||
* @param[in] size The size of the input data block in bytes.
|
||||
* @param[in] p_crc The previous calculated CRC-16 value or NULL if first call.
|
||||
*
|
||||
* @return The updated CRC-16 value, based on the input supplied.
|
||||
*/
|
||||
uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CRC16_H__
|
||||
|
||||
/** @} */
|
||||
214
lib/sdk/components/libraries/fifo/app_fifo.c
Normal file
214
lib/sdk/components/libraries/fifo/app_fifo.c
Normal file
@ -0,0 +1,214 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_common.h"
|
||||
#if NRF_MODULE_ENABLED(APP_FIFO)
|
||||
#include "app_fifo.h"
|
||||
|
||||
static __INLINE uint32_t fifo_length(app_fifo_t * p_fifo)
|
||||
{
|
||||
uint32_t tmp = p_fifo->read_pos;
|
||||
return p_fifo->write_pos - tmp;
|
||||
}
|
||||
|
||||
|
||||
#define FIFO_LENGTH() fifo_length(p_fifo) /**< Macro for calculating the FIFO length. */
|
||||
|
||||
|
||||
/**@brief Put one byte to the FIFO. */
|
||||
static __INLINE void fifo_put(app_fifo_t * p_fifo, uint8_t byte)
|
||||
{
|
||||
p_fifo->p_buf[p_fifo->write_pos & p_fifo->buf_size_mask] = byte;
|
||||
p_fifo->write_pos++;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Look at one byte in the FIFO. */
|
||||
static __INLINE void fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte)
|
||||
{
|
||||
*p_byte = p_fifo->p_buf[(p_fifo->read_pos + index) & p_fifo->buf_size_mask];
|
||||
}
|
||||
|
||||
|
||||
/**@brief Get one byte from the FIFO. */
|
||||
static __INLINE void fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte)
|
||||
{
|
||||
fifo_peek(p_fifo, 0, p_byte);
|
||||
p_fifo->read_pos++;
|
||||
}
|
||||
|
||||
|
||||
uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size)
|
||||
{
|
||||
// Check buffer for null pointer.
|
||||
if (p_buf == NULL)
|
||||
{
|
||||
return NRF_ERROR_NULL;
|
||||
}
|
||||
|
||||
// Check that the buffer size is a power of two.
|
||||
if (!IS_POWER_OF_TWO(buf_size))
|
||||
{
|
||||
return NRF_ERROR_INVALID_LENGTH;
|
||||
}
|
||||
|
||||
p_fifo->p_buf = p_buf;
|
||||
p_fifo->buf_size_mask = buf_size - 1;
|
||||
p_fifo->read_pos = 0;
|
||||
p_fifo->write_pos = 0;
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte)
|
||||
{
|
||||
if (FIFO_LENGTH() <= p_fifo->buf_size_mask)
|
||||
{
|
||||
fifo_put(p_fifo, byte);
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
return NRF_ERROR_NO_MEM;
|
||||
}
|
||||
|
||||
|
||||
uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte)
|
||||
{
|
||||
if (FIFO_LENGTH() != 0)
|
||||
{
|
||||
fifo_get(p_fifo, p_byte);
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
return NRF_ERROR_NOT_FOUND;
|
||||
|
||||
}
|
||||
|
||||
|
||||
uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte)
|
||||
{
|
||||
if (FIFO_LENGTH() > index)
|
||||
{
|
||||
fifo_peek(p_fifo, index, p_byte);
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
return NRF_ERROR_NOT_FOUND;
|
||||
}
|
||||
|
||||
|
||||
uint32_t app_fifo_flush(app_fifo_t * p_fifo)
|
||||
{
|
||||
p_fifo->read_pos = p_fifo->write_pos;
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size)
|
||||
{
|
||||
VERIFY_PARAM_NOT_NULL(p_fifo);
|
||||
VERIFY_PARAM_NOT_NULL(p_size);
|
||||
|
||||
const uint32_t byte_count = fifo_length(p_fifo);
|
||||
const uint32_t requested_len = (*p_size);
|
||||
uint32_t index = 0;
|
||||
uint32_t read_size = MIN(requested_len, byte_count);
|
||||
|
||||
(*p_size) = byte_count;
|
||||
|
||||
// Check if the FIFO is empty.
|
||||
if (byte_count == 0)
|
||||
{
|
||||
return NRF_ERROR_NOT_FOUND;
|
||||
}
|
||||
|
||||
// Check if application has requested only the size.
|
||||
if (p_byte_array == NULL)
|
||||
{
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
// Fetch bytes from the FIFO.
|
||||
while (index < read_size)
|
||||
{
|
||||
fifo_get(p_fifo, &p_byte_array[index++]);
|
||||
}
|
||||
|
||||
(*p_size) = read_size;
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size)
|
||||
{
|
||||
VERIFY_PARAM_NOT_NULL(p_fifo);
|
||||
VERIFY_PARAM_NOT_NULL(p_size);
|
||||
|
||||
const uint32_t available_count = p_fifo->buf_size_mask - fifo_length(p_fifo) + 1;
|
||||
const uint32_t requested_len = (*p_size);
|
||||
uint32_t index = 0;
|
||||
uint32_t write_size = MIN(requested_len, available_count);
|
||||
|
||||
(*p_size) = available_count;
|
||||
|
||||
// Check if the FIFO is FULL.
|
||||
if (available_count == 0)
|
||||
{
|
||||
return NRF_ERROR_NO_MEM;
|
||||
}
|
||||
|
||||
// Check if application has requested only the size.
|
||||
if (p_byte_array == NULL)
|
||||
{
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
//Fetch bytes from the FIFO.
|
||||
while (index < write_size)
|
||||
{
|
||||
fifo_put(p_fifo, p_byte_array[index++]);
|
||||
}
|
||||
|
||||
(*p_size) = write_size;
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
#endif //NRF_MODULE_ENABLED(APP_FIFO)
|
||||
181
lib/sdk/components/libraries/fifo/app_fifo.h
Normal file
181
lib/sdk/components/libraries/fifo/app_fifo.h
Normal file
@ -0,0 +1,181 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**@file
|
||||
*
|
||||
* @defgroup app_fifo FIFO implementation
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief FIFO implementation.
|
||||
*/
|
||||
|
||||
#ifndef APP_FIFO_H__
|
||||
#define APP_FIFO_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**@brief A FIFO instance structure.
|
||||
* @details Keeps track of which bytes to read and write next.
|
||||
* Also, it keeps the information about which memory is allocated for the buffer
|
||||
* and its size. This structure must be initialized by app_fifo_init() before use.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */
|
||||
uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */
|
||||
volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */
|
||||
volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */
|
||||
} app_fifo_t;
|
||||
|
||||
/**@brief Function for initializing the FIFO.
|
||||
*
|
||||
* @param[out] p_fifo FIFO object.
|
||||
* @param[in] p_buf FIFO buffer for storing data. The buffer size must be a power of two.
|
||||
* @param[in] buf_size Size of the FIFO buffer provided. This size must be a power of two.
|
||||
*
|
||||
* @retval NRF_SUCCESS If initialization was successful.
|
||||
* @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer.
|
||||
* @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two.
|
||||
*/
|
||||
uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size);
|
||||
|
||||
/**@brief Function for adding an element to the FIFO.
|
||||
*
|
||||
* @param[in] p_fifo Pointer to the FIFO.
|
||||
* @param[in] byte Data byte to add to the FIFO.
|
||||
*
|
||||
* @retval NRF_SUCCESS If an element has been successfully added to the FIFO.
|
||||
* @retval NRF_ERROR_NO_MEM If the FIFO is full.
|
||||
*/
|
||||
uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte);
|
||||
|
||||
/**@brief Function for getting the next element from the FIFO.
|
||||
*
|
||||
* @param[in] p_fifo Pointer to the FIFO.
|
||||
* @param[out] p_byte Byte fetched from the FIFO.
|
||||
*
|
||||
* @retval NRF_SUCCESS If an element was returned.
|
||||
* @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue.
|
||||
*/
|
||||
uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte);
|
||||
|
||||
/**@brief Function for looking at an element in the FIFO, without consuming it.
|
||||
*
|
||||
* @param[in] p_fifo Pointer to the FIFO.
|
||||
* @param[in] index Which element to look at. The lower the index, the earlier it was put.
|
||||
* @param[out] p_byte Byte fetched from the FIFO.
|
||||
*
|
||||
* @retval NRF_SUCCESS If an element was returned.
|
||||
* @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue, or the index was
|
||||
* too large.
|
||||
*/
|
||||
uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte);
|
||||
|
||||
/**@brief Function for flushing the FIFO.
|
||||
*
|
||||
* @param[in] p_fifo Pointer to the FIFO.
|
||||
*
|
||||
* @retval NRF_SUCCESS If the FIFO was flushed successfully.
|
||||
*/
|
||||
uint32_t app_fifo_flush(app_fifo_t * p_fifo);
|
||||
|
||||
/**@brief Function for reading bytes from the FIFO.
|
||||
*
|
||||
* This function can also be used to get the number of bytes in the FIFO.
|
||||
*
|
||||
* @param[in] p_fifo Pointer to the FIFO. Must not be NULL.
|
||||
* @param[out] p_byte_array Memory pointer where the read bytes are fetched from the FIFO.
|
||||
* Can be NULL. If NULL, the number of bytes that can be read in the FIFO
|
||||
* are returned in the p_size parameter.
|
||||
* @param[inout] p_size Address to memory indicating the maximum number of bytes to be read.
|
||||
* The provided memory is overwritten with the actual number of bytes
|
||||
* read if the procedure was successful. This field must not be NULL.
|
||||
* If p_byte_array is set to NULL by the application, this parameter
|
||||
* returns the number of bytes in the FIFO.
|
||||
*
|
||||
* @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes read might
|
||||
* be less than the requested maximum, depending on how many elements exist
|
||||
* in the FIFO. Even if less bytes are returned, the procedure is considered
|
||||
* successful.
|
||||
* @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not
|
||||
* be NULL.
|
||||
* @retval NRF_ERROR_NOT_FOUND If the FIFO is empty.
|
||||
*/
|
||||
uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size);
|
||||
|
||||
/**@brief Function for writing bytes to the FIFO.
|
||||
*
|
||||
* This function can also be used to get the available size on the FIFO.
|
||||
*
|
||||
* @param[in] p_fifo Pointer to the FIFO. Must not be NULL.
|
||||
* @param[in] p_byte_array Memory pointer containing the bytes to be written to the FIFO.
|
||||
* Can be NULL. If NULL, this function returns the number of bytes
|
||||
* that can be written to the FIFO.
|
||||
* @param[inout] p_size Address to memory indicating the maximum number of bytes to be written.
|
||||
* The provided memory is overwritten with the number of bytes that were actually
|
||||
* written if the procedure is successful. This field must not be NULL.
|
||||
* If p_byte_array is set to NULL by the application, this parameter
|
||||
* returns the number of bytes available in the FIFO.
|
||||
*
|
||||
* @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes written might
|
||||
* be less than the requested maximum, depending on how much room there is in
|
||||
* the FIFO. Even if less bytes are written, the procedure is considered
|
||||
* successful. If the write was partial, the application should use
|
||||
* subsequent calls to attempt writing the data again.
|
||||
* @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not
|
||||
* be NULL.
|
||||
* @retval NRF_ERROR_NO_MEM If the FIFO is full.
|
||||
*
|
||||
*/
|
||||
uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // APP_FIFO_H__
|
||||
|
||||
/** @} */
|
||||
264
lib/sdk/components/libraries/hci/hci_mem_pool.c
Normal file
264
lib/sdk/components/libraries/hci/hci_mem_pool.c
Normal file
@ -0,0 +1,264 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_common.h"
|
||||
#if NRF_MODULE_ENABLED(HCI_MEM_POOL)
|
||||
#include "hci_mem_pool.h"
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
|
||||
/**@brief RX buffer element instance structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t rx_buffer[HCI_RX_BUF_SIZE]; /**< RX buffer memory array. */
|
||||
uint32_t length; /**< Length of the RX buffer memory array. */
|
||||
} rx_buffer_elem_t;
|
||||
|
||||
/**@brief RX buffer queue element instance structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
rx_buffer_elem_t * p_buffer; /**< Pointer to RX buffer element. */
|
||||
uint32_t free_window_count; /**< Free space element count. */
|
||||
uint32_t free_available_count; /**< Free area element count. */
|
||||
uint32_t read_available_count; /**< Read area element count. */
|
||||
uint32_t write_index; /**< Write position index. */
|
||||
uint32_t read_index; /**< Read position index. */
|
||||
uint32_t free_index; /**< Free position index. */
|
||||
} rx_buffer_queue_t;
|
||||
|
||||
static bool m_is_tx_allocated; /**< Boolean value to determine if the TX buffer is allocated. */
|
||||
static rx_buffer_elem_t m_rx_buffer_elem_queue[HCI_RX_BUF_QUEUE_SIZE]; /**< RX buffer element instances. */
|
||||
static rx_buffer_queue_t m_rx_buffer_queue; /**< RX buffer queue element instance. */
|
||||
|
||||
|
||||
uint32_t hci_mem_pool_open(void)
|
||||
{
|
||||
m_is_tx_allocated = false;
|
||||
m_rx_buffer_queue.p_buffer = m_rx_buffer_elem_queue;
|
||||
m_rx_buffer_queue.free_window_count = HCI_RX_BUF_QUEUE_SIZE;
|
||||
m_rx_buffer_queue.free_available_count = 0;
|
||||
m_rx_buffer_queue.read_available_count = 0;
|
||||
m_rx_buffer_queue.write_index = 0;
|
||||
m_rx_buffer_queue.read_index = 0;
|
||||
m_rx_buffer_queue.free_index = 0;
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_mem_pool_close(void)
|
||||
{
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer)
|
||||
{
|
||||
static uint8_t tx_buffer[HCI_TX_BUF_SIZE];
|
||||
|
||||
uint32_t err_code;
|
||||
|
||||
if (pp_buffer == NULL)
|
||||
{
|
||||
return NRF_ERROR_NULL;
|
||||
}
|
||||
|
||||
if (!m_is_tx_allocated)
|
||||
{
|
||||
m_is_tx_allocated = true;
|
||||
*pp_buffer = tx_buffer;
|
||||
err_code = NRF_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_NO_MEM;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_mem_pool_tx_free(void)
|
||||
{
|
||||
m_is_tx_allocated = false;
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
if (pp_buffer == NULL)
|
||||
{
|
||||
return NRF_ERROR_NULL;
|
||||
}
|
||||
*pp_buffer = NULL;
|
||||
|
||||
if (m_rx_buffer_queue.free_window_count != 0)
|
||||
{
|
||||
if (length <= HCI_RX_BUF_SIZE)
|
||||
{
|
||||
--(m_rx_buffer_queue.free_window_count);
|
||||
++(m_rx_buffer_queue.read_available_count);
|
||||
|
||||
*pp_buffer =
|
||||
m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.write_index].rx_buffer;
|
||||
|
||||
m_rx_buffer_queue.free_index |= (1u << m_rx_buffer_queue.write_index);
|
||||
|
||||
// @note: Adjust the write_index making use of the fact that the buffer size is of
|
||||
// power of two and two's complement arithmetic. For details refer example to book
|
||||
// "Making embedded systems: Elicia White".
|
||||
m_rx_buffer_queue.write_index =
|
||||
(m_rx_buffer_queue.write_index + 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
|
||||
|
||||
err_code = NRF_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_DATA_SIZE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_NO_MEM;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer)
|
||||
{
|
||||
uint32_t err_code;
|
||||
uint32_t consume_index;
|
||||
uint32_t start_index;
|
||||
|
||||
if (m_rx_buffer_queue.free_available_count != 0)
|
||||
{
|
||||
// Find the buffer that has been freed -
|
||||
// Start at read_index minus free_available_count and then increment until read index.
|
||||
err_code = NRF_ERROR_INVALID_ADDR;
|
||||
consume_index = (m_rx_buffer_queue.read_index - m_rx_buffer_queue.free_available_count) &
|
||||
(HCI_RX_BUF_QUEUE_SIZE - 1u);
|
||||
start_index = consume_index;
|
||||
|
||||
do
|
||||
{
|
||||
if (m_rx_buffer_queue.p_buffer[consume_index].rx_buffer == p_buffer)
|
||||
{
|
||||
m_rx_buffer_queue.free_index ^= (1u << consume_index);
|
||||
err_code = NRF_SUCCESS;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
consume_index = (consume_index + 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
|
||||
}
|
||||
}
|
||||
while (consume_index != m_rx_buffer_queue.read_index);
|
||||
|
||||
while (!(m_rx_buffer_queue.free_index & (1 << start_index)) &&
|
||||
(m_rx_buffer_queue.free_available_count != 0))
|
||||
{
|
||||
--(m_rx_buffer_queue.free_available_count);
|
||||
++(m_rx_buffer_queue.free_window_count);
|
||||
start_index = (consume_index + 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_NO_MEM;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_mem_pool_rx_data_size_set(uint32_t length)
|
||||
{
|
||||
// @note: Adjust the write_index making use of the fact that the buffer size is of power
|
||||
// of two and two's complement arithmetic. For details refer example to book
|
||||
// "Making embedded systems: Elicia White".
|
||||
const uint32_t index = (m_rx_buffer_queue.write_index - 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
|
||||
m_rx_buffer_queue.p_buffer[index].length = length;
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
if ((pp_buffer == NULL) || (p_length == NULL))
|
||||
{
|
||||
return NRF_ERROR_NULL;
|
||||
}
|
||||
|
||||
if (m_rx_buffer_queue.read_available_count != 0)
|
||||
{
|
||||
--(m_rx_buffer_queue.read_available_count);
|
||||
++(m_rx_buffer_queue.free_available_count);
|
||||
|
||||
*pp_buffer =
|
||||
m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].rx_buffer;
|
||||
*p_length =
|
||||
m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].length;
|
||||
|
||||
// @note: Adjust the write_index making use of the fact that the buffer size is of power
|
||||
// of two and two's complement arithmetic. For details refer example to book
|
||||
// "Making embedded systems: Elicia White".
|
||||
m_rx_buffer_queue.read_index =
|
||||
(m_rx_buffer_queue.read_index + 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
|
||||
|
||||
err_code = NRF_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_NO_MEM;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
#endif //NRF_MODULE_ENABLED(HCI_MEM_POOL)
|
||||
168
lib/sdk/components/libraries/hci/hci_mem_pool.h
Normal file
168
lib/sdk/components/libraries/hci/hci_mem_pool.h
Normal file
@ -0,0 +1,168 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
*
|
||||
* @defgroup hci_mem_pool Memory pool
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief Memory pool implementation
|
||||
*
|
||||
* Memory pool implementation, based on circular buffer data structure, which supports asynchronous
|
||||
* processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers.
|
||||
* The memory managed by the pool is allocated from static storage instead of heap. The internal
|
||||
* design of the circular buffer implementing the RX memory layout is illustrated in the picture
|
||||
* below.
|
||||
*
|
||||
* @image html memory_pool.svg "Circular buffer design"
|
||||
*
|
||||
* The expected call order for the RX APIs is as follows:
|
||||
* - hci_mem_pool_rx_produce
|
||||
* - hci_mem_pool_rx_data_size_set
|
||||
* - hci_mem_pool_rx_extract
|
||||
* - hci_mem_pool_rx_consume
|
||||
*
|
||||
* @warning If the above mentioned expected call order is violated the end result can be undefined.
|
||||
*
|
||||
* \par Component specific configuration options
|
||||
*
|
||||
* The following compile time configuration options are available to suit various implementations:
|
||||
* - TX_BUF_SIZE TX buffer size in bytes.
|
||||
* - RX_BUF_SIZE RX buffer size in bytes.
|
||||
* - RX_BUF_QUEUE_SIZE RX buffer element size.
|
||||
*/
|
||||
|
||||
#ifndef HCI_MEM_POOL_H__
|
||||
#define HCI_MEM_POOL_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include "nrf_error.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**@brief Function for opening the module.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
*/
|
||||
uint32_t hci_mem_pool_open(void);
|
||||
|
||||
/**@brief Function for closing the module.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
*/
|
||||
uint32_t hci_mem_pool_close(void);
|
||||
|
||||
/**@brief Function for allocating requested amount of TX memory.
|
||||
*
|
||||
* @param[out] pp_buffer Pointer to the allocated memory.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success. Memory was allocated.
|
||||
* @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation.
|
||||
* @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
|
||||
*/
|
||||
uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer);
|
||||
|
||||
/**@brief Function for freeing previously allocated TX memory.
|
||||
*
|
||||
* @note Memory management follows the FIFO principle meaning that free() order must match the
|
||||
* alloc(...) order, which is the reason for omitting exact memory block identifier as an
|
||||
* input parameter.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success. Memory was freed.
|
||||
*/
|
||||
uint32_t hci_mem_pool_tx_free(void);
|
||||
|
||||
/**@brief Function for producing a free RX memory block for usage.
|
||||
*
|
||||
* @note Upon produce request amount being 0, NRF_SUCCESS is returned.
|
||||
*
|
||||
* @param[in] length Amount, in bytes, of free memory to be produced.
|
||||
* @param[out] pp_buffer Pointer to the allocated memory.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success. Free RX memory block produced.
|
||||
* @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation.
|
||||
* @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit.
|
||||
* @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
|
||||
*/
|
||||
uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer);
|
||||
|
||||
/**@brief Function for setting the length of the last produced RX memory block.
|
||||
*
|
||||
* @warning If call to this API is omitted the end result is that the following call to
|
||||
* mem_pool_rx_extract will return incorrect data in the p_length output parameter.
|
||||
*
|
||||
* @param[in] length Amount, in bytes, of actual memory used.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success. Length was set.
|
||||
*/
|
||||
uint32_t hci_mem_pool_rx_data_size_set(uint32_t length);
|
||||
|
||||
/**@brief Function for extracting a packet, which has been filled with read data, for further
|
||||
* processing.
|
||||
*
|
||||
* @param[out] pp_buffer Pointer to the packet data.
|
||||
* @param[out] p_length Length of packet data in bytes.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
* @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
|
||||
* @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
|
||||
*/
|
||||
uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length);
|
||||
|
||||
/**@brief Function for freeing previously extracted packet, which has been filled with read data.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to consumed buffer.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
* @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free.
|
||||
* @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
|
||||
*/
|
||||
uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // HCI_MEM_POOL_H__
|
||||
|
||||
/** @} */
|
||||
457
lib/sdk/components/libraries/hci/hci_slip.c
Normal file
457
lib/sdk/components/libraries/hci/hci_slip.c
Normal file
@ -0,0 +1,457 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_common.h"
|
||||
#if NRF_MODULE_ENABLED(HCI_SLIP)
|
||||
#include "hci_slip.h"
|
||||
#include <stdlib.h>
|
||||
#include "app_uart.h"
|
||||
#include "nrf_error.h"
|
||||
|
||||
#define APP_SLIP_END 0xC0 /**< SLIP code for identifying the beginning and end of a packet frame.. */
|
||||
#define APP_SLIP_ESC 0xDB /**< SLIP escape code. This code is used to specify that the following character is specially encoded. */
|
||||
#define APP_SLIP_ESC_END 0xDC /**< SLIP special code. When this code follows 0xDB, this character is interpreted as payload data 0xC0.. */
|
||||
#define APP_SLIP_ESC_ESC 0xDD /**< SLIP special code. When this code follows 0xDB, this character is interpreted as payload data 0xDB. */
|
||||
|
||||
/** @brief States for the SLIP state machine. */
|
||||
typedef enum
|
||||
{
|
||||
SLIP_OFF, /**< SLIP state OFF. */
|
||||
SLIP_READY, /**< SLIP state ON. */
|
||||
SLIP_TRANSMITTING, /**< SLIP state is transmitting indicating write() has been called but data transmission has not completed. */
|
||||
} slip_states_t;
|
||||
|
||||
static slip_states_t m_current_state = SLIP_OFF; /** Current state for the SLIP TX state machine. */
|
||||
|
||||
static hci_slip_event_handler_t m_slip_event_handler; /** Event callback function for handling of SLIP events, @ref hci_slip_evt_type_t . */
|
||||
|
||||
static const uint8_t * mp_tx_buffer; /** Pointer to the current TX buffer that is in transmission. */
|
||||
static uint32_t m_tx_buffer_length; /** Length of the current TX buffer that is in transmission. */
|
||||
static volatile uint32_t m_tx_buffer_index; /** Current index for next byte to transmit in the mp_tx_buffer. */
|
||||
|
||||
static uint8_t * mp_rx_buffer; /** Pointer to the current RX buffer where the next SLIP decoded packet will be stored. */
|
||||
static uint32_t m_rx_buffer_length; /** Length of the current RX buffer. */
|
||||
static uint32_t m_rx_received_count; /** Number of SLIP decoded bytes received and stored in mp_rx_buffer. */
|
||||
|
||||
|
||||
/**@brief Function for parsing bytes received on the UART until a SLIP escape byte is received.
|
||||
*
|
||||
* @param[in] byte Byte received in UART module.
|
||||
*/
|
||||
static void handle_rx_byte_default(uint8_t byte);
|
||||
|
||||
/**@brief Function for parsing bytes received on the UART until SLIP end byte is received.
|
||||
*
|
||||
* @param[in] byte Byte received in UART module.
|
||||
*/
|
||||
static void handle_rx_byte_wait_start(uint8_t byte);
|
||||
|
||||
/**@brief Function for decoding a received SLIP escape byte.
|
||||
* It will ensure correct decoding of the byte following the SLIP escape byte.
|
||||
*
|
||||
* @param[in] byte Byte received in UART module.
|
||||
*/
|
||||
static void handle_rx_byte_esc(uint8_t byte);
|
||||
|
||||
/**@brief Function pointer for parsing and decoding SLIP bytes from the UART module.
|
||||
*
|
||||
* @param[in] byte Byte received in UART module.
|
||||
*/
|
||||
static void (*handle_rx_byte) (uint8_t byte) = handle_rx_byte_wait_start;
|
||||
|
||||
/**@brief Function pointer for sending a byte through the UART module.
|
||||
*/
|
||||
static uint32_t send_tx_byte_default(void);
|
||||
|
||||
/**@brief Function for transferring a SLIP escape byte (0xDB) when special bytes are transferred,
|
||||
* that is 0xC0 and 0xDB.
|
||||
*/
|
||||
static uint32_t send_tx_byte_esc(void);
|
||||
|
||||
/**@brief Function for transferring a byte when it collides with SLIP commands and follows the SLIP
|
||||
* escape byte, that is 0xC0 => 0xDC and 0xDB => 0xDD.
|
||||
*/
|
||||
static uint32_t send_tx_byte_encoded(void);
|
||||
|
||||
/**@brief Function for transferring the SLIP end frame byte, 0xC0.
|
||||
*/
|
||||
static uint32_t send_tx_byte_end(void);
|
||||
|
||||
/**@brief Function pointer for sending a byte through the UART module.
|
||||
*/
|
||||
uint32_t (*send_tx_byte) (void) = send_tx_byte_default;
|
||||
|
||||
|
||||
static uint32_t send_tx_byte_end(void)
|
||||
{
|
||||
uint32_t err_code = app_uart_put(APP_SLIP_END);
|
||||
|
||||
if ((err_code == NRF_SUCCESS) && (m_tx_buffer_index == 0))
|
||||
{
|
||||
// Packet transmission started.
|
||||
send_tx_byte = send_tx_byte_default;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
static uint32_t send_tx_byte_default(void)
|
||||
{
|
||||
uint32_t err_code = app_uart_put(mp_tx_buffer[m_tx_buffer_index]);
|
||||
|
||||
if (err_code == NRF_SUCCESS)
|
||||
{
|
||||
m_tx_buffer_index++;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
static uint32_t send_tx_byte_encoded(void)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
switch (mp_tx_buffer[m_tx_buffer_index])
|
||||
{
|
||||
case APP_SLIP_END:
|
||||
err_code = app_uart_put(APP_SLIP_ESC_END);
|
||||
break;
|
||||
|
||||
case APP_SLIP_ESC:
|
||||
err_code = app_uart_put(APP_SLIP_ESC_ESC);
|
||||
break;
|
||||
|
||||
default:
|
||||
err_code = NRF_ERROR_NO_MEM;
|
||||
break;
|
||||
}
|
||||
|
||||
if (err_code == NRF_SUCCESS)
|
||||
{
|
||||
m_tx_buffer_index++;
|
||||
send_tx_byte = send_tx_byte_default;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
static uint32_t send_tx_byte_esc(void)
|
||||
{
|
||||
uint32_t err_code = app_uart_put(APP_SLIP_ESC);
|
||||
|
||||
if (err_code == NRF_SUCCESS)
|
||||
{
|
||||
send_tx_byte = send_tx_byte_encoded;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
/** @brief Function for transferring the content of the mp_tx_buffer to the UART.
|
||||
* It continues to transfer bytes until the UART buffer is full or the complete buffer is
|
||||
* transferred.
|
||||
*/
|
||||
static void transmit_buffer(void)
|
||||
{
|
||||
uint32_t err_code = NRF_SUCCESS;
|
||||
|
||||
while (m_tx_buffer_index < m_tx_buffer_length)
|
||||
{
|
||||
if ((mp_tx_buffer[m_tx_buffer_index] == APP_SLIP_END ||
|
||||
mp_tx_buffer[m_tx_buffer_index] == APP_SLIP_ESC) &&
|
||||
send_tx_byte == send_tx_byte_default)
|
||||
{
|
||||
send_tx_byte = send_tx_byte_esc;
|
||||
}
|
||||
|
||||
err_code = send_tx_byte();
|
||||
|
||||
if (err_code == NRF_ERROR_NO_MEM || err_code == NRF_ERROR_BUSY)
|
||||
{
|
||||
// No memory left in UART TX buffer. Abort and wait for APP_UART_TX_EMPTY to continue.
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
send_tx_byte = send_tx_byte_end;
|
||||
|
||||
err_code = send_tx_byte();
|
||||
|
||||
if (err_code == NRF_SUCCESS)
|
||||
{
|
||||
// Packet transmission ended. Notify higher level.
|
||||
m_current_state = SLIP_READY;
|
||||
|
||||
if (m_slip_event_handler != NULL)
|
||||
{
|
||||
hci_slip_evt_t event = {HCI_SLIP_TX_DONE, mp_tx_buffer, m_tx_buffer_index};
|
||||
|
||||
m_slip_event_handler(event);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/** @brief Function for handling the reception of a SLIP end byte.
|
||||
* If the number of bytes received is greater than zero it will call m_slip_event_handler
|
||||
* with number of bytes received and invalidate the mp_rx_buffer to protect against data
|
||||
* corruption.
|
||||
* No new bytes can be received until a new RX buffer is supplied.
|
||||
*/
|
||||
static void handle_slip_end(void)
|
||||
{
|
||||
if (m_rx_received_count > 0)
|
||||
{
|
||||
// Full packet received, push it up.
|
||||
if (m_slip_event_handler != NULL)
|
||||
{
|
||||
hci_slip_evt_t event = {HCI_SLIP_RX_RDY, mp_rx_buffer, m_rx_received_count};
|
||||
|
||||
m_rx_received_count = 0;
|
||||
mp_rx_buffer = NULL;
|
||||
|
||||
m_slip_event_handler(event);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void handle_rx_byte_esc(uint8_t byte)
|
||||
{
|
||||
switch (byte)
|
||||
{
|
||||
case APP_SLIP_END:
|
||||
handle_slip_end();
|
||||
break;
|
||||
|
||||
case APP_SLIP_ESC_END:
|
||||
mp_rx_buffer[m_rx_received_count++] = APP_SLIP_END;
|
||||
break;
|
||||
|
||||
case APP_SLIP_ESC_ESC:
|
||||
mp_rx_buffer[m_rx_received_count++] = APP_SLIP_ESC;
|
||||
break;
|
||||
|
||||
default:
|
||||
mp_rx_buffer[m_rx_received_count++] = byte;
|
||||
break;
|
||||
}
|
||||
|
||||
handle_rx_byte = handle_rx_byte_default;
|
||||
}
|
||||
|
||||
|
||||
static void handle_rx_byte_default(uint8_t byte)
|
||||
{
|
||||
switch (byte)
|
||||
{
|
||||
case APP_SLIP_END:
|
||||
handle_slip_end();
|
||||
break;
|
||||
|
||||
case APP_SLIP_ESC:
|
||||
handle_rx_byte = handle_rx_byte_esc;
|
||||
break;
|
||||
|
||||
default:
|
||||
mp_rx_buffer[m_rx_received_count++] = byte;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void handle_rx_byte_wait_start(uint8_t byte)
|
||||
{
|
||||
if (byte == APP_SLIP_END)
|
||||
{
|
||||
handle_rx_byte = handle_rx_byte_default;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/** @brief Function for checking the current index and length of the RX buffer to determine if the
|
||||
* buffer is full. If an event handler has been registered, the callback function will
|
||||
* be executed..
|
||||
*
|
||||
* @retval true If RX buffer has overflowed.
|
||||
* @retval false otherwise.
|
||||
*
|
||||
*/
|
||||
static bool rx_buffer_overflowed(void)
|
||||
{
|
||||
if (mp_rx_buffer == NULL || m_rx_received_count >= m_rx_buffer_length)
|
||||
{
|
||||
if (m_slip_event_handler != NULL)
|
||||
{
|
||||
hci_slip_evt_t event = {HCI_SLIP_RX_OVERFLOW, mp_rx_buffer, m_rx_received_count};
|
||||
m_slip_event_handler(event);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
/** @brief Function for handling the UART module event. It parses events from the UART when
|
||||
* bytes are received/transmitted.
|
||||
*
|
||||
* @param[in] uart_event Event received from app_uart module.
|
||||
*/
|
||||
static void slip_uart_eventhandler(app_uart_evt_t * uart_event)
|
||||
{
|
||||
if (uart_event->evt_type == APP_UART_TX_EMPTY && m_current_state == SLIP_TRANSMITTING)
|
||||
{
|
||||
transmit_buffer();
|
||||
}
|
||||
|
||||
if ((uart_event->evt_type == APP_UART_DATA) && (!rx_buffer_overflowed()))
|
||||
{
|
||||
handle_rx_byte(uart_event->data.value);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/** @brief Function for enabling the UART module when the SLIP layer is opened.
|
||||
*/
|
||||
static uint32_t slip_uart_open(void)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
app_uart_comm_params_t comm_params =
|
||||
{
|
||||
HCI_UART_RX_PIN,
|
||||
HCI_UART_TX_PIN,
|
||||
HCI_UART_RTS_PIN,
|
||||
HCI_UART_CTS_PIN,
|
||||
(app_uart_flow_control_t)HCI_UART_FLOW_CONTROL,
|
||||
false,
|
||||
HCI_UART_BAUDRATE
|
||||
};
|
||||
|
||||
err_code = app_uart_init(&comm_params,
|
||||
NULL,
|
||||
slip_uart_eventhandler,
|
||||
APP_IRQ_PRIORITY_LOWEST);
|
||||
|
||||
if (err_code == NRF_SUCCESS)
|
||||
{
|
||||
m_current_state = SLIP_READY;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler)
|
||||
{
|
||||
m_slip_event_handler = event_handler;
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_slip_open()
|
||||
{
|
||||
switch (m_current_state)
|
||||
{
|
||||
case SLIP_OFF:
|
||||
return slip_uart_open();
|
||||
|
||||
default:
|
||||
// Do nothing.
|
||||
break;
|
||||
}
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_slip_close()
|
||||
{
|
||||
m_current_state = SLIP_OFF;
|
||||
uint32_t err_code = app_uart_close();
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length)
|
||||
{
|
||||
if (p_buffer == NULL)
|
||||
{
|
||||
return NRF_ERROR_INVALID_ADDR;
|
||||
}
|
||||
|
||||
switch (m_current_state)
|
||||
{
|
||||
case SLIP_READY:
|
||||
m_tx_buffer_index = 0;
|
||||
m_tx_buffer_length = length;
|
||||
mp_tx_buffer = p_buffer;
|
||||
m_current_state = SLIP_TRANSMITTING;
|
||||
send_tx_byte = send_tx_byte_end;
|
||||
|
||||
transmit_buffer();
|
||||
return NRF_SUCCESS;
|
||||
|
||||
case SLIP_TRANSMITTING:
|
||||
return NRF_ERROR_NO_MEM;
|
||||
|
||||
case SLIP_OFF:
|
||||
default:
|
||||
return NRF_ERROR_INVALID_STATE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length)
|
||||
{
|
||||
mp_rx_buffer = p_buffer;
|
||||
m_rx_buffer_length = length;
|
||||
m_rx_received_count = 0;
|
||||
handle_rx_byte = handle_rx_byte_wait_start;
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
#endif //NRF_MODULE_ENABLED(HCI_SLIP)
|
||||
165
lib/sdk/components/libraries/hci/hci_slip.h
Normal file
165
lib/sdk/components/libraries/hci/hci_slip.h
Normal file
@ -0,0 +1,165 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
*
|
||||
* @defgroup hci_slip SLIP module
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief SLIP layer for supporting packet framing in HCI transport.
|
||||
*
|
||||
* @details This module implements SLIP packet framing as described in the Bluetooth Core
|
||||
* Specification 4.0, Volume 4, Part D, Chapter 3 SLIP Layer.
|
||||
*
|
||||
* SLIP framing ensures that all packets sent on the UART are framed as:
|
||||
* <0xC0> SLIP packet 1 <0xC0> <0xC0> SLIP packet 2 <0xC0>.
|
||||
*
|
||||
* The SLIP layer uses events to notify the upper layer when data transmission is complete
|
||||
* and when a SLIP packet is received.
|
||||
*/
|
||||
|
||||
#ifndef HCI_SLIP_H__
|
||||
#define HCI_SLIP_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**@brief Event types from the SLIP Layer. */
|
||||
typedef enum
|
||||
{
|
||||
HCI_SLIP_RX_RDY, /**< An event indicating that an RX packet is ready to be read. */
|
||||
HCI_SLIP_TX_DONE, /**< An event indicating write completion of the TX packet provided in the function call \ref hci_slip_write . */
|
||||
HCI_SLIP_RX_OVERFLOW, /**< An event indicating that RX data has been discarded due to lack of free RX memory. */
|
||||
HCI_SLIP_ERROR, /**< An event indicating that an unrecoverable error has occurred. */
|
||||
HCI_SLIP_EVT_TYPE_MAX /**< Enumeration upper bound. */
|
||||
} hci_slip_evt_type_t;
|
||||
|
||||
/**@brief Structure containing an event from the SLIP layer.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
hci_slip_evt_type_t evt_type; /**< Type of event. */
|
||||
const uint8_t * packet; /**< This field contains a pointer to the packet for which the event relates, i.e. SLIP_TX_DONE: the packet transmitted, SLIP_RX_RDY: the packet received, SLIP_RX_OVERFLOW: The packet which overflow/or NULL if no receive buffer is available. */
|
||||
uint32_t packet_length; /**< Packet length, i.e. SLIP_TX_DONE: Bytes transmitted, SLIP_RX_RDY: Bytes received, SLIP_RX_OVERFLOW: index at which the packet overflowed. */
|
||||
} hci_slip_evt_t;
|
||||
|
||||
/**@brief Function for the SLIP layer event callback.
|
||||
*/
|
||||
typedef void (*hci_slip_event_handler_t)(hci_slip_evt_t event);
|
||||
|
||||
/**@brief Function for registering the event handler provided as parameter and this event handler
|
||||
* will be used by SLIP layer to send events described in \ref hci_slip_evt_type_t.
|
||||
*
|
||||
* @note Multiple registration requests will overwrite any existing registration.
|
||||
*
|
||||
* @param[in] event_handler This function is called by the SLIP layer upon an event.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
*/
|
||||
uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler);
|
||||
|
||||
/**@brief Function for opening the SLIP layer. This function must be called before
|
||||
* \ref hci_slip_write and before any data can be received.
|
||||
*
|
||||
* @note Can be called multiple times.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
*
|
||||
* The SLIP layer module will propagate errors from underlying sub-modules.
|
||||
* This implementation is using UART module as a physical transmission layer, and hci_slip_open
|
||||
* executes \ref app_uart_init . For an extended error list, please refer to \ref app_uart_init .
|
||||
*/
|
||||
uint32_t hci_slip_open(void);
|
||||
|
||||
/**@brief Function for closing the SLIP layer. After this function is called no data can be
|
||||
* transmitted or received in this layer.
|
||||
*
|
||||
* @note This function can be called multiple times and also for an unopened channel.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
*/
|
||||
uint32_t hci_slip_close(void);
|
||||
|
||||
/**@brief Function for writing a packet with SLIP encoding. Packet transmission is confirmed when
|
||||
* the HCI_SLIP_TX_DONE event is received by the function caller.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to the packet to transmit.
|
||||
* @param[in] length Packet length, in bytes.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success. Packet was encoded and added to the
|
||||
* transmission queue and an event will be sent upon transmission
|
||||
* completion.
|
||||
* @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
|
||||
* added to the transmission queue. Application shall wait for
|
||||
* the \ref HCI_SLIP_TX_DONE event. After HCI_SLIP_TX_DONE this
|
||||
* function can be executed for transmission of next packet.
|
||||
* @retval NRF_ERROR_INVALID_ADDR If a NULL pointer is provided.
|
||||
* @retval NRF_ERROR_INVALID_STATE Operation failure. Module is not open.
|
||||
*/
|
||||
uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length);
|
||||
|
||||
/**@brief Function for registering a receive buffer. The receive buffer will be used for storage of
|
||||
* received and SLIP decoded data.
|
||||
* No data can be received by the SLIP layer until a receive buffer has been registered.
|
||||
*
|
||||
* @note The lifetime of the buffer must be valid during complete reception of data. A static
|
||||
* buffer is recommended.
|
||||
*
|
||||
* @warning Multiple registration requests will overwrite any existing registration.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to receive buffer. The received and SLIP decoded packet
|
||||
* will be placed in this buffer.
|
||||
* @param[in] length Buffer length, in bytes.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
*/
|
||||
uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // HCI_SLIP_H__
|
||||
|
||||
/** @} */
|
||||
808
lib/sdk/components/libraries/hci/hci_transport.c
Normal file
808
lib/sdk/components/libraries/hci/hci_transport.c
Normal file
@ -0,0 +1,808 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_common.h"
|
||||
#if NRF_MODULE_ENABLED(HCI_TRANSPORT)
|
||||
#include "hci_transport.h"
|
||||
#include "hci_slip.h"
|
||||
#include "crc16.h"
|
||||
#include "hci_mem_pool.h"
|
||||
#include "app_timer.h"
|
||||
#include "app_error.h"
|
||||
#include <stdio.h>
|
||||
|
||||
#define PKT_HDR_SIZE 4u /**< Packet header size in number of bytes. */
|
||||
#define PKT_CRC_SIZE 2u /**< Packet CRC size in number of bytes. */
|
||||
#define PKT_TYPE_VENDOR_SPECIFIC 14u /**< Packet type vendor specific. */
|
||||
#define PKT_TYPE_ACK 0 /**< Packet type acknowledgement. */
|
||||
#define DATA_INTEGRITY_MASK (1u << 6u) /**< Mask for data integrity bit in the packet header. */
|
||||
#define RELIABLE_PKT_MASK (1u << 7u) /**< Mask for reliable packet bit in the packet header. */
|
||||
#define INITIAL_ACK_NUMBER_EXPECTED 1u /**< Initial acknowledge number expected. */
|
||||
#define INITIAL_ACK_NUMBER_TX INITIAL_ACK_NUMBER_EXPECTED /**< Initial acknowledge number transmitted. */
|
||||
#define INVALID_PKT_TYPE 0xFFFFFFFFu /**< Internal invalid packet type value. */
|
||||
#define HCI_UART_REG_VALUE_TO_BAUDRATE(BAUDRATE) ((BAUDRATE)/268) /**< Estimated relation between UART baudrate register value and actual baudrate */
|
||||
#define MAX_TRANSMISSION_TIME \
|
||||
(ROUNDED_DIV((HCI_MAX_PACKET_SIZE_IN_BITS * 1000u), \
|
||||
HCI_UART_REG_VALUE_TO_BAUDRATE(HCI_UART_BAUDRATE))) /**< Max transmission time of a single application packet over UART in units of mseconds. */
|
||||
#define RETRANSMISSION_TIMEOUT_IN_MS (3u * MAX_TRANSMISSION_TIME) /**< Retransmission timeout for application packet in units of mseconds. */
|
||||
#define RETRANSMISSION_TIMEOUT_IN_TICKS APP_TIMER_TICKS(RETRANSMISSION_TIMEOUT_IN_MS) /**< Retransmission timeout for application packet in units of timer ticks. */
|
||||
#define MAX_RETRY_COUNT 5u /**< Max retransmission retry count for application packets. */
|
||||
#define ACK_BUF_SIZE 5u /**< Length of module internal RX buffer which is big enough to hold an acknowledgement packet. */
|
||||
|
||||
/**@brief States of the TX state machine. */
|
||||
typedef enum
|
||||
{
|
||||
TX_STATE_IDLE, /**< State for: no application transmission packet processing in progress. */
|
||||
TX_STATE_PENDING, /**< State for: TX in progress in slip layer and TX-done event is waited for to signal the end of transmission. */
|
||||
TX_STATE_ACTIVE /**< State for: application packet has been delivered to slip for transmission and peer transport entity acknowledgement packet is waited for. */
|
||||
} tx_state_t;
|
||||
|
||||
/**@brief TX state machine events. */
|
||||
typedef enum
|
||||
{
|
||||
TX_EVENT_STATE_ENTRY, /**< Event for: state entry use case. */
|
||||
TX_EVENT_SLIP_TX_DONE, /**< Event for: HCI_SLIP_TX_DONE event use case. */
|
||||
TX_EVENT_TIMEOUT, /**< Event for: retransmission timeout use case. */
|
||||
TX_EVENT_VALID_RX_ACK /**< Event for: valid acknowledgement received for TX packet use case. */
|
||||
} tx_event_t;
|
||||
|
||||
static void tx_sm_state_change(tx_state_t new_state);
|
||||
|
||||
static tx_state_t m_tx_state; /**< Current TX state. */
|
||||
static hci_transport_tx_done_handler_t m_transport_tx_done_handle; /**< TX done event callback function. */
|
||||
static hci_transport_event_handler_t m_transport_event_handle; /**< Event handler callback function. */
|
||||
static uint8_t * mp_slip_used_rx_buffer; /**< Reference to RX buffer used by the slip layer. */
|
||||
static uint32_t m_packet_expected_seq_number; /**< Sequence number counter of the packet expected to be received . */
|
||||
static uint32_t m_packet_transmit_seq_number; /**< Sequence number counter of the transmitted packet for which acknowledgement packet is waited for. */
|
||||
static uint8_t * mp_tx_buffer; /**< Pointer to TX application buffer to be transmitted. */
|
||||
static uint32_t m_tx_buffer_length; /**< Length of application TX packet data to be transmitted in bytes. */
|
||||
static bool m_is_slip_decode_ready; /**< Boolean to determine has slip decode been completed or not. */
|
||||
APP_TIMER_DEF(m_app_timer_id); /**< Application timer id. */
|
||||
static uint32_t m_tx_retry_counter; /**< Application packet retransmission counter. */
|
||||
static hci_transport_tx_done_result_t m_tx_done_result_code; /**< TX done event callback function result code. */
|
||||
static uint8_t m_rx_ack_buffer[ACK_BUF_SIZE];/**< RX buffer big enough to hold an acknowledgement packet and which is taken in use upon receiving HCI_SLIP_RX_OVERFLOW event. */
|
||||
|
||||
|
||||
/**@brief Function for validating a received packet.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to the packet data.
|
||||
* @param[in] length Length of packet data in bytes.
|
||||
*
|
||||
* @return true if received packet is valid, false in other case.
|
||||
*/
|
||||
static bool is_rx_pkt_valid(const uint8_t * p_buffer, uint32_t length)
|
||||
{
|
||||
// Executed packet filtering algorithm order:
|
||||
// - verify packet overall length
|
||||
// - verify data integrity bit set
|
||||
// - verify reliable packet bit set
|
||||
// - verify supported packet type
|
||||
// - verify header checksum
|
||||
// - verify payload length field
|
||||
// - verify CRC
|
||||
if (length <= PKT_HDR_SIZE)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!(p_buffer[0] & DATA_INTEGRITY_MASK))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!(p_buffer[0] & RELIABLE_PKT_MASK))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
if ((p_buffer[1] & 0x0Fu) != PKT_TYPE_VENDOR_SPECIFIC)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
const uint32_t expected_checksum =
|
||||
((p_buffer[0] + p_buffer[1] + p_buffer[2] + p_buffer[3])) & 0xFFu;
|
||||
if (expected_checksum != 0)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
const uint16_t crc_calculated = crc16_compute(p_buffer, (length - PKT_CRC_SIZE), NULL);
|
||||
const uint16_t crc_received = uint16_decode(&p_buffer[length - PKT_CRC_SIZE]);
|
||||
if (crc_calculated != crc_received)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for getting the sequence number of the next reliable packet expected.
|
||||
*
|
||||
* @return sequence number of the next reliable packet expected.
|
||||
*/
|
||||
static __INLINE uint8_t packet_number_expected_get(void)
|
||||
{
|
||||
return (uint8_t) m_packet_expected_seq_number;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for calculating a packet header checksum.
|
||||
*
|
||||
* @param[in] p_hdr Pointer to the packet header.
|
||||
*
|
||||
* @return Calculated checksum.
|
||||
*/
|
||||
static uint8_t header_checksum_calculate(const uint8_t * p_hdr)
|
||||
{
|
||||
// @note: no pointer validation check needed as already checked by calling function.
|
||||
uint32_t checksum;
|
||||
|
||||
checksum = p_hdr[0];
|
||||
checksum += p_hdr[1];
|
||||
checksum += p_hdr[2];
|
||||
checksum &= 0xFFu;
|
||||
checksum = (~checksum + 1u);
|
||||
|
||||
return (uint8_t)checksum;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for writing an acknowledgment packet for transmission.
|
||||
*/
|
||||
static void ack_transmit(void)
|
||||
{
|
||||
static uint8_t ack_packet[PKT_HDR_SIZE];
|
||||
|
||||
// TX ACK packet format:
|
||||
// - Unreliable Packet type
|
||||
// - Payload Length set to 0
|
||||
// - Sequence Number set to 0
|
||||
// - Header checksum calculated
|
||||
// - Acknowledge Number set correctly
|
||||
ack_packet[0] = (packet_number_expected_get() << 3u);
|
||||
ack_packet[1] = 0;
|
||||
ack_packet[2] = 0;
|
||||
ack_packet[3] = header_checksum_calculate(ack_packet);
|
||||
|
||||
// @note: no return value check needed for hci_slip_write(...) call as acknowledgement packets
|
||||
// are considered to be from system design point of view unreliable packets.Use case where
|
||||
// underlying slip layer does not accept a packet for transmission is managed either by:
|
||||
// - acknowledged by possible future application packet as acknowledgement number header field
|
||||
// is included
|
||||
// - protocol peer entity will retransmit the packet
|
||||
UNUSED_VARIABLE(hci_slip_write(ack_packet, sizeof(ack_packet)));
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for validating a received packet.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to the packet data.
|
||||
*
|
||||
* @return sequence number field of the packet header with unrelated data masked out.
|
||||
*/
|
||||
static __INLINE uint8_t packet_seq_nmbr_extract(const uint8_t * p_buffer)
|
||||
{
|
||||
return (p_buffer[0] & 0x07u);
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for incrementing the sequence number counter for next reliable packet expected.
|
||||
*/
|
||||
static __INLINE void packet_number_expected_inc(void)
|
||||
{
|
||||
++m_packet_expected_seq_number;
|
||||
m_packet_expected_seq_number &= 0x07u;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a packet type field.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to the packet data.
|
||||
* @param[in] length Length of packet data in bytes.
|
||||
*
|
||||
* @return Packet type field or INVALID_PKT_TYPE in case of decode error.
|
||||
*/
|
||||
static __INLINE uint32_t packet_type_decode(const uint8_t * p_buffer, uint32_t length)
|
||||
{
|
||||
// @note: no pointer validation check needed as allready checked by calling function.
|
||||
uint32_t return_value;
|
||||
|
||||
if (length >= PKT_HDR_SIZE)
|
||||
{
|
||||
return_value = (p_buffer[1] & 0x0Fu);
|
||||
}
|
||||
else
|
||||
{
|
||||
return_value = INVALID_PKT_TYPE;
|
||||
}
|
||||
|
||||
return return_value;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for processing a received vendor specific packet.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to the packet data.
|
||||
* @param[in] length Length of packet data in bytes.
|
||||
*/
|
||||
static void rx_vendor_specific_pkt_type_handle(const uint8_t * p_buffer, uint32_t length)
|
||||
{
|
||||
// @note: no pointer validation check needed as allready checked by calling function.
|
||||
uint32_t err_code;
|
||||
|
||||
if (is_rx_pkt_valid(p_buffer, length))
|
||||
{
|
||||
// RX packet is valid: validate sequence number.
|
||||
const uint8_t rx_seq_number = packet_seq_nmbr_extract(p_buffer);
|
||||
if (packet_number_expected_get() == rx_seq_number)
|
||||
{
|
||||
// Sequence number is valid: transmit acknowledgement.
|
||||
packet_number_expected_inc();
|
||||
ack_transmit();
|
||||
|
||||
m_is_slip_decode_ready = true;
|
||||
|
||||
err_code = hci_mem_pool_rx_data_size_set(length);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
|
||||
err_code = hci_mem_pool_rx_produce(HCI_RX_BUF_SIZE, (void **)&mp_slip_used_rx_buffer);
|
||||
APP_ERROR_CHECK_BOOL((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NO_MEM));
|
||||
|
||||
// If memory pool RX buffer produce succeeded we register that buffer to slip layer
|
||||
// otherwise we register the internal acknowledgement buffer.
|
||||
err_code = hci_slip_rx_buffer_register(
|
||||
(err_code == NRF_SUCCESS) ? mp_slip_used_rx_buffer : m_rx_ack_buffer,
|
||||
(err_code == NRF_SUCCESS) ? HCI_RX_BUF_SIZE : ACK_BUF_SIZE);
|
||||
|
||||
APP_ERROR_CHECK(err_code);
|
||||
|
||||
if (m_transport_event_handle != NULL)
|
||||
{
|
||||
// Send application event of RX packet reception.
|
||||
const hci_transport_evt_t evt = {HCI_TRANSPORT_RX_RDY};
|
||||
m_transport_event_handle(evt);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// RX packet discarded: sequence number not valid, set the same buffer to slip layer in
|
||||
// order to avoid buffer overrun.
|
||||
err_code = hci_slip_rx_buffer_register(mp_slip_used_rx_buffer, HCI_RX_BUF_SIZE);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
|
||||
// As packet did not have expected sequence number: send acknowledgement with the
|
||||
// current expected sequence number.
|
||||
ack_transmit();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// RX packet discarded: reset the same buffer to slip layer in order to avoid buffer
|
||||
// overrun.
|
||||
err_code = hci_slip_rx_buffer_register(mp_slip_used_rx_buffer, HCI_RX_BUF_SIZE);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for getting the sequence number of a reliable TX packet for which peer protocol
|
||||
* entity acknowledgment is pending.
|
||||
*
|
||||
* @return sequence number of a reliable TX packet for which peer protocol entity acknowledgement
|
||||
* is pending.
|
||||
*/
|
||||
static __INLINE uint8_t packet_number_to_transmit_get(void)
|
||||
{
|
||||
return m_packet_transmit_seq_number;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for getting the expected acknowledgement number.
|
||||
*
|
||||
* @return expected acknowledgement number.
|
||||
*/
|
||||
static __INLINE uint8_t expected_ack_number_get(void)
|
||||
{
|
||||
uint8_t seq_nmbr = packet_number_to_transmit_get();
|
||||
++seq_nmbr;
|
||||
seq_nmbr &= 0x07u;
|
||||
|
||||
return seq_nmbr;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for processing a received acknowledgement packet.
|
||||
*
|
||||
* Verifies does the received acknowledgement packet has the expected acknowledgement number and
|
||||
* that the header checksum is correct.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to the packet data.
|
||||
*
|
||||
* @return true if valid acknowledgement packet received.
|
||||
*/
|
||||
static __INLINE bool rx_ack_pkt_type_handle(const uint8_t * p_buffer)
|
||||
{
|
||||
// @note: no pointer validation check needed as allready checked by calling function.
|
||||
|
||||
// Verify header checksum.
|
||||
const uint32_t expected_checksum =
|
||||
((p_buffer[0] + p_buffer[1] + p_buffer[2] + p_buffer[3])) & 0xFFu;
|
||||
if (expected_checksum != 0)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
const uint8_t ack_number = (p_buffer[0] >> 3u) & 0x07u;
|
||||
|
||||
// Verify expected acknowledgment number.
|
||||
return (ack_number == expected_ack_number_get());
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for incrementing the sequence number counter of the TX packet.
|
||||
*/
|
||||
static __INLINE void packet_number_tx_inc(void)
|
||||
{
|
||||
++m_packet_transmit_seq_number;
|
||||
m_packet_transmit_seq_number &= 0x07u;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for TX state machine event processing in a state centric manner.
|
||||
*
|
||||
* @param[in] event Type of event occurred.
|
||||
*/
|
||||
static void tx_sm_event_handle(tx_event_t event)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
switch (m_tx_state)
|
||||
{
|
||||
case TX_STATE_IDLE:
|
||||
if (event == TX_EVENT_STATE_ENTRY)
|
||||
{
|
||||
err_code = app_timer_stop(m_app_timer_id);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
|
||||
// Send TX-done event if registered handler exists.
|
||||
if (m_transport_tx_done_handle != NULL)
|
||||
{
|
||||
m_transport_tx_done_handle(m_tx_done_result_code);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case TX_STATE_PENDING:
|
||||
if (event == TX_EVENT_SLIP_TX_DONE)
|
||||
{
|
||||
// @note: this call should always succeed as called from HCI_SLIP_TX_DONE context
|
||||
// and error cases are managed by dedicated error event from the slip layer.
|
||||
err_code = hci_slip_write(mp_tx_buffer,
|
||||
(m_tx_buffer_length + PKT_HDR_SIZE + PKT_CRC_SIZE));
|
||||
APP_ERROR_CHECK(err_code);
|
||||
tx_sm_state_change(TX_STATE_ACTIVE);
|
||||
}
|
||||
break;
|
||||
|
||||
case TX_STATE_ACTIVE:
|
||||
switch (event)
|
||||
{
|
||||
case TX_EVENT_VALID_RX_ACK:
|
||||
// Tx sequence number counter incremented as packet transmission
|
||||
// acknowledged by peer transport entity.
|
||||
packet_number_tx_inc();
|
||||
tx_sm_state_change(TX_STATE_IDLE);
|
||||
break;
|
||||
|
||||
case TX_EVENT_STATE_ENTRY:
|
||||
m_tx_retry_counter = 0;
|
||||
err_code = app_timer_start(m_app_timer_id,
|
||||
RETRANSMISSION_TIMEOUT_IN_TICKS,
|
||||
NULL);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
break;
|
||||
|
||||
case TX_EVENT_TIMEOUT:
|
||||
if (m_tx_retry_counter != MAX_RETRY_COUNT)
|
||||
{
|
||||
++m_tx_retry_counter;
|
||||
// @note: no return value check done for hci_slip_write(...) call as current
|
||||
// system design allows use case where retransmission is not accepted by the
|
||||
// slip layer due to existing acknowledgement packet transmission in the
|
||||
// slip layer.
|
||||
UNUSED_VARIABLE(hci_slip_write(mp_tx_buffer,
|
||||
(m_tx_buffer_length +
|
||||
PKT_HDR_SIZE +
|
||||
PKT_CRC_SIZE)));
|
||||
}
|
||||
else
|
||||
{
|
||||
// Application packet retransmission count reached:
|
||||
// - set correct TX done event callback function result code
|
||||
// - execute state change
|
||||
// @note: m_tx_retry_counter is reset in TX_STATE_ACTIVE state entry.
|
||||
m_tx_done_result_code = HCI_TRANSPORT_TX_DONE_FAILURE;
|
||||
tx_sm_state_change(TX_STATE_IDLE);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
// No implementation needed.
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
// No implementation needed.
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for changing the state of the TX state machine.
|
||||
*
|
||||
* @param[in] new_state State TX state machine transits to.
|
||||
*/
|
||||
static void tx_sm_state_change(tx_state_t new_state)
|
||||
{
|
||||
m_tx_state = new_state;
|
||||
tx_sm_event_handle(TX_EVENT_STATE_ENTRY);
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for handling slip events.
|
||||
*
|
||||
* @param[in] event The event structure.
|
||||
*/
|
||||
void slip_event_handle(hci_slip_evt_t event)
|
||||
{
|
||||
uint32_t return_code;
|
||||
uint32_t err_code;
|
||||
|
||||
switch (event.evt_type)
|
||||
{
|
||||
case HCI_SLIP_TX_DONE:
|
||||
tx_sm_event_handle(TX_EVENT_SLIP_TX_DONE);
|
||||
break;
|
||||
|
||||
case HCI_SLIP_RX_RDY:
|
||||
return_code = packet_type_decode(event.packet, event.packet_length);
|
||||
|
||||
switch (return_code)
|
||||
{
|
||||
case PKT_TYPE_VENDOR_SPECIFIC:
|
||||
rx_vendor_specific_pkt_type_handle(event.packet, event.packet_length);
|
||||
break;
|
||||
|
||||
case PKT_TYPE_ACK:
|
||||
if (rx_ack_pkt_type_handle(event.packet))
|
||||
{
|
||||
// Valid expected acknowledgement packet received: set correct TX done event
|
||||
// callback function result code and execute state change.
|
||||
m_tx_done_result_code = HCI_TRANSPORT_TX_DONE_SUCCESS;
|
||||
tx_sm_event_handle(TX_EVENT_VALID_RX_ACK);
|
||||
}
|
||||
|
||||
/* fall-through */
|
||||
default:
|
||||
// RX packet dropped: reset memory buffer to slip in order to avoid RX buffer
|
||||
// overflow.
|
||||
// If existing mem pool produced RX buffer exists reuse that one. If existing
|
||||
// mem pool produced RX buffer does not exist try to produce new one. If
|
||||
// producing fails use the internal acknowledgement buffer.
|
||||
if (mp_slip_used_rx_buffer != NULL)
|
||||
{
|
||||
err_code = hci_slip_rx_buffer_register(mp_slip_used_rx_buffer, HCI_RX_BUF_SIZE);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = hci_mem_pool_rx_produce(HCI_RX_BUF_SIZE,
|
||||
(void **)&mp_slip_used_rx_buffer);
|
||||
APP_ERROR_CHECK_BOOL((err_code == NRF_SUCCESS) ||
|
||||
(err_code == NRF_ERROR_NO_MEM));
|
||||
|
||||
err_code = hci_slip_rx_buffer_register(
|
||||
(err_code == NRF_SUCCESS) ? mp_slip_used_rx_buffer : m_rx_ack_buffer,
|
||||
(err_code == NRF_SUCCESS) ? HCI_RX_BUF_SIZE : ACK_BUF_SIZE);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case HCI_SLIP_RX_OVERFLOW:
|
||||
err_code = hci_slip_rx_buffer_register(m_rx_ack_buffer, ACK_BUF_SIZE);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
break;
|
||||
|
||||
case HCI_SLIP_ERROR:
|
||||
APP_ERROR_HANDLER(event.evt_type);
|
||||
break;
|
||||
|
||||
default:
|
||||
APP_ERROR_HANDLER(event.evt_type);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
m_transport_event_handle = event_handler;
|
||||
err_code = hci_slip_evt_handler_register(slip_event_handle);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
|
||||
return (event_handler != NULL) ? NRF_SUCCESS : NRF_ERROR_NULL;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
m_transport_tx_done_handle = event_handler;
|
||||
err_code = hci_slip_evt_handler_register(slip_event_handle);
|
||||
APP_ERROR_CHECK(err_code);
|
||||
|
||||
return (event_handler != NULL) ? NRF_SUCCESS : NRF_ERROR_NULL;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for handling the application packet retransmission timeout.
|
||||
*
|
||||
* This function is registered in the @ref app_timer module when a timer is created on
|
||||
* @ref hci_transport_open.
|
||||
*
|
||||
* @note This function must be executed in APP-LO context otherwise retransmission behaviour is
|
||||
* undefined, see @ref nrf51_system_integration_serialization.
|
||||
*
|
||||
* @param[in] p_context The timeout context.
|
||||
*/
|
||||
void hci_transport_timeout_handle(void * p_context)
|
||||
{
|
||||
tx_sm_event_handle(TX_EVENT_TIMEOUT);
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_transport_open(void)
|
||||
{
|
||||
mp_tx_buffer = NULL;
|
||||
m_tx_buffer_length = 0;
|
||||
m_tx_retry_counter = 0;
|
||||
m_is_slip_decode_ready = false;
|
||||
m_tx_state = TX_STATE_IDLE;
|
||||
m_packet_expected_seq_number = INITIAL_ACK_NUMBER_EXPECTED;
|
||||
m_packet_transmit_seq_number = INITIAL_ACK_NUMBER_TX;
|
||||
m_tx_done_result_code = HCI_TRANSPORT_TX_DONE_FAILURE;
|
||||
|
||||
uint32_t err_code = app_timer_create(&m_app_timer_id,
|
||||
APP_TIMER_MODE_REPEATED,
|
||||
hci_transport_timeout_handle);
|
||||
if (err_code != NRF_SUCCESS)
|
||||
{
|
||||
// @note: conduct required interface adjustment.
|
||||
return NRF_ERROR_INTERNAL;
|
||||
}
|
||||
|
||||
err_code = hci_mem_pool_open();
|
||||
VERIFY_SUCCESS(err_code);
|
||||
|
||||
err_code = hci_slip_open();
|
||||
VERIFY_SUCCESS(err_code);
|
||||
|
||||
err_code = hci_mem_pool_rx_produce(HCI_RX_BUF_SIZE, (void **)&mp_slip_used_rx_buffer);
|
||||
if (err_code != NRF_SUCCESS)
|
||||
{
|
||||
// @note: conduct required interface adjustment.
|
||||
return NRF_ERROR_INTERNAL;
|
||||
}
|
||||
|
||||
err_code = hci_slip_rx_buffer_register(mp_slip_used_rx_buffer, HCI_RX_BUF_SIZE);
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_transport_close(void)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
m_transport_tx_done_handle = NULL;
|
||||
m_transport_event_handle = NULL;
|
||||
|
||||
err_code = hci_mem_pool_close();
|
||||
APP_ERROR_CHECK(err_code);
|
||||
err_code = hci_slip_close();
|
||||
APP_ERROR_CHECK(err_code);
|
||||
|
||||
// @note: NRF_ERROR_NO_MEM is the only return value which should never be returned.
|
||||
err_code = app_timer_stop(m_app_timer_id);
|
||||
APP_ERROR_CHECK_BOOL(err_code != NRF_ERROR_NO_MEM);
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory)
|
||||
{
|
||||
const uint32_t err_code = hci_mem_pool_tx_alloc((void **)pp_memory);
|
||||
if (err_code == NRF_SUCCESS)
|
||||
{
|
||||
// @note: no need to validate pp_memory against null as validation has already been done
|
||||
// by hci_mem_pool_tx_alloc(...) and visible to us from the method return code.
|
||||
//lint -e(413) "Likely use of null pointer"
|
||||
*pp_memory += PKT_HDR_SIZE;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_transport_tx_free(void)
|
||||
{
|
||||
return hci_mem_pool_tx_free();
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for constructing 1st byte of the packet header of the packet to be transmitted.
|
||||
*
|
||||
* @return 1st byte of the packet header of the packet to be transmitted
|
||||
*/
|
||||
static __INLINE uint8_t tx_packet_byte_zero_construct(void)
|
||||
{
|
||||
const uint32_t value = DATA_INTEGRITY_MASK |
|
||||
RELIABLE_PKT_MASK |
|
||||
(packet_number_expected_get() << 3u) |
|
||||
packet_number_to_transmit_get();
|
||||
|
||||
return (uint8_t) value;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for handling the application packet write request in tx-idle state.
|
||||
*/
|
||||
static uint32_t pkt_write_handle(void)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
// Set packet header fields.
|
||||
|
||||
mp_tx_buffer -= PKT_HDR_SIZE;
|
||||
mp_tx_buffer[0] = tx_packet_byte_zero_construct();
|
||||
|
||||
const uint16_t type_and_length_fields = ((m_tx_buffer_length << 4u) | PKT_TYPE_VENDOR_SPECIFIC);
|
||||
// @note: no use case for uint16_encode(...) return value.
|
||||
UNUSED_VARIABLE(uint16_encode(type_and_length_fields, &(mp_tx_buffer[1])));
|
||||
mp_tx_buffer[3] = header_checksum_calculate(mp_tx_buffer);
|
||||
|
||||
// Calculate, append CRC to the packet and write it.
|
||||
|
||||
const uint16_t crc = crc16_compute(mp_tx_buffer, (PKT_HDR_SIZE + m_tx_buffer_length), NULL);
|
||||
// @note: no use case for uint16_encode(...) return value.
|
||||
UNUSED_VARIABLE(uint16_encode(crc, &(mp_tx_buffer[PKT_HDR_SIZE + m_tx_buffer_length])));
|
||||
err_code = hci_slip_write(mp_tx_buffer, (m_tx_buffer_length + PKT_HDR_SIZE + PKT_CRC_SIZE));
|
||||
switch (err_code)
|
||||
{
|
||||
case NRF_SUCCESS:
|
||||
tx_sm_state_change(TX_STATE_ACTIVE);
|
||||
break;
|
||||
|
||||
case NRF_ERROR_NO_MEM:
|
||||
tx_sm_state_change(TX_STATE_PENDING);
|
||||
err_code = NRF_SUCCESS;
|
||||
break;
|
||||
|
||||
default:
|
||||
// No implementation needed.
|
||||
break;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
if (p_buffer)
|
||||
{
|
||||
switch (m_tx_state)
|
||||
{
|
||||
case TX_STATE_IDLE:
|
||||
mp_tx_buffer = (uint8_t *)p_buffer;
|
||||
m_tx_buffer_length = length;
|
||||
err_code = pkt_write_handle();
|
||||
break;
|
||||
|
||||
default:
|
||||
err_code = NRF_ERROR_NO_MEM;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_NULL;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
if (pp_buffer != NULL && p_length != NULL)
|
||||
{
|
||||
uint32_t length = 0;
|
||||
|
||||
if (m_is_slip_decode_ready)
|
||||
{
|
||||
m_is_slip_decode_ready = false;
|
||||
err_code = hci_mem_pool_rx_extract(pp_buffer, &length);
|
||||
length -= (PKT_HDR_SIZE + PKT_CRC_SIZE);
|
||||
|
||||
*p_length = (uint16_t)length;
|
||||
*pp_buffer += PKT_HDR_SIZE;
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_NO_MEM;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_NULL;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer)
|
||||
{
|
||||
return (hci_mem_pool_rx_consume(p_buffer - PKT_HDR_SIZE));
|
||||
}
|
||||
#endif //NRF_MODULE_ENABLED(HCI_TRANSPORT)
|
||||
256
lib/sdk/components/libraries/hci/hci_transport.h
Normal file
256
lib/sdk/components/libraries/hci/hci_transport.h
Normal file
@ -0,0 +1,256 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**@file
|
||||
*
|
||||
* @defgroup hci_transport HCI Transport
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief HCI transport module implementation.
|
||||
*
|
||||
* This module implements certain specific features from the three-wire UART transport layer,
|
||||
* defined by the Bluetooth specification version 4.0 [Vol 4] part D.
|
||||
*
|
||||
* \par Features supported
|
||||
* - Transmission and reception of Vendor Specific HCI packet type application packets.
|
||||
* - Transmission and reception of reliable packets: defined by chapter 6 of the specification.
|
||||
*
|
||||
* \par Features not supported
|
||||
* - Link establishment procedure: defined by chapter 8 of the specification.
|
||||
* - Low power: defined by chapter 9 of the specification.
|
||||
*
|
||||
* \par Implementation specific behaviour
|
||||
* - As Link establishment procedure is not supported following static link configuration parameters
|
||||
* are used:
|
||||
* + TX window size is 1.
|
||||
* + 16 bit CCITT-CRC must be used.
|
||||
* + Out of frame software flow control not supported.
|
||||
* + Parameters specific for resending reliable packets are compile time configurable (clarifed
|
||||
* later in this document).
|
||||
* + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for
|
||||
* transmission within same context which the corresponding application packet was received.
|
||||
*
|
||||
* \par Implementation specific limitations
|
||||
* Current implementation has the following limitations which will have impact to system wide
|
||||
* behaviour:
|
||||
* - Delayed acknowledgement scheduling not implemented:
|
||||
* There exists a possibility that acknowledgement TX packet and application TX packet will collide
|
||||
* in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX
|
||||
* pipeline which will trigger the retransmission algorithm within the peer protocol entity.
|
||||
* - Delayed retransmission scheduling not implemented:
|
||||
* There exists a possibility that retransmitted application TX packet and acknowledgement TX packet
|
||||
* will collide in the TX pipeline having the end result that retransmitted application TX packet
|
||||
* will be excluded from the TX pipeline.
|
||||
* - Processing of the acknowledgement number from RX application packets:
|
||||
* Acknowledgement number is not processed from the RX application packets having the end result
|
||||
* that unnecessary application packet retransmissions can occur.
|
||||
*
|
||||
* The application TX packet processing flow is illustrated by the statemachine below.
|
||||
*
|
||||
* @image html hci_transport_tx_sm.svg "TX - application packet statemachine"
|
||||
*
|
||||
* \par Component specific configuration options
|
||||
*
|
||||
* The following compile time configuration options are available, and used to configure the
|
||||
* application TX packet retransmission interval, in order to suite various application specific
|
||||
* implementations:
|
||||
* - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits.
|
||||
* - USED_BAUD_RATE Used uart baudrate.
|
||||
*
|
||||
* The following compile time configuration option is available to configure module specific
|
||||
* behaviour:
|
||||
* - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets.
|
||||
*/
|
||||
|
||||
#ifndef HCI_TRANSPORT_H__
|
||||
#define HCI_TRANSPORT_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include "nrf_error.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**@brief Generic event callback function events. */
|
||||
typedef enum
|
||||
{
|
||||
HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */
|
||||
HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */
|
||||
} hci_transport_evt_type_t;
|
||||
|
||||
/**@brief Struct containing events from the Transport layer.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
hci_transport_evt_type_t evt_type; /**< Type of event. */
|
||||
} hci_transport_evt_t;
|
||||
|
||||
/**@brief Transport layer generic event callback function type.
|
||||
*
|
||||
* @param[in] event Transport layer event.
|
||||
*/
|
||||
typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event);
|
||||
|
||||
/**@brief TX done event callback function result codes. */
|
||||
typedef enum
|
||||
{
|
||||
HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */
|
||||
HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */
|
||||
} hci_transport_tx_done_result_t;
|
||||
|
||||
/**@brief Transport layer TX done event callback function type.
|
||||
*
|
||||
* @param[in] result TX done event result code.
|
||||
*/
|
||||
typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result);
|
||||
|
||||
/**@brief Function for registering a generic event handler.
|
||||
*
|
||||
* @note Multiple registration requests will overwrite any possible existing registration.
|
||||
*
|
||||
* @param[in] event_handler The function to be called by the transport layer upon an event.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
* @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
|
||||
*/
|
||||
uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler);
|
||||
|
||||
/**@brief Function for registering a handler for TX done event.
|
||||
*
|
||||
* @note Multiple registration requests will overwrite any possible existing registration.
|
||||
*
|
||||
* @param[in] event_handler The function to be called by the transport layer upon TX done
|
||||
* event.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
* @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
|
||||
*/
|
||||
uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler);
|
||||
|
||||
/**@brief Function for opening the transport channel and initializing the transport layer.
|
||||
*
|
||||
* @warning Must not be called for a channel which has been allready opened.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
* @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
|
||||
*/
|
||||
uint32_t hci_transport_open(void);
|
||||
|
||||
/**@brief Function for closing the transport channel.
|
||||
*
|
||||
* @note Can be called multiple times and also for not opened channel.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
*/
|
||||
uint32_t hci_transport_close(void);
|
||||
|
||||
/**@brief Function for allocating tx packet memory.
|
||||
*
|
||||
* @param[out] pp_memory Pointer to the packet data.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success. Memory was allocated.
|
||||
* @retval NRF_ERROR_NO_MEM Operation failure. No memory available.
|
||||
* @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
|
||||
*/
|
||||
uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory);
|
||||
|
||||
/**@brief Function for freeing tx packet memory.
|
||||
*
|
||||
* @note Memory management works in FIFO principle meaning that free order must match the alloc
|
||||
* order.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success. Memory was freed.
|
||||
*/
|
||||
uint32_t hci_transport_tx_free(void);
|
||||
|
||||
/**@brief Function for writing a packet.
|
||||
*
|
||||
* @note Completion of this method does not guarantee that actual peripheral transmission would
|
||||
* have completed.
|
||||
*
|
||||
* @note In case of 0 byte packet length write request, message will consist of only transport
|
||||
* module specific headers.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue
|
||||
* and an event will be send upon transmission completion.
|
||||
* @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
|
||||
* added to the transmission queue. User should wait for
|
||||
* a appropriate event prior issuing this operation again.
|
||||
* @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit.
|
||||
* @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
|
||||
* @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open.
|
||||
*/
|
||||
uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length);
|
||||
|
||||
/**@brief Function for extracting received packet.
|
||||
*
|
||||
* @note Extracted memory can't be reused by the underlying transport layer untill freed by call to
|
||||
* hci_transport_rx_pkt_consume().
|
||||
*
|
||||
* @param[out] pp_buffer Pointer to the packet data.
|
||||
* @param[out] p_length Length of packet data in bytes.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success. Packet was extracted.
|
||||
* @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
|
||||
* @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
|
||||
*/
|
||||
uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length);
|
||||
|
||||
/**@brief Function for consuming extracted packet described by p_buffer.
|
||||
*
|
||||
* RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer.
|
||||
*
|
||||
* @param[in] p_buffer Pointer to the buffer that has been consumed.
|
||||
*
|
||||
* @retval NRF_SUCCESS Operation success.
|
||||
* @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume.
|
||||
* @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
|
||||
*/
|
||||
uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // HCI_TRANSPORT_H__
|
||||
|
||||
/** @} */
|
||||
288
lib/sdk/components/libraries/scheduler/app_scheduler.c
Normal file
288
lib/sdk/components/libraries/scheduler/app_scheduler.c
Normal file
@ -0,0 +1,288 @@
|
||||
/**
|
||||
* Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_common.h"
|
||||
#if NRF_MODULE_ENABLED(APP_SCHEDULER)
|
||||
#include "app_scheduler.h"
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include "nrf_soc.h"
|
||||
#include "nrf_assert.h"
|
||||
#include "app_util_platform.h"
|
||||
|
||||
/**@brief Structure for holding a scheduled event header. */
|
||||
typedef struct
|
||||
{
|
||||
app_sched_event_handler_t handler; /**< Pointer to event handler to receive the event. */
|
||||
uint16_t event_data_size; /**< Size of event data. */
|
||||
} event_header_t;
|
||||
|
||||
STATIC_ASSERT(sizeof(event_header_t) <= APP_SCHED_EVENT_HEADER_SIZE);
|
||||
|
||||
static event_header_t * m_queue_event_headers; /**< Array for holding the queue event headers. */
|
||||
static uint8_t * m_queue_event_data; /**< Array for holding the queue event data. */
|
||||
static volatile uint8_t m_queue_start_index; /**< Index of queue entry at the start of the queue. */
|
||||
static volatile uint8_t m_queue_end_index; /**< Index of queue entry at the end of the queue. */
|
||||
static uint16_t m_queue_event_size; /**< Maximum event size in queue. */
|
||||
static uint16_t m_queue_size; /**< Number of queue entries. */
|
||||
|
||||
#if APP_SCHEDULER_WITH_PROFILER
|
||||
static uint16_t m_max_queue_utilization; /**< Maximum observed queue utilization. */
|
||||
#endif
|
||||
|
||||
#if APP_SCHEDULER_WITH_PAUSE
|
||||
static uint32_t m_scheduler_paused_counter = 0; /**< Counter storing the difference between pausing
|
||||
and resuming the scheduler. */
|
||||
#endif
|
||||
|
||||
/**@brief Function for incrementing a queue index, and handle wrap-around.
|
||||
*
|
||||
* @param[in] index Old index.
|
||||
*
|
||||
* @return New (incremented) index.
|
||||
*/
|
||||
static __INLINE uint8_t next_index(uint8_t index)
|
||||
{
|
||||
return (index < m_queue_size) ? (index + 1) : 0;
|
||||
}
|
||||
|
||||
|
||||
static __INLINE uint8_t app_sched_queue_full()
|
||||
{
|
||||
uint8_t tmp = m_queue_start_index;
|
||||
return next_index(m_queue_end_index) == tmp;
|
||||
}
|
||||
|
||||
/**@brief Macro for checking if a queue is full. */
|
||||
#define APP_SCHED_QUEUE_FULL() app_sched_queue_full()
|
||||
|
||||
|
||||
static __INLINE uint8_t app_sched_queue_empty()
|
||||
{
|
||||
uint8_t tmp = m_queue_start_index;
|
||||
return m_queue_end_index == tmp;
|
||||
}
|
||||
|
||||
/**@brief Macro for checking if a queue is empty. */
|
||||
#define APP_SCHED_QUEUE_EMPTY() app_sched_queue_empty()
|
||||
|
||||
|
||||
uint32_t app_sched_init(uint16_t event_size, uint16_t queue_size, void * p_event_buffer)
|
||||
{
|
||||
uint16_t data_start_index = (queue_size + 1) * sizeof(event_header_t);
|
||||
|
||||
// Check that buffer is correctly aligned
|
||||
if (!is_word_aligned(p_event_buffer))
|
||||
{
|
||||
return NRF_ERROR_INVALID_PARAM;
|
||||
}
|
||||
|
||||
// Initialize event scheduler
|
||||
m_queue_event_headers = p_event_buffer;
|
||||
m_queue_event_data = &((uint8_t *)p_event_buffer)[data_start_index];
|
||||
m_queue_end_index = 0;
|
||||
m_queue_start_index = 0;
|
||||
m_queue_event_size = event_size;
|
||||
m_queue_size = queue_size;
|
||||
|
||||
#if APP_SCHEDULER_WITH_PROFILER
|
||||
m_max_queue_utilization = 0;
|
||||
#endif
|
||||
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
uint16_t app_sched_queue_space_get()
|
||||
{
|
||||
uint16_t start = m_queue_start_index;
|
||||
uint16_t end = m_queue_end_index;
|
||||
uint16_t free_space = m_queue_size - ((end >= start) ?
|
||||
(end - start) : (m_queue_size + 1 - start + end));
|
||||
return free_space;
|
||||
}
|
||||
|
||||
|
||||
#if APP_SCHEDULER_WITH_PROFILER
|
||||
static void queue_utilization_check(void)
|
||||
{
|
||||
uint16_t start = m_queue_start_index;
|
||||
uint16_t end = m_queue_end_index;
|
||||
uint16_t queue_utilization = (end >= start) ? (end - start) :
|
||||
(m_queue_size + 1 - start + end);
|
||||
|
||||
if (queue_utilization > m_max_queue_utilization)
|
||||
{
|
||||
m_max_queue_utilization = queue_utilization;
|
||||
}
|
||||
}
|
||||
|
||||
uint16_t app_sched_queue_utilization_get(void)
|
||||
{
|
||||
return m_max_queue_utilization;
|
||||
}
|
||||
#endif // APP_SCHEDULER_WITH_PROFILER
|
||||
|
||||
|
||||
uint32_t app_sched_event_put(void const * p_event_data,
|
||||
uint16_t event_data_size,
|
||||
app_sched_event_handler_t handler)
|
||||
{
|
||||
uint32_t err_code;
|
||||
|
||||
if (event_data_size <= m_queue_event_size)
|
||||
{
|
||||
uint16_t event_index = 0xFFFF;
|
||||
|
||||
CRITICAL_REGION_ENTER();
|
||||
|
||||
if (!APP_SCHED_QUEUE_FULL())
|
||||
{
|
||||
event_index = m_queue_end_index;
|
||||
m_queue_end_index = next_index(m_queue_end_index);
|
||||
|
||||
#if APP_SCHEDULER_WITH_PROFILER
|
||||
// This function call must be protected with critical region because
|
||||
// it modifies 'm_max_queue_utilization'.
|
||||
queue_utilization_check();
|
||||
#endif
|
||||
}
|
||||
|
||||
CRITICAL_REGION_EXIT();
|
||||
|
||||
if (event_index != 0xFFFF)
|
||||
{
|
||||
// NOTE: This can be done outside the critical region since the event consumer will
|
||||
// always be called from the main loop, and will thus never interrupt this code.
|
||||
m_queue_event_headers[event_index].handler = handler;
|
||||
if ((p_event_data != NULL) && (event_data_size > 0))
|
||||
{
|
||||
memcpy(&m_queue_event_data[event_index * m_queue_event_size],
|
||||
p_event_data,
|
||||
event_data_size);
|
||||
m_queue_event_headers[event_index].event_data_size = event_data_size;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_queue_event_headers[event_index].event_data_size = 0;
|
||||
}
|
||||
|
||||
err_code = NRF_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_NO_MEM;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_INVALID_LENGTH;
|
||||
}
|
||||
|
||||
return err_code;
|
||||
}
|
||||
|
||||
|
||||
#if APP_SCHEDULER_WITH_PAUSE
|
||||
void app_sched_pause(void)
|
||||
{
|
||||
CRITICAL_REGION_ENTER();
|
||||
|
||||
if (m_scheduler_paused_counter < UINT32_MAX)
|
||||
{
|
||||
m_scheduler_paused_counter++;
|
||||
}
|
||||
CRITICAL_REGION_EXIT();
|
||||
}
|
||||
|
||||
void app_sched_resume(void)
|
||||
{
|
||||
CRITICAL_REGION_ENTER();
|
||||
|
||||
if (m_scheduler_paused_counter > 0)
|
||||
{
|
||||
m_scheduler_paused_counter--;
|
||||
}
|
||||
CRITICAL_REGION_EXIT();
|
||||
}
|
||||
#endif //APP_SCHEDULER_WITH_PAUSE
|
||||
|
||||
|
||||
/**@brief Function for checking if scheduler is paused which means that should break processing
|
||||
* events.
|
||||
*
|
||||
* @return Boolean value - true if scheduler is paused, false otherwise.
|
||||
*/
|
||||
static __INLINE bool is_app_sched_paused(void)
|
||||
{
|
||||
#if APP_SCHEDULER_WITH_PAUSE
|
||||
return (m_scheduler_paused_counter > 0);
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void app_sched_execute(void)
|
||||
{
|
||||
while (!is_app_sched_paused() && !APP_SCHED_QUEUE_EMPTY())
|
||||
{
|
||||
// Since this function is only called from the main loop, there is no
|
||||
// need for a critical region here, however a special care must be taken
|
||||
// regarding update of the queue start index (see the end of the loop).
|
||||
uint16_t event_index = m_queue_start_index;
|
||||
|
||||
void * p_event_data;
|
||||
uint16_t event_data_size;
|
||||
app_sched_event_handler_t event_handler;
|
||||
|
||||
p_event_data = &m_queue_event_data[event_index * m_queue_event_size];
|
||||
event_data_size = m_queue_event_headers[event_index].event_data_size;
|
||||
event_handler = m_queue_event_headers[event_index].handler;
|
||||
|
||||
event_handler(p_event_data, event_data_size);
|
||||
|
||||
// Event processed, now it is safe to move the queue start index,
|
||||
// so the queue entry occupied by this event can be used to store
|
||||
// a next one.
|
||||
m_queue_start_index = next_index(m_queue_start_index);
|
||||
}
|
||||
}
|
||||
#endif //NRF_MODULE_ENABLED(APP_SCHEDULER)
|
||||
211
lib/sdk/components/libraries/scheduler/app_scheduler.h
Normal file
211
lib/sdk/components/libraries/scheduler/app_scheduler.h
Normal file
@ -0,0 +1,211 @@
|
||||
/**
|
||||
* Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
*
|
||||
* @defgroup app_scheduler Scheduler
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief The scheduler is used for transferring execution from the interrupt context to the main
|
||||
* context.
|
||||
*
|
||||
* @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events
|
||||
* when using the Scheduler.
|
||||
*
|
||||
* @section app_scheduler_req Requirements:
|
||||
*
|
||||
* @subsection main_context_logic Logic in main context:
|
||||
*
|
||||
* - Define an event handler for each type of event expected.
|
||||
* - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the
|
||||
* application main loop.
|
||||
* - Call app_sched_execute() from the main loop each time the application wakes up because of an
|
||||
* event (typically when sd_app_evt_wait() returns).
|
||||
*
|
||||
* @subsection int_context_logic Logic in interrupt context:
|
||||
*
|
||||
* - In the interrupt handler, call app_sched_event_put()
|
||||
* with the appropriate data and event handler. This will insert an event into the
|
||||
* scheduler's queue. The app_sched_execute() function will pull this event and call its
|
||||
* handler in the main context.
|
||||
*
|
||||
* @if (PERIPHERAL)
|
||||
* For an example usage of the scheduler, see the implementations of
|
||||
* @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard.
|
||||
* @endif
|
||||
*
|
||||
* @image html scheduler_working.svg The high level design of the scheduler
|
||||
*/
|
||||
|
||||
#ifndef APP_SCHEDULER_H__
|
||||
#define APP_SCHEDULER_H__
|
||||
|
||||
#include "sdk_config.h"
|
||||
#include <stdint.h>
|
||||
#include "app_error.h"
|
||||
#include "app_util.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */
|
||||
|
||||
/**@brief Compute number of bytes required to hold the scheduler buffer.
|
||||
*
|
||||
* @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
|
||||
* @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
|
||||
* that can be scheduled for execution).
|
||||
*
|
||||
* @return Required scheduler buffer size (in bytes).
|
||||
*/
|
||||
#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \
|
||||
(((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1))
|
||||
|
||||
/**@brief Scheduler event handler type. */
|
||||
typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size);
|
||||
|
||||
/**@brief Macro for initializing the event scheduler.
|
||||
*
|
||||
* @details It will also handle dimensioning and allocation of the memory buffer required by the
|
||||
* scheduler, making sure the buffer is correctly aligned.
|
||||
*
|
||||
* @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
|
||||
* @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
|
||||
* that can be scheduled for execution).
|
||||
*
|
||||
* @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
|
||||
* several times as long as it is from the same location, e.g. to do a reinitialization).
|
||||
*/
|
||||
#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \
|
||||
do \
|
||||
{ \
|
||||
static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \
|
||||
sizeof(uint32_t))]; \
|
||||
uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \
|
||||
APP_ERROR_CHECK(ERR_CODE); \
|
||||
} while (0)
|
||||
|
||||
/**@brief Function for initializing the Scheduler.
|
||||
*
|
||||
* @details It must be called before entering the main loop.
|
||||
*
|
||||
* @param[in] max_event_size Maximum size of events to be passed through the scheduler.
|
||||
* @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of
|
||||
* events that can be scheduled for execution).
|
||||
* @param[in] p_evt_buffer Pointer to memory buffer for holding the scheduler queue. It must
|
||||
* be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer
|
||||
* must be aligned to a 4 byte boundary.
|
||||
*
|
||||
* @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both
|
||||
* allocate the scheduler buffer, and also align the buffer correctly.
|
||||
*
|
||||
* @retval NRF_SUCCESS Successful initialization.
|
||||
* @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
|
||||
* boundary).
|
||||
*/
|
||||
uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer);
|
||||
|
||||
/**@brief Function for executing all scheduled events.
|
||||
*
|
||||
* @details This function must be called from within the main loop. It will execute all events
|
||||
* scheduled since the last time it was called.
|
||||
*/
|
||||
void app_sched_execute(void);
|
||||
|
||||
/**@brief Function for scheduling an event.
|
||||
*
|
||||
* @details Puts an event into the event queue.
|
||||
*
|
||||
* @param[in] p_event_data Pointer to event data to be scheduled.
|
||||
* @param[in] event_size Size of event data to be scheduled.
|
||||
* @param[in] handler Event handler to receive the event.
|
||||
*
|
||||
* @return NRF_SUCCESS on success, otherwise an error code.
|
||||
*/
|
||||
uint32_t app_sched_event_put(void const * p_event_data,
|
||||
uint16_t event_size,
|
||||
app_sched_event_handler_t handler);
|
||||
|
||||
/**@brief Function for getting the maximum observed queue utilization.
|
||||
*
|
||||
* Function for tuning the module and determining QUEUE_SIZE value and thus module RAM usage.
|
||||
*
|
||||
* @note @ref APP_SCHEDULER_WITH_PROFILER must be enabled to use this functionality.
|
||||
*
|
||||
* @return Maximum number of events in queue observed so far.
|
||||
*/
|
||||
uint16_t app_sched_queue_utilization_get(void);
|
||||
|
||||
/**@brief Function for getting the current amount of free space in the queue.
|
||||
*
|
||||
* @details The real amount of free space may be less if entries are being added from an interrupt.
|
||||
* To get the sxact value, this function should be called from the critical section.
|
||||
*
|
||||
* @return Amount of free space in the queue.
|
||||
*/
|
||||
uint16_t app_sched_queue_space_get(void);
|
||||
|
||||
/**@brief A function to pause the scheduler.
|
||||
*
|
||||
* @details When the scheduler is paused events are not pulled from the scheduler queue for
|
||||
* processing. The function can be called multiple times. To unblock the scheduler the
|
||||
* function @ref app_sched_resume has to be called the same number of times.
|
||||
*
|
||||
* @note @ref APP_SCHEDULER_WITH_PAUSE must be enabled to use this functionality.
|
||||
*/
|
||||
void app_sched_pause(void);
|
||||
|
||||
/**@brief A function to resume a scheduler.
|
||||
*
|
||||
* @details To unblock the scheduler this function has to be called the same number of times as
|
||||
* @ref app_sched_pause function.
|
||||
*
|
||||
* @note @ref APP_SCHEDULER_WITH_PAUSE must be enabled to use this functionality.
|
||||
*/
|
||||
void app_sched_resume(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // APP_SCHEDULER_H__
|
||||
|
||||
/** @} */
|
||||
1070
lib/sdk/components/libraries/timer/app_timer.c
Normal file
1070
lib/sdk/components/libraries/timer/app_timer.c
Normal file
File diff suppressed because it is too large
Load Diff
264
lib/sdk/components/libraries/timer/app_timer.h
Normal file
264
lib/sdk/components/libraries/timer/app_timer.h
Normal file
@ -0,0 +1,264 @@
|
||||
/**
|
||||
* Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
*
|
||||
* @defgroup app_timer Application Timer
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief Application timer functionality.
|
||||
*
|
||||
* @details This module enables the application to create multiple timer instances based on the RTC1
|
||||
* peripheral. Checking for time-outs and invocation of user time-out handlers is performed
|
||||
* in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0).
|
||||
* Both interrupt handlers are running in APP_LOW priority level.
|
||||
*
|
||||
* @details When calling app_timer_start() or app_timer_stop(), the timer operation is just queued,
|
||||
* and the software interrupt is triggered. The actual timer start/stop operation is
|
||||
* executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW,
|
||||
* if the application code calling the timer function is running in APP_LOW or APP_HIGH,
|
||||
* the timer operation will not be performed until the application handler has returned.
|
||||
* This will be the case, for example, when stopping a timer from a time-out handler when not using
|
||||
* the scheduler.
|
||||
*
|
||||
* @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the
|
||||
* @ref app_scheduler should be used or not. Even if the scheduler is
|
||||
* not used, app_timer.h will include app_scheduler.h, so when
|
||||
* compiling, app_scheduler.h must be available in one of the compiler include paths.
|
||||
*/
|
||||
|
||||
#ifndef APP_TIMER_H__
|
||||
#define APP_TIMER_H__
|
||||
#include "sdk_config.h"
|
||||
#include "app_error.h"
|
||||
#include "app_util.h"
|
||||
#include "compiler_abstraction.h"
|
||||
#include "nordic_common.h"
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */
|
||||
#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */
|
||||
|
||||
#ifdef RTX
|
||||
#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (used to allocate data). */
|
||||
#else
|
||||
#define APP_TIMER_NODE_SIZE 32 /**< Size of app_timer.timer_node_t (used to allocate data). */
|
||||
#endif // RTX
|
||||
|
||||
#define APP_TIMER_SCHED_EVENT_DATA_SIZE sizeof(app_timer_event_t) /**< Size of event data when scheduler is used. */
|
||||
|
||||
/**@brief Convert milliseconds to timer ticks.
|
||||
*
|
||||
* This macro uses 64-bit integer arithmetic, but as long as the macro parameters are
|
||||
* constants (i.e. defines), the computation will be done by the preprocessor.
|
||||
*
|
||||
* @param[in] MS Milliseconds.
|
||||
*
|
||||
* @return Number of timer ticks.
|
||||
*/
|
||||
#ifndef FREERTOS
|
||||
#define APP_TIMER_TICKS(MS) \
|
||||
((uint32_t)ROUNDED_DIV( \
|
||||
(MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, \
|
||||
1000 * (APP_TIMER_CONFIG_RTC_FREQUENCY + 1)))
|
||||
#else
|
||||
#include "FreeRTOSConfig.h"
|
||||
#define APP_TIMER_TICKS(MS) (uint32_t)ROUNDED_DIV((MS)*configTICK_RATE_HZ,1000)
|
||||
#endif
|
||||
typedef struct app_timer_t { uint32_t data[CEIL_DIV(APP_TIMER_NODE_SIZE, sizeof(uint32_t))]; } app_timer_t;
|
||||
|
||||
/**@brief Timer ID type.
|
||||
* Never declare a variable of this type, but use the macro @ref APP_TIMER_DEF instead.*/
|
||||
typedef app_timer_t * app_timer_id_t;
|
||||
|
||||
/**
|
||||
* @brief Create a timer identifier and statically allocate memory for the timer.
|
||||
*
|
||||
* @param timer_id Name of the timer identifier variable that will be used to control the timer.
|
||||
*/
|
||||
#define APP_TIMER_DEF(timer_id) \
|
||||
static app_timer_t CONCAT_2(timer_id,_data) = { {0} }; \
|
||||
static const app_timer_id_t timer_id = &CONCAT_2(timer_id,_data)
|
||||
|
||||
|
||||
/**@brief Application time-out handler type. */
|
||||
typedef void (*app_timer_timeout_handler_t)(void * p_context);
|
||||
|
||||
/**@brief Structure passed to app_scheduler. */
|
||||
typedef struct
|
||||
{
|
||||
app_timer_timeout_handler_t timeout_handler;
|
||||
void * p_context;
|
||||
} app_timer_event_t;
|
||||
|
||||
/**@brief Timer modes. */
|
||||
typedef enum
|
||||
{
|
||||
APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */
|
||||
APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */
|
||||
} app_timer_mode_t;
|
||||
|
||||
/**@brief Function for initializing the timer module.
|
||||
*
|
||||
* @retval NRF_SUCCESS If the module was initialized successfully.
|
||||
*/
|
||||
ret_code_t app_timer_init(void);
|
||||
|
||||
/**@brief Function for creating a timer instance.
|
||||
*
|
||||
* @param[in] p_timer_id Pointer to timer identifier.
|
||||
* @param[in] mode Timer mode.
|
||||
* @param[in] timeout_handler Function to be executed when the timer expires.
|
||||
*
|
||||
* @retval NRF_SUCCESS If the timer was successfully created.
|
||||
* @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid.
|
||||
* @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or
|
||||
* the timer is running.
|
||||
*
|
||||
* @note This function does the timer allocation in the caller's context. It is also not protected
|
||||
* by a critical region. Therefore care must be taken not to call it from several interrupt
|
||||
* levels simultaneously.
|
||||
* @note The function can be called again on the timer instance and will re-initialize the instance if
|
||||
* the timer is not running.
|
||||
* @attention The FreeRTOS and RTX app_timer implementation does not allow app_timer_create to
|
||||
* be called on the previously initialized instance.
|
||||
*/
|
||||
ret_code_t app_timer_create(app_timer_id_t const * p_timer_id,
|
||||
app_timer_mode_t mode,
|
||||
app_timer_timeout_handler_t timeout_handler);
|
||||
|
||||
/**@brief Function for starting a timer.
|
||||
*
|
||||
* @param[in] timer_id Timer identifier.
|
||||
* @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to time-out event
|
||||
* (minimum 5 ticks).
|
||||
* @param[in] p_context General purpose pointer. Will be passed to the time-out handler when
|
||||
* the timer expires.
|
||||
*
|
||||
* @retval NRF_SUCCESS If the timer was successfully started.
|
||||
* @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid.
|
||||
* @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or the timer
|
||||
* has not been created.
|
||||
* @retval NRF_ERROR_NO_MEM If the timer operations queue was full.
|
||||
*
|
||||
* @note The minimum timeout_ticks value is 5.
|
||||
* @note For multiple active timers, time-outs occurring in close proximity to each other (in the
|
||||
* range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks.
|
||||
* @note When calling this method on a timer that is already running, the second start operation
|
||||
* is ignored.
|
||||
*/
|
||||
ret_code_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context);
|
||||
|
||||
/**@brief Function for stopping the specified timer.
|
||||
*
|
||||
* @param[in] timer_id Timer identifier.
|
||||
*
|
||||
* @retval NRF_SUCCESS If the timer was successfully stopped.
|
||||
* @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid.
|
||||
* @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or the timer
|
||||
* has not been created.
|
||||
* @retval NRF_ERROR_NO_MEM If the timer operations queue was full.
|
||||
*/
|
||||
ret_code_t app_timer_stop(app_timer_id_t timer_id);
|
||||
|
||||
/**@brief Function for stopping all running timers.
|
||||
*
|
||||
* @retval NRF_SUCCESS If all timers were successfully stopped.
|
||||
* @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized.
|
||||
* @retval NRF_ERROR_NO_MEM If the timer operations queue was full.
|
||||
*/
|
||||
ret_code_t app_timer_stop_all(void);
|
||||
|
||||
/**@brief Function for returning the current value of the RTC1 counter.
|
||||
*
|
||||
* @return Current value of the RTC1 counter.
|
||||
*/
|
||||
uint32_t app_timer_cnt_get(void);
|
||||
|
||||
/**@brief Function for computing the difference between two RTC1 counter values.
|
||||
*
|
||||
* @param[in] ticks_to Value returned by app_timer_cnt_get().
|
||||
* @param[in] ticks_from Value returned by app_timer_cnt_get().
|
||||
*
|
||||
* @return Number of ticks from ticks_from to ticks_to.
|
||||
*/
|
||||
uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to,
|
||||
uint32_t ticks_from);
|
||||
|
||||
|
||||
/**@brief Function for getting the maximum observed operation queue utilization.
|
||||
*
|
||||
* Function for tuning the module and determining OP_QUEUE_SIZE value and thus module RAM usage.
|
||||
*
|
||||
* @note APP_TIMER_WITH_PROFILER must be enabled to use this functionality.
|
||||
*
|
||||
* @return Maximum number of events in queue observed so far.
|
||||
*/
|
||||
uint8_t app_timer_op_queue_utilization_get(void);
|
||||
|
||||
/**
|
||||
* @brief Function for pausing RTC activity which drives app_timer.
|
||||
*
|
||||
* @note This function can be used for debugging purposes to ensure
|
||||
* that application is halted when entering a breakpoint.
|
||||
*/
|
||||
void app_timer_pause(void);
|
||||
|
||||
/**
|
||||
* @brief Function for resuming RTC activity which drives app_timer.
|
||||
*
|
||||
* @note This function can be used for debugging purposes to resume
|
||||
* application activity.
|
||||
*/
|
||||
void app_timer_resume(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // APP_TIMER_H__
|
||||
|
||||
/** @} */
|
||||
167
lib/sdk/components/libraries/uart/app_uart.c
Normal file
167
lib/sdk/components/libraries/uart/app_uart.c
Normal file
@ -0,0 +1,167 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_common.h"
|
||||
#if NRF_MODULE_ENABLED(APP_UART)
|
||||
#include "app_uart.h"
|
||||
#include "nrf_drv_uart.h"
|
||||
#include "nrf_assert.h"
|
||||
|
||||
static uint8_t tx_buffer[1];
|
||||
static uint8_t rx_buffer[1];
|
||||
static volatile bool rx_done;
|
||||
static app_uart_event_handler_t m_event_handler; /**< Event handler function. */
|
||||
static nrf_drv_uart_t app_uart_inst = NRF_DRV_UART_INSTANCE(APP_UART_DRIVER_INSTANCE);
|
||||
|
||||
static void uart_event_handler(nrf_drv_uart_event_t * p_event, void* p_context)
|
||||
{
|
||||
if (p_event->type == NRF_DRV_UART_EVT_RX_DONE)
|
||||
{
|
||||
app_uart_evt_t app_uart_event;
|
||||
app_uart_event.evt_type = APP_UART_DATA;
|
||||
app_uart_event.data.value = p_event->data.rxtx.p_data[0];
|
||||
(void)nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1);
|
||||
rx_done = true;
|
||||
m_event_handler(&app_uart_event);
|
||||
}
|
||||
else if (p_event->type == NRF_DRV_UART_EVT_ERROR)
|
||||
{
|
||||
app_uart_evt_t app_uart_event;
|
||||
app_uart_event.evt_type = APP_UART_COMMUNICATION_ERROR;
|
||||
app_uart_event.data.error_communication = p_event->data.error.error_mask;
|
||||
(void)nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1);
|
||||
m_event_handler(&app_uart_event);
|
||||
}
|
||||
else if (p_event->type == NRF_DRV_UART_EVT_TX_DONE)
|
||||
{
|
||||
// Last byte from FIFO transmitted, notify the application.
|
||||
// Notify that new data is available if this was first byte put in the buffer.
|
||||
app_uart_evt_t app_uart_event;
|
||||
app_uart_event.evt_type = APP_UART_TX_EMPTY;
|
||||
m_event_handler(&app_uart_event);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params,
|
||||
app_uart_buffers_t * p_buffers,
|
||||
app_uart_event_handler_t event_handler,
|
||||
app_irq_priority_t irq_priority)
|
||||
{
|
||||
nrf_drv_uart_config_t config = NRF_DRV_UART_DEFAULT_CONFIG;
|
||||
config.baudrate = (nrf_uart_baudrate_t)p_comm_params->baud_rate;
|
||||
config.hwfc = (p_comm_params->flow_control == APP_UART_FLOW_CONTROL_DISABLED) ?
|
||||
NRF_UART_HWFC_DISABLED : NRF_UART_HWFC_ENABLED;
|
||||
config.interrupt_priority = irq_priority;
|
||||
config.parity = p_comm_params->use_parity ? NRF_UART_PARITY_INCLUDED : NRF_UART_PARITY_EXCLUDED;
|
||||
config.pselcts = p_comm_params->cts_pin_no;
|
||||
config.pselrts = p_comm_params->rts_pin_no;
|
||||
config.pselrxd = p_comm_params->rx_pin_no;
|
||||
config.pseltxd = p_comm_params->tx_pin_no;
|
||||
|
||||
m_event_handler = event_handler;
|
||||
|
||||
rx_done = false;
|
||||
|
||||
uint32_t err_code = nrf_drv_uart_init(&app_uart_inst, &config, uart_event_handler);
|
||||
VERIFY_SUCCESS(err_code);
|
||||
|
||||
// Turn on receiver if RX pin is connected
|
||||
if (p_comm_params->rx_pin_no != UART_PIN_DISCONNECTED)
|
||||
{
|
||||
#ifdef UARTE_PRESENT
|
||||
if (!config.use_easy_dma)
|
||||
#endif
|
||||
{
|
||||
nrf_drv_uart_rx_enable(&app_uart_inst);
|
||||
}
|
||||
|
||||
return nrf_drv_uart_rx(&app_uart_inst, rx_buffer,1);
|
||||
}
|
||||
else
|
||||
{
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
uint32_t app_uart_get(uint8_t * p_byte)
|
||||
{
|
||||
ASSERT(p_byte);
|
||||
uint32_t err_code = NRF_SUCCESS;
|
||||
if (rx_done)
|
||||
{
|
||||
*p_byte = rx_buffer[0];
|
||||
rx_done = false;
|
||||
}
|
||||
else
|
||||
{
|
||||
err_code = NRF_ERROR_NOT_FOUND;
|
||||
}
|
||||
return err_code;
|
||||
}
|
||||
|
||||
uint32_t app_uart_put(uint8_t byte)
|
||||
{
|
||||
tx_buffer[0] = byte;
|
||||
ret_code_t ret = nrf_drv_uart_tx(&app_uart_inst, tx_buffer, 1);
|
||||
if (NRF_ERROR_BUSY == ret)
|
||||
{
|
||||
return NRF_ERROR_NO_MEM;
|
||||
}
|
||||
else if (ret != NRF_SUCCESS)
|
||||
{
|
||||
return NRF_ERROR_INTERNAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t app_uart_flush(void)
|
||||
{
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
|
||||
uint32_t app_uart_close(void)
|
||||
{
|
||||
nrf_drv_uart_uninit(&app_uart_inst);
|
||||
return NRF_SUCCESS;
|
||||
}
|
||||
#endif //NRF_MODULE_ENABLED(APP_UART)
|
||||
262
lib/sdk/components/libraries/uart/app_uart.h
Normal file
262
lib/sdk/components/libraries/uart/app_uart.h
Normal file
@ -0,0 +1,262 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**@file
|
||||
*
|
||||
* @defgroup app_uart UART module
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief UART module interface.
|
||||
*/
|
||||
|
||||
#ifndef APP_UART_H__
|
||||
#define APP_UART_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "app_util_platform.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */
|
||||
|
||||
/**@brief UART Flow Control modes for the peripheral.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */
|
||||
APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */
|
||||
} app_uart_flow_control_t;
|
||||
|
||||
/**@brief UART communication structure holding configuration settings for the peripheral.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t rx_pin_no; /**< RX pin number. */
|
||||
uint32_t tx_pin_no; /**< TX pin number. */
|
||||
uint32_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */
|
||||
uint32_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */
|
||||
app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */
|
||||
bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */
|
||||
uint32_t baud_rate; /**< Baud rate configuration. */
|
||||
} app_uart_comm_params_t;
|
||||
|
||||
/**@brief UART buffer for transmitting/receiving data.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t * rx_buf; /**< Pointer to the RX buffer. */
|
||||
uint32_t rx_buf_size; /**< Size of the RX buffer. */
|
||||
uint8_t * tx_buf; /**< Pointer to the TX buffer. */
|
||||
uint32_t tx_buf_size; /**< Size of the TX buffer. */
|
||||
} app_uart_buffers_t;
|
||||
|
||||
/**@brief Enumeration which defines events used by the UART module upon data reception or error.
|
||||
*
|
||||
* @details The event type is used to indicate the type of additional information in the event
|
||||
* @ref app_uart_evt_t.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */
|
||||
APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */
|
||||
APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */
|
||||
APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */
|
||||
APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */
|
||||
} app_uart_evt_type_t;
|
||||
|
||||
/**@brief Struct containing events from the UART module.
|
||||
*
|
||||
* @details The app_uart_evt_t is used to notify the application of asynchronous events when data
|
||||
* are received on the UART peripheral or in case an error occured during data reception.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
app_uart_evt_type_t evt_type; /**< Type of event. */
|
||||
union
|
||||
{
|
||||
uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from nrf5x_bitfields.h can be used to parse the error code. See also the \nRFXX Series Reference Manual for specification. */
|
||||
uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
|
||||
uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
|
||||
} data;
|
||||
} app_uart_evt_t;
|
||||
|
||||
/**@brief Function for handling app_uart event callback.
|
||||
*
|
||||
* @details Upon an event in the app_uart module this callback function will be called to notify
|
||||
* the application about the event.
|
||||
*
|
||||
* @param[in] p_app_uart_event Pointer to UART event.
|
||||
*/
|
||||
typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event);
|
||||
|
||||
/**@brief Macro for safe initialization of the UART module in a single user instance when using
|
||||
* a FIFO together with UART.
|
||||
*
|
||||
* @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
|
||||
* @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO).
|
||||
* @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO).
|
||||
* @param[in] EVT_HANDLER Event handler function to be called when an event occurs in the
|
||||
* UART module.
|
||||
* @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
|
||||
* @param[out] ERR_CODE The return value of the UART initialization function will be
|
||||
* written to this parameter.
|
||||
*
|
||||
* @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow
|
||||
* control is enabled, it must only be called once.
|
||||
*/
|
||||
#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
|
||||
do \
|
||||
{ \
|
||||
app_uart_buffers_t buffers; \
|
||||
static uint8_t rx_buf[RX_BUF_SIZE]; \
|
||||
static uint8_t tx_buf[TX_BUF_SIZE]; \
|
||||
\
|
||||
buffers.rx_buf = rx_buf; \
|
||||
buffers.rx_buf_size = sizeof (rx_buf); \
|
||||
buffers.tx_buf = tx_buf; \
|
||||
buffers.tx_buf_size = sizeof (tx_buf); \
|
||||
ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO); \
|
||||
} while (0)
|
||||
|
||||
/**@brief Macro for safe initialization of the UART module in a single user instance.
|
||||
*
|
||||
* @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
|
||||
* @param[in] EVT_HANDLER Event handler function to be called when an event occurs in the
|
||||
* UART module.
|
||||
* @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
|
||||
* @param[out] ERR_CODE The return value of the UART initialization function will be
|
||||
* written to this parameter.
|
||||
*
|
||||
* @note Since this macro allocates registers the module as a GPIOTE user when flow control is
|
||||
* enabled, it must only be called once.
|
||||
*/
|
||||
#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
|
||||
do \
|
||||
{ \
|
||||
ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO); \
|
||||
} while (0)
|
||||
|
||||
/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART
|
||||
* module are needed.
|
||||
*
|
||||
*
|
||||
* @note Normally single initialization should be done using the APP_UART_INIT() or
|
||||
* APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as
|
||||
* that will allocate the buffers needed by the UART module (including aligning the buffer
|
||||
* correctly).
|
||||
|
||||
* @param[in] p_comm_params Pin and communication parameters.
|
||||
* @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used.
|
||||
* @param[in] error_handler Function to be called in case of an error.
|
||||
* @param[in] irq_priority Interrupt priority level.
|
||||
*
|
||||
* @retval NRF_SUCCESS If successful initialization.
|
||||
* @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two.
|
||||
* @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer.
|
||||
*
|
||||
* The below errors are propagated by the UART module to the caller upon registration when Hardware
|
||||
* Flow Control is enabled. When Hardware Flow Control is not used, these errors cannot occur.
|
||||
* @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering
|
||||
* the UART module as a user.
|
||||
* @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when
|
||||
* registering the UART module as a user.
|
||||
* Or the value pointed to by *p_uart_uid is not a valid
|
||||
* GPIOTE number.
|
||||
* @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users.
|
||||
*/
|
||||
uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params,
|
||||
app_uart_buffers_t * p_buffers,
|
||||
app_uart_event_handler_t error_handler,
|
||||
app_irq_priority_t irq_priority);
|
||||
|
||||
/**@brief Function for getting a byte from the UART.
|
||||
*
|
||||
* @details This function will get the next byte from the RX buffer. If the RX buffer is empty
|
||||
* an error code will be returned and the app_uart module will generate an event upon
|
||||
* reception of the first byte which is added to the RX buffer.
|
||||
*
|
||||
* @param[out] p_byte Pointer to an address where next byte received on the UART will be copied.
|
||||
*
|
||||
* @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided.
|
||||
* @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module.
|
||||
*/
|
||||
uint32_t app_uart_get(uint8_t * p_byte);
|
||||
|
||||
/**@brief Function for putting a byte on the UART.
|
||||
*
|
||||
* @details This call is non-blocking.
|
||||
*
|
||||
* @param[in] byte Byte to be transmitted on the UART.
|
||||
*
|
||||
* @retval NRF_SUCCESS If the byte was successfully put on the TX buffer for transmission.
|
||||
* @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer.
|
||||
* NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal
|
||||
* is high for a long period and the buffer fills up.
|
||||
* @retval NRF_ERROR_INTERNAL If UART driver reported error.
|
||||
*/
|
||||
uint32_t app_uart_put(uint8_t byte);
|
||||
|
||||
/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used).
|
||||
* This function does nothing if FIFO is not used.
|
||||
*
|
||||
* @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed).
|
||||
*/
|
||||
uint32_t app_uart_flush(void);
|
||||
|
||||
/**@brief Function for closing the UART module.
|
||||
*
|
||||
* @retval NRF_SUCCESS If successfully closed.
|
||||
* @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from
|
||||
* the current active user.
|
||||
*/
|
||||
uint32_t app_uart_close(void);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //APP_UART_H__
|
||||
|
||||
/** @} */
|
||||
143
lib/sdk/components/libraries/util/app_error.c
Normal file
143
lib/sdk/components/libraries/util/app_error.c
Normal file
@ -0,0 +1,143 @@
|
||||
/**
|
||||
* Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
*
|
||||
* @defgroup app_error Common application error handler
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief Common application error handler.
|
||||
*/
|
||||
|
||||
#include "nrf.h"
|
||||
#include <stdio.h>
|
||||
#include "app_error.h"
|
||||
#include "nordic_common.h"
|
||||
#include "sdk_errors.h"
|
||||
/**@brief Function for error handling, which is called when an error has occurred.
|
||||
*
|
||||
* @warning This handler is an example only and does not fit a final product. You need to analyze
|
||||
* how your product is supposed to react in case of error.
|
||||
*
|
||||
* @param[in] error_code Error code supplied to the handler.
|
||||
* @param[in] line_num Line number where the handler is called.
|
||||
* @param[in] p_file_name Pointer to the file name.
|
||||
*/
|
||||
|
||||
/*lint -save -e14 */
|
||||
void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name)
|
||||
{
|
||||
error_info_t error_info =
|
||||
{
|
||||
.line_num = line_num,
|
||||
.p_file_name = p_file_name,
|
||||
.err_code = error_code,
|
||||
};
|
||||
app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info));
|
||||
|
||||
UNUSED_VARIABLE(error_info);
|
||||
}
|
||||
|
||||
/*lint -save -e14 */
|
||||
void app_error_handler_bare(ret_code_t error_code)
|
||||
{
|
||||
error_info_t error_info =
|
||||
{
|
||||
.line_num = 0,
|
||||
.p_file_name = NULL,
|
||||
.err_code = error_code,
|
||||
};
|
||||
|
||||
app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info));
|
||||
|
||||
UNUSED_VARIABLE(error_info);
|
||||
}
|
||||
|
||||
|
||||
void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info)
|
||||
{
|
||||
/* static error variables - in order to prevent removal by optimizers */
|
||||
static volatile struct
|
||||
{
|
||||
uint32_t fault_id;
|
||||
uint32_t pc;
|
||||
uint32_t error_info;
|
||||
assert_info_t * p_assert_info;
|
||||
error_info_t * p_error_info;
|
||||
ret_code_t err_code;
|
||||
uint32_t line_num;
|
||||
const uint8_t * p_file_name;
|
||||
} m_error_data = {0};
|
||||
|
||||
// The following variable helps Keil keep the call stack visible, in addition, it can be set to
|
||||
// 0 in the debugger to continue executing code after the error check.
|
||||
volatile bool loop = true;
|
||||
UNUSED_VARIABLE(loop);
|
||||
|
||||
m_error_data.fault_id = id;
|
||||
m_error_data.pc = pc;
|
||||
m_error_data.error_info = info;
|
||||
|
||||
switch (id)
|
||||
{
|
||||
case NRF_FAULT_ID_SDK_ASSERT:
|
||||
m_error_data.p_assert_info = (assert_info_t *)info;
|
||||
m_error_data.line_num = m_error_data.p_assert_info->line_num;
|
||||
m_error_data.p_file_name = m_error_data.p_assert_info->p_file_name;
|
||||
break;
|
||||
|
||||
case NRF_FAULT_ID_SDK_ERROR:
|
||||
m_error_data.p_error_info = (error_info_t *)info;
|
||||
m_error_data.err_code = m_error_data.p_error_info->err_code;
|
||||
m_error_data.line_num = m_error_data.p_error_info->line_num;
|
||||
m_error_data.p_file_name = m_error_data.p_error_info->p_file_name;
|
||||
break;
|
||||
}
|
||||
|
||||
UNUSED_VARIABLE(m_error_data);
|
||||
|
||||
// If printing is disrupted, remove the irq calls, or set the loop variable to 0 in the debugger.
|
||||
__disable_irq();
|
||||
while (loop);
|
||||
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
/*lint -restore */
|
||||
172
lib/sdk/components/libraries/util/app_error.h
Normal file
172
lib/sdk/components/libraries/util/app_error.h
Normal file
@ -0,0 +1,172 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
*
|
||||
* @defgroup app_error Common application error handler
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief Common application error handler and macros for utilizing a common error handler.
|
||||
*/
|
||||
|
||||
#ifndef APP_ERROR_H__
|
||||
#define APP_ERROR_H__
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "sdk_errors.h"
|
||||
#include "nordic_common.h"
|
||||
#include "app_error_weak.h"
|
||||
#ifdef ANT_STACK_SUPPORT_REQD
|
||||
#include "ant_error.h"
|
||||
#endif // ANT_STACK_SUPPORT_REQD
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NRF_FAULT_ID_SDK_RANGE_START 0x00004000 /**< The start of the range of error IDs defined in the SDK. */
|
||||
|
||||
/**@defgroup APP_ERROR_FAULT_IDS Fault ID types
|
||||
* @{ */
|
||||
#define NRF_FAULT_ID_SDK_ERROR NRF_FAULT_ID_SDK_RANGE_START + 1 /**< An error stemming from a call to @ref APP_ERROR_CHECK or @ref APP_ERROR_CHECK_BOOL. The info parameter is a pointer to an @ref error_info_t variable. */
|
||||
#define NRF_FAULT_ID_SDK_ASSERT NRF_FAULT_ID_SDK_RANGE_START + 2 /**< An error stemming from a call to ASSERT (nrf_assert.h). The info parameter is a pointer to an @ref assert_info_t variable. */
|
||||
/**@} */
|
||||
|
||||
/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ERROR.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t line_num; /**< The line number where the error occurred. */
|
||||
uint8_t const * p_file_name; /**< The file in which the error occurred. */
|
||||
uint32_t err_code; /**< The error code representing the error that occurred. */
|
||||
} error_info_t;
|
||||
|
||||
/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ASSERT.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t line_num; /**< The line number where the error occurred. */
|
||||
uint8_t const * p_file_name; /**< The file in which the error occurred. */
|
||||
} assert_info_t;
|
||||
|
||||
/**@brief Function for error handling, which is called when an error has occurred.
|
||||
*
|
||||
* @param[in] error_code Error code supplied to the handler.
|
||||
* @param[in] line_num Line number where the handler is called.
|
||||
* @param[in] p_file_name Pointer to the file name.
|
||||
*/
|
||||
void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
|
||||
|
||||
/**@brief Function for error handling, which is called when an error has occurred.
|
||||
*
|
||||
* @param[in] error_code Error code supplied to the handler.
|
||||
*/
|
||||
void app_error_handler_bare(ret_code_t error_code);
|
||||
|
||||
/**@brief Function for saving the parameters and entering an eternal loop, for debug purposes.
|
||||
*
|
||||
* @param[in] id Fault identifier. See @ref NRF_FAULT_IDS.
|
||||
* @param[in] pc The program counter of the instruction that triggered the fault, or 0 if
|
||||
* unavailable.
|
||||
* @param[in] info Optional additional information regarding the fault. Refer to each fault
|
||||
* identifier for details.
|
||||
*/
|
||||
void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info);
|
||||
|
||||
|
||||
/**@brief Macro for calling error handler function.
|
||||
*
|
||||
* @param[in] ERR_CODE Error code supplied to the error handler.
|
||||
*/
|
||||
#ifdef DEBUG
|
||||
#define APP_ERROR_HANDLER(ERR_CODE) \
|
||||
do \
|
||||
{ \
|
||||
app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \
|
||||
} while (0)
|
||||
#else
|
||||
#define APP_ERROR_HANDLER(ERR_CODE) \
|
||||
do \
|
||||
{ \
|
||||
app_error_handler_bare((ERR_CODE)); \
|
||||
} while (0)
|
||||
#endif
|
||||
/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS.
|
||||
*
|
||||
* @param[in] ERR_CODE Error code supplied to the error handler.
|
||||
*/
|
||||
#define APP_ERROR_CHECK(ERR_CODE) \
|
||||
do \
|
||||
{ \
|
||||
const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \
|
||||
if (LOCAL_ERR_CODE != NRF_SUCCESS) \
|
||||
{ \
|
||||
APP_ERROR_HANDLER(LOCAL_ERR_CODE); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/**@brief Macro for calling error handler function if supplied boolean value is false.
|
||||
*
|
||||
* @param[in] BOOLEAN_VALUE Boolean value to be evaluated.
|
||||
*/
|
||||
#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \
|
||||
do \
|
||||
{ \
|
||||
const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \
|
||||
if (!LOCAL_BOOLEAN_VALUE) \
|
||||
{ \
|
||||
APP_ERROR_HANDLER(0); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // APP_ERROR_H__
|
||||
|
||||
/** @} */
|
||||
85
lib/sdk/components/libraries/util/app_error_weak.h
Normal file
85
lib/sdk/components/libraries/util/app_error_weak.h
Normal file
@ -0,0 +1,85 @@
|
||||
/**
|
||||
* Copyright (c) 2016 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef APP_ERROR_WEAK_H__
|
||||
#define APP_ERROR_WEAK_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @file
|
||||
*
|
||||
* @defgroup app_error Common application error handler
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief Common application error handler.
|
||||
*/
|
||||
|
||||
/**@brief Callback function for errors, asserts, and faults.
|
||||
*
|
||||
* @details This function is called every time an error is raised in app_error, nrf_assert, or
|
||||
* in the SoftDevice. Information about the error can be found in the @p info
|
||||
* parameter.
|
||||
*
|
||||
* See also @ref nrf_fault_handler_t for more details.
|
||||
*
|
||||
* @note The function is implemented as weak so that it can be redefined by a custom error
|
||||
* handler when needed.
|
||||
*
|
||||
* @param[in] id Fault identifier. See @ref NRF_FAULT_IDS.
|
||||
* @param[in] pc The program counter of the instruction that triggered the fault, or 0 if
|
||||
* unavailable.
|
||||
* @param[in] info Optional additional information regarding the fault. The value of the @p id
|
||||
* parameter dictates how to interpret this parameter. Refer to the documentation
|
||||
* for each fault identifier (@ref NRF_FAULT_IDS and @ref APP_ERROR_FAULT_IDS) for
|
||||
* details about interpreting @p info.
|
||||
*/
|
||||
void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info);
|
||||
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // APP_ERROR_WEAK_H__
|
||||
1082
lib/sdk/components/libraries/util/app_util.h
Normal file
1082
lib/sdk/components/libraries/util/app_util.h
Normal file
File diff suppressed because it is too large
Load Diff
449
lib/sdk/components/libraries/util/app_util_bds.h
Normal file
449
lib/sdk/components/libraries/util/app_util_bds.h
Normal file
@ -0,0 +1,449 @@
|
||||
/**
|
||||
* Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
*
|
||||
* @defgroup app_util Utility Functions and Definitions
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief Various types and definitions available to all applications.
|
||||
*/
|
||||
|
||||
#ifndef APP_UTIL_BDS_H__
|
||||
#define APP_UTIL_BDS_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdbool.h>
|
||||
#include "compiler_abstraction.h"
|
||||
#include "app_util.h"
|
||||
#include "ble_srv_common.h"
|
||||
#include "nordic_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef uint8_t nibble_t;
|
||||
typedef uint32_t uint24_t;
|
||||
typedef uint64_t uint40_t;
|
||||
|
||||
/**@brief IEEE 11073-20601 Regulatory Certification Data List Structure */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t * p_list; /**< Pointer the byte array containing the encoded opaque structure based on IEEE 11073-20601 specification. */
|
||||
uint8_t list_len; /**< Length of the byte array. */
|
||||
} regcertdatalist_t;
|
||||
|
||||
/**@brief SFLOAT format (IEEE-11073 16-bit FLOAT, meaning 4 bits for exponent (base 10) and 12 bits mantissa) */
|
||||
typedef struct
|
||||
{
|
||||
int8_t exponent; /**< Base 10 exponent, should be using only 4 bits */
|
||||
int16_t mantissa; /**< Mantissa, should be using only 12 bits */
|
||||
} sfloat_t;
|
||||
|
||||
/**@brief Date and Time structure. */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t year;
|
||||
uint8_t month;
|
||||
uint8_t day;
|
||||
uint8_t hours;
|
||||
uint8_t minutes;
|
||||
uint8_t seconds;
|
||||
} ble_date_time_t;
|
||||
|
||||
|
||||
/**@brief Function for encoding a uint16 value.
|
||||
*
|
||||
* @param[in] p_value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
*
|
||||
* @return Number of bytes written.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint16_encode(const uint16_t * p_value, uint8_t * p_encoded_data)
|
||||
{
|
||||
p_encoded_data[0] = (uint8_t) ((*p_value & 0x00FF) >> 0);
|
||||
p_encoded_data[1] = (uint8_t) ((*p_value & 0xFF00) >> 8);
|
||||
return sizeof(uint16_t);
|
||||
}
|
||||
|
||||
static __INLINE uint8_t bds_int16_encode(const int16_t * p_value, uint8_t * p_encoded_data)
|
||||
{
|
||||
uint16_t tmp = *p_value;
|
||||
return bds_uint16_encode(&tmp, p_encoded_data);
|
||||
}
|
||||
|
||||
/**@brief Function for encoding a uint24 value.
|
||||
*
|
||||
* @param[in] p_value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
*
|
||||
* @return Number of bytes written.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint24_encode(const uint32_t * p_value, uint8_t * p_encoded_data)
|
||||
{
|
||||
p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0);
|
||||
p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8);
|
||||
p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16);
|
||||
return (3);
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for encoding a uint32 value.
|
||||
*
|
||||
* @param[in] p_value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
*
|
||||
* @return Number of bytes written.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint32_encode(const uint32_t * p_value, uint8_t * p_encoded_data)
|
||||
{
|
||||
p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0);
|
||||
p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8);
|
||||
p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16);
|
||||
p_encoded_data[3] = (uint8_t) ((*p_value & 0xFF000000) >> 24);
|
||||
return sizeof(uint32_t);
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for encoding a uint40 value.
|
||||
*
|
||||
* @param[in] p_value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
*
|
||||
* @return Number of bytes written.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint40_encode(const uint64_t * p_value, uint8_t * p_encoded_data)
|
||||
{
|
||||
p_encoded_data[0] = (uint8_t) ((*p_value & 0x00000000000000FF) >> 0);
|
||||
p_encoded_data[1] = (uint8_t) ((*p_value & 0x000000000000FF00) >> 8);
|
||||
p_encoded_data[2] = (uint8_t) ((*p_value & 0x0000000000FF0000) >> 16);
|
||||
p_encoded_data[3] = (uint8_t) ((*p_value & 0x00000000FF000000) >> 24);
|
||||
p_encoded_data[4] = (uint8_t) ((*p_value & 0x000000FF00000000) >> 32);
|
||||
return 5;
|
||||
}
|
||||
|
||||
/**@brief Function for encoding a sfloat value.
|
||||
*
|
||||
* @param[in] p_value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
*
|
||||
* @return Number of bytes written.
|
||||
*/
|
||||
static __INLINE uint8_t bds_sfloat_encode(const sfloat_t * p_value, uint8_t * p_encoded_data)
|
||||
{
|
||||
uint16_t encoded_val;
|
||||
|
||||
encoded_val = ((p_value->exponent << 12) & 0xF000) |
|
||||
((p_value->mantissa << 0) & 0x0FFF);
|
||||
|
||||
return(bds_uint16_encode(&encoded_val, p_encoded_data));
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for encoding a uint8_array value.
|
||||
*
|
||||
* @param[in] p_value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint8_array_encode(const uint8_array_t * p_value,
|
||||
uint8_t * p_encoded_data)
|
||||
{
|
||||
memcpy(p_encoded_data, p_value->p_data, p_value->size);
|
||||
return p_value->size;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for encoding a utf8_str value.
|
||||
*
|
||||
* @param[in] p_value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
|
||||
*/
|
||||
static __INLINE uint8_t bds_ble_srv_utf8_str_encode(const ble_srv_utf8_str_t * p_value,
|
||||
uint8_t * p_encoded_data)
|
||||
{
|
||||
memcpy(p_encoded_data, p_value->p_str, p_value->length);
|
||||
return p_value->length;
|
||||
}
|
||||
|
||||
/**@brief Function for encoding a regcertdatalist value.
|
||||
*
|
||||
* @param[in] p_value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
|
||||
*/
|
||||
static __INLINE uint8_t bds_regcertdatalist_encode(const regcertdatalist_t * p_value,
|
||||
uint8_t * p_encoded_data)
|
||||
{
|
||||
memcpy(p_encoded_data, p_value->p_list, p_value->list_len);
|
||||
return p_value->list_len;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a date_time value.
|
||||
*
|
||||
* @param[in] p_date_time pointer to the date_time structure to encode.
|
||||
* @param[in] p_encoded_data pointer to the encoded data
|
||||
* @return length of the encoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_ble_date_time_encode(const ble_date_time_t * p_date_time,
|
||||
uint8_t * p_encoded_data)
|
||||
{
|
||||
uint8_t len = bds_uint16_encode(&p_date_time->year, &p_encoded_data[0]);
|
||||
|
||||
p_encoded_data[len++] = p_date_time->month;
|
||||
p_encoded_data[len++] = p_date_time->day;
|
||||
p_encoded_data[len++] = p_date_time->hours;
|
||||
p_encoded_data[len++] = p_date_time->minutes;
|
||||
p_encoded_data[len++] = p_date_time->seconds;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a uint16 value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_decoded_val pointer to the decoded value
|
||||
* @return length of the decoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint16_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
uint16_t * p_decoded_val)
|
||||
{
|
||||
UNUSED_VARIABLE(len);
|
||||
*p_decoded_val = (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
|
||||
(((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 );
|
||||
return (sizeof(uint16_t));
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a int16 value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_decoded_val pointer to the decoded value
|
||||
* @return length of the decoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_int16_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
int16_t * p_decoded_val)
|
||||
{
|
||||
UNUSED_VARIABLE(len);
|
||||
uint16_t tmp = 0;
|
||||
uint8_t retval = bds_uint16_decode(len, p_encoded_data, &tmp);
|
||||
*p_decoded_val = (int16_t)tmp;
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a uint24 value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_decoded_val pointer to the decoded value
|
||||
*
|
||||
* @return length of the decoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint24_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
uint32_t * p_decoded_val)
|
||||
{
|
||||
UNUSED_VARIABLE(len);
|
||||
*p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) |
|
||||
(((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) |
|
||||
(((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16);
|
||||
return (3);
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a uint32 value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_decoded_val pointer to the decoded value
|
||||
*
|
||||
* @return length of the decoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint32_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
uint32_t * p_decoded_val)
|
||||
{
|
||||
UNUSED_VARIABLE(len);
|
||||
*p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) |
|
||||
(((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) |
|
||||
(((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
|
||||
(((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 );
|
||||
return (sizeof(uint32_t));
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a uint40 value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_decoded_val pointer to the decoded value
|
||||
*
|
||||
* @return length of the decoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint40_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
uint64_t * p_decoded_val)
|
||||
{
|
||||
UNUSED_VARIABLE(len);
|
||||
*p_decoded_val = (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0) |
|
||||
(((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8) |
|
||||
(((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) |
|
||||
(((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24 )|
|
||||
(((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32 );
|
||||
return (40);
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a sfloat value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_decoded_val pointer to the decoded value
|
||||
*
|
||||
* @return length of the decoded field.
|
||||
|
||||
*/
|
||||
static __INLINE uint8_t bds_sfloat_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
sfloat_t * p_decoded_val)
|
||||
{
|
||||
|
||||
p_decoded_val->exponent = 0;
|
||||
bds_uint16_decode(len, p_encoded_data, (uint16_t*)&p_decoded_val->mantissa);
|
||||
p_decoded_val->exponent = (uint8_t)((p_decoded_val->mantissa & 0xF000) >> 12);
|
||||
p_decoded_val->mantissa &= 0x0FFF;
|
||||
return len;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a uint8_array value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_decoded_val pointer to the decoded value
|
||||
*
|
||||
* @return length of the decoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_uint8_array_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
uint8_array_t * p_decoded_val)
|
||||
{
|
||||
memcpy(p_decoded_val->p_data, p_encoded_data, len);
|
||||
p_decoded_val->size = len;
|
||||
return p_decoded_val->size;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a utf8_str value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_decoded_val pointer to the decoded value
|
||||
*
|
||||
* @return length of the decoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_ble_srv_utf8_str_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
ble_srv_utf8_str_t * p_decoded_val)
|
||||
{
|
||||
p_decoded_val->p_str = (uint8_t*)p_encoded_data;
|
||||
p_decoded_val->length = len;
|
||||
return p_decoded_val->length;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a regcertdatalist value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_decoded_val pointer to the decoded value
|
||||
*
|
||||
* @return length of the decoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_regcertdatalist_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
regcertdatalist_t * p_decoded_val)
|
||||
{
|
||||
memcpy(p_decoded_val->p_list, p_encoded_data, len);
|
||||
p_decoded_val->list_len = len;
|
||||
return p_decoded_val->list_len;
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for decoding a date_time value.
|
||||
*
|
||||
* @param[in] len length of the field to be decoded.
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
* @param[in] p_date_time pointer to the decoded value
|
||||
*
|
||||
* @return length of the decoded field.
|
||||
*/
|
||||
static __INLINE uint8_t bds_ble_date_time_decode(const uint8_t len,
|
||||
const uint8_t * p_encoded_data,
|
||||
ble_date_time_t * p_date_time)
|
||||
{
|
||||
UNUSED_VARIABLE(len);
|
||||
uint8_t pos = bds_uint16_decode(len, &p_encoded_data[0], &p_date_time->year);
|
||||
p_date_time->month = p_encoded_data[pos++];
|
||||
p_date_time->day = p_encoded_data[pos++];
|
||||
p_date_time->hours = p_encoded_data[pos++];
|
||||
p_date_time->minutes = p_encoded_data[pos++];
|
||||
p_date_time->seconds = p_encoded_data[pos++];
|
||||
|
||||
return pos;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // APP_UTIL_BDS_H__
|
||||
|
||||
/** @} */
|
||||
127
lib/sdk/components/libraries/util/app_util_platform.c
Normal file
127
lib/sdk/components/libraries/util/app_util_platform.c
Normal file
@ -0,0 +1,127 @@
|
||||
/**
|
||||
* Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "app_util_platform.h"
|
||||
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
/* Global nvic state instance, required by nrf_nvic.h */
|
||||
nrf_nvic_state_t nrf_nvic_state;
|
||||
#endif
|
||||
|
||||
static uint32_t m_in_critical_region = 0;
|
||||
|
||||
void app_util_disable_irq(void)
|
||||
{
|
||||
__disable_irq();
|
||||
m_in_critical_region++;
|
||||
}
|
||||
|
||||
void app_util_enable_irq(void)
|
||||
{
|
||||
m_in_critical_region--;
|
||||
if (m_in_critical_region == 0)
|
||||
{
|
||||
__enable_irq();
|
||||
}
|
||||
}
|
||||
|
||||
void app_util_critical_region_enter(uint8_t *p_nested)
|
||||
{
|
||||
#if __CORTEX_M == (0x04U)
|
||||
ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
|
||||
#endif
|
||||
|
||||
#if defined(SOFTDEVICE_PRESENT)
|
||||
/* return value can be safely ignored */
|
||||
(void) sd_nvic_critical_region_enter(p_nested);
|
||||
#else
|
||||
app_util_disable_irq();
|
||||
#endif
|
||||
}
|
||||
|
||||
void app_util_critical_region_exit(uint8_t nested)
|
||||
{
|
||||
#if __CORTEX_M == (0x04U)
|
||||
ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
|
||||
#endif
|
||||
|
||||
#if defined(SOFTDEVICE_PRESENT)
|
||||
/* return value can be safely ignored */
|
||||
(void) sd_nvic_critical_region_exit(nested);
|
||||
#else
|
||||
app_util_enable_irq();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
uint8_t privilege_level_get(void)
|
||||
{
|
||||
#if __CORTEX_M == (0x00U) || defined(_WIN32) || defined(__unix) || defined(__APPLE__)
|
||||
/* the Cortex-M0 has no concept of privilege */
|
||||
return APP_LEVEL_PRIVILEGED;
|
||||
#elif __CORTEX_M == (0x04U)
|
||||
uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ;
|
||||
if (0 == isr_vector_num)
|
||||
{
|
||||
/* Thread Mode, check nPRIV */
|
||||
int32_t control = __get_CONTROL();
|
||||
return control & CONTROL_nPRIV_Msk ? APP_LEVEL_UNPRIVILEGED : APP_LEVEL_PRIVILEGED;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Handler Mode, always privileged */
|
||||
return APP_LEVEL_PRIVILEGED;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
uint8_t current_int_priority_get(void)
|
||||
{
|
||||
uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ;
|
||||
if (isr_vector_num > 0)
|
||||
{
|
||||
int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET);
|
||||
return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF);
|
||||
}
|
||||
else
|
||||
{
|
||||
return APP_IRQ_PRIORITY_THREAD;
|
||||
}
|
||||
}
|
||||
262
lib/sdk/components/libraries/util/app_util_platform.h
Normal file
262
lib/sdk/components/libraries/util/app_util_platform.h
Normal file
@ -0,0 +1,262 @@
|
||||
/**
|
||||
* Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**@file
|
||||
*
|
||||
* @defgroup app_util_platform Utility Functions and Definitions (Platform)
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief Various types and definitions available to all applications when using SoftDevice.
|
||||
*/
|
||||
|
||||
#ifndef APP_UTIL_PLATFORM_H__
|
||||
#define APP_UTIL_PLATFORM_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include "compiler_abstraction.h"
|
||||
#include "nrf.h"
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
#include "nrf_soc.h"
|
||||
#include "nrf_nvic.h"
|
||||
#endif
|
||||
#include "nrf_assert.h"
|
||||
#include "app_error.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if __CORTEX_M == (0x00U)
|
||||
#define _PRIO_SD_HIGH 0
|
||||
#define _PRIO_APP_HIGH 1
|
||||
#define _PRIO_APP_MID 1
|
||||
#define _PRIO_SD_LOW 2
|
||||
#define _PRIO_APP_LOW 3
|
||||
#define _PRIO_APP_LOWEST 3
|
||||
#define _PRIO_THREAD 4
|
||||
#elif __CORTEX_M == (0x04U)
|
||||
#define _PRIO_SD_HIGH 0
|
||||
#define _PRIO_SD_MID 1
|
||||
#define _PRIO_APP_HIGH 2
|
||||
#define _PRIO_APP_MID 3
|
||||
#define _PRIO_SD_LOW 4
|
||||
#define _PRIO_SD_LOWEST 5
|
||||
#define _PRIO_APP_LOW 6
|
||||
#define _PRIO_APP_LOWEST 7
|
||||
#define _PRIO_THREAD 15
|
||||
#else
|
||||
#error "No platform defined"
|
||||
#endif
|
||||
|
||||
|
||||
//lint -save -e113 -e452
|
||||
/**@brief The interrupt priorities available to the application while the SoftDevice is active. */
|
||||
typedef enum
|
||||
{
|
||||
#ifndef SOFTDEVICE_PRESENT
|
||||
APP_IRQ_PRIORITY_HIGHEST = _PRIO_SD_HIGH,
|
||||
#else
|
||||
APP_IRQ_PRIORITY_HIGHEST = _PRIO_APP_HIGH,
|
||||
#endif
|
||||
APP_IRQ_PRIORITY_HIGH = _PRIO_APP_HIGH,
|
||||
#ifndef SOFTDEVICE_PRESENT
|
||||
APP_IRQ_PRIORITY_MID = _PRIO_SD_LOW,
|
||||
#else
|
||||
APP_IRQ_PRIORITY_MID = _PRIO_APP_MID,
|
||||
#endif
|
||||
APP_IRQ_PRIORITY_LOW = _PRIO_APP_LOW,
|
||||
APP_IRQ_PRIORITY_LOWEST = _PRIO_APP_LOWEST,
|
||||
APP_IRQ_PRIORITY_THREAD = _PRIO_THREAD /**< "Interrupt level" when running in Thread Mode. */
|
||||
} app_irq_priority_t;
|
||||
//lint -restore
|
||||
|
||||
|
||||
/*@brief The privilege levels available to applications in Thread Mode */
|
||||
typedef enum
|
||||
{
|
||||
APP_LEVEL_UNPRIVILEGED,
|
||||
APP_LEVEL_PRIVILEGED
|
||||
} app_level_t;
|
||||
|
||||
/**@cond NO_DOXYGEN */
|
||||
#define EXTERNAL_INT_VECTOR_OFFSET 16
|
||||
/**@endcond */
|
||||
|
||||
/**@brief Macro for setting a breakpoint.
|
||||
*/
|
||||
#if defined(__GNUC__)
|
||||
#define NRF_BREAKPOINT __builtin_trap()
|
||||
#else
|
||||
#define NRF_BREAKPOINT __BKPT(0)
|
||||
#endif
|
||||
|
||||
/** @brief Macro for setting a breakpoint.
|
||||
*
|
||||
* If it is possible to detect debugger presence then it is set only in that case.
|
||||
*
|
||||
*/
|
||||
#if __CORTEX_M == 0x04
|
||||
#define NRF_BREAKPOINT_COND do { \
|
||||
/* C_DEBUGEN == 1 -> Debugger Connected */ \
|
||||
if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) \
|
||||
{ \
|
||||
/* Generate breakpoint if debugger is connected */ \
|
||||
NRF_BREAKPOINT; \
|
||||
} \
|
||||
}while (0)
|
||||
#else
|
||||
#define NRF_BREAKPOINT_COND NRF_BREAKPOINT
|
||||
#endif // __CORTEX_M == 0x04
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define PACKED(TYPE) __packed TYPE
|
||||
#define PACKED_STRUCT PACKED(struct)
|
||||
#elif defined ( __GNUC__ )
|
||||
#define PACKED __attribute__((packed))
|
||||
#define PACKED_STRUCT struct PACKED
|
||||
#elif defined (__ICCARM__)
|
||||
#define PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
|
||||
void app_util_critical_region_enter (uint8_t *p_nested);
|
||||
void app_util_critical_region_exit (uint8_t nested);
|
||||
|
||||
/**@brief Macro for entering a critical region.
|
||||
*
|
||||
* @note Due to implementation details, there must exist one and only one call to
|
||||
* CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
|
||||
* in the same scope.
|
||||
*/
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
#define CRITICAL_REGION_ENTER() \
|
||||
{ \
|
||||
uint8_t __CR_NESTED = 0; \
|
||||
app_util_critical_region_enter(&__CR_NESTED);
|
||||
#else
|
||||
#define CRITICAL_REGION_ENTER() app_util_critical_region_enter(NULL)
|
||||
#endif
|
||||
|
||||
/**@brief Macro for leaving a critical region.
|
||||
*
|
||||
* @note Due to implementation details, there must exist one and only one call to
|
||||
* CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
|
||||
* in the same scope.
|
||||
*/
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
#define CRITICAL_REGION_EXIT() \
|
||||
app_util_critical_region_exit(__CR_NESTED); \
|
||||
}
|
||||
#else
|
||||
#define CRITICAL_REGION_EXIT() app_util_critical_region_exit(0)
|
||||
#endif
|
||||
|
||||
/* Workaround for Keil 4 */
|
||||
#ifndef IPSR_ISR_Msk
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/**@brief Macro to enable anonymous unions from a certain point in the code.
|
||||
*/
|
||||
#if defined(__CC_ARM)
|
||||
#define ANON_UNIONS_ENABLE _Pragma("push") \
|
||||
_Pragma("anon_unions")
|
||||
#elif defined(__ICCARM__)
|
||||
#define ANON_UNIONS_ENABLE _Pragma("language=extended")
|
||||
#else
|
||||
#define ANON_UNIONS_ENABLE
|
||||
// No action will be taken.
|
||||
// For GCC anonymous unions are enabled by default.
|
||||
#endif
|
||||
|
||||
/**@brief Macro to disable anonymous unions from a certain point in the code.
|
||||
* @note Call only after first calling @ref ANON_UNIONS_ENABLE.
|
||||
*/
|
||||
#if defined(__CC_ARM)
|
||||
#define ANON_UNIONS_DISABLE _Pragma("pop")
|
||||
#elif defined(__ICCARM__)
|
||||
#define ANON_UNIONS_DISABLE
|
||||
// for IAR leave anonymous unions enabled
|
||||
#else
|
||||
#define ANON_UNIONS_DISABLE
|
||||
// No action will be taken.
|
||||
// For GCC anonymous unions are enabled by default.
|
||||
#endif
|
||||
|
||||
/**@brief Macro for adding pragma directive only for GCC.
|
||||
*/
|
||||
#ifdef __GNUC__
|
||||
#define GCC_PRAGMA(v) _Pragma(v)
|
||||
#else
|
||||
#define GCC_PRAGMA(v)
|
||||
#endif
|
||||
|
||||
/* Workaround for Keil 4 */
|
||||
#ifndef CONTROL_nPRIV_Msk
|
||||
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
|
||||
#endif
|
||||
|
||||
/**@brief Function for finding the current interrupt level.
|
||||
*
|
||||
* @return Current interrupt level.
|
||||
* @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level.
|
||||
* @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level.
|
||||
* @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode.
|
||||
*/
|
||||
uint8_t current_int_priority_get(void);
|
||||
|
||||
|
||||
/**@brief Function for finding out the current privilege level.
|
||||
*
|
||||
* @return Current privilege level.
|
||||
* @retval APP_LEVEL_UNPRIVILEGED We are running in unprivileged level.
|
||||
* @retval APP_LEVEL_PRIVILEGED We are running in privileged level.
|
||||
*/
|
||||
uint8_t privilege_level_get(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // APP_UTIL_PLATFORM_H__
|
||||
|
||||
/** @} */
|
||||
211
lib/sdk/components/libraries/util/nordic_common.h
Normal file
211
lib/sdk/components/libraries/util/nordic_common.h
Normal file
@ -0,0 +1,211 @@
|
||||
/**
|
||||
* Copyright (c) 2008 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
* @brief Common defines and macros for firmware developed by Nordic Semiconductor.
|
||||
*/
|
||||
|
||||
#ifndef NORDIC_COMMON_H__
|
||||
#define NORDIC_COMMON_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Check if selected module is enabled
|
||||
*
|
||||
* This is save function for driver enable checking.
|
||||
* Correct from Lint point of view (not using default of undefined value).
|
||||
*
|
||||
* Usage:
|
||||
* @code
|
||||
#if NRF_MODULE_ENABLED(UART)
|
||||
...
|
||||
#endif
|
||||
* @endcode
|
||||
*
|
||||
* @param module The module name.
|
||||
*
|
||||
* @retval 1 The macro <module>_ENABLE is defined and is non-zero.
|
||||
* @retval 0 The macro <module>_ENABLE is not defined or it equals zero.
|
||||
*
|
||||
* @note
|
||||
* This macro intentionally does not implement second expansion level.
|
||||
* The name of the module to be checked has to be given directly as a parameter.
|
||||
* And given parameter would be connected with @c _ENABLED postfix directly
|
||||
* without evaluating its value.
|
||||
*/
|
||||
//lint -emacro(491,NRF_MODULE_ENABLED) // Suppers warning 491 "non-standard use of 'defined' preprocessor operator"
|
||||
#define NRF_MODULE_ENABLED(module) \
|
||||
((defined(module ## _ENABLED) && (module ## _ENABLED)) ? 1 : 0)
|
||||
|
||||
/** The upper 8 bits of a 32 bit value */
|
||||
//lint -emacro(572,MSB_32) // Suppress warning 572 "Excessive shift value"
|
||||
#define MSB_32(a) (((a) & 0xFF000000) >> 24)
|
||||
/** The lower 8 bits (of a 32 bit value) */
|
||||
#define LSB_32(a) ((a) & 0x000000FF)
|
||||
|
||||
/** The upper 8 bits of a 16 bit value */
|
||||
//lint -emacro(572,MSB_16) // Suppress warning 572 "Excessive shift value"
|
||||
#define MSB_16(a) (((a) & 0xFF00) >> 8)
|
||||
/** The lower 8 bits (of a 16 bit value) */
|
||||
#define LSB_16(a) ((a) & 0x00FF)
|
||||
|
||||
/** Leaves the minimum of the two 32-bit arguments */
|
||||
/*lint -emacro(506, MIN) */ /* Suppress "Constant value Boolean */
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
/** Leaves the maximum of the two 32-bit arguments */
|
||||
/*lint -emacro(506, MAX) */ /* Suppress "Constant value Boolean */
|
||||
#define MAX(a, b) ((a) < (b) ? (b) : (a))
|
||||
|
||||
/**@brief Concatenates two parameters.
|
||||
*
|
||||
* It realizes two level expansion to make it sure that all the parameters
|
||||
* are actually expanded before gluing them together.
|
||||
*
|
||||
* @param p1 First parameter to concatenating
|
||||
* @param p2 Second parameter to concatenating
|
||||
*
|
||||
* @return Two parameters glued together.
|
||||
* They have to create correct C mnemonic in other case
|
||||
* preprocessor error would be generated.
|
||||
*
|
||||
* @sa CONCAT_3
|
||||
*/
|
||||
#define CONCAT_2(p1, p2) CONCAT_2_(p1, p2)
|
||||
/** Auxiliary macro used by @ref CONCAT_2 */
|
||||
#define CONCAT_2_(p1, p2) p1##p2
|
||||
|
||||
/**@brief Concatenates three parameters.
|
||||
*
|
||||
* It realizes two level expansion to make it sure that all the parameters
|
||||
* are actually expanded before gluing them together.
|
||||
*
|
||||
* @param p1 First parameter to concatenating
|
||||
* @param p2 Second parameter to concatenating
|
||||
* @param p3 Third parameter to concatenating
|
||||
*
|
||||
* @return Three parameters glued together.
|
||||
* They have to create correct C mnemonic in other case
|
||||
* preprocessor error would be generated.
|
||||
*
|
||||
* @sa CONCAT_2
|
||||
*/
|
||||
#define CONCAT_3(p1, p2, p3) CONCAT_3_(p1, p2, p3)
|
||||
/** Auxiliary macro used by @ref CONCAT_3 */
|
||||
#define CONCAT_3_(p1, p2, p3) p1##p2##p3
|
||||
|
||||
#define STRINGIFY_(val) #val
|
||||
/** Converts a macro argument into a character constant.
|
||||
*/
|
||||
#define STRINGIFY(val) STRINGIFY_(val)
|
||||
|
||||
/** Counts number of elements inside the array
|
||||
*/
|
||||
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
|
||||
|
||||
/**@brief Set a bit in the uint32 word.
|
||||
*
|
||||
* @param[in] W Word whose bit is being set.
|
||||
* @param[in] B Bit number in the word to be set.
|
||||
*/
|
||||
#define SET_BIT(W, B) ((W) |= (uint32_t)(1U << (B)))
|
||||
|
||||
|
||||
/**@brief Clears a bit in the uint32 word.
|
||||
*
|
||||
* @param[in] W Word whose bit is to be cleared.
|
||||
* @param[in] B Bit number in the word to be cleared.
|
||||
*/
|
||||
#define CLR_BIT(W, B) ((W) &= (~(uint32_t)(1U << (B))))
|
||||
|
||||
|
||||
/**@brief Checks if a bit is set.
|
||||
*
|
||||
* @param[in] W Word whose bit is to be checked.
|
||||
* @param[in] B Bit number in the word to be checked.
|
||||
*
|
||||
* @retval 1 if bit is set.
|
||||
* @retval 0 if bit is not set.
|
||||
*/
|
||||
#define IS_SET(W, B) (((W) >> (B)) & 1)
|
||||
|
||||
#define BIT_0 0x01 /**< The value of bit 0 */
|
||||
#define BIT_1 0x02 /**< The value of bit 1 */
|
||||
#define BIT_2 0x04 /**< The value of bit 2 */
|
||||
#define BIT_3 0x08 /**< The value of bit 3 */
|
||||
#define BIT_4 0x10 /**< The value of bit 4 */
|
||||
#define BIT_5 0x20 /**< The value of bit 5 */
|
||||
#define BIT_6 0x40 /**< The value of bit 6 */
|
||||
#define BIT_7 0x80 /**< The value of bit 7 */
|
||||
#define BIT_8 0x0100 /**< The value of bit 8 */
|
||||
#define BIT_9 0x0200 /**< The value of bit 9 */
|
||||
#define BIT_10 0x0400 /**< The value of bit 10 */
|
||||
#define BIT_11 0x0800 /**< The value of bit 11 */
|
||||
#define BIT_12 0x1000 /**< The value of bit 12 */
|
||||
#define BIT_13 0x2000 /**< The value of bit 13 */
|
||||
#define BIT_14 0x4000 /**< The value of bit 14 */
|
||||
#define BIT_15 0x8000 /**< The value of bit 15 */
|
||||
#define BIT_16 0x00010000 /**< The value of bit 16 */
|
||||
#define BIT_17 0x00020000 /**< The value of bit 17 */
|
||||
#define BIT_18 0x00040000 /**< The value of bit 18 */
|
||||
#define BIT_19 0x00080000 /**< The value of bit 19 */
|
||||
#define BIT_20 0x00100000 /**< The value of bit 20 */
|
||||
#define BIT_21 0x00200000 /**< The value of bit 21 */
|
||||
#define BIT_22 0x00400000 /**< The value of bit 22 */
|
||||
#define BIT_23 0x00800000 /**< The value of bit 23 */
|
||||
#define BIT_24 0x01000000 /**< The value of bit 24 */
|
||||
#define BIT_25 0x02000000 /**< The value of bit 25 */
|
||||
#define BIT_26 0x04000000 /**< The value of bit 26 */
|
||||
#define BIT_27 0x08000000 /**< The value of bit 27 */
|
||||
#define BIT_28 0x10000000 /**< The value of bit 28 */
|
||||
#define BIT_29 0x20000000 /**< The value of bit 29 */
|
||||
#define BIT_30 0x40000000 /**< The value of bit 30 */
|
||||
#define BIT_31 0x80000000 /**< The value of bit 31 */
|
||||
|
||||
#define UNUSED_VARIABLE(X) ((void)(X))
|
||||
#define UNUSED_PARAMETER(X) UNUSED_VARIABLE(X)
|
||||
#define UNUSED_RETURN_VALUE(X) UNUSED_VARIABLE(X)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NORDIC_COMMON_H__
|
||||
54
lib/sdk/components/libraries/util/nrf_assert.c
Normal file
54
lib/sdk/components/libraries/util/nrf_assert.c
Normal file
@ -0,0 +1,54 @@
|
||||
/**
|
||||
* Copyright (c) 2006 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "nrf_assert.h"
|
||||
#include "app_error.h"
|
||||
#include "nordic_common.h"
|
||||
|
||||
__WEAK void assert_nrf_callback(uint16_t line_num, const uint8_t * file_name)
|
||||
{
|
||||
assert_info_t assert_info =
|
||||
{
|
||||
.line_num = line_num,
|
||||
.p_file_name = file_name,
|
||||
};
|
||||
app_error_fault_handler(NRF_FAULT_ID_SDK_ASSERT, 0, (uint32_t)(&assert_info));
|
||||
|
||||
UNUSED_VARIABLE(assert_info);
|
||||
}
|
||||
123
lib/sdk/components/libraries/util/nrf_assert.h
Normal file
123
lib/sdk/components/libraries/util/nrf_assert.h
Normal file
@ -0,0 +1,123 @@
|
||||
/**
|
||||
* Copyright (c) 2006 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
* @brief Utilities for verifying program logic
|
||||
*/
|
||||
|
||||
#ifndef NRF_ASSERT_H_
|
||||
#define NRF_ASSERT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "nrf.h"
|
||||
#include "app_error.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @brief Function for handling assertions.
|
||||
*
|
||||
*
|
||||
* @note
|
||||
* This function is called when an assertion has triggered.
|
||||
*
|
||||
* @note
|
||||
* This function is deprecated and will be removed in future releases.
|
||||
* Use app_error_fault_handler instead.
|
||||
*
|
||||
*
|
||||
* @post
|
||||
* All hardware is put into an idle non-emitting state (in particular the radio is highly
|
||||
* important to switch off since the radio might be in a state that makes it send
|
||||
* packets continiously while a typical final infinit ASSERT loop is executing).
|
||||
*
|
||||
*
|
||||
* @param line_num The line number where the assertion is called
|
||||
* @param file_name Pointer to the file name
|
||||
*/
|
||||
//lint -save -esym(14, assert_nrf_callback)
|
||||
void assert_nrf_callback(uint16_t line_num, const uint8_t *file_name);
|
||||
//lint -restore
|
||||
|
||||
#if (defined(DEBUG_NRF) || defined(DEBUG_NRF_USER))
|
||||
#define NRF_ASSERT_PRESENT 1
|
||||
#else
|
||||
#define NRF_ASSERT_PRESENT 0
|
||||
#endif
|
||||
|
||||
//#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER)
|
||||
|
||||
/*lint -emacro(506, ASSERT) */ /* Suppress "Constant value Boolean */
|
||||
/*lint -emacro(774, ASSERT) */ /* Suppress "Boolean within 'if' always evaluates to True" */ \
|
||||
|
||||
/** @brief Function for checking intended for production code.
|
||||
*
|
||||
* Check passes if "expr" evaluates to true. */
|
||||
|
||||
#ifdef _lint
|
||||
#define ASSERT(expr) \
|
||||
if (expr) \
|
||||
{ \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
while (1); \
|
||||
}
|
||||
#else //_lint
|
||||
#define ASSERT(expr) \
|
||||
if (NRF_ASSERT_PRESENT) \
|
||||
{ \
|
||||
if (expr) \
|
||||
{ \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
assert_nrf_callback((uint16_t)__LINE__, (uint8_t *)__FILE__); \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* NRF_ASSERT_H_ */
|
||||
147
lib/sdk/components/libraries/util/nrf_bitmask.h
Normal file
147
lib/sdk/components/libraries/util/nrf_bitmask.h
Normal file
@ -0,0 +1,147 @@
|
||||
/**
|
||||
* Copyright (c) 2006 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef NRF_BITMASK_H
|
||||
#define NRF_BITMASK_H
|
||||
|
||||
#include "compiler_abstraction.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BITMASK_BYTE_GET(abs_bit) ((abs_bit)/8)
|
||||
#define BITMASK_RELBIT_GET(abs_bit) ((abs_bit) & 0x00000007)
|
||||
|
||||
/**
|
||||
* Function for checking if bit in the multi-byte bit mask is set.
|
||||
*
|
||||
* @param bit Bit index.
|
||||
* @param p_mask A pointer to mask with bit fields.
|
||||
*
|
||||
* @return 0 if bit is not set, positive value otherwise.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t nrf_bitmask_bit_is_set(uint32_t bit, void const * p_mask)
|
||||
{
|
||||
uint8_t const * p_mask8 = (uint8_t const *)p_mask;
|
||||
uint32_t byte_idx = BITMASK_BYTE_GET(bit);
|
||||
bit = BITMASK_RELBIT_GET(bit);
|
||||
return (1 << bit) & p_mask8[byte_idx];
|
||||
}
|
||||
|
||||
/**
|
||||
* Function for setting a bit in the multi-byte bit mask.
|
||||
*
|
||||
* @param bit Bit index.
|
||||
* @param p_mask A pointer to mask with bit fields.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_bitmask_bit_set(uint32_t bit, void * p_mask)
|
||||
{
|
||||
uint8_t * p_mask8 = (uint8_t *)p_mask;
|
||||
uint32_t byte_idx = BITMASK_BYTE_GET(bit);
|
||||
bit = BITMASK_RELBIT_GET(bit);
|
||||
p_mask8[byte_idx] |= (1 << bit);
|
||||
}
|
||||
|
||||
/**
|
||||
* Function for clearing a bit in the multi-byte bit mask.
|
||||
*
|
||||
* @param bit Bit index.
|
||||
* @param p_mask A pointer to mask with bit fields.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
|
||||
{
|
||||
uint8_t * p_mask8 = (uint8_t *)p_mask;
|
||||
uint32_t byte_idx = BITMASK_BYTE_GET(bit);
|
||||
bit = BITMASK_RELBIT_GET(bit);
|
||||
p_mask8[byte_idx] &= ~(1 << bit);
|
||||
}
|
||||
|
||||
/**
|
||||
* Function for performing bitwise OR operation on two multi-byte bit masks.
|
||||
*
|
||||
* @param p_mask1 A pointer to the first bit mask.
|
||||
* @param p_mask2 A pointer to the second bit mask.
|
||||
* @param p_mask_out A pointer to the output bit mask.
|
||||
* @param length Length of output mask in bytes.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_bitmask_masks_or(void const * p_mask1,
|
||||
void const * p_mask2,
|
||||
void * p_out_mask,
|
||||
uint32_t length)
|
||||
{
|
||||
uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1;
|
||||
uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2;
|
||||
uint8_t * p_mask8_out = (uint8_t *)p_out_mask;
|
||||
uint32_t i;
|
||||
for (i = 0; i < length; i++)
|
||||
{
|
||||
p_mask8_out[i] = p_mask8_1[i] | p_mask8_2[i];
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Function for performing bitwise AND operation on two multi-byte bit masks.
|
||||
*
|
||||
* @param p_mask1 A pointer to the first bit mask.
|
||||
* @param p_mask2 A pointer to the second bit mask.
|
||||
* @param p_mask_out A pointer to the output bit mask.
|
||||
* @param length Length of output mask in bytes.
|
||||
*/
|
||||
__STATIC_INLINE void nrf_bitmask_masks_and(void const * p_mask1,
|
||||
void const * p_mask2,
|
||||
void * p_out_mask,
|
||||
uint32_t length)
|
||||
{
|
||||
uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1;
|
||||
uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2;
|
||||
uint8_t * p_mask8_out = (uint8_t *)p_out_mask;
|
||||
uint32_t i;
|
||||
for (i = 0; i < length; i++)
|
||||
{
|
||||
p_mask8_out[i] = p_mask8_1[i] & p_mask8_2[i];
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //NRF_BITMASK_H
|
||||
77
lib/sdk/components/libraries/util/sdk_common.h
Normal file
77
lib/sdk/components/libraries/util/sdk_common.h
Normal file
@ -0,0 +1,77 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @cond */
|
||||
/**@file
|
||||
*
|
||||
* @ingroup experimental_api
|
||||
* @defgroup sdk_common SDK Common Header
|
||||
* @brief All common headers needed for SDK examples will be included here so that application
|
||||
* developer does not have to include headers on him/herself.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SDK_COMMON_H__
|
||||
#define SDK_COMMON_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include "sdk_config.h"
|
||||
#include "nordic_common.h"
|
||||
#include "compiler_abstraction.h"
|
||||
#include "sdk_os.h"
|
||||
#include "sdk_errors.h"
|
||||
#include "app_util.h"
|
||||
#include "sdk_macros.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/** @} */
|
||||
/** @endcond */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SDK_COMMON_H__
|
||||
|
||||
166
lib/sdk/components/libraries/util/sdk_errors.h
Normal file
166
lib/sdk/components/libraries/util/sdk_errors.h
Normal file
@ -0,0 +1,166 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**@file
|
||||
*
|
||||
* @defgroup sdk_error SDK Error codes
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
* @{
|
||||
* @details Error codes are 32-bit unsigned integers with the most significant 16-bit reserved for
|
||||
* identifying the module where the error occurred while the least least significant LSB
|
||||
* are used to provide the cause or nature of error. Each module is assigned a 16-bit
|
||||
* unsigned integer. Which it will use to identify all errors that occurred in it. 16-bit
|
||||
* LSB range is with module id as the MSB in the 32-bit error code is reserved for the
|
||||
* module. As an example, if 0x8800 identifies a certain SDK module, all values from
|
||||
* 0x88000000 - 0x8800FFFF are reserved for this module.
|
||||
* It should be noted that common error reasons have been assigned values to make it
|
||||
* possible to decode error reason easily. As an example, lets module uninitialized has
|
||||
* been assigned an error code 0x000A0. Then, if application encounters an error code
|
||||
* 0xZZZZ00A0, it knows that it accessing a certain module without initializing it.
|
||||
* Apart from this, each module is allowed to define error codes that are not covered by
|
||||
* the common ones, however, these values are defined in a range that does not conflict
|
||||
* with common error values. For module, specific error however, it is possible that the
|
||||
* same error value is used by two different modules to indicated errors of very different
|
||||
* nature. If error is already defined by the NRF common error codes, these are reused.
|
||||
* A range is reserved for application as well, it can use this range for defining
|
||||
* application specific errors.
|
||||
*
|
||||
* @note Success code, NRF_SUCCESS, does not include any module identifier.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef SDK_ERRORS_H__
|
||||
#define SDK_ERRORS_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include "nrf_error.h"
|
||||
#include "sdk_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup sdk_err_base Base defined for SDK Modules
|
||||
* @{
|
||||
*/
|
||||
#define NRF_ERROR_SDK_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x8000) /**< Base value defined for SDK module identifiers. */
|
||||
#define NRF_ERROR_SDK_COMMON_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x0080) /**< Base error value to be used for SDK error values. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup sdk_module_codes Codes reserved as identification for module where the error occurred.
|
||||
* @{
|
||||
*/
|
||||
#define NRF_ERROR_MEMORY_MANAGER_ERR_BASE (0x8100)
|
||||
#define NRF_ERROR_PERIPH_DRIVERS_ERR_BASE (0x8200)
|
||||
#define NRF_ERROR_GAZELLE_ERR_BASE (0x8300)
|
||||
#define NRF_ERROR_BLE_IPSP_ERR_BASE (0x8400)
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup sdk_iot_errors Codes reserved as identification for IoT errors.
|
||||
* @{
|
||||
*/
|
||||
#define NRF_ERROR_IOT_ERR_BASE_START (0xA000)
|
||||
#define NRF_ERROR_IOT_ERR_BASE_STOP (0xAFFF)
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup sdk_common_errors Codes reserved as identification for common errors.
|
||||
* @{
|
||||
*/
|
||||
#define NRF_ERROR_MODULE_NOT_INITIALZED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0000)
|
||||
#define NRF_ERROR_MUTEX_INIT_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0001)
|
||||
#define NRF_ERROR_MUTEX_LOCK_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0002)
|
||||
#define NRF_ERROR_MUTEX_UNLOCK_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0003)
|
||||
#define NRF_ERROR_MUTEX_COND_INIT_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0004)
|
||||
#define NRF_ERROR_MODULE_ALREADY_INITIALIZED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0005)
|
||||
#define NRF_ERROR_STORAGE_FULL (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0006)
|
||||
#define NRF_ERROR_API_NOT_IMPLEMENTED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0010)
|
||||
#define NRF_ERROR_FEATURE_NOT_ENABLED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0011)
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup drv_specific_errors Error / status codes specific to drivers.
|
||||
* @{
|
||||
*/
|
||||
#define NRF_ERROR_DRV_TWI_ERR_OVERRUN (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0000)
|
||||
#define NRF_ERROR_DRV_TWI_ERR_ANACK (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0001)
|
||||
#define NRF_ERROR_DRV_TWI_ERR_DNACK (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0002)
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup ble_ipsp_errors IPSP codes
|
||||
* @brief Error and status codes specific to IPSP.
|
||||
* @{
|
||||
*/
|
||||
#define NRF_ERROR_BLE_IPSP_RX_PKT_TRUNCATED (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0000)
|
||||
#define NRF_ERROR_BLE_IPSP_CHANNEL_ALREADY_EXISTS (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0001)
|
||||
#define NRF_ERROR_BLE_IPSP_LINK_DISCONNECTED (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0002)
|
||||
#define NRF_ERROR_BLE_IPSP_PEER_REJECTED (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0003)
|
||||
/* @} */
|
||||
|
||||
|
||||
/**
|
||||
* @brief API Result.
|
||||
*
|
||||
* @details Indicates success or failure of an API procedure. In case of failure, a comprehensive
|
||||
* error code indicating cause or reason for failure is provided.
|
||||
*
|
||||
* Though called an API result, it could used in Asynchronous notifications callback along
|
||||
* with asynchronous callback as event result. This mechanism is employed when an event
|
||||
* marks the end of procedure initiated using API. API result, in this case, will only be
|
||||
* an indicative of whether the procedure has been requested successfully.
|
||||
*/
|
||||
typedef uint32_t ret_code_t;
|
||||
|
||||
/** @} */
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SDK_ERRORS_H__
|
||||
191
lib/sdk/components/libraries/util/sdk_macros.h
Normal file
191
lib/sdk/components/libraries/util/sdk_macros.h
Normal file
@ -0,0 +1,191 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/**@file
|
||||
*
|
||||
|
||||
* @defgroup sdk_common_macros SDK Common Header
|
||||
* @ingroup app_common
|
||||
* @brief Macros for parameter checking and similar tasks
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SDK_MACROS_H__
|
||||
#define SDK_MACROS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**@brief Macro for verifying statement to be true. It will cause the exterior function to return
|
||||
* err_code if the statement is not true.
|
||||
*
|
||||
* @param[in] statement Statement to test.
|
||||
* @param[in] err_code Error value to return if test was invalid.
|
||||
*
|
||||
* @retval nothing, but will cause the exterior function to return @p err_code if @p statement
|
||||
* is false.
|
||||
*/
|
||||
#define VERIFY_TRUE(statement, err_code) \
|
||||
do \
|
||||
{ \
|
||||
if (!(statement)) \
|
||||
{ \
|
||||
return err_code; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
/**@brief Macro for verifying statement to be true. It will cause the exterior function to return
|
||||
* if the statement is not true.
|
||||
*
|
||||
* @param[in] statement Statement to test.
|
||||
*/
|
||||
#define VERIFY_TRUE_VOID(statement) VERIFY_TRUE((statement), )
|
||||
|
||||
|
||||
/**@brief Macro for verifying statement to be false. It will cause the exterior function to return
|
||||
* err_code if the statement is not false.
|
||||
*
|
||||
* @param[in] statement Statement to test.
|
||||
* @param[in] err_code Error value to return if test was invalid.
|
||||
*
|
||||
* @retval nothing, but will cause the exterior function to return @p err_code if @p statement
|
||||
* is true.
|
||||
*/
|
||||
#define VERIFY_FALSE(statement, err_code) \
|
||||
do \
|
||||
{ \
|
||||
if ((statement)) \
|
||||
{ \
|
||||
return err_code; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
/**@brief Macro for verifying statement to be false. It will cause the exterior function to return
|
||||
* if the statement is not false.
|
||||
*
|
||||
* @param[in] statement Statement to test.
|
||||
*/
|
||||
#define VERIFY_FALSE_VOID(statement) VERIFY_FALSE((statement), )
|
||||
|
||||
|
||||
/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior
|
||||
* function to return err_code if the err_code is not @ref NRF_SUCCESS.
|
||||
*
|
||||
* @param[in] err_code The error code to check.
|
||||
*/
|
||||
#ifdef DISABLE_PARAM_CHECK
|
||||
#define VERIFY_SUCCESS()
|
||||
#else
|
||||
#define VERIFY_SUCCESS(err_code) VERIFY_TRUE((err_code) == NRF_SUCCESS, (err_code))
|
||||
#endif /* DISABLE_PARAM_CHECK */
|
||||
|
||||
|
||||
/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior
|
||||
* function to return if the err_code is not @ref NRF_SUCCESS.
|
||||
*
|
||||
* @param[in] err_code The error code to check.
|
||||
*/
|
||||
#ifdef DISABLE_PARAM_CHECK
|
||||
#define VERIFY_SUCCESS_VOID()
|
||||
#else
|
||||
#define VERIFY_SUCCESS_VOID(err_code) VERIFY_TRUE_VOID((err_code) == NRF_SUCCESS)
|
||||
#endif /* DISABLE_PARAM_CHECK */
|
||||
|
||||
|
||||
/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to
|
||||
* return @ref NRF_ERROR_INVALID_STATE if not.
|
||||
*
|
||||
* @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED
|
||||
* should be true if the module is initialized, false if not.
|
||||
*/
|
||||
#ifdef DISABLE_PARAM_CHECK
|
||||
#define VERIFY_MODULE_INITIALIZED()
|
||||
#else
|
||||
#define VERIFY_MODULE_INITIALIZED() VERIFY_TRUE((MODULE_INITIALIZED), NRF_ERROR_INVALID_STATE)
|
||||
#endif /* DISABLE_PARAM_CHECK */
|
||||
|
||||
|
||||
/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to
|
||||
* return if not.
|
||||
*
|
||||
* @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED
|
||||
* should be true if the module is initialized, false if not.
|
||||
*/
|
||||
#ifdef DISABLE_PARAM_CHECK
|
||||
#define VERIFY_MODULE_INITIALIZED_VOID()
|
||||
#else
|
||||
#define VERIFY_MODULE_INITIALIZED_VOID() VERIFY_TRUE_VOID((MODULE_INITIALIZED))
|
||||
#endif /* DISABLE_PARAM_CHECK */
|
||||
|
||||
|
||||
/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to
|
||||
* return if not.
|
||||
*
|
||||
* @param[in] param The variable to check if is NULL.
|
||||
*/
|
||||
#ifdef DISABLE_PARAM_CHECK
|
||||
#define VERIFY_PARAM_NOT_NULL()
|
||||
#else
|
||||
#define VERIFY_PARAM_NOT_NULL(param) VERIFY_FALSE(((param) == NULL), NRF_ERROR_NULL)
|
||||
#endif /* DISABLE_PARAM_CHECK */
|
||||
|
||||
|
||||
/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to
|
||||
* return if not.
|
||||
*
|
||||
* @param[in] param The variable to check if is NULL.
|
||||
*/
|
||||
#ifdef DISABLE_PARAM_CHECK
|
||||
#define VERIFY_PARAM_NOT_NULL_VOID()
|
||||
#else
|
||||
#define VERIFY_PARAM_NOT_NULL_VOID(param) VERIFY_FALSE_VOID(((param) == NULL))
|
||||
#endif /* DISABLE_PARAM_CHECK */
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SDK_MACROS_H__
|
||||
|
||||
220
lib/sdk/components/libraries/util/sdk_mapped_flags.c
Normal file
220
lib/sdk/components/libraries/util/sdk_mapped_flags.c
Normal file
@ -0,0 +1,220 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include "sdk_mapped_flags.h"
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include "compiler_abstraction.h"
|
||||
|
||||
|
||||
// Test whether the flag collection type is large enough to hold all the flags. If this fails,
|
||||
// reduce SDK_MAPPED_FLAGS_N_KEYS or increase the size of sdk_mapped_flags_t.
|
||||
STATIC_ASSERT((sizeof(sdk_mapped_flags_t) * SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE) >= SDK_MAPPED_FLAGS_N_KEYS);
|
||||
|
||||
|
||||
/**@brief Function for setting the state of a flag to true.
|
||||
*
|
||||
* @note This function does not check whether the index is valid.
|
||||
*
|
||||
* @param[in] p_flags The collection of flags to modify.
|
||||
* @param[in] index The index of the flag to modify.
|
||||
*/
|
||||
static __INLINE void sdk_mapped_flags_set_by_index(sdk_mapped_flags_t * p_flags, uint16_t index)
|
||||
{
|
||||
*p_flags |= (1U << index);
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for setting the state of a flag to false.
|
||||
*
|
||||
* @note This function does not check whether the index is valid.
|
||||
*
|
||||
* @param[in] p_flags The collection of flags to modify.
|
||||
* @param[in] index The index of the flag to modify.
|
||||
*/
|
||||
static __INLINE void sdk_mapped_flags_clear_by_index(sdk_mapped_flags_t * p_flags, uint16_t index)
|
||||
{
|
||||
*p_flags &= ~(1U << index);
|
||||
}
|
||||
|
||||
|
||||
/**@brief Function for getting the state of a flag.
|
||||
*
|
||||
* @note This function does not check whether the index is valid.
|
||||
*
|
||||
* @param[in] p_flags The collection of flags to read.
|
||||
* @param[in] index The index of the flag to get.
|
||||
*/
|
||||
static __INLINE bool sdk_mapped_flags_get_by_index(sdk_mapped_flags_t flags, uint16_t index)
|
||||
{
|
||||
return ((flags & (1 << index)) != 0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags)
|
||||
{
|
||||
for (uint16_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
|
||||
{
|
||||
if (sdk_mapped_flags_get_by_index(flags, i))
|
||||
{
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return SDK_MAPPED_FLAGS_INVALID_INDEX;
|
||||
}
|
||||
|
||||
|
||||
void sdk_mapped_flags_update_by_key(uint16_t * p_keys,
|
||||
sdk_mapped_flags_t * p_flags,
|
||||
uint16_t key,
|
||||
bool value)
|
||||
{
|
||||
sdk_mapped_flags_bulk_update_by_key(p_keys, p_flags, 1, key, value);
|
||||
}
|
||||
|
||||
|
||||
void sdk_mapped_flags_bulk_update_by_key(uint16_t * p_keys,
|
||||
sdk_mapped_flags_t * p_flags,
|
||||
uint32_t n_flag_collections,
|
||||
uint16_t key,
|
||||
bool value)
|
||||
{
|
||||
if ((p_keys != NULL) && (p_flags != NULL) && (n_flag_collections > 0))
|
||||
{
|
||||
for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
|
||||
{
|
||||
if (p_keys[i] == key)
|
||||
{
|
||||
for (uint32_t j = 0; j < n_flag_collections; j++)
|
||||
{
|
||||
if (value)
|
||||
{
|
||||
sdk_mapped_flags_set_by_index(&p_flags[j], i);
|
||||
}
|
||||
else
|
||||
{
|
||||
sdk_mapped_flags_clear_by_index(&p_flags[j], i);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
bool sdk_mapped_flags_get_by_key_w_idx(uint16_t * p_keys,
|
||||
sdk_mapped_flags_t flags,
|
||||
uint16_t key,
|
||||
uint8_t * p_index)
|
||||
{
|
||||
if (p_keys != NULL)
|
||||
{
|
||||
for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
|
||||
{
|
||||
if (p_keys[i] == key)
|
||||
{
|
||||
if (p_index != NULL)
|
||||
{
|
||||
*p_index = i;
|
||||
}
|
||||
return sdk_mapped_flags_get_by_index(flags, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
if (p_index != NULL)
|
||||
{
|
||||
*p_index = SDK_MAPPED_FLAGS_N_KEYS;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key)
|
||||
{
|
||||
if (p_keys != NULL)
|
||||
{
|
||||
for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
|
||||
{
|
||||
if (p_keys[i] == key)
|
||||
{
|
||||
return sdk_mapped_flags_get_by_index(flags, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t * p_keys,
|
||||
sdk_mapped_flags_t flags)
|
||||
{
|
||||
sdk_mapped_flags_key_list_t key_list;
|
||||
key_list.len = 0;
|
||||
|
||||
if (p_keys != NULL)
|
||||
{
|
||||
for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
|
||||
{
|
||||
if (sdk_mapped_flags_get_by_index(flags, i))
|
||||
{
|
||||
key_list.flag_keys[key_list.len++] = p_keys[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return key_list;
|
||||
}
|
||||
|
||||
|
||||
uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags)
|
||||
{
|
||||
uint32_t n_flags_set = 0;
|
||||
|
||||
for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
|
||||
{
|
||||
if (sdk_mapped_flags_get_by_index(flags, i))
|
||||
{
|
||||
n_flags_set += 1;
|
||||
}
|
||||
}
|
||||
return n_flags_set;
|
||||
}
|
||||
199
lib/sdk/components/libraries/util/sdk_mapped_flags.h
Normal file
199
lib/sdk/components/libraries/util/sdk_mapped_flags.h
Normal file
@ -0,0 +1,199 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef SDK_MAPPED_FLAGS_H__
|
||||
#define SDK_MAPPED_FLAGS_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "app_util.h"
|
||||
#include "compiler_abstraction.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @defgroup sdk_mapped_flags Mapped flags
|
||||
* @ingroup app_common
|
||||
* @{
|
||||
* @brief Module for writing and reading flags that are associated
|
||||
* with keys.
|
||||
*
|
||||
* @details The flags are represented as bits in a bitmap called a <i>flag collection</i>. The keys
|
||||
* are uint16_t. Each flag collection contains all flags of the same type, one flag for
|
||||
* each key.
|
||||
*
|
||||
* The mapped flags module does not keep the flag states, nor the list of keys. These are
|
||||
* provided in the API calls. A key's index in the key list determines which bit in the
|
||||
* flag collection is associated with it. This module does not ever edit the key list, and
|
||||
* does not edit flags except in function calls that take the flag collection as a pointer.
|
||||
*
|
||||
*/
|
||||
|
||||
#define SDK_MAPPED_FLAGS_N_KEYS 32 /**< The number of keys to keep flags for. This is also the number of flags in a flag collection. If changing this value, you might also need change the width of the sdk_mapped_flags_t type. */
|
||||
#define SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE 8 /**< The number of flags that fit in one byte. */
|
||||
#define SDK_MAPPED_FLAGS_INVALID_INDEX 0xFFFF /**< A flag index guaranteed to be invalid. */
|
||||
|
||||
typedef uint32_t sdk_mapped_flags_t; /**< The bitmap to hold flags. Each flag is one bit, and each bit represents the flag state associated with one key. */
|
||||
|
||||
|
||||
/**@brief Type used to present a subset of the registered keys.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t len; /**< The length of the list. */
|
||||
uint16_t flag_keys[SDK_MAPPED_FLAGS_N_KEYS]; /**< The list of keys. */
|
||||
} sdk_mapped_flags_key_list_t;
|
||||
|
||||
|
||||
/**@brief Function for getting the first index at which the flag is true in the provided
|
||||
* collection.
|
||||
*
|
||||
* @param[in] flags The flag collection to search for a flag set to true.
|
||||
*
|
||||
* @return The first index that has its flag set to true. If none were found, the
|
||||
* function returns @ref SDK_MAPPED_FLAGS_INVALID_INDEX.
|
||||
*/
|
||||
uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags);
|
||||
|
||||
|
||||
/**@brief Function for updating the state of a flag.
|
||||
*
|
||||
* @param[in] p_keys The list of associated keys (assumed to have a length of
|
||||
* @ref SDK_MAPPED_FLAGS_N_KEYS).
|
||||
* @param[out] p_flags The flag collection to modify.
|
||||
* @param[in] key The key to modify the flag of.
|
||||
* @param[in] value The state to set the flag to.
|
||||
*/
|
||||
void sdk_mapped_flags_update_by_key(uint16_t * p_keys,
|
||||
sdk_mapped_flags_t * p_flags,
|
||||
uint16_t key,
|
||||
bool value);
|
||||
|
||||
|
||||
/**@brief Function for updating the state of the same flag in multiple flag collections.
|
||||
*
|
||||
* @details The key and value are the same for all flag collections in the p_flags array.
|
||||
*
|
||||
* @param[in] p_keys The list of associated keys (assumed to have a length of
|
||||
* @ref SDK_MAPPED_FLAGS_N_KEYS).
|
||||
* @param[out] p_flags The flag collections to modify.
|
||||
* @param[out] n_flag_collections The number of flag collections in p_flags.
|
||||
* @param[in] key The key to modify the flag of.
|
||||
* @param[in] value The state to set the flag to.
|
||||
*/
|
||||
void sdk_mapped_flags_bulk_update_by_key(uint16_t * p_keys,
|
||||
sdk_mapped_flags_t * p_flags,
|
||||
uint32_t n_flag_collections,
|
||||
uint16_t key,
|
||||
bool value);
|
||||
|
||||
|
||||
/**@brief Function for getting the state of a specific flag.
|
||||
*
|
||||
* @param[in] p_keys The list of associated keys (assumed to have a length of
|
||||
* @ref SDK_MAPPED_FLAGS_N_KEYS).
|
||||
* @param[in] flags The flag collection to read from.
|
||||
* @param[in] key The key to get the flag for.
|
||||
*
|
||||
* @return The state of the flag.
|
||||
*/
|
||||
bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key);
|
||||
|
||||
|
||||
/**@brief Function for getting the state of a specific flag.
|
||||
*
|
||||
* @param[in] p_keys The list of associated keys (assumed to have a length of
|
||||
* @ref SDK_MAPPED_FLAGS_N_KEYS).
|
||||
* @param[in] flags The flag collection from which to read.
|
||||
* @param[in] key The key for which to get the flag.
|
||||
* @param[out] p_index If not NULL, the index of the key.
|
||||
*
|
||||
* @return The state of the flag.
|
||||
*/
|
||||
bool sdk_mapped_flags_get_by_key_w_idx(uint16_t * p_keys,
|
||||
sdk_mapped_flags_t flags,
|
||||
uint16_t key,
|
||||
uint8_t * p_index);
|
||||
|
||||
|
||||
/**@brief Function for getting a list of all keys that have a specific flag set to true.
|
||||
*
|
||||
* @param[in] p_keys The list of associated keys (assumed to have a length of
|
||||
* @ref SDK_MAPPED_FLAGS_N_KEYS).
|
||||
* @param[in] flags The flag collection to search.
|
||||
*
|
||||
* @return The list of keys.
|
||||
*/
|
||||
sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t * p_keys,
|
||||
sdk_mapped_flags_t flags);
|
||||
|
||||
|
||||
/**@brief Function for getting the number of keys that have a specific flag set to true.
|
||||
*
|
||||
* @param[in] flags The flag collection to search.
|
||||
*
|
||||
* @return The number of keys.
|
||||
*/
|
||||
uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags);
|
||||
|
||||
|
||||
/**@brief Function for querying whether any flags in the collection are set.
|
||||
*
|
||||
* @param[in] flags The flag collection to query.
|
||||
*
|
||||
* @retval true If one or more flags are set to true.
|
||||
* @retval false Otherwise.
|
||||
*/
|
||||
static __INLINE bool sdk_mapped_flags_any_set(sdk_mapped_flags_t flags)
|
||||
{
|
||||
return (flags != 0);
|
||||
}
|
||||
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SDK_MAPPED_FLAGS_H__ */
|
||||
76
lib/sdk/components/libraries/util/sdk_os.h
Normal file
76
lib/sdk/components/libraries/util/sdk_os.h
Normal file
@ -0,0 +1,76 @@
|
||||
/**
|
||||
* Copyright (c) 2013 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @cond */
|
||||
/**@file
|
||||
*
|
||||
* @defgroup sdk_os SDK OS Abstraction
|
||||
* @ingroup experimental_api
|
||||
* @details In order to made SDK modules independent of use of an embedded OS, and permit
|
||||
* application with varied task architecture, SDK abstracts the OS specific
|
||||
* elements here in order to make all other modules agnostic to the OS or task
|
||||
* architecture.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SDK_OS_H__
|
||||
#define SDK_OS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SDK_MUTEX_DEFINE(X)
|
||||
#define SDK_MUTEX_INIT(X)
|
||||
#define SDK_MUTEX_LOCK(X)
|
||||
#define SDK_MUTEX_UNLOCK(X)
|
||||
|
||||
/**
|
||||
* @defgroup os_data_type Data types.
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/** @endcond */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SDK_OS_H__
|
||||
|
||||
86
lib/sdk/components/libraries/util/sdk_resources.h
Normal file
86
lib/sdk/components/libraries/util/sdk_resources.h
Normal file
@ -0,0 +1,86 @@
|
||||
/**
|
||||
* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/** @file
|
||||
* @brief Definition file for resource usage by SoftDevice, ESB and Gazell.
|
||||
*/
|
||||
|
||||
#ifndef APP_RESOURCES_H__
|
||||
#define APP_RESOURCES_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
#include "nrf_sd_def.h"
|
||||
#else
|
||||
#define SD_PPI_RESTRICTED 0uL /**< 1 if PPI peripheral is restricted, 0 otherwise. */
|
||||
#define SD_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by SotfDevice (not available to th spplication). */
|
||||
#define SD_PPI_GROUPS_USED 0uL /**< PPI groups utilized by SotfDevice (not available to th spplication). */
|
||||
#define SD_TIMERS_USED 0uL /**< Timers used by SoftDevice. */
|
||||
#define SD_SWI_USED 0uL /**< Software interrupts used by SoftDevice. */
|
||||
#endif
|
||||
|
||||
#ifdef GAZELL_PRESENT
|
||||
#include "nrf_gzll_resources.h"
|
||||
#else
|
||||
#define GZLL_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by Gazell (not available to th spplication). */
|
||||
#define GZLL_TIMERS_USED 0uL /**< Timers used by Gazell. */
|
||||
#define GZLL_SWI_USED 0uL /**< Software interrupts used by Gazell */
|
||||
#endif
|
||||
|
||||
#ifdef ESB_PRESENT
|
||||
#include "nrf_esb_resources.h"
|
||||
#else
|
||||
#define ESB_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by ESB (not available to th spplication). */
|
||||
#define ESB_TIMERS_USED 0uL /**< Timers used by ESB. */
|
||||
#define ESB_SWI_USED 0uL /**< Software interrupts used by ESB */
|
||||
#endif
|
||||
|
||||
#define NRF_PPI_CHANNELS_USED (SD_PPI_CHANNELS_USED | GZLL_PPI_CHANNELS_USED | ESB_PPI_CHANNELS_USED)
|
||||
#define NRF_PPI_GROUPS_USED (SD_PPI_GROUPS_USED)
|
||||
#define NRF_SWI_USED (SD_SWI_USED | GZLL_SWI_USED | ESB_SWI_USED)
|
||||
#define NRF_TIMERS_USED (SD_TIMERS_USED | GZLL_TIMERS_USED | ESB_TIMERS_USED)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // APP_RESOURCES_H__
|
||||
136
lib/sdk/components/toolchain/cmsis/include/arm_common_tables.h
Normal file
136
lib/sdk/components/toolchain/cmsis/include/arm_common_tables.h
Normal file
@ -0,0 +1,136 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. October 2015
|
||||
* $Revision: V.1.4.5 a
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
*
|
||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
/* extern const q31_t realCoefAQ31[1024]; */
|
||||
/* extern const q31_t realCoefBQ31[1024]; */
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
@ -0,0 +1,79 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. March 2015
|
||||
* $Revision: V.1.4.5
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
*
|
||||
* Description: This file has constant structs that are initialized for
|
||||
* user convenience. For example, some can be given as
|
||||
* arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
7030
lib/sdk/components/toolchain/cmsis/include/arm_math.h
Normal file
7030
lib/sdk/components/toolchain/cmsis/include/arm_math.h
Normal file
File diff suppressed because it is too large
Load Diff
734
lib/sdk/components/toolchain/cmsis/include/cmsis_armcc.h
Normal file
734
lib/sdk/components/toolchain/cmsis/include/cmsis_armcc.h
Normal file
@ -0,0 +1,734 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
|
||||
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in integer value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in two unsigned short values.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Reverse byte order in signed short value
|
||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x04) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
1800
lib/sdk/components/toolchain/cmsis/include/cmsis_armcc_V6.h
Normal file
1800
lib/sdk/components/toolchain/cmsis/include/cmsis_armcc_V6.h
Normal file
File diff suppressed because it is too large
Load Diff
1373
lib/sdk/components/toolchain/cmsis/include/cmsis_gcc.h
Normal file
1373
lib/sdk/components/toolchain/cmsis/include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
798
lib/sdk/components/toolchain/cmsis/include/core_cm0.h
Normal file
798
lib/sdk/components/toolchain/cmsis/include/core_cm0.h
Normal file
@ -0,0 +1,798 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0 Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
914
lib/sdk/components/toolchain/cmsis/include/core_cm0plus.h
Normal file
914
lib/sdk/components/toolchain/cmsis/include/core_cm0plus.h
Normal file
@ -0,0 +1,914 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0plus.h
|
||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC
|
||||
#define __CORE_CM0PLUS_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex-M0+
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS CM0+ definitions */
|
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_DEPENDANT
|
||||
#define __CORE_CM0PLUS_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0PLUS_REV
|
||||
#define __CM0PLUS_REV 0x0000U
|
||||
#warning "__CM0PLUS_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex-M0+ */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
- Core MPU Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
|
||||
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||
#else
|
||||
uint32_t RESERVED0;
|
||||
#endif
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
#endif
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||
|
||||
/*@} end of group CMSIS_MPU */
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0+ header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0+ Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
1763
lib/sdk/components/toolchain/cmsis/include/core_cm3.h
Normal file
1763
lib/sdk/components/toolchain/cmsis/include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
1937
lib/sdk/components/toolchain/cmsis/include/core_cm4.h
Normal file
1937
lib/sdk/components/toolchain/cmsis/include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
2512
lib/sdk/components/toolchain/cmsis/include/core_cm7.h
Normal file
2512
lib/sdk/components/toolchain/cmsis/include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user