572 lines
20 KiB
C
572 lines
20 KiB
C
/**
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* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
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* Semiconductor ASA integrated circuit in a product or a software update for
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/**
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* @defgroup nrf_spim_hal SPIM HAL
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* @{
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* @ingroup nrf_spi
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*
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* @brief Hardware access layer for accessing the SPIM peripheral.
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*/
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#ifndef NRF_SPIM_H__
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#define NRF_SPIM_H__
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#include <stddef.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "nrf.h"
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#include "nrf_peripherals.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief This value can be used as a parameter for the @ref nrf_spim_pins_set
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* function to specify that a given SPI signal (SCK, MOSI, or MISO)
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* shall not be connected to a physical pin.
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*/
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#define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF
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/**
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* @brief SPIM tasks.
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*/
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typedef enum
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{
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/*lint -save -e30*/
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NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction.
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NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction.
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NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction.
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NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME) ///< Resume SPI transaction.
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/*lint -restore*/
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} nrf_spim_task_t;
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/**
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* @brief SPIM events.
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*/
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typedef enum
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{
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/*lint -save -e30*/
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NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped.
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NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached.
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NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END), ///< End of RXD buffer and TXD buffer reached.
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NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached.
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NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED) ///< Transaction started.
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/*lint -restore*/
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} nrf_spim_event_t;
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/**
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* @brief SPIM shortcuts.
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*/
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typedef enum
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{
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NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk ///< Shortcut between END event and START task.
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} nrf_spim_short_mask_t;
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/**
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* @brief SPIM interrupts.
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*/
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typedef enum
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{
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NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
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NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
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NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event.
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NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
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NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk ///< Interrupt on STARTED event.
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} nrf_spim_int_mask_t;
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/**
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* @brief SPI master data rates.
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*/
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typedef enum
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{
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NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
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NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
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NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
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NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
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NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
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NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
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// [conversion to 'int' needed to prevent compilers from complaining
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// that the provided value (0x80000000UL) is out of range of "int"]
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NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8,///< 8 Mbps.
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#ifndef SPI_PRESENT
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NRF_SPI_FREQ_125K = NRF_SPIM_FREQ_125K,
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NRF_SPI_FREQ_250K = NRF_SPIM_FREQ_250K,
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NRF_SPI_FREQ_500K = NRF_SPIM_FREQ_500K,
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NRF_SPI_FREQ_1M = NRF_SPIM_FREQ_1M,
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NRF_SPI_FREQ_2M = NRF_SPIM_FREQ_2M,
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NRF_SPI_FREQ_4M = NRF_SPIM_FREQ_4M,
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NRF_SPI_FREQ_8M = NRF_SPIM_FREQ_8M,
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#endif
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} nrf_spim_frequency_t;
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/**
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* @brief SPI modes.
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*/
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typedef enum
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{
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NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
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NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
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NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock.
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NRF_SPIM_MODE_3, ///< SCK active low, sample on trailing edge of clock.
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#ifndef SPI_PRESENT
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NRF_SPI_MODE_0 = NRF_SPIM_MODE_0,
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NRF_SPI_MODE_1 = NRF_SPIM_MODE_1,
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NRF_SPI_MODE_2 = NRF_SPIM_MODE_2,
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NRF_SPI_MODE_3 = NRF_SPIM_MODE_3,
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#endif
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} nrf_spim_mode_t;
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/**
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* @brief SPI bit orders.
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*/
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typedef enum
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{
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NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
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NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst, ///< Least significant bit shifted out first.
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#ifndef SPI_PRESENT
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NRF_SPI_BIT_ORDER_MSB_FIRST = NRF_SPIM_BIT_ORDER_MSB_FIRST,
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NRF_SPI_BIT_ORDER_LSB_FIRST = NRF_SPIM_BIT_ORDER_LSB_FIRST,
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#endif
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} nrf_spim_bit_order_t;
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/**
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* @brief Function for activating a specific SPIM task.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_task Task to activate.
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*/
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__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
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nrf_spim_task_t spim_task);
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/**
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* @brief Function for getting the address of a specific SPIM task register.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_task Requested task.
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*
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* @return Address of the specified task register.
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*/
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__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
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nrf_spim_task_t spim_task);
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/**
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* @brief Function for clearing a specific SPIM event.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_event Event to clear.
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*/
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__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
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nrf_spim_event_t spim_event);
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/**
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* @brief Function for checking the state of a specific SPIM event.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_event Event to check.
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*
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* @retval true If the event is set.
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* @retval false If the event is not set.
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*/
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__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
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nrf_spim_event_t spim_event);
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/**
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* @brief Function for getting the address of a specific SPIM event register.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_event Requested event.
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*
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* @return Address of the specified event register.
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*/
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__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
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nrf_spim_event_t spim_event);
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/**
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* @brief Function for enabling specified shortcuts.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_shorts_mask Shortcuts to enable.
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*/
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__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
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uint32_t spim_shorts_mask);
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/**
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* @brief Function for disabling specified shortcuts.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_shorts_mask Shortcuts to disable.
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*/
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__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
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uint32_t spim_shorts_mask);
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/**
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* @brief Function for getting shorts setting.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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*/
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__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg);
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/**
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* @brief Function for enabling specified interrupts.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_int_mask Interrupts to enable.
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*/
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__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
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uint32_t spim_int_mask);
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/**
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* @brief Function for disabling specified interrupts.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_int_mask Interrupts to disable.
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*/
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__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
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uint32_t spim_int_mask);
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/**
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* @brief Function for retrieving the state of a given interrupt.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spim_int Interrupt to check.
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*
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* @retval true If the interrupt is enabled.
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* @retval false If the interrupt is not enabled.
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*/
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__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
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nrf_spim_int_mask_t spim_int);
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/**
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* @brief Function for enabling the SPIM peripheral.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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*/
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__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg);
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/**
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* @brief Function for disabling the SPIM peripheral.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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*/
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__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
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/**
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* @brief Function for configuring SPIM pins.
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*
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* If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
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* value instead of its pin number.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] sck_pin SCK pin number.
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* @param[in] mosi_pin MOSI pin number.
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* @param[in] miso_pin MISO pin number.
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*/
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__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
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uint32_t sck_pin,
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uint32_t mosi_pin,
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uint32_t miso_pin);
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/**
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* @brief Function for setting the SPI master data rate.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] frequency SPI frequency.
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*/
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__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
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nrf_spim_frequency_t frequency);
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/**
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* @brief Function for setting the transmit buffer.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] p_buffer Pointer to the buffer with data to send.
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* @param[in] length Maximum number of data bytes to transmit.
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*/
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__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
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uint8_t const * p_buffer,
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uint8_t length);
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/**
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* @brief Function for setting the receive buffer.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] p_buffer Pointer to the buffer for received data.
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* @param[in] length Maximum number of data bytes to receive.
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*/
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__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
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uint8_t * p_buffer,
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uint8_t length);
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/**
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* @brief Function for setting the SPI configuration.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] spi_mode SPI mode.
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* @param[in] spi_bit_order SPI bit order.
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*/
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__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
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nrf_spim_mode_t spi_mode,
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nrf_spim_bit_order_t spi_bit_order);
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/**
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* @brief Function for setting the over-read character.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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* @param[in] orc Over-read character that is clocked out in case of
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* an over-read of the TXD buffer.
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*/
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__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
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uint8_t orc);
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/**
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* @brief Function for enabling the TX list feature.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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*/
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__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg);
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/**
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* @brief Function for disabling the TX list feature.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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*/
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__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg);
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/**
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* @brief Function for enabling the RX list feature.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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*/
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__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg);
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/**
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* @brief Function for disabling the RX list feature.
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*
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* @param[in] p_reg Pointer to the peripheral registers structure.
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*/
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__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg);
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#ifndef SUPPRESS_INLINE_IMPLEMENTATION
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__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
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nrf_spim_task_t spim_task)
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{
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*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_task)) = 0x1UL;
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}
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__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
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nrf_spim_task_t spim_task)
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{
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return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_task);
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}
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__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
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nrf_spim_event_t spim_event)
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{
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*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)) = 0x0UL;
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#if __CORTEX_M == 0x04
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volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event));
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(void)dummy;
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#endif
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}
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__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
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nrf_spim_event_t spim_event)
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{
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return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event);
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}
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__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
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nrf_spim_event_t spim_event)
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{
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return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_event);
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}
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__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
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uint32_t spim_shorts_mask)
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{
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p_reg->SHORTS |= spim_shorts_mask;
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}
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__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
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uint32_t spim_shorts_mask)
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{
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p_reg->SHORTS &= ~(spim_shorts_mask);
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}
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__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg)
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{
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return p_reg->SHORTS;
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}
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|
|
|
__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
|
|
uint32_t spim_int_mask)
|
|
{
|
|
p_reg->INTENSET = spim_int_mask;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
|
|
uint32_t spim_int_mask)
|
|
{
|
|
p_reg->INTENCLR = spim_int_mask;
|
|
}
|
|
|
|
__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
|
|
nrf_spim_int_mask_t spim_int)
|
|
{
|
|
return (bool)(p_reg->INTENSET & spim_int);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg)
|
|
{
|
|
p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg)
|
|
{
|
|
p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
|
|
uint32_t sck_pin,
|
|
uint32_t mosi_pin,
|
|
uint32_t miso_pin)
|
|
{
|
|
p_reg->PSEL.SCK = sck_pin;
|
|
p_reg->PSEL.MOSI = mosi_pin;
|
|
p_reg->PSEL.MISO = miso_pin;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
|
|
nrf_spim_frequency_t frequency)
|
|
{
|
|
p_reg->FREQUENCY = frequency;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
|
|
uint8_t const * p_buffer,
|
|
uint8_t length)
|
|
{
|
|
p_reg->TXD.PTR = (uint32_t)p_buffer;
|
|
p_reg->TXD.MAXCNT = length;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
|
|
uint8_t * p_buffer,
|
|
uint8_t length)
|
|
{
|
|
p_reg->RXD.PTR = (uint32_t)p_buffer;
|
|
p_reg->RXD.MAXCNT = length;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
|
|
nrf_spim_mode_t spi_mode,
|
|
nrf_spim_bit_order_t spi_bit_order)
|
|
{
|
|
uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
|
|
SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
|
|
switch (spi_mode)
|
|
{
|
|
default:
|
|
case NRF_SPIM_MODE_0:
|
|
config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
|
|
(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
|
|
break;
|
|
|
|
case NRF_SPIM_MODE_1:
|
|
config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
|
|
(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
|
|
break;
|
|
|
|
case NRF_SPIM_MODE_2:
|
|
config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
|
|
(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
|
|
break;
|
|
|
|
case NRF_SPIM_MODE_3:
|
|
config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
|
|
(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
|
|
break;
|
|
}
|
|
p_reg->CONFIG = config;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
|
|
uint8_t orc)
|
|
{
|
|
p_reg->ORC = orc;
|
|
}
|
|
|
|
|
|
__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
|
|
{
|
|
p_reg->TXD.LIST = 1;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
|
|
{
|
|
p_reg->TXD.LIST = 0;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
|
|
{
|
|
p_reg->RXD.LIST = 1;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
|
|
{
|
|
p_reg->RXD.LIST = 0;
|
|
}
|
|
|
|
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // NRF_SPIM_H__
|
|
|
|
/** @} */
|