diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h b/lib/sdk/components/device/compiler_abstraction.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h rename to lib/sdk/components/device/compiler_abstraction.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h b/lib/sdk/components/device/nrf.h similarity index 96% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf.h rename to lib/sdk/components/device/nrf.h index bb1ad22..6f5bf34 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h +++ b/lib/sdk/components/device/nrf.h @@ -64,7 +64,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #if defined(_WIN32) /* Do not include nrf specific files when building for PC host */ -//#elif defined(__unix) +#elif defined(__unix) /* Do not include nrf specific files when building for PC host */ #elif defined(__APPLE__) /* Do not include nrf specific files when building for PC host */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h b/lib/sdk/components/device/nrf51_to_nrf52.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h rename to lib/sdk/components/device/nrf51_to_nrf52.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52840.h b/lib/sdk/components/device/nrf51_to_nrf52840.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52840.h rename to lib/sdk/components/device/nrf51_to_nrf52840.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h b/lib/sdk/components/device/nrf52.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h rename to lib/sdk/components/device/nrf52.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52832_peripherals.h b/lib/sdk/components/device/nrf52832_peripherals.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf52832_peripherals.h rename to lib/sdk/components/device/nrf52832_peripherals.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52840.h b/lib/sdk/components/device/nrf52840.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf52840.h rename to lib/sdk/components/device/nrf52840.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52840_bitfields.h b/lib/sdk/components/device/nrf52840_bitfields.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf52840_bitfields.h rename to lib/sdk/components/device/nrf52840_bitfields.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52840_peripherals.h b/lib/sdk/components/device/nrf52840_peripherals.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf52840_peripherals.h rename to lib/sdk/components/device/nrf52840_peripherals.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h b/lib/sdk/components/device/nrf52_bitfields.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h rename to lib/sdk/components/device/nrf52_bitfields.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h b/lib/sdk/components/device/nrf52_name_change.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h rename to lib/sdk/components/device/nrf52_name_change.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_to_nrf52840.h b/lib/sdk/components/device/nrf52_to_nrf52840.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/device/nrf52_to_nrf52840.h rename to lib/sdk/components/device/nrf52_to_nrf52840.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.c b/lib/sdk/components/drivers_nrf/common/nrf_drv_common.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.c rename to lib/sdk/components/drivers_nrf/common/nrf_drv_common.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.h b/lib/sdk/components/drivers_nrf/common/nrf_drv_common.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.h rename to lib/sdk/components/drivers_nrf/common/nrf_drv_common.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.h b/lib/sdk/components/drivers_nrf/delay/nrf_delay.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.h rename to lib/sdk/components/drivers_nrf/delay/nrf_delay.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_clock.h b/lib/sdk/components/drivers_nrf/hal/nrf_clock.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_clock.h rename to lib/sdk/components/drivers_nrf/hal/nrf_clock.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_comp.h b/lib/sdk/components/drivers_nrf/hal/nrf_comp.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_comp.h rename to lib/sdk/components/drivers_nrf/hal/nrf_comp.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.c b/lib/sdk/components/drivers_nrf/hal/nrf_ecb.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.c rename to lib/sdk/components/drivers_nrf/hal/nrf_ecb.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.h b/lib/sdk/components/drivers_nrf/hal/nrf_ecb.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.h rename to lib/sdk/components/drivers_nrf/hal/nrf_ecb.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_egu.h b/lib/sdk/components/drivers_nrf/hal/nrf_egu.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_egu.h rename to lib/sdk/components/drivers_nrf/hal/nrf_egu.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpio.h b/lib/sdk/components/drivers_nrf/hal/nrf_gpio.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpio.h rename to lib/sdk/components/drivers_nrf/hal/nrf_gpio.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpiote.h b/lib/sdk/components/drivers_nrf/hal/nrf_gpiote.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpiote.h rename to lib/sdk/components/drivers_nrf/hal/nrf_gpiote.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_i2s.h b/lib/sdk/components/drivers_nrf/hal/nrf_i2s.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_i2s.h rename to lib/sdk/components/drivers_nrf/hal/nrf_i2s.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_lpcomp.h b/lib/sdk/components/drivers_nrf/hal/nrf_lpcomp.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_lpcomp.h rename to lib/sdk/components/drivers_nrf/hal/nrf_lpcomp.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.c b/lib/sdk/components/drivers_nrf/hal/nrf_nvmc.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.c rename to lib/sdk/components/drivers_nrf/hal/nrf_nvmc.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.h b/lib/sdk/components/drivers_nrf/hal/nrf_nvmc.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.h rename to lib/sdk/components/drivers_nrf/hal/nrf_nvmc.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pdm.h b/lib/sdk/components/drivers_nrf/hal/nrf_pdm.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pdm.h rename to lib/sdk/components/drivers_nrf/hal/nrf_pdm.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_peripherals.h b/lib/sdk/components/drivers_nrf/hal/nrf_peripherals.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_peripherals.h rename to lib/sdk/components/drivers_nrf/hal/nrf_peripherals.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_power.h b/lib/sdk/components/drivers_nrf/hal/nrf_power.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_power.h rename to lib/sdk/components/drivers_nrf/hal/nrf_power.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ppi.h b/lib/sdk/components/drivers_nrf/hal/nrf_ppi.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ppi.h rename to lib/sdk/components/drivers_nrf/hal/nrf_ppi.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pwm.h b/lib/sdk/components/drivers_nrf/hal/nrf_pwm.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pwm.h rename to lib/sdk/components/drivers_nrf/hal/nrf_pwm.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_qdec.h b/lib/sdk/components/drivers_nrf/hal/nrf_qdec.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_qdec.h rename to lib/sdk/components/drivers_nrf/hal/nrf_qdec.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_qspi.h b/lib/sdk/components/drivers_nrf/hal/nrf_qspi.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_qspi.h rename to lib/sdk/components/drivers_nrf/hal/nrf_qspi.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rng.h b/lib/sdk/components/drivers_nrf/hal/nrf_rng.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rng.h rename to lib/sdk/components/drivers_nrf/hal/nrf_rng.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rtc.h b/lib/sdk/components/drivers_nrf/hal/nrf_rtc.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rtc.h rename to lib/sdk/components/drivers_nrf/hal/nrf_rtc.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.c b/lib/sdk/components/drivers_nrf/hal/nrf_saadc.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.c rename to lib/sdk/components/drivers_nrf/hal/nrf_saadc.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.h b/lib/sdk/components/drivers_nrf/hal/nrf_saadc.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.h rename to lib/sdk/components/drivers_nrf/hal/nrf_saadc.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spi.h b/lib/sdk/components/drivers_nrf/hal/nrf_spi.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spi.h rename to lib/sdk/components/drivers_nrf/hal/nrf_spi.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spim.h b/lib/sdk/components/drivers_nrf/hal/nrf_spim.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spim.h rename to lib/sdk/components/drivers_nrf/hal/nrf_spim.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spis.h b/lib/sdk/components/drivers_nrf/hal/nrf_spis.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spis.h rename to lib/sdk/components/drivers_nrf/hal/nrf_spis.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_systick.h b/lib/sdk/components/drivers_nrf/hal/nrf_systick.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_systick.h rename to lib/sdk/components/drivers_nrf/hal/nrf_systick.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_temp.h b/lib/sdk/components/drivers_nrf/hal/nrf_temp.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_temp.h rename to lib/sdk/components/drivers_nrf/hal/nrf_temp.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_timer.h b/lib/sdk/components/drivers_nrf/hal/nrf_timer.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_timer.h rename to lib/sdk/components/drivers_nrf/hal/nrf_timer.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twi.h b/lib/sdk/components/drivers_nrf/hal/nrf_twi.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twi.h rename to lib/sdk/components/drivers_nrf/hal/nrf_twi.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twim.h b/lib/sdk/components/drivers_nrf/hal/nrf_twim.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twim.h rename to lib/sdk/components/drivers_nrf/hal/nrf_twim.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twis.h b/lib/sdk/components/drivers_nrf/hal/nrf_twis.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twis.h rename to lib/sdk/components/drivers_nrf/hal/nrf_twis.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uart.h b/lib/sdk/components/drivers_nrf/hal/nrf_uart.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uart.h rename to lib/sdk/components/drivers_nrf/hal/nrf_uart.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uarte.h b/lib/sdk/components/drivers_nrf/hal/nrf_uarte.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uarte.h rename to lib/sdk/components/drivers_nrf/hal/nrf_uarte.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_usbd.h b/lib/sdk/components/drivers_nrf/hal/nrf_usbd.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_usbd.h rename to lib/sdk/components/drivers_nrf/hal/nrf_usbd.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_wdt.h b/lib/sdk/components/drivers_nrf/hal/nrf_wdt.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_wdt.h rename to lib/sdk/components/drivers_nrf/hal/nrf_wdt.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.c b/lib/sdk/components/drivers_nrf/timer/nrf_drv_timer.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.c rename to lib/sdk/components/drivers_nrf/timer/nrf_drv_timer.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.h b/lib/sdk/components/drivers_nrf/timer/nrf_drv_timer.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.h rename to lib/sdk/components/drivers_nrf/timer/nrf_drv_timer.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.c b/lib/sdk/components/drivers_nrf/uart/nrf_drv_uart.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.c rename to lib/sdk/components/drivers_nrf/uart/nrf_drv_uart.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.h b/lib/sdk/components/drivers_nrf/uart/nrf_drv_uart.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.h rename to lib/sdk/components/drivers_nrf/uart/nrf_drv_uart.h diff --git a/lib/sdk/components/drivers_nrf/usbd/nrf_drv_usbd_errata.h b/lib/sdk/components/drivers_nrf/usbd/nrf_drv_usbd_errata.h new file mode 100644 index 0000000..a06a0a5 --- /dev/null +++ b/lib/sdk/components/drivers_nrf/usbd/nrf_drv_usbd_errata.h @@ -0,0 +1,141 @@ +/** + * Copyright (c) 2017 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_DRV_USBD_ERRATA_H__ +#define NRF_DRV_USBD_ERRATA_H__ + +#include +/** + * @defgroup nrf_drv_usbd_errata Functions to check if selected PAN is present in current chip + * @{ + * @ingroup nrf_drv_usbd + * + * Functions here are checking the presence of an error in current chip. + * The checking is done at runtime based on the microcontroller version. + * This file is subject to removal when nRF51840 prototype support is removed. + */ + +#ifndef NRF_DRV_USBD_ERRATA_ENABLE +/** + * @brief The constant that informs if errata should be enabled at all + * + * If this constant is set to 0, all the Errata bug fixes will be automatically disabled. + */ +#define NRF_DRV_USBD_ERRATA_ENABLE 1 +#endif + +/** + * @brief Internal auxiliary function to check if the program is running on NRF52840 chip + * @retval true It is NRF52480 chip + * @retval false It is other chip + */ +static inline bool nrf_drv_usbd_errata_type_52840(void) +{ + return ((((*(uint32_t *)0xF0000FE0) & 0xFF) == 0x08) && + (((*(uint32_t *)0xF0000FE4) & 0x0F) == 0x0)); +} + +/** + * @brief Internal auxiliary function to check if the program is running on first sample of + * NRF52840 chip + * @retval true It is NRF52480 chip and it is first sample version + * @retval false It is other chip + */ +static inline bool nrf_drv_usbd_errata_type_52840_proto1(void) +{ + return ( nrf_drv_usbd_errata_type_52840() && + ( ((*(uint32_t *)0xF0000FE8) & 0xF0) == 0x00 ) && + ( ((*(uint32_t *)0xF0000FEC) & 0xF0) == 0x00 ) ); +} + +/** + * @brief Function to check if chip requires errata 104 + * + * Errata: USBD: EPDATA event is not always generated. + * + * @retval true Errata should be implemented + * @retval false Errata should not be implemented + */ +static inline bool nrf_drv_usbd_errata_104(void) +{ + return NRF_DRV_USBD_ERRATA_ENABLE && nrf_drv_usbd_errata_type_52840_proto1(); +} + +/** + * @brief Function to check if chip requires errata 154 + * + * Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task. + * + * @retval true Errata should be implemented + * @retval false Errata should not be implemented + */ +static inline bool nrf_drv_usbd_errata_154(void) +{ + return NRF_DRV_USBD_ERRATA_ENABLE && nrf_drv_usbd_errata_type_52840_proto1(); +} + +/** + * @brief Function to check if chip requires errata 166 + * + * Errata: ISO double buffering not functional + * + * @retval true Errata should be implemented + * @retval false Errata should not be implemented + */ +static inline bool nrf_drv_usbd_errata_166(void) +{ + return NRF_DRV_USBD_ERRATA_ENABLE && true; +} + +/** + * @brief Function to check if chip requires errata ??? + * + * Errata: SIZE.EPOUT not writable + * + * @retval true Errata should be implemented + * @retval false Errata should not be implemented + */ +static inline bool nrf_drv_usbd_errata_sizeepout_rw(void) +{ + return NRF_DRV_USBD_ERRATA_ENABLE && nrf_drv_usbd_errata_type_52840_proto1(); +} + +/** @} */ +#endif /* NRF_DRV_USBD_ERRATA_H__ */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.c b/lib/sdk/components/libraries/crc16/crc16.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.c rename to lib/sdk/components/libraries/crc16/crc16.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.h b/lib/sdk/components/libraries/crc16/crc16.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.h rename to lib/sdk/components/libraries/crc16/crc16.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.c b/lib/sdk/components/libraries/fifo/app_fifo.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.c rename to lib/sdk/components/libraries/fifo/app_fifo.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.h b/lib/sdk/components/libraries/fifo/app_fifo.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.h rename to lib/sdk/components/libraries/fifo/app_fifo.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.c b/lib/sdk/components/libraries/hci/hci_mem_pool.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.c rename to lib/sdk/components/libraries/hci/hci_mem_pool.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.h b/lib/sdk/components/libraries/hci/hci_mem_pool.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.h rename to lib/sdk/components/libraries/hci/hci_mem_pool.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.c b/lib/sdk/components/libraries/hci/hci_slip.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.c rename to lib/sdk/components/libraries/hci/hci_slip.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.h b/lib/sdk/components/libraries/hci/hci_slip.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.h rename to lib/sdk/components/libraries/hci/hci_slip.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.c b/lib/sdk/components/libraries/hci/hci_transport.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.c rename to lib/sdk/components/libraries/hci/hci_transport.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.h b/lib/sdk/components/libraries/hci/hci_transport.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.h rename to lib/sdk/components/libraries/hci/hci_transport.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.c b/lib/sdk/components/libraries/scheduler/app_scheduler.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.c rename to lib/sdk/components/libraries/scheduler/app_scheduler.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.h b/lib/sdk/components/libraries/scheduler/app_scheduler.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.h rename to lib/sdk/components/libraries/scheduler/app_scheduler.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.c b/lib/sdk/components/libraries/timer/app_timer.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.c rename to lib/sdk/components/libraries/timer/app_timer.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.h b/lib/sdk/components/libraries/timer/app_timer.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.h rename to lib/sdk/components/libraries/timer/app_timer.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.c b/lib/sdk/components/libraries/uart/app_uart.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.c rename to lib/sdk/components/libraries/uart/app_uart.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.h b/lib/sdk/components/libraries/uart/app_uart.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.h rename to lib/sdk/components/libraries/uart/app_uart.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.c b/lib/sdk/components/libraries/util/app_error.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.c rename to lib/sdk/components/libraries/util/app_error.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.h b/lib/sdk/components/libraries/util/app_error.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.h rename to lib/sdk/components/libraries/util/app_error.h diff --git a/lib/sdk/components/libraries/util/app_error_weak.h b/lib/sdk/components/libraries/util/app_error_weak.h new file mode 100644 index 0000000..c4e19f2 --- /dev/null +++ b/lib/sdk/components/libraries/util/app_error_weak.h @@ -0,0 +1,85 @@ +/** + * Copyright (c) 2016 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef APP_ERROR_WEAK_H__ +#define APP_ERROR_WEAK_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @file + * + * @defgroup app_error Common application error handler + * @{ + * @ingroup app_common + * + * @brief Common application error handler. + */ + +/**@brief Callback function for errors, asserts, and faults. + * + * @details This function is called every time an error is raised in app_error, nrf_assert, or + * in the SoftDevice. Information about the error can be found in the @p info + * parameter. + * + * See also @ref nrf_fault_handler_t for more details. + * + * @note The function is implemented as weak so that it can be redefined by a custom error + * handler when needed. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if + * unavailable. + * @param[in] info Optional additional information regarding the fault. The value of the @p id + * parameter dictates how to interpret this parameter. Refer to the documentation + * for each fault identifier (@ref NRF_FAULT_IDS and @ref APP_ERROR_FAULT_IDS) for + * details about interpreting @p info. + */ +void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info); + + +/** @} */ + + +#ifdef __cplusplus +} +#endif + +#endif // APP_ERROR_WEAK_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util.h b/lib/sdk/components/libraries/util/app_util.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util.h rename to lib/sdk/components/libraries/util/app_util.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_bds.h b/lib/sdk/components/libraries/util/app_util_bds.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_bds.h rename to lib/sdk/components/libraries/util/app_util_bds.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.c b/lib/sdk/components/libraries/util/app_util_platform.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.c rename to lib/sdk/components/libraries/util/app_util_platform.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.h b/lib/sdk/components/libraries/util/app_util_platform.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.h rename to lib/sdk/components/libraries/util/app_util_platform.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nordic_common.h b/lib/sdk/components/libraries/util/nordic_common.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/nordic_common.h rename to lib/sdk/components/libraries/util/nordic_common.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.c b/lib/sdk/components/libraries/util/nrf_assert.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.c rename to lib/sdk/components/libraries/util/nrf_assert.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.h b/lib/sdk/components/libraries/util/nrf_assert.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.h rename to lib/sdk/components/libraries/util/nrf_assert.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_bitmask.h b/lib/sdk/components/libraries/util/nrf_bitmask.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_bitmask.h rename to lib/sdk/components/libraries/util/nrf_bitmask.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_common.h b/lib/sdk/components/libraries/util/sdk_common.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_common.h rename to lib/sdk/components/libraries/util/sdk_common.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_errors.h b/lib/sdk/components/libraries/util/sdk_errors.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_errors.h rename to lib/sdk/components/libraries/util/sdk_errors.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_macros.h b/lib/sdk/components/libraries/util/sdk_macros.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_macros.h rename to lib/sdk/components/libraries/util/sdk_macros.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.c b/lib/sdk/components/libraries/util/sdk_mapped_flags.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.c rename to lib/sdk/components/libraries/util/sdk_mapped_flags.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.h b/lib/sdk/components/libraries/util/sdk_mapped_flags.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.h rename to lib/sdk/components/libraries/util/sdk_mapped_flags.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_os.h b/lib/sdk/components/libraries/util/sdk_os.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_os.h rename to lib/sdk/components/libraries/util/sdk_os.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_resources.h b/lib/sdk/components/libraries/util/sdk_resources.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_resources.h rename to lib/sdk/components/libraries/util/sdk_resources.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_common_tables.h b/lib/sdk/components/toolchain/cmsis/include/arm_common_tables.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_common_tables.h rename to lib/sdk/components/toolchain/cmsis/include/arm_common_tables.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_const_structs.h b/lib/sdk/components/toolchain/cmsis/include/arm_const_structs.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_const_structs.h rename to lib/sdk/components/toolchain/cmsis/include/arm_const_structs.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_math.h b/lib/sdk/components/toolchain/cmsis/include/arm_math.h similarity index 93% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_math.h rename to lib/sdk/components/toolchain/cmsis/include/arm_math.h index 580cbbd..0be65d3 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_math.h +++ b/lib/sdk/components/toolchain/cmsis/include/arm_math.h @@ -38,130 +38,6 @@ * POSSIBILITY OF SUCH DAMAGE. * -------------------------------------------------------------------- */ -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - /** * @defgroup groupMath Basic Math Functions */ @@ -546,7 +422,7 @@ extern "C" uint32_t count = 0; uint32_t mask = 0x80000000; - while((data & mask) == 0) + while ((data & mask) == 0) { count += 1u; mask = mask >> 1u; @@ -570,7 +446,7 @@ extern "C" uint32_t index, i; uint32_t signBits; - if(in > 0) + if (in > 0) { signBits = ((uint32_t) (__CLZ( in) - 1)); } @@ -621,7 +497,7 @@ extern "C" uint32_t index = 0, i = 0; uint32_t signBits = 0; - if(in > 0) + if (in > 0) { signBits = ((uint32_t)(__CLZ( in) - 17)); } @@ -676,11 +552,11 @@ extern "C" posMax = posMax * 2; } - if(x > 0) + if (x > 0) { posMax = (posMax - 1); - if(x > posMax) + if (x > posMax) { x = posMax; } @@ -689,7 +565,7 @@ extern "C" { negMin = -posMax; - if(x < negMin) + if (x < negMin) { x = negMin; } @@ -1029,7 +905,7 @@ extern "C" typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q7; @@ -1039,7 +915,7 @@ extern "C" typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q15; @@ -1049,7 +925,7 @@ extern "C" typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_q31; @@ -1059,7 +935,7 @@ extern "C" typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_f32; @@ -2912,7 +2788,7 @@ void arm_rfft_fast_f32( * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @param[out] pDst points to the location where the output result is written. Length srcALen + srcBLen-1. */ void arm_conv_f32( float32_t * pSrcA, @@ -2928,7 +2804,7 @@ void arm_rfft_fast_f32( * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ @@ -2948,7 +2824,7 @@ void arm_rfft_fast_f32( * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @param[out] pDst points to the location where the output result is written. Length srcALen + srcBLen-1. */ void arm_conv_q15( q15_t * pSrcA, @@ -2964,7 +2840,7 @@ void arm_rfft_fast_f32( * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. */ void arm_conv_fast_q15( q15_t * pSrcA, @@ -2980,7 +2856,7 @@ void arm_rfft_fast_f32( * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ @@ -3000,7 +2876,7 @@ void arm_rfft_fast_f32( * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. */ void arm_conv_q31( q31_t * pSrcA, @@ -3016,7 +2892,7 @@ void arm_rfft_fast_f32( * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. */ void arm_conv_fast_q31( q31_t * pSrcA, @@ -3032,7 +2908,7 @@ void arm_rfft_fast_f32( * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ @@ -3052,7 +2928,7 @@ void arm_rfft_fast_f32( * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. */ void arm_conv_q7( q7_t * pSrcA, @@ -3071,7 +2947,7 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. */ arm_status arm_conv_partial_f32( float32_t * pSrcA, @@ -3094,7 +2970,7 @@ void arm_rfft_fast_f32( * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. */ arm_status arm_conv_partial_opt_q15( q15_t * pSrcA, @@ -3117,7 +2993,7 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. */ arm_status arm_conv_partial_q15( q15_t * pSrcA, @@ -3138,7 +3014,7 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. */ arm_status arm_conv_partial_fast_q15( q15_t * pSrcA, @@ -3161,7 +3037,7 @@ void arm_rfft_fast_f32( * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. */ arm_status arm_conv_partial_fast_opt_q15( q15_t * pSrcA, @@ -3184,7 +3060,7 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. */ arm_status arm_conv_partial_q31( q31_t * pSrcA, @@ -3205,7 +3081,7 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. */ arm_status arm_conv_partial_fast_q31( q31_t * pSrcA, @@ -3228,7 +3104,7 @@ void arm_rfft_fast_f32( * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. */ arm_status arm_conv_partial_opt_q7( q7_t * pSrcA, @@ -3251,7 +3127,7 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. */ arm_status arm_conv_partial_q7( q7_t * pSrcA, @@ -3271,7 +3147,7 @@ void arm_rfft_fast_f32( uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ } arm_fir_decimate_instance_q15; /** @@ -3282,7 +3158,7 @@ void arm_rfft_fast_f32( uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ } arm_fir_decimate_instance_q31; /** @@ -3293,7 +3169,7 @@ void arm_rfft_fast_f32( uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ } arm_fir_decimate_instance_f32; @@ -3434,7 +3310,7 @@ void arm_rfft_fast_f32( uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize + phaseLength-1. */ } arm_fir_interpolate_instance_q15; /** @@ -3445,7 +3321,7 @@ void arm_rfft_fast_f32( uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize + phaseLength-1. */ } arm_fir_interpolate_instance_q31; /** @@ -3456,7 +3332,7 @@ void arm_rfft_fast_f32( uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength + numTaps-1. */ } arm_fir_interpolate_instance_f32; @@ -3838,9 +3714,9 @@ void arm_rfft_fast_f32( typedef struct { uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages + blockSize. */ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages + 1. */ } arm_iir_lattice_instance_q15; /** @@ -3849,9 +3725,9 @@ void arm_rfft_fast_f32( typedef struct { uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages + blockSize. */ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages + 1. */ } arm_iir_lattice_instance_q31; /** @@ -3860,9 +3736,9 @@ void arm_rfft_fast_f32( typedef struct { uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages + blockSize. */ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages + 1. */ } arm_iir_lattice_instance_f32; @@ -3885,8 +3761,8 @@ void arm_rfft_fast_f32( * @param[in] S points to an instance of the floating-point IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages + 1. + * @param[in] pState points to the state buffer. The array is of length numStages + blockSize-1. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_f32( @@ -3917,8 +3793,8 @@ void arm_rfft_fast_f32( * @param[in] S points to an instance of the Q31 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages + 1. + * @param[in] pState points to the state buffer. The array is of length numStages + blockSize. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_q31( @@ -3949,8 +3825,8 @@ void arm_rfft_fast_f32( * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages + 1. + * @param[in] pState points to state buffer. The array is of length numStages + blockSize. * @param[in] blockSize number of samples to process per call. */ void arm_iir_lattice_init_q15( @@ -3968,7 +3844,7 @@ void arm_rfft_fast_f32( typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that controls filter coefficient updates. */ } arm_lms_instance_f32; @@ -4016,7 +3892,7 @@ void arm_rfft_fast_f32( typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ @@ -4067,7 +3943,7 @@ void arm_rfft_fast_f32( typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ @@ -4118,7 +3994,7 @@ void arm_rfft_fast_f32( typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that control filter coefficient updates. */ float32_t energy; /**< saves previous frame energy. */ @@ -4168,7 +4044,7 @@ void arm_rfft_fast_f32( typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ @@ -4222,7 +4098,7 @@ void arm_rfft_fast_f32( typedef struct { uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ @@ -4431,7 +4307,7 @@ void arm_rfft_fast_f32( { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay + blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ @@ -4444,7 +4320,7 @@ void arm_rfft_fast_f32( { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay + blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ @@ -4457,7 +4333,7 @@ void arm_rfft_fast_f32( { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay + blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ @@ -4470,7 +4346,7 @@ void arm_rfft_fast_f32( { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay + blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ @@ -5444,12 +5320,12 @@ void arm_rfft_fast_f32( /* Calculation of index */ i = (int32_t) ((x - S->x1) / xSpacing); - if(i < 0) + if (i < 0) { /* Iniatilize output for below specified range as least output value of table */ y = pYData[0]; } - else if((uint32_t)i >= S->nValues) + else if ((uint32_t)i >= S->nValues) { /* Iniatilize output for above specified range as last output value of table */ y = pYData[S->nValues - 1]; @@ -5502,11 +5378,11 @@ void arm_rfft_fast_f32( /* Index value calculation */ index = ((x & (q31_t)0xFFF00000) >> 20); - if(index >= (int32_t)(nValues - 1)) + if (index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } - else if(index < 0) + else if (index < 0) { return (pYData[0]); } @@ -5560,11 +5436,11 @@ void arm_rfft_fast_f32( /* Index value calculation */ index = ((x & (int32_t)0xFFF00000) >> 20); - if(index >= (int32_t)(nValues - 1)) + if (index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } - else if(index < 0) + else if (index < 0) { return (pYData[0]); } @@ -5621,7 +5497,7 @@ void arm_rfft_fast_f32( } index = (x >> 20) & 0xfff; - if(index >= (nValues - 1)) + if (index >= (nValues - 1)) { return (pYData[nValues - 1]); } @@ -5746,7 +5622,7 @@ void arm_rfft_fast_f32( float32_t in, float32_t * pOut) { - if(in >= 0.0f) + if (in >= 0.0f) { #if (__FPU_USED == 1) && defined ( __CC_ARM ) @@ -5821,7 +5697,7 @@ void arm_rfft_fast_f32( /* Loop over the blockSize */ i = blockSize; - while(i > 0u) + while (i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; @@ -5831,7 +5707,7 @@ void arm_rfft_fast_f32( /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; - if(wOffset >= L) + if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ @@ -5869,7 +5745,7 @@ void arm_rfft_fast_f32( /* Loop over the blockSize */ i = blockSize; - while(i > 0u) + while (i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; @@ -5877,7 +5753,7 @@ void arm_rfft_fast_f32( /* Update the input pointer */ dst += dstInc; - if(dst == (int32_t *) dst_end) + if (dst == (int32_t *) dst_end) { dst = dst_base; } @@ -5885,7 +5761,7 @@ void arm_rfft_fast_f32( /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; - if(rOffset >= L) + if (rOffset >= L) { rOffset -= L; } @@ -5921,7 +5797,7 @@ void arm_rfft_fast_f32( /* Loop over the blockSize */ i = blockSize; - while(i > 0u) + while (i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; @@ -5931,7 +5807,7 @@ void arm_rfft_fast_f32( /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; - if(wOffset >= L) + if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ @@ -5969,7 +5845,7 @@ void arm_rfft_fast_f32( /* Loop over the blockSize */ i = blockSize; - while(i > 0u) + while (i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; @@ -5977,7 +5853,7 @@ void arm_rfft_fast_f32( /* Update the input pointer */ dst += dstInc; - if(dst == (q15_t *) dst_end) + if (dst == (q15_t *) dst_end) { dst = dst_base; } @@ -5985,7 +5861,7 @@ void arm_rfft_fast_f32( /* Circularly update wOffset. Watch out for positive and negative value */ rOffset += bufferInc; - if(rOffset >= L) + if (rOffset >= L) { rOffset -= L; } @@ -6021,7 +5897,7 @@ void arm_rfft_fast_f32( /* Loop over the blockSize */ i = blockSize; - while(i > 0u) + while (i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; @@ -6031,7 +5907,7 @@ void arm_rfft_fast_f32( /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; - if(wOffset >= L) + if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ @@ -6069,7 +5945,7 @@ void arm_rfft_fast_f32( /* Loop over the blockSize */ i = blockSize; - while(i > 0u) + while (i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; @@ -6077,7 +5953,7 @@ void arm_rfft_fast_f32( /* Update the input pointer */ dst += dstInc; - if(dst == (q7_t *) dst_end) + if (dst == (q7_t *) dst_end) { dst = dst_base; } @@ -6085,7 +5961,7 @@ void arm_rfft_fast_f32( /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; - if(rOffset >= L) + if (rOffset >= L) { rOffset -= L; } @@ -6723,9 +6599,9 @@ void arm_rfft_fast_f32( * The interpolated output point is computed as: * 
    *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *           + f(XF + 1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF + 1) * (1-(x-XF))*(y-YF)
+   *           + f(XF + 1, YF + 1) * (x-XF)*(y-YF)
    *
* Note that the coordinates (x, y) contain integer and fractional components. * The integer components specify which portion of the table to use while the @@ -6766,7 +6642,7 @@ void arm_rfft_fast_f32( /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { return (0); } @@ -6840,7 +6716,7 @@ void arm_rfft_fast_f32( /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } @@ -6914,7 +6790,7 @@ void arm_rfft_fast_f32( /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } @@ -6992,7 +6868,7 @@ void arm_rfft_fast_f32( /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc.h b/lib/sdk/components/toolchain/cmsis/include/cmsis_armcc.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc.h rename to lib/sdk/components/toolchain/cmsis/include/cmsis_armcc.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc_V6.h b/lib/sdk/components/toolchain/cmsis/include/cmsis_armcc_V6.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc_V6.h rename to lib/sdk/components/toolchain/cmsis/include/cmsis_armcc_V6.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_gcc.h b/lib/sdk/components/toolchain/cmsis/include/cmsis_gcc.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_gcc.h rename to lib/sdk/components/toolchain/cmsis/include/cmsis_gcc.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0.h b/lib/sdk/components/toolchain/cmsis/include/core_cm0.h similarity index 97% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0.h rename to lib/sdk/components/toolchain/cmsis/include/core_cm0.h index fdee521..70b5b42 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0.h +++ b/lib/sdk/components/toolchain/cmsis/include/core_cm0.h @@ -735,7 +735,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ - for(;;) /* wait until reset */ + for (;;) /* wait until reset */ { __NOP(); } diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0plus.h b/lib/sdk/components/toolchain/cmsis/include/core_cm0plus.h similarity index 97% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0plus.h rename to lib/sdk/components/toolchain/cmsis/include/core_cm0plus.h index 7614450..58ef339 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0plus.h +++ b/lib/sdk/components/toolchain/cmsis/include/core_cm0plus.h @@ -851,7 +851,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ - for(;;) /* wait until reset */ + for (;;) /* wait until reset */ { __NOP(); } diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm3.h b/lib/sdk/components/toolchain/cmsis/include/core_cm3.h similarity index 98% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm3.h rename to lib/sdk/components/toolchain/cmsis/include/core_cm3.h index 34ed84c..915ba11 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm3.h +++ b/lib/sdk/components/toolchain/cmsis/include/core_cm3.h @@ -1622,7 +1622,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ - for(;;) /* wait until reset */ + for (;;) /* wait until reset */ { __NOP(); } diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm4.h b/lib/sdk/components/toolchain/cmsis/include/core_cm4.h similarity index 98% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm4.h rename to lib/sdk/components/toolchain/cmsis/include/core_cm4.h index 01cb73b..7002e4e 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm4.h +++ b/lib/sdk/components/toolchain/cmsis/include/core_cm4.h @@ -1796,7 +1796,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ - for(;;) /* wait until reset */ + for (;;) /* wait until reset */ { __NOP(); } diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm7.h b/lib/sdk/components/toolchain/cmsis/include/core_cm7.h similarity index 98% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm7.h rename to lib/sdk/components/toolchain/cmsis/include/core_cm7.h index 20963c1..92054b8 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm7.h +++ b/lib/sdk/components/toolchain/cmsis/include/core_cm7.h @@ -2004,7 +2004,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ - for(;;) /* wait until reset */ + for (;;) /* wait until reset */ { __NOP(); } @@ -2143,7 +2143,7 @@ __STATIC_INLINE void SCB_EnableDCache (void) __schedule_barrier(); #endif } while (ways--); - } while(sets--); + } while (sets--); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ @@ -2183,7 +2183,7 @@ __STATIC_INLINE void SCB_DisableDCache (void) __schedule_barrier(); #endif } while (ways--); - } while(sets--); + } while (sets--); __DSB(); __ISB(); @@ -2218,7 +2218,7 @@ __STATIC_INLINE void SCB_InvalidateDCache (void) __schedule_barrier(); #endif } while (ways--); - } while(sets--); + } while (sets--); __DSB(); __ISB(); @@ -2253,7 +2253,7 @@ __STATIC_INLINE void SCB_CleanDCache (void) __schedule_barrier(); #endif } while (ways--); - } while(sets--); + } while (sets--); __DSB(); __ISB(); @@ -2288,7 +2288,7 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void) __schedule_barrier(); #endif } while (ways--); - } while(sets--); + } while (sets--); __DSB(); __ISB(); diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmFunc.h b/lib/sdk/components/toolchain/cmsis/include/core_cmFunc.h similarity index 97% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmFunc.h rename to lib/sdk/components/toolchain/cmsis/include/core_cmFunc.h index ca319a5..cb1ebf8 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmFunc.h +++ b/lib/sdk/components/toolchain/cmsis/include/core_cmFunc.h @@ -31,7 +31,6 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmInstr.h b/lib/sdk/components/toolchain/cmsis/include/core_cmInstr.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmInstr.h rename to lib/sdk/components/toolchain/cmsis/include/core_cmInstr.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmSimd.h b/lib/sdk/components/toolchain/cmsis/include/core_cmSimd.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmSimd.h rename to lib/sdk/components/toolchain/cmsis/include/core_cmSimd.h diff --git a/lib/sdk/components/toolchain/cmsis/include/core_sc000.h b/lib/sdk/components/toolchain/cmsis/include/core_sc000.h new file mode 100644 index 0000000..43ec9c3 --- /dev/null +++ b/lib/sdk/components/toolchain/cmsis/include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/sdk/components/toolchain/cmsis/include/core_sc300.h b/lib/sdk/components/toolchain/cmsis/include/core_sc300.h new file mode 100644 index 0000000..420a655 --- /dev/null +++ b/lib/sdk/components/toolchain/cmsis/include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/gcc_startup_nrf52840.S b/lib/sdk/components/toolchain/gcc/gcc_startup_nrf52840.S similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/gcc_startup_nrf52840.S rename to lib/sdk/components/toolchain/gcc/gcc_startup_nrf52840.S diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_common.ld b/lib/sdk/components/toolchain/gcc/nrf52_common.ld similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_common.ld rename to lib/sdk/components/toolchain/gcc/nrf52_common.ld diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_xxaa.ld b/lib/sdk/components/toolchain/gcc/nrf52_xxaa.ld similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_xxaa.ld rename to lib/sdk/components/toolchain/gcc/nrf52_xxaa.ld diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf5x_common.ld b/lib/sdk/components/toolchain/gcc/nrf5x_common.ld similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf5x_common.ld rename to lib/sdk/components/toolchain/gcc/nrf5x_common.ld diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52840.c b/lib/sdk/components/toolchain/system_nrf52840.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52840.c rename to lib/sdk/components/toolchain/system_nrf52840.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52840.h b/lib/sdk/components/toolchain/system_nrf52840.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52840.h rename to lib/sdk/components/toolchain/system_nrf52840.h diff --git a/lib/sdk/readme.md b/lib/sdk/readme.md new file mode 100644 index 0000000..17d1ecd --- /dev/null +++ b/lib/sdk/readme.md @@ -0,0 +1 @@ +SDK version is 14.2.0_17b948a diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.c b/lib/sdk11/components/ble/ble_services/ble_dfu/ble_dfu.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.c rename to lib/sdk11/components/ble/ble_services/ble_dfu/ble_dfu.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.h b/lib/sdk11/components/ble/ble_services/ble_dfu/ble_dfu.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.h rename to lib/sdk11/components/ble/ble_services/ble_dfu/ble_dfu.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.c b/lib/sdk11/components/ble/ble_services/ble_dis/ble_dis.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.c rename to lib/sdk11/components/ble/ble_services/ble_dis/ble_dis.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.h b/lib/sdk11/components/ble/ble_services/ble_dis/ble_dis.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.h rename to lib/sdk11/components/ble/ble_services/ble_dis/ble_dis.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.h b/lib/sdk11/components/ble/common/ble_srv_common.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.h rename to lib/sdk11/components/ble/common/ble_srv_common.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage.h b/lib/sdk11/components/drivers_nrf/pstorage/pstorage.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage.h rename to lib/sdk11/components/drivers_nrf/pstorage/pstorage.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage_raw.c b/lib/sdk11/components/drivers_nrf/pstorage/pstorage_raw.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage_raw.c rename to lib/sdk11/components/drivers_nrf/pstorage/pstorage_raw.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/ble_transport/hci_mem_pool_internal.h b/lib/sdk11/components/libraries/bootloader_dfu/ble_transport/hci_mem_pool_internal.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/ble_transport/hci_mem_pool_internal.h rename to lib/sdk11/components/libraries/bootloader_dfu/ble_transport/hci_mem_pool_internal.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.c b/lib/sdk11/components/libraries/bootloader_dfu/bootloader.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.c rename to lib/sdk11/components/libraries/bootloader_dfu/bootloader.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.h b/lib/sdk11/components/libraries/bootloader_dfu/bootloader.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.h rename to lib/sdk11/components/libraries/bootloader_dfu/bootloader.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.c b/lib/sdk11/components/libraries/bootloader_dfu/bootloader_settings.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.c rename to lib/sdk11/components/libraries/bootloader_dfu/bootloader_settings.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.h b/lib/sdk11/components/libraries/bootloader_dfu/bootloader_settings.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.h rename to lib/sdk11/components/libraries/bootloader_dfu/bootloader_settings.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_types.h b/lib/sdk11/components/libraries/bootloader_dfu/bootloader_types.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_types.h rename to lib/sdk11/components/libraries/bootloader_dfu/bootloader_types.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.c b/lib/sdk11/components/libraries/bootloader_dfu/bootloader_util.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.c rename to lib/sdk11/components/libraries/bootloader_dfu/bootloader_util.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.h b/lib/sdk11/components/libraries/bootloader_dfu/bootloader_util.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.h rename to lib/sdk11/components/libraries/bootloader_dfu/bootloader_util.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu.h b/lib/sdk11/components/libraries/bootloader_dfu/dfu.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu.h rename to lib/sdk11/components/libraries/bootloader_dfu/dfu.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_bank_internal.h b/lib/sdk11/components/libraries/bootloader_dfu/dfu_bank_internal.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_bank_internal.h rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_bank_internal.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc.h b/lib/sdk11/components/libraries/bootloader_dfu/dfu_ble_svc.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc.h rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_ble_svc.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc_internal.h b/lib/sdk11/components/libraries/bootloader_dfu/dfu_ble_svc_internal.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc_internal.h rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_ble_svc_internal.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_dual_bank.c b/lib/sdk11/components/libraries/bootloader_dfu/dfu_dual_bank.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_dual_bank.c rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_dual_bank.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init.h b/lib/sdk11/components/libraries/bootloader_dfu/dfu_init.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init.h rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_init.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init_template.c b/lib/sdk11/components/libraries/bootloader_dfu/dfu_init_template.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init_template.c rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_init_template.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_single_bank.c b/lib/sdk11/components/libraries/bootloader_dfu/dfu_single_bank.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_single_bank.c rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_single_bank.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport.h b/lib/sdk11/components/libraries/bootloader_dfu/dfu_transport.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport.h rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_transport.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_ble.c b/lib/sdk11/components/libraries/bootloader_dfu/dfu_transport_ble.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_ble.c rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_transport_ble.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_serial.c b/lib/sdk11/components/libraries/bootloader_dfu/dfu_transport_serial.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_serial.c rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_transport_serial.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_types.h b/lib/sdk11/components/libraries/bootloader_dfu/dfu_types.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_types.h rename to lib/sdk11/components/libraries/bootloader_dfu/dfu_types.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h b/lib/sdk11/components/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h rename to lib/sdk11/components/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_transport_config.h b/lib/sdk11/components/libraries/bootloader_dfu/hci_transport/hci_transport_config.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_transport_config.h rename to lib/sdk11/components/libraries/bootloader_dfu/hci_transport/hci_transport_config.h diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.c b/lib/sdk11/components/libraries/util/nrf_log.c similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.c rename to lib/sdk11/components/libraries/util/nrf_log.c diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.h b/lib/sdk11/components/libraries/util/nrf_log.h similarity index 100% rename from nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.h rename to lib/sdk11/components/libraries/util/nrf_log.h diff --git a/lib/sdk11/readme.md b/lib/sdk11/readme.md new file mode 100644 index 0000000..24931b8 --- /dev/null +++ b/lib/sdk11/readme.md @@ -0,0 +1 @@ +This bootloader is based on the non-secure one in the SDK version 11.0.0_89a8197. It still has some dependency/code that is dropped in the later sdk diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.c b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.c deleted file mode 100644 index c239cf1..0000000 --- a/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.c +++ /dev/null @@ -1,197 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/* Attention! -* To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile -* qualification listings, this section of source code must not be modified. -*/ - -#include "ble_srv_common.h" -#include -#include "nordic_common.h" -#include "app_error.h" -#include "ble.h" - -uint8_t ble_srv_report_ref_encode(uint8_t * p_encoded_buffer, - const ble_srv_report_ref_t * p_report_ref) -{ - uint8_t len = 0; - - p_encoded_buffer[len++] = p_report_ref->report_id; - p_encoded_buffer[len++] = p_report_ref->report_type; - - APP_ERROR_CHECK_BOOL(len == BLE_SRV_ENCODED_REPORT_REF_LEN); - return len; -} - - -void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii) -{ - p_utf8->length = (uint16_t)strlen(p_ascii); - p_utf8->p_str = (uint8_t *)p_ascii; -} - - -/**@brief Function for setting security requirements of a characteristic. - * - * @param[in] level required security level. - * @param[out] p_perm Characteristic security requirements. - * - * @return encoded security level and security mode. - */ -static inline void set_security_req(security_req_t level, ble_gap_conn_sec_mode_t * p_perm) -{ - - - BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm); - switch (level) - { - case SEC_NO_ACCESS: - BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm); - break; - case SEC_OPEN: - BLE_GAP_CONN_SEC_MODE_SET_OPEN(p_perm); - break; - case SEC_JUST_WORKS: - BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(p_perm); - break; - case SEC_MITM: - BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(p_perm); - break; - case SEC_SIGNED: - BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(p_perm); - break; - case SEC_SIGNED_MITM: - BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(p_perm); - break; - } - return; -} - - -uint32_t characteristic_add(uint16_t service_handle, - ble_add_char_params_t * p_char_props, - ble_gatts_char_handles_t * p_char_handle) -{ - ble_gatts_char_md_t char_md; - ble_gatts_attr_t attr_char_value; - ble_uuid_t char_uuid; - ble_gatts_attr_md_t attr_md; - ble_gatts_attr_md_t user_descr_attr_md; - ble_gatts_attr_md_t cccd_md; - - if (p_char_props->uuid_type == 0) - { - char_uuid.type = BLE_UUID_TYPE_BLE; - } - else - { - char_uuid.type = p_char_props->uuid_type; - } - char_uuid.uuid = p_char_props->uuid; - - memset(&attr_md, 0, sizeof(ble_gatts_attr_md_t)); - set_security_req(p_char_props->read_access, &attr_md.read_perm); - set_security_req(p_char_props->write_access, & attr_md.write_perm); - attr_md.rd_auth = (p_char_props->is_defered_read ? 1 : 0); - attr_md.wr_auth = (p_char_props->is_defered_write ? 1 : 0); - attr_md.vlen = (p_char_props->is_var_len ? 1 : 0); - attr_md.vloc = (p_char_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK); - - - memset(&char_md, 0, sizeof(ble_gatts_char_md_t)); - if ((p_char_props->char_props.notify == 1)||(p_char_props->char_props.indicate == 1)) - { - - memset(&cccd_md, 0, sizeof(cccd_md)); - set_security_req(p_char_props->cccd_write_access, &cccd_md.write_perm); - BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm); - - cccd_md.vloc = BLE_GATTS_VLOC_STACK; - - char_md.p_cccd_md = &cccd_md; - } - char_md.char_props = p_char_props->char_props; - - memset(&attr_char_value, 0, sizeof(ble_gatts_attr_t)); - attr_char_value.p_uuid = &char_uuid; - attr_char_value.p_attr_md = &attr_md; - attr_char_value.max_len = p_char_props->max_len; - if (p_char_props->p_init_value != NULL) - { - attr_char_value.init_len = p_char_props->init_len; - attr_char_value.p_value = p_char_props->p_init_value; - } - if (p_char_props->p_user_descr != NULL) - { - memset(&user_descr_attr_md, 0, sizeof(ble_gatts_attr_md_t)); - char_md.char_user_desc_max_size = p_char_props->p_user_descr->max_size; - char_md.char_user_desc_size = p_char_props->p_user_descr->size; - char_md.p_char_user_desc = p_char_props->p_user_descr->p_char_user_desc; - - char_md.p_user_desc_md = &user_descr_attr_md; - - set_security_req(p_char_props->p_user_descr->read_access, &user_descr_attr_md.read_perm); - set_security_req(p_char_props->p_user_descr->write_access, &user_descr_attr_md.write_perm); - - user_descr_attr_md.rd_auth = (p_char_props->p_user_descr->is_defered_read ? 1 : 0); - user_descr_attr_md.wr_auth = (p_char_props->p_user_descr->is_defered_write ? 1 : 0); - user_descr_attr_md.vlen = (p_char_props->p_user_descr->is_var_len ? 1 : 0); - user_descr_attr_md.vloc = (p_char_props->p_user_descr->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK); - } - if (p_char_props->p_presentation_format != NULL) - { - char_md.p_char_pf = p_char_props->p_presentation_format; - } - return sd_ble_gatts_characteristic_add(service_handle, - &char_md, - &attr_char_value, - p_char_handle); -} - - -uint32_t descriptor_add(uint16_t char_handle, - ble_add_descr_params_t * p_descr_props, - uint16_t * p_descr_handle) -{ - ble_gatts_attr_t descr_params; - ble_uuid_t desc_uuid; - ble_gatts_attr_md_t attr_md; - - memset(&descr_params, 0, sizeof(descr_params)); - if (p_descr_props->uuid_type == 0) - { - desc_uuid.type = BLE_UUID_TYPE_BLE; - } - else - { - desc_uuid.type = p_descr_props->uuid_type; - } - desc_uuid.uuid = p_descr_props->uuid; - descr_params.p_uuid = &desc_uuid; - - set_security_req(p_descr_props->read_access, &attr_md.read_perm); - set_security_req(p_descr_props->write_access,&attr_md.write_perm); - - attr_md.rd_auth = (p_descr_props->is_defered_read ? 1 : 0); - attr_md.wr_auth = (p_descr_props->is_defered_write ? 1 : 0); - attr_md.vlen = (p_descr_props->is_var_len ? 1 : 0); - attr_md.vloc = (p_descr_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK); - descr_params.p_attr_md = &attr_md; - - descr_params.init_len = p_descr_props->init_len; - descr_params.init_offs = p_descr_props->init_offs; - descr_params.max_len = p_descr_props->max_len; - descr_params.p_value = p_descr_props->p_value; - - return sd_ble_gatts_descriptor_add(char_handle, &descr_params, p_descr_handle); -} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error_weak.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error_weak.h deleted file mode 100644 index 551a431..0000000 --- a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error_weak.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#ifndef APP_ERROR_WEAK_H__ -#define APP_ERROR_WEAK_H__ - -/** @file - * - * @defgroup app_error Common application error handler - * @{ - * @ingroup app_common - * - * @brief Common application error handler. - */ - -/**@brief Callback function for asserts in the SoftDevice. - * - * @details A pointer to this function will be passed to the SoftDevice. This function will be - * called by the SoftDevice if certain unrecoverable errors occur within the - * application or SoftDevice. - * - * See @ref nrf_fault_handler_t for more details. - * - * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. - * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if - * unavailable. - * @param[in] info Optional additional information regarding the fault. Refer to each fault - * identifier for details. - * - * @remarks Function is implemented as weak so that it can be overwritten by custom application - * error handler when needed. - */ -#ifdef __CC_ARM - void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info); -#else -__WEAK void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info); -#endif - - -/** @} */ - -#endif // APP_ERROR_WEAK_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/documentation/license.txt b/nRF5_SDK_11.0.0_89a8197/documentation/license.txt deleted file mode 100644 index 2322a73..0000000 --- a/nRF5_SDK_11.0.0_89a8197/documentation/license.txt +++ /dev/null @@ -1,117 +0,0 @@ -This text contains two licenses (License #1, License #2). -License #1 applies to the whole SDK, except i) files including Dynastream copyright notices and ii) source files including BSD 3-clause license texts. -License #2 applies only to files including Dynastream copyright notices. -All must be read and accepted before proceeding. - - -License #1 - -License Agreement -Nordic Semiconductor ASA ("Nordic") -Software Development Kit - - -You ("You" or "Licensee") must carefully and thoroughly read this License Agreement ("Agreement"), and accept to adhere to this Agreement before downloading, installing and/or using any software or content in the Software Development Kit ("SDK") provided herewith. - -YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SDK, IN THIS CASE YOU AGREE THAT THE USE OF THE SDK CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS. - -IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SDK OR RELATED CONTENT. - - -1. Grant of License -Subject to the terms in this Agreement Nordic grants Licensee a limited, non-exclusive, non-transferable, non-sub licensable, revocable license ("License"): (a) to use the SDK as a development platform solely in connection with a Nordic Integrated Circuit ("nRF IC"), (b) to modify any source code contained in the SDK solely as necessary to implement products developed by Licensee that incorporate an nRF IC ("Licensee Product"), and (c) to distribute the SDK solely as implemented in Licensee Product. Licensee shall not use the SDK for any purpose other than specifically authorized herein. - -2. Title -As between the parties, Nordic retains full rights, title, and ownership of the SDK and any and all patents, copyrights, trade secrets, trade names, trademarks, and other intellectual property rights in and to the SDK. - -3. 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No Other Rights -Licensee shall use the SDK only in compliance with this Agreement and shall refrain from using the SDK in any way that may be contrary to this Agreement. - - -6. Fees -Nordic grants the License to the Licensee free of charge provided that the Licensee undertakes the obligations in the Agreement and warrants to comply with the Agreement. - - -7. DISCLAIMER OF WARRANTY -THE SDK IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED AND NEITHER NORDIC, ITS LICENSORS OR AFFILIATES NOR THE COPYRIGHT HOLDERS MAKE ANY REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR THAT THE SDK WILL NOT INFRINGE ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS. THERE IS NO WARRANTY BY NORDIC OR BY ANY OTHER PARTY THAT THE FUNCTIONS CONTAINED IN THE SDK WILL MEET THE REQUIREMENTS OF LICENSEE OR THAT THE OPERATION OF THE SDK WILL BE UNINTERRUPTED OR ERROR-FREE. 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Upon termination Licensee must promptly cease the use of the License and destroy all copies of the Licensed Technology and any other material provided by Nordic or its affiliate, or produced by the Licensee in connection with the Agreement or the Licensed Technology. - - -License #2 - -This software is subject to the ANT+ Shared Source License -www.thisisant.com/swlicenses -Copyright (c) Dynastream Innovations, Inc. 2015 -All rights reserved. - -Redistribution and use in source and binary forms, with or -without modification, are permitted provided that the following -conditions are met: - - 1) Redistributions of source code must retain the above - copyright notice,this list of conditions and the following - disclaimer. - - 2) Redistributions in binary form must reproduce the above - copyright notice, this list of conditions and the following - disclaimer in the documentation and/or other materials - provided with the distribution. - - 3) Neither the name of Dynastream nor the names of its - contributors may be used to endorse or promote products - derived from this software without specific prior - written permission. - -The following actions are prohibited: - - 1) Redistribution of source code containing the ANT+ Network - Key. The ANT+ Network Key is available to ANT+ Adopters. - Please refer to http://thisisant.com to become an ANT+ - Adopter and access the key. - - 2) Reverse engineering, decompilation, and/or disassembly of - software provided in binary form under this license. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND -CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE HEREBY -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; DAMAGE TO ANY DEVICE, LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. SOME STATES DO NOT ALLOW -THE EXCLUSION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES, SO THE -ABOVE LIMITATIONS MAY NOT APPLY TO YOU. diff --git a/nRF5_SDK_11.0.0_89a8197/documentation/release_notes.txt b/nRF5_SDK_11.0.0_89a8197/documentation/release_notes.txt deleted file mode 100644 index 09e8346..0000000 --- a/nRF5_SDK_11.0.0_89a8197/documentation/release_notes.txt +++ /dev/null @@ -1,3267 +0,0 @@ -nRF5 SDK v11.0.0 ----------------- -Release date: Week 10, 2016 - -Highlights: -- Combined SDK supporting both the nRF51 and the nRF52 Series -- Moved Peer Manager out of experimental -- Moved NFC libraries out of experimental and added support for low - power mode -- Added drivers for all nRF52 peripherals -- Added serialization of the S132 and S130 SoftDevices -- Added support for SoftDevices S130 v2.0.0, S132 v2.0.0, S212 v0.9.x, - and S332 v0.9.x -- Replaced the Enhanced ShockBurst library with a new implementation - (based on µESB) -- Included a critical MDK update (v8.5.0) -- Removed support for CMSIS Packs - -The following toolchains/devices have been used for testing and -verification: -- ARM: MDK-ARM version 5.16a -- GCC: GCC ARM Embedded 4.9 2015q1 -- IAR: IAR Workbench 7.30.4 - -Supported SoftDevices: -- S130 v2.0.0 -- S132 v2.0.0 -- S212 v0.9.x -- S332 v0.9.x - -Supported IC revisions: -- nRF51 IC revision 3 -- nRF52 IC revision 1 -- nRF52 Engineering C -- nRF52 Engineering A and Engineering B (see Compatibility) - -Supported boards: -- PCA10028 -- PCA10031 -- PCA10036 (see Compatibility) -- PCA10040 (see Compatibility) -- PCA20006 (only for beacon examples) -For other devices and boards, see the SDK documentation, section -"Using the SDK with other boards". - -Compatibility: -The SoftDevices that are supported in this SDK are not compatible -out-of-the-box with nRF52 Engineering A and Engineering B (the -IC revisions present on all versions of PCA10036 and on PCA10040 -v0.9.0). -However, you can use the latest SoftDevices on Engineering A and B -nRF52 chips for development purposes if you implement the -workaround for anomaly 73 (TIMER: Event lost, see -http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52/dita/nrf52/errata.html). - -*** New features -**************** - -** Drivers and libraries ** -- Added a COMP driver (nRF52 only) - -** BLE ** -- Extended the Peer Manager functionality: - - Added an additional data unit (Peer Rank) that can be used for - tracking which bonds are most (and least) recently used - - Added support for LE Secure Connections in Peer Manager - (experimental) -- Added an example application for LE Secure Connections (experimental, - support for Keil5, IAR, and GCC only) - -** ANT ** -- Added new examples (experimental): - - Advanced Burst - - Asynchronous Transmitter - - Continuous Scanning Controller - - Debug Demo - - IO Demo - - Message Types - - Search Sharing - - Search Uplink -- ANT OTA bootloader application now uses the SoCLibrary API to perform - NVIC operations instead of direct operations -- Added multiprotocol examples for the S332 SoftDevice: - - Heart Rate Monitor Relay Application - - Shared Channels (experimental) - -** Serialization ** -- Added serialization of the S130 and S132 v2.0.0 SoftDevices - -** NFC ** -- Added a generic NDEF message parser that can parse NDEF messages to - the format that is used by the generic NFC NDEF message builder -- Added a module and example for creating NDEF text records -- Added and modified NFC pairing examples (experimental): - - HID Keyboard Application with BLE pairing using NFC (new) - - Heart Rate Application with BLE pairing using NFC (improved user - experience) - -** Proprietary ** -- Added a Low Power Transmitter/Receiver example for ESB - -*** Changes -*********** - -** Overall ** -- Support for CMSIS Packs has been removed. The SDK is delivered as zip - file only. - -** Drivers and libraries ** -- The MSB and LSB macros have been renamed to MSB_32 and LSB_32. Code - using these macros should be changed to use either the 16- or the - 32-bit variant. - -** BLE ** -- Multi-instance handling of Service client modules has been greatly - improved. The client examples now handle service discovery in the main - application context. The main application context must manage which - client instance belongs to which connection link. -- The Multi-link Example has been modified to demonstrate multiple - client instances in a better way. -- The ble_app_multilink_peripheral example has been removed. - ble_app_blinky now acts as the peripheral for ble_app_multilink_central. -- Heart Rate Application with RTX: Support for nRF52 has been removed. -- The Peer Manager is no longer experimental. -- The following BLE examples now use Peer Manager: - - Central: - Running Speed and Cadence Collector (ble_app_rscs_c) - - Central and Peripheral: - BLE Relay (ble_app_hrs_rscs_relay) - BLE LE Secure Connections Multirole (ble_app_multirole_lesc) - - Peripheral: - Alert Notification (ble_app_alert_notification) - Proximity (ble_app_proximity) - Glucose (ble_app_gls) - HID Keyboard Application with BLE pairing using NFC (experimental_ble_app_hids_keyboard_pairing_nfc) -- The behavior of Peer Manager and Device Manager has changed to reject - pairing requests from already bonded peer centrals. -- Several BLE peripheral examples now support the S332 SoftDevice. -- Minor bugfixes in DFU. - -** ANT ** -- The ANT bootloader was aligned to MBR version 2.0.0. -- The following ANT examples now support the S332 SoftDevice - (experimental): - - ANT Bootloader/DFU - - Message Types - -** NFC ** -- The Adafruit Tag Reader Example has been extended to show added NDEF - parsing functionality. -- The NFC Type 2 Tag HAL was improved with a workaround for supporting - low power mode. - -** Proprietary ** -- A new implementation of the Enhanced ShockBurst (ESB) protocol - supporting both nRF51 and nRF52 has been added. - -*** Fixed issues -**************** - -** Drivers and libraries ** -- GPIOTE: Fixed the problem of lost events in low-accuracy sense toggle - mode -- SAADC: Added functionality to use one AIN with multiple channels -- UART: Fixed a glitch on TX pin when initializing the driver -- UART: Fixed the problem that TX bytes were sent in wrong order in - app_uart_fifo - -** BLE ** -- Removed a vulnerability in Peer Manager and Device Manager that would - allow malicious attackers to overwrite the bonding information of a - bonded device - -** ANT ** -- Fixed the handling of send-until-success request types in the ANT - request controller -- Fixed an ant_evt_t structure member alignment bug - -** NFC ** -- Fixed the NFC examples to work when the UART logger is enabled -- Fixed a buffer leakage bug in the module for creating - application/vnd.bluetooth.le.oob records - -*** Known issues -**************** - -** Drivers and libraries ** -- Using the NVIC API directly and not through a SoftDevice causes - problems, especially when NVIC_EnableIRQ or NVIC_DisableIRQ are called - from critical sections. - -** BLE ** -- All BLE examples have been tested only on PCA10028 and PCA10040. -- BLE Examples that use pairing are incompatible with examples in SDK - version 6.1 and earlier that do not use pairing. - -** ANT ** -- Previous versions of the ANT DFU example are incompatible with the ANT - S212/S332 SoftDevices version 0.9.x. - -** NFC ** -- NFCT requires using TIMER4 on nRF52832. - -** FPU ** -- When the FPU is in use, it triggers the FPU_IRQn interrupt when one of - the six exception flags (IDC, IXC, UFC, OFC, DZC, IOC) is set. - The FPU interrupt will always set the pending flag (even if the - interrupt is not enabled), irrespective of whether the user is - interested in the exception bit. - The pending flag then prevents the SoftDevice from going into low - power mode when sd_app_evt_wait() is called. - Therefore, always clear the exception bits and the pending interrupt - before calling sd_app_evt_wait(). See the code below for an example - implementation. - FPU exception bit definition: - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/BABBFJEC.html - Example code: - { - // Set bit 7 and bits 4..0 in the mask to one (0x ...00 1001 1111) - #define FPU_EXCEPTION_MASK 0x0000009F - - ... - /* Clear exceptions and PendingIRQ from the FPU unit */ - __set_FPSCR(__get_FPSCR() & ~(FPU_EXCEPTION_MASK)); - (void) __get_FPSCR(); - NVIC_ClearPendingIRQ(FPU_IRQn); - - /* Call SoftDevice Wait For event */ - error_code = sd_app_evt_wait(); - } - - -======================================================================== - -nRF5 SDK v11.0.0-2.alpha ------------------------- -Release date: Week 51, 2015 - -Highlights: -- Common SDK supporting both the nRF51 and the nRF52 Series -- Added support for SoftDevices S130 v2.0.0, S132 v2.0.0, and S212 v0.5.1 -- Permanently removed support for SoftDevices S110 and S120 -- Temporarily removed support for ANTBLE SoftDevices -- Enhanced Peer Manager and FDS modules -- Enhanced DFU module -- Configured nrf_log to use UART by default -- Added HardFault handler -- Added drivers for nRF52 peripherals: nrf_drv_i2s, nrf_drv_pdm, - nrf_drv_pwm -- Enhanced drivers to work for both nRF51 and nRF52: nrf_drv_twi, - nrf_drv_spi, nrf_drv_uart, nrf_drv_timer, nrf_drv_ppi, nrf_drv_clock -- Added FreeRTOS and RTX support for nRF52 -- Added NFC modules: Type 2 Tag parser, generic NDEF message builder, - new NFC records and messages -- Added support for Adafruit PN532 NFC shield to provide NFC Forum - Device (Poller) functionality -- Improved support for NFC: enhanced NFC Type 2 Tag library and - Connection Handover module - -The following toolchains/devices have been used for testing and -verification: -- ARM: MDK-ARM version 5.16a -- GCC: GCC ARM Embedded 4.9 2015q1 -- IAR: IAR Workbench 7.30.4 -- Windows XP SP3 32-bit -- Windows 7 SP1 64-bit -- Windows 8.1 - -Supported SoftDevices: -- S130 v2.0.0-7.alpha -- S132 v2.0.0-7.alpha -- S210 v5.0.0 -- S212 v0.5.1.alpha - -Supported boards: -- PCA10028 -- PCA10031 -- PCA10036 -- PCA10040 -- PCA20006 (only for beacon examples) -- Dynastream's N5DK1 (only for ANT examples) - -For other devices and boards, see the SDK documentation, section "Using -the SDK with other boards". - - -Drivers and libraries: - - New features: - - Added driver and example for PWM peripheral (nrf_drv_pwm). - - Added driver and example for I2S peripheral (nrf_drv_i2s). - - Added driver for PDM peripheral (nrf_drv_pdm). - - Enhanced nrf_drv_twi and nrf_drv_spi to support AUTOLOG and - triggering transfers from PPI. - - Added double buffering of RX buffers to nrf_drv_uart. - - Extended nrf_drv_timer to support more compare channels and low - power counter mode in nRF52. - - Extended nrf_drv_ppi API to support forks. - - Added support for FreeRTOS and RTX on nRF52. - - Simplified SPI and SPIS examples. - - Fixed issues: - - In certain cases, FreeRTOS on nRF51 kept interrupts disabled after - context switch (see https://devzone.nordicsemi.com/question/57993/tickless-freertos-in-sdk-100-app_uart). - - Known issues: - - The FreeRTOS nRF51 port has a wrong assertion during system startup. - If you are using assertions, you can safely ignore it. Alternatively, - comment out line 188 in port_cmsis.c. - - Changes: - - Enhanced nrf_drv_clock driver (asynchronous clock management). - - -Serialization: - - - Work in progress; not included in this release. - - -ANT: - - New features: - - Added support for the S212 SoftDevice v0.5.1.alpha. - - Added ANT DFU support for nRF52. - - Known issues: - - When using the ANT OTA Updater v1.2. for nRF52, there is a flash - memory address limitation of 0x40000 (256 KB) for the application. - - -BLE: - - Changes: - - All BLE examples have been tested only on PCA10028 and PCA10040. - - The S13x SoftDevice v2.0.0-7.alpha is configurable, which leads to a - variable RAM setup: - - Added a macro to the softdevice_handler module to check the RAM - configuration against the SoftDevice parameters. - - Added a wrapper function for the sd_enable function to the - softdevice_handler module, which can output the required RAM - start address if the one passed to the SoftDevice is not - correct. - - DFU: - - Added an experimental nRF52 bootloader. - - Updated the SoftDevice initalization according to API changes in - S132 v2.0.0-7.alpha. - - Updated to MBR version v2.0.0-1 alpha. - - Introduced nrf_log as default logging module (UART) in all BLE - examples. - - Peer Manager & FDS have received incremental improvements and bug - fixes. - - Known issues: - - In the HRS/RSCS Relay example, button presses do not have any effect. - - ble_app_cts_c requires an increased UART_TX_BUF_SIZE. The size can be - set in nrf_log.c. - - DTM for nRF52 does not support long packets according to the - Bluetooth 4.2 specification. - - Inconsistent behavior in DFU with devices running Android v6.0.1. - - The BLE and serial DFU examples do not work when using CMSIS Packs. - Use the zip version of the SDK instead. - - -NFC: - - New features: - - Added a Type 2 Tag parser. - - Added a generic NFC NDEF message builder (the builder is used to - implement all specific records and messages). - - Added modules to create Windows LaunchApp records, Android - Application Records, and common application launch messages. Added - an associated example. - - Ported the Adafruit NFC library for the Adafruit PN532 Shield, which - provides NFC Forum Device capabilities. Added an associated example - to read tags. - - Added modules to create application/vnd.bluetooth.le.oob records, - application/vnd.bluetooth.ep.oob records, ac records, Hs records, - and BLE pairing messages. - - Changes: - - Improved the NFC Type 2 Tag library: tested and power-optimized the - library and enhanced it with RTT logger capability. - - Re-implemented NFC URI record and message. Refactored the associated - example. - - Enhanced and re-implemented the NFC Connection Handover solution - (pairing using NFC). - - Re-implemented the BLE NFC pairing example. - - Known issues: - - NFC examples do not work when UART logger is enabled. - - -======================================================================== - -nRF51 SDK v10.0.0 ------------------ -Release date: Week 46, 2015 - -Highlights: - - New BLE Peer Manager (experimental), replacement for the BLE Device - Manager - - FreeRTOS support - - New ANT modules, additional examples, and new and expanded ANT+ - profiles - - Support for Dynastream's N5 Starter Kit - - Three new BLE Services - - Precompiled HEX files - -The following toolchains/devices have been used for testing and -verification: - - ARM: MDK-ARM version 5.14.0.0 and 5.16a - - GCC: GCC ARM Embedded 4.9 2015q1 - - IAR: IAR Workbench 7.30.4 - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - - Windows 8.1 - -Supported SoftDevices: - - S110 v8.0.0 - - S120 v2.1.0 - - S130 v1.0.0 - - S210 v5.0.0 - - S310 v3.0.0 - -Supported boards: - - PCA10028 - - PCA10031 - - Dynastream's N5DK1 (only for ANT examples) - - For other devices and boards, see the SDK documentation, section "Using - the SDK with other boards". - -Changes: - - Drivers and libraries: - New features: - - Ported FreeRTOS to run on nRF51. Added two FreeRTOS examples: one - to run on bare metal and one running a BLE HRS example using the - S110 and S130 SoftDevices. - - Added a TWI transaction manager module for managing access to an - I2C bus. Added an example that uses this module to control two - sensors on the same I2C bus. - - Added an example that shows how to use the TWI driver. - - Added a low-power PWM module (software-controlled low-accuracy - PWM). Added an example that shows how to use this module. - - Added an LED softblink module that uses the low-power PWM. Added - an example that shows how to use this module. - - Ported app_uart to use the UART driver and moved it to the - libraries folder. - - Ported app_gpiote to use the GPIOTE driver. - - Added nrf_log, a logging module that supports printf and that can - use either UART or SEGGER RTT as transport medium. - Fixed issues: - - Mailbox module moved out of serialization. - - Bug fixes in app_timer module. - - App_timer module no longer requires to define the number of - timers used in the application. - - Bug fixes in PWM module. - Changes: - - FIFO library: Extended APIs for multi-byte read and write to the - FIFO. - - Memory Manager module: - - Extended number of block categories to 7 (from 3). - - More RAM-efficient management of memory blocks. - - Added a diagnostic function to help determine the right - configuration needed for the application. - - Serialization: - New features: - - Added a command for resetting the connectivity chip. - - ANT: - New features: - - Added the following new ANT modules: - - ant_encryption - - ant_key_manager - - ant_search_config - - Extended/changed the following existing ANT modules: - - ant_channel_config - - ant_stack_config - - ant_state_indicator - - Refactored the ANT/ANT+ examples and profiles to make them look more - similar to the BLE profiles and examples: - - The following ANT+ profiles have been extracted and extended: - Bicycle Power (ant_bpwr), Bicycle Speed & Cadence (ant_bsc), - Stride Based Speed & Distance (ant_sdm) - - All ANT+ examples have been refactored to use extracted - profiles. - - All ANT+/ANT examples have been refactored to use created - modules. - - Added three new ANT examples: - - ant_scalable - - ant_scalable_encrypted - - ant_scan_and_forward - - BLE: - - Added an experimental module named Peer Manager. This module will - eventually replace the existing Device Manager. The new Peer Manager - improves on the Device Manager in multiple ways, mainly by - supporting concurrent central and peripheral connections. - - Added an experimental flash memory module named Flash Data Storage - (FDS), which greatly reduces the need for time-consuming write and - clear operations. When using FDS, data can be arbitrarily long or - short (within about a page). All pieces of data are tagged with - types, which makes it easy to version data. - - Updated the experimental HRS/RSCS Relay example: - - It now uses the new Peer Manager instead of the Device Manager. - Therefore, it now supports bonding in both central and peripheral - roles. - - It uses the new nrf_log module, which can use SEGGER RTT. - - Removed the app_s130_demo example. - - Added an experimental example supporting the Eddystone beacon - format. - - Added the BLE Connection State module, which keeps track of certain - states of each connection (for example, whether it is encrypted) and - can also keep track of user-defined states. - - Added the Mapped Flags module, which keeps track of flags that are - mapped to keys. It is used by the BLE Connection State module. - - Added ble_gatt_db.h (containing a GATT service structure) and - modified ble_db_discovery module to use it. - BLE Services: - - Updated the Bluetoothds_template application (experimental) to be - compatible with Bluetooth Developer Studio v1.0 and the Nordic - Semiconductor NRF5X v1.1.8 plugin. - - Added three new services: - - Location Navigation Service (experimental) - - Proprietary LED Button Service (experimental) - - Nordic UART Client Service (experimental) - -Fixed issues: - - App_pwm occasionally gives inverted signal. - -Known issues: - - Device Manager is not supported in multi-role S130 operation. - - Device Manager works in peripheral or central only operation on - S130. This must be decided at compile time. - - The DFU over BLE example has been tested to work with a minimum - connection interval of 11.25 ms. The application cannot handle - connection intervals lower than 11.25 ms and may undergo a system - reset in the middle of a firmware update. - Workaround: If you face unexpected disconnects during the firmware - update process, consider increasing the connection - interval used by the master. - - The old manual procedure for testing buttonless DFU, as specified in - the documentation, can lead to the DFU process hanging or returning - an error when used with Master Control Panel 3.8 and newer. - - Bootloader binaries (.bin files) generated with the GCC makefile - should not be used. Instead, generate the bootloader bin files using - nrfutils, found on GitHub. - -======================================================================== - -nRF52 SDK v0.9.2 ----------------- -Release date: Week 42, 2015 - -This is an amendment to nRF52 SDK v0.9.1. - -Highlights: - - New targets to enable the two near field communication (NFC) - examples to run on the new PCA10040 development board with - nRF52832 IC rev. Engineering B. - -Libraries: - - Extended the NFC HAL layer of the NFC library to support the NFCT - peripherial for both the chip version delivered with the nRF52 - Preview Development Kit (Engineering A: QFAA-AA0, QFAA-AC0, - CGAA-AA0) and the chip version delivered with the nRF52 Development - Kit (Engineering B: QFAA-BA0, QFAA-BB0, CHAA-AA0, CHAA-AB0). - -Examples: - - Added PCA10040 as target bord for the following examples: - - Heart Rate Example with pairing over NFC - - NFC URL Record Application - -Known issues/workarounds: - - To use the software workarounds implemented for PCA10036 (part - of nRF52 Preview Development Kit), globally define - HAL_NFC_ENGINEERING_A_FTPAN_WORKAROUND in your project. - - The TIMER4 peripheral is used to implement one of the workarounds - for PCA10036. This workaround is not used for PCA10040. - - The ble_app_hrs_pairing_nfc example is unable to wake up from - system off. - -======================================================================== - -nRF52 SDK v0.9.1 ----------------- -Release date: Week 29, 2015 - -This is an amendment to nRF52 SDK v0.9.0. - -Highlights: - - Support for near field communication (NFC) - -Libraries/Services: - - Added a library that supports Type 2 NFC-A tag functionality in - read-only state - - Added a module to generate NFC NDEF messages for BLE pairing over NFC - - Added a module to generate NFC NDEF messages with an URI record type - - Extended the ble_advdata module - -Examples: - - Added ble_app_hrs_pairing_nfc example that demonstrates pairing over - NFC (with S132 SoftDevice) - - Added record_url NFC example that demonstrates exposing a URL record - (without SoftDevice) - -Limitations: - - The current version of the NFC library uses TIMER4. - - The ble_app_hrs_pairing_nfc example has been tested only with Samsung - Galaxy S6. - - If the path to the SDK directory is too long, compilation in Keil fails. - To work around this problem, move the SDK higher in the folder tree - or use shorter folder names. - -======================================================================== - -nRF51 SDK v9.0.0 ----------------- -Release Date: Week 28, 2015 - -Highlights: - - Support for S210 SoftDevice v5.0.0 - - Support for S310 SoftDevice v3.0.0 - - Documentation moved to Infocenter - - DFU Signing using Elliptic Curve Cryptography added as experimental - - Available in the zip file only - - Running Speed and Cadence relay example showing concurrent - central/peripheral functionality of S130 - -The following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM version 5.14.0.0 - - GCC: GCC ARM Embedded 4.9 2015q1 - - IAR: IAR Workbench 7.20 - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - - Windows 8.1 - -Supported SoftDevices: - - S110 v8.0.0 - - S120 v2.1.0 - - S130 v1.0.0 - - S210 v5.0.0 - - S310 v3.0.0 - -Supported boards: - - PCA10028 - - PCA10031 - - For other devices and boards, see the SDK documentation, section - "Using the SDK with other boards". - -Changes: - - - Flash access module has been refactored (pstorage). - - ANT: - - Both the S310 and the S210 SoftDevices now support an extended - number of ANT channels (16). - - - Libraries: - - Heart Rate Monitor Profile - - ANT stack configuration - - ANT channel configuration - - ANT channel state indicator - - ANT pulse simulator - - Examples: - - The ANT HRM examples have been refactored. - - The Bicycle Power examples (ant_bicycle_pwr) support S310. - - ANT + BLE (S310): - The following examples were added: - - Bluetooth LE and ANT combined heart rate example (ble_ant_app_hrm). - - Experimental ANT Shared Channels (experimental_ant_shared_channel_master_to_master, - experimental_ant_shared_channel_slave). - - BLE: - - Advertising module has a new mode: Low Duty Cycle Directed Advertising. - - Running Speed and Cadence Client added as experimental. - - Bluetooth Developer Studio template added as experimental. - - Heart Rate Sensor example (ble_app_hrs) supports S310. - - Running Speed and Cadence example (ble_app_rscs) supports S310. - - Combined Peripheral and Central example added as experimental. - - DFU Signing using Elliptic Curve Cryptography added as experimental - (using the same elliptic curve and hashing algorithm as Bluetooth - Low Energy 4.2 Secure Connections). - -Fixed issues: - - Pstorage now supports updates of bond split across two pages. - - Advertising module can be set to infinite time-out. - - Corrected clock source in BLE multiactivity beacon example. - - Serialization HCI transport layer: Receiving packet-buffer is not - freed while sending ACK or NACK. - -Known issues: - - Device Manager is not supported in multi-role S130 operation. - - Device Manager works in peripheral or central only operation on - S130. This must be decided at compile time. - - The DFU over BLE example has been tested to work with a minimum - connection interval of 11.25 ms. The application cannot handle - connection intervals lower than 11.25 ms and may undergo a system - reset in the middle of a firmware update. - Workaround: If you face unexpected disconnects during the firmware - update process, consider increasing the connection interval used - by the master. - - App_pwm occasionally gives inverted signal. - - The old manual procedure for testing buttonless DFU, as specified in - the documentation, can lead to the DFU process hanging or returning - an error when used with Master Control Panel 3.8 and newer. - -======================================================================== - -nRF52 SDK v0.9.0 ----------------- -Release date: 17.06.2015 - -Highlights: - - Support for PCA10036 board v1.0.0 with nRF52832 QFAAAA - - Support for S132 SoftDevice v1.0.0-3.alpha (hex included) - - Support for S212 SoftDevice v0.2.0-1.alpha - - Support for Keil5 without CMSIS Packs - - Support for GCC - - Same structure as nRF51 SDK v8.1.0 - - New peripheral drivers - - Documentation moved to Infocenter - -The following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM version 5.14.0.0 - - GCC: GCC ARM Embedded 4.9 2015q1 - - Windows 7 SP1 64-bit - -Supported SoftDevices: - - S132 v1.0.0-3.alpha - - S212 v0.2.0-1.alpha - -Supported boards: - - PCA10036 v1.0.0 - -Examples: - - Most examples are ported from nRF51 SDK v8.1.0 - - BLE examples run with the S132 SoftDevice - - ANT examples run with the S212 SoftDevice - - The following examples are included: - - BLE peripheral examples - - BLE central example - - New BLE combined central and peripheral example - - ANT examples - - HW peripheral examples - - New SAADC example - - New TWI master with TWI slave example - - BLE/serial DFU bootloader - - Direct Test Mode Application - -Drivers: - - Includes all drivers from nRF51 SDK v8.1.0 - - New drivers: - - SPI driver that supports SPI and SPIM - - UART driver that supports UART and UARTE - - SAADC HAL driver - - TWI slave driver - - SAADC driver - -Libraries/Services: - - Same functionality as for nRF51 SDK v8.1.0 - - The following libraries and services are included: - - BLE libraries - - BLE Services - - Transport Services - - Other libraries/components - -Known issues: - - Device might reset when a Bluetooth link layer procedure and flash operation happens in parallel. - - Inconsistent behavior with Nexus devices running Android v5.1.1, for example: - - DFU fails - - Link loss might reset the nRF52 device - (such behavior might occur with other devices as well) - - After a power cycle, a UART lockup between Segger J-Link and nRF52 might occur - - Before a serial DFU operation or DTM can be executed, "nrfjprog --reset" must be run - -======================================================================== - -nRF51 SDK v. 8.1.1 ------------------- -This is a supplement to the nRF51 SDK v8.1.0 release notes. -This release does not include any code changes compared to nRF51 SDK v8.1.0., except for a minor addition that is described in the "Changes" section. - -Fixed issues: - - - Project does not compile if nrf_drv_ppi is used together with SoftDevice S110, S120 or S210. - Issue exists only in CMSIS PACK release. - -Changes: - - Released new SoftDevice packs: nRF_SoftDevice_S110.8.0.1, nRF_SoftDevice_S120.2.0.1 and - nRF_SoftDevice_S210.4.0.1-5 with updated nrf_sd_def.h. - -Supported SoftDevices: - - S110 8.0.0 - - S120 2.0.0 - - S130 1.0.0 - - S210 4.0.1 - -======================================================================== - -nRF51 SDK v8.1.0 ----------------- - -Highlights: - - Support for SoftDevice S130 v1.0.0 - - Serialization supporting SoftDevice S110, S120, and S130 - - ANCS updated and no longer in experimental state - - GCC updated to new version: ARMGCC 4.9 q1-2015 - - DFU example now has support for IAR and GCC - -The following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM version 4.72.10, 5.13.0.0, 5.14.0.0 - - GCC: gcc-arm-embedded 4.9 2015q1 - - IAR: IAR Embedded Workbench for ARM version 7.20.2 - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - - Windows 8.1 - -Supported devices: - - This SDK is optimized for IC revision 3. - For details, see the "nRF51 Series Compatibility Matrix" document (ATTN-51) available on - www.nordicsemi.com. - - Note 1: To run the ANT examples, you must use an nRF51422 device. - Note 2: Some of the examples using the SoftDevice will not fit on the 128 kB variant of the - chip. - -Supported SoftDevices: - - S110 8.0.0 - - S120 2.0.0 - - S130 1.0.0 - - S210 4.0.1 - -Supported boards: - - PCA10028 - - PCA10031 - - For other devices and boards, see the SDK documentation, section "Using the SDK with other - boards", or use SDK v6.x.x. - -Changes: - ANT + BLE (dual stack): - - Not included in this release due to conflicting interface between SoftDevice S310 and S110. Use SDK v7.2.0 for S310 support. - - S310 support will be reintroduced in a future release. - BLE: - - SoftDevices: - - Support for S130 v1.0.0. - - Serialization: - - Fully serialized S110, S120, and S130 API. - - Modules/Services: - - New button module (bsp_btn_ble) that enables functionality such as disconnect, turn off whitelist, go to sleep. - - Advertising module now supports scan response data - - Examples: - - ANCS example is no longer in experimental state. - Proprietary: - - IAR support for proprietary examples. - -Peripheral drivers & libraries: - - New peripheral drivers: TWI, SWI, and GPIOTE. - - New PWM driver. PWM example updated to use the driver. - -Fixed issues: - - NRFFOSDK-2044: Fixed issue in app_gpiote. - - NRFFOSDK-3855: Fixed issue in Current Time Service. - -Known issues: - - Device Manager is not supported in multirole S130 operation. - - Device Manager works in peripheral or central only operation on S130. This must be decided at compile time. - - The DFU over BLE example has been tested to work with a minimum connection interval of - 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may - undergo a system reset in the middle of a firmware update. - Workaround: If you face unexpected disconnects during the firmware update process, consider - increasing the connection interval. - - - ANT: - - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time. - - - BLE: - - A few APIs of the Device Manager are not implemented. Also, documentation providing - examples of how the API can be used is missing. - - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two - pages. - - - Proprietary: - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box - with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy - Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and - channel tables require adjustment. - - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the - nrf_gzll_set_timeslot_period() function in the nRF51 projects - (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the - nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v8.0.0 ----------------- - -Highlights: - - Support for the latest S110, S120, and S130 SoftDevices. (S310 is not supported.) - - SoftDevices included in the SDK. - - Greatly increased driver and HAL coverage. - - New service client and profile example: Current Time Service/Time Profile. - - IAR support for most examples. - -The following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.72.10, 5.13.0.0, 5.14.0.0 - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: IAR Embedded Workbench for ARM version 7.20.2 - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - - Windows 8.1 - -Supported devices: - - This SDK is optimized for IC revision 3. - For details, see the "nRF51 Series Compatibility Matrix" document (ATTN-51) available on - www.nordicsemi.com. - - Note 1: To run the ANT examples, you must use an nRF51422 device. - Note 2: Some of the examples using the SoftDevice will not fit on the 128 kB variant of the - chip. - -Supported SoftDevices: - - S110 8.0.0 - - S120 2.0.0 - - S130 0.9.0-1.alpha - - S210 4.0.1 - -Supported boards: - - PCA10028 - - PCA10031 - - For other devices and boards, see the SDK documentation, section "Using the SDK with other - boards", or use SDK v6.x.x. - -Changes: - Toolchain/IDE: - - The nRF51 SDK now supports the following toolchains in most examples: - - Keil 5.14 (with packs) - - Keil 5.14 (without packs) - - Keil 4.72.10 - - ARM GCC 4.7 2013q1 - - IAR 7.20.2 - - The supported SoftDevices are now included in the SDK and can be flashed directly from - Keil, as a separate target. - - ANT + BLE (dual stack): - - Removed support for the S310 SoftDevice for BLE API compatibility reasons. For support, - use SDK v7.2.0. - - BLE: - - SoftDevices: - - The SDK now supports the S110 SoftDevice v8.0.0. - - The SDK now supports the S120 SoftDevice v2.0.0. - - The SDK now supports the S130 SoftDevice v0.9.0-1.alpha. - - Serialization: - - Serialization support has been removed. For support, use SDK v7.2.0 with appropriate - SoftDevices. - - Modules/Services: - - Added a new advertising module (ble_advertising) that provides automatic handling of - directed/fast/slow advertising, with and without whitelist. - - Nordic UART Service (ble_nus), detached from the UART over BLE Example. - - Added Current Time Service Client (ble_cts_c). - - Service Changed characteristic has been implemented for DFU, so that the indication is - sent when transitioning between application and bootloader. - - Implemented a mechanism for sharing of IRK and LTK from application to bootloader. - This allows for whitelist advertising and reconnection in DFU mode using existing - keys. - - Examples: - - The UART over BLE Example is no longer experimental. - - Added a Time Profile (ble_app_cts_c) example using the Current Time Service Client - implementation. - - Drivers/Libraries: - - Added hardware abstraction layer for the following hardware peripherals: - - ADC (Analog-to-digital converter) - - CLOCK (Clock management) - - LPCOMP (Low power comparator) - - PPI (Programmable Peripheral Interconnect) - - QDEC (Quadrature decoder) - - RNG (Random number generator) - - RTC (Real time counter) - - TIMER (Timer/counter) - - WDT (Watchdog timer) - - Added drivers for the following peripherals: - - CLOCK (Clock management) - - LPCOMP (Low power comparator) - - PPI (Programmable Peripheral Interconnect) - - QDEC (Quadrature decoder) - - RNG (Random number generator) - - RTC (Real time counter) - - TIMER (Timer/counter) - - WDT (Watchdog timer) - - Added modules: - - app_simple_timer (Simple timer based on TIMER1) - - Hardware Examples: - - Added: - - adc_simple (NRF_ADC) - - clock (NRF_DRV_CLOCK) - - lpcomp (NRF_DRV_LPCOMP) - - qdec (NRF_DRV_QDEC) - - simple_timer (APP_SIMPLE_TIMER) - - wdt (NRF_DRV_WDT) - - Modified: - - ppi (NRF_DRV_PPI) - - rng (NRF_DRV_RNG) - - rtc (NRF_DRV_RTC) - - timer (NRF_DRV_TIMER) - -Fixed issues: - - Fixed pstorage issue where different applications could write to the same page. - -Known issues: - - The DFU over BLE example has been tested to work with a minimum connection interval of - 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may - undergo a system reset in the middle of a firmware update. - Workaround: If you face unexpected disconnects during the firmware update process, consider - increasing the connection interval used by the master. - - - ANT: - - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time - - - BLE: - - A few APIs of the Device Manager are not implemented. Also, documentation providing - examples of how the API can be used is missing. - - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two - pages. - - - Proprietary: - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box - with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy - Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and - channel tables require adjustment. - - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the - nrf_gzll_set_timeslot_period() function in the nRF51 projects - (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the - nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v7.2.0 ----------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 5.12, 5.13 - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: no support in this release - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - - Windows 8.1 - -Supported devices - - This SDK is optimized for IC revision 3. - For details, see the "nRF51 Series Compatibility Matrix" document (ATTN-51) available on - www.nordicsemi.com. - - Note 1: To run the ANT examples, you must use an nRF51422 device. - Note 2: Some of the examples using the SoftDevice will not fit on the 128 kB variant of the - chip. - Note 3: Some of the serialization examples are too big to be compiled using the free version - of Keil. - -Supported SoftDevices: - - S110 7.1.0 - - S120 1.0.1 - - S130 0.5.0-1.alpha - - S210 4.0.1 - - S310 2.0.1 - -Supported boards: - - PCA10028 - - PCA10031 - - S110 connectivity support for Wavetek WT51822 - - For other devices and boards, see the SDK documentation, section "Using the SDK with other - boards", or use SDK v6.x.x. - -Changes: - - ANT: - - ANT-FS client example: Added callback to allow applications to execute custom code while - waiting for the burst to complete - - Major rework on ANT DFU example - - Added new ANT hub-2-hub/shared channel example - - Added S310 target support for DTM example - - BLE DFU is now supported for S310 - -Fixed issues: - - ANT: - - ANT-FS: Fixed bug with transfer sequence number error causing download failures - - ANT-FS: Fixed bug where upon exhaustion of m_retry, the link time-out has been mistakenly - disabled by a burst transfer - - Fixed issue in linker script for S310 - - Fixed memory corruption issue by using dedicated buffers for ANT and BLE stack events - respectively on S310 - - Fixed an issue where the ANT OTA Updater application v0.8 would not support hex files - with code size larger than 65535 bytes - -Known issues: - - SEGGER J-Link software has some issues with Keil. - See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for details. - - Keil 5.13 may issue a warning about missing packs even when all Nordic Semiconductor packs are - correctly installed. - - The DFU over BLE example has been tested to work with a minimum connection interval of - 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may - undergo a system reset in the middle of a firmware update. - Workaround: If you face unexpected disconnects during the firmware update process, consider - increasing the connection interval used by the master. - - - ANT: - - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time - - - BLE: - - NRFFOSDK-3135: S120 examples: RAM is limited to 16 kB, because S120 V1.0.1 does not - support utilizing the whole flash on the QFACAB chip - - NRFFOSDK-119: Only the ble_app_proximity_low_power and ble_app_hrs applications are power - optimized - - S120 examples: Flash clear operation may fail when connected. Impact of this in the S120 - examples is that if the peer loses the bond and a rebonding occurs, flash clear fails and - a DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. - - A few APIs of the Device Manager are not implemented. Also, documentation providing - examples of how the API can be used is missing. - - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two - pages. - - - Proprietary: - - Temperature example does not give sane output values. This is a hardware-related issue - described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box - with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy - Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and - channel tables require adjustment. - - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the - nrf_gzll_set_timeslot_period() function in the nRF51 projects - (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the - nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v7.1.0 ----------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 5.12 - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: no support in this release - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - - Windows 8.1 - -Tested with devices: - - nRF51422 QFACAB - - For others devices, use SDK 6.x.x. - -Supported SoftDevices: - - S110 7.1.0 - - S120 1.0.1 - - S130 0.5.0-1.alpha - - S210 4.0.1 - - S310 2.0.0 - -Supported boards: - - PCA10028 - - PCA10031 - - S110 connectivity support for Wavetek WT51822 - - For other boards, use SDK V6.x.x. - -Changes: - - Experimental support for over-the-air firmware update using the ANT radio protocol - - New experimental example ANT relay demo - - Support for S310 ANT+BLE version 2.0.0 - - Re-introduce Device Firmware Update via UART - - BLE DFU single bank support for bootloader+softdevice update - -Fixed issues: - - NRFFOSDK-3119 Fixed issue in app_timer where issuing start/stop from interrupt context caused long delays - -Known issues: - - - SEGGER J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. - Workaround: If you face unexpected disconnects during the firmware update process, consider increasing the connection interval used by the master - - ANT - - The OTA Updater application v.0.8 does not support hex files with code size larger than 65535 bytes. - - NRFFOSDK-366: ANT-FS host: download sometimes fails when downloading a large file - - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time - - BLE - - NRFFOSDK-3135: S120 examples: RAM is limited to 16 kB, because S120 V1.0.1 does not support utilizing the whole flash on the QFACAB chip - - NRFFOSDK-119: Only the ble_app_proximity_low_power and ble_app_hrs applications are power optimized - - S120 examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if the peer loses the bond and a rebonding occurs, flash clear fails and a DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. - - A few APIs of the Device Manager are not implemented. Also, documentation providing examples of how the API can be used is missing. - - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two pages. - - Proprietary: - - Temperature example does not give sane output values. This is a hardware-related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 7.0.1 ------------------- -This is a supplement to the nRF51 SDK v7.0.0 release notes. -This release does not include any code changes compared to nRF51 SDK v7.0.0, except for a minor addition that is described in the "Changes" section. - -Fixed issues: - - - Replaced DeviceFamilyPack v1.1.3, which has a wrong URL, with DeviceFamilyPack v1.1.4. - - Added a version field to Pack examples descriptions (NordicSemiconductor.nRF_Examples.pdsc). - - Added missing Nordic Semiconductor nRF51 MDK installer to the repository distribution (nRF51_SDK_x.x.x_xxxxxxx.zip). - - Added missing message sequence charts to the documentation. - - Changed incorrect description of supported SoftDevices in the release notes (see below for the correct list of supported SoftDevices). - -Changes: - - - Added all the register and bitfields for the SPIM peripheral (present in the nRF51802 device) to the HAL header files and replaced the pack nRF_Drivers v1.0.0 with nRF_Drivers v1.1.0. - -Supported SoftDevices: - - - S110 7.1.0 - - S120 1.0.1 - - S130 0.5.0-1.alpha - - S210 4.0.1 - -nRF51 SDK v7.0.0 ----------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 5.12 - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: no support in this release - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - - Windows 8.1 - -Tested with devices: - - - nRF51422 QFACAB - - For others devices, use SDK 6.x.x. - -Supported SoftDevices: - - - S110 7.1.0 - - S120 1.0.0 S120 1.0.1 - - S130 0.5.0-1.alpha - - S210 4.0.1 - - S310 1.0.0 - -Supported boards: - - - PCA10028 - - PCA10031 - - S110 connectivity support for Wavetek WT51822 - - For other boards, use SDK V6.x.x. - - - -Changes: - - - New folder structure - - Moved from installer to CMSIS pack format - - Added support for PCA100028 and PCA10031 - - Deprecated support for previous boards - - Added support for RTX tickless - - ANT - - Changed the ANT examples to support S210 SoftDevice v4.0.1 - - Added experimental Background Scanning example - - ANT + BLE (Dual stack) - - Removed support for S310 SoftDevice (for support, use SDK v6.x.x) - - BLE - - DFU: Added experimental mechanism to exchange encryption keys between application and BootLoader - - DFU: Added identification of firmware versions in the init packet - - Added experimental BLE nRF UART example - - Added experimental ANCS example - - Added experimental example demonstrating usage of S130 SoftDevice - - Added HRS example with RTX - - Proprietary - - Deprecated the following examples (for support, use SDK v6.x.x): - * ADNS2080 Mouse Sensor Driver Application - * Cherry8x16 Keyboard Application - * Button Debouncer Example - * nRF6350 Radio Configuration Example - * PWM Analyzer Example - * Motor Control Example - * TWI Master Example - - -Fixed issues: - - - NRFFOSDK-362: Reset button won't work after programming without cycling the target power - - NRFFOETT-205: The nRF51822 installer will not run if no C:\ drive exists - No installer - - NRFFOSDK-236: When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear - No installer - - NRFFOSDK-363: Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - -Known issues: - - - SEGGER J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. - Workaround: If you face unexpected disconnects during the firmware update process, consider increasing the connection interval used by the master - - ANT - - NRFFOSDK-366: ANT-FS host: download sometimes fails when downloading a large file - - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time - - BLE - - NRFFOSDK-3135: S120 examples: RAM is limited to 16 kB, because S120 V1.0.1 does not support utilizing the whole flash on the QFACAB chip - - NRFFOSDK-119: Only the ble_app_proximity_low_power and ble_app_hrs applications are power optimized - - S120 examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if the peer loses the bond and a rebonding occurs, flash clear fails and a DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. - - A few APIs of the Device Manager are not implemented. Also, documentation providing examples of how the API can be used is missing. - - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two pages. - - Proprietary: - - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Temperature example does not give sane output values. This is a hardware-related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 6.1.0 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 5.10.x/5.11.x - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: Embedded Workbench for ARM 6.60 - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - Windows 8.0/8.1 - -Tested with devices: - - - nRF51822 QFAAG0 - - nRF51822 QFAAGC - - nRF51822 QFAAFA - - nRF51422 QFAAE0 - - For others devices, use SDK 4.x.x - -Supported SoftDevices: - - - S110 7.0.0 - - S120 1.0.0 - - S210 3.0.0 - - S310 1.0.0 - -Supported boards: - - - PCA10000 v1.0 (Only for use with Master Emulator) - - PCA10000 v2.1.0 and 2.2.0 - - PCA10001 v2.1.0 and 2.2.0 - - PCA10004 v2.1.0 - - PCA10005 v2.1.0 and 2.2.0 - - PCA10003 v3.0.0 - - -Changes: - - - Added Keil 5 uvprojx files for most example projects. - - Extended GCC support, most examples now supplied with Makefiles. - - ANT - - None. - - ANT + BLE (Dual stack) - - None. - - BLE - - Device firmware upgrade with support for OTA update of SoftDevice, app and bootloader is no longer in experimental status. - - Buttonless bootloader mode, enter bootloader mode via over-the-air command (see ble_app_hrs example, using ble_app_hrs_dfu.uvproj project). - - Device manager (BLE bond handling) for S110 and S120 are no longer in experimental status. - - db_discovery module (for GATT database discovery) for S120 is no longer in experimental status. - - New reliable transport layer for S110 SoftDevice serialization. - - Example ble_app_hrs_c (heart rate collector) for S120 is no longer in experimental status. - - Example ble_app_multilink_central for S120 is no longer in experimental status. - - Example ble_app_multilink_peripheral for S110 is no longer in experimental status. - - Experimental examples ble_app_ancs and ble_app_multiactivity have been deprecated from this release. - - Experimental example ble_app_uart for pca10001 has been deprecated from this release. - - Proprietary - - None. - -Fixed issues: - - NRFFOSDK-2884: Fixed issue in app_button module (function app_button_is_pushed). - - NRFFOSDK-1341: Added missing characteristic in Blood Glucose application. - - NRFFOSDK-2859: Removed redundant code in Blood Glucose application. - - NRFFOSDK-2557: Fixed some doxygen documentation errors. - -Known issues: - - - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". - Solution: - - Write new flash algorithm settings to the uvopt file. - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Utilities". - Press "Settings" button to see flashing algorithms. - Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. - Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. - - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. - This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. - Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. - - ANT - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - S120 Examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if peer loses the bond and a re-bonding occurs, flash clear fails, and DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. - - Device manager has a few APIs unimplemented. Also documentation providing examples of how API can be used is missing. - - NRFFOSDK-2824: Device manager (pstorage) doesn't support update of bond split across two pages. - - Proprietary: - - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 6.0.0 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 5.10.x/5.11.x - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: Embedded Workbench for ARM 6.60 - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - Windows 8.0/8.1 - -Tested with devices: - - - nRF51822 QFAAG0 - - nRF51822 QFAAGC - - nRF51822 QFAAFA - - nRF51422 QFAAE0 - - For others devices, use SDK 4.x.x - -Supported SoftDevices: - - - S110 7.0.0 - - S120 1.0.0 - - S210 3.0.0 - - S310 1.0.0 - -Supported boards: - - - PCA10000 v1.0 (Only for use with Master Emulator) - - PCA10000 v2.1.0 and 2.2.0 - - PCA10001 v2.1.0 and 2.2.0 - - PCA10004 v2.1.0 - - PCA10005 v2.1.0 and 2.2.0 - - PCA10003 v3.0.0 - - -Changes: - - - Added partial support for Keil 5 uvprojx files. - - ANT - - None - - ANT + BLE (Dual stack) - - BLE - - New module device manager replaces bond manager for storing persistent data - - Experimental device manager support for s120 (BLE central) - - S110 serialization solution has been reworked - - 100% s110 BLE APIs are now serialized - - S110 support for application concurrent multiprotocol radio access - - Pstorage module: Added API for doing range updates - - Experimental: Device firmware upgrade now supports updating both SoftDevice and bootloader for s110 - - Proprietary - - Enhanced ShockBurst: Added nrf_esb_reuse_pid() function to API, giving "reuse payload" functionality. - - Gazell: Added "suspend" mode enabling sharing of radio and PPI. - - Gazell: HW resources are released when Gazell is being disabled or entering suspend mode. - - Gazell: HW resources are reconfigured when Gazell is being enabled or exiting from suspend mode. - -Fixed issues: - - - NRFFOSDK-2542 - SoftDevice related documentation for S110, S120 and S310 BLE stack is not consistent. When looking up SoftDevice application interface or message sequence charts, it is possible that one is looking at incorrect interface. Recommendation hence is to look at SoftDevice headers to ensure correct appplication interface. This is also applicable for Serialization library references. This will be fixed in next release. - - SDK documentation has been splitted into 4 seperate documents with a common index page. - - ANT - - None - - ANT + BLE (Dual stack) - - S310 Heart Rate Relay Example: Bonding does not always function as expected. If bonding is enabled using compiler flag it is recommended to perform service discovery before bonding to minimize chances of unexpected behaviour. - - BLE - - Proprietary - - Enhanced ShockBurst/Gazell: Received packets in Host/PRX mode with CRC error can no longer return ACK to device. - - NRFFOSDK-2470: app_timer - Fixed issue where starting and stopping the timer repeatedly caused errors in the module - -Known issues: - - - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". - Solution: - - Write new flash algorithm settings to the uvopt file. - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Utilities". - Press "Settings" button to see flashing algorithms. - Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. - Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. - - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. - This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. - Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. - - ANT - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - S120 Examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if peer loses the bond and a re-bonding occurs, flash clear fails, and DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. - - Device manager has a few APIs unimplemented. Also documentation providing examples of how API can be used is missing. - - NRFFOSDK-2824: Device manager (pstorage) doesn't support update of bond split across two pages. - - Proprietary: - - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 5.2.0 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 5.10.x - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: Embedded Workbench for ARM 6.60 - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - Windows 8.0/8.1 - - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. - -Tested with devices: - - - nRF51822 QFAAG0 - - nRF51822 QFAAGC - - nRF51822 QFAAFA - - nRF51422 QFAAE0 - - For others devices, use SDK 4.x.x - -Supported SoftDevices: - - - S110 6.0.0 - - S120 1.0.0-1.alpha - - S210 3.0.0 - - S310 1.0.0 - -Supported boards: - - - PCA10000 v1.0 (Only for use with Master Emulator) - - PCA10000 v2.1.0 and 2.2.0 - - PCA10001 v2.1.0 and 2.2.0 - - PCA10004 v2.1.0 - - PCA10005 v2.1.0 and 2.2.0 - - PCA10003 v3.0.0 - - -Changes: - - - app_button module: Detect both push and release, instead of just push - - Persistent storage (pstorage) module: - - Support for writing to used memory regions with the new update API. - - Support for clearing single blocks. - - Added get_status API to identify pending flash operations. - - ANT - - None - - ANT + BLE (Dual stack) - - Support for s310 SoftDevice added. - - Heart rate monitor example project support added. - - Added Device Firmware Update (DFU) example for s310. - BLE - - New experimental device manager module for managing bonds on s120. - - Beacon example added. It is available at nrf51822\Board\nrf6310\s110\ble_app_beacon - and nrf51822\Board\pca10001\s110\ble_app_beacon. - - Multiple GATT clients: The Database Discovery module available in - nrf51822\Board\nrf6310\s120\experimental\common folder can now be used to - discover two GATT services at the peer. - - Serialized s110 advertisement example has been removed. - - HID Keyboard application modified to send upper case letters on pressing Button 2. - - Proprietary - - None - -Fixed issues: - - ANT - - None - - ANT + BLE (Dual stack) - - None - - BLE - - NRFFOSDK-1897: Glucose: Fixed bug where authentication was not initiated when connecting to already bonded master. - - NRFFOSDK-2318: Glucose Feature values had incorrect values for 'General Device Fault Supported', 'Time fault Supported', and 'Multiple Bond Supported'. This has been fixed. - - ANCS: The advertising interval of the Apple Notification Center Client example application is reduced to 25 ms. Previously it was 250 ms which made it hard to discover from the peer device. - - NRFFOSDK-2357: Blood Pressure application changed to check if indication is enabled before attempting to send an indication to the peer - - NRFFOSDK-2336: HID Keyboard application fixed to send the correct Input Report bytes when in Boot Mode. - - Fixed issue in bond manager related to clearing of whitelist on deleting all bonds. - - NRFFOSDK-2162: New pstorage get_status API used to allow for flash access to be completed before system off. - - Proprietary - - NRFFOETT-644 - Gazell / ESB: Fixed some documentation issues. - -Known issues: - - - NRFFOSDK-2542 - SoftDevice related documentation for S110, S120 and S310 BLE stack is not consistent. When looking up SoftDevice application interface or message sequence charts, it is possible that one is looking at incorrect interface. Recommendation hence is to look at SoftDevice headers to ensure correct appplication interface. This is also applicable for Serialization library references. This will be fixed in next release. - - - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". - Solution: - - Write new flash algorithm settings to the uvopt file. - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Utilities". - Press "Settings" button to see flashing algorithms. - Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. - Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. - - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. - This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. - Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. - - ANT - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - ANT + BLE (Dual stack) - - S310 Heart Rate Relay Example: Bonding does not always function as expected. If bonding is enabled using compiler flag it is recommended to perform service discovery before bonding to minimize chances of unexpected behavior. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. - (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) - - S120 Examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if peer loses the bond and a re-bonding occurs, flash clear fails, and DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. - - Device manager is an experimental module and has a few APIs unimplemented. Also documentation providing examples of how API can be used is missing. - - Proprietary: - - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 5.1.0 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 5.0.5.x - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: Embedded Workbench for ARM 6.60 - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - Windows 8.0/8.1 - - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. - -Tested with devices: - - - nRF51822 QFAAGC (For others, use SDK 4.x.x) - - nRF51822 QFAAFA (For others, use SDK 4.x.x) - - nRF51422 QFAADA (For others, use SDK 4.x.x) - -Supported SoftDevices: - - - S110 6.0.0 - - S120 0.8.0-2.alpha - - S210 3.0.0-3.beta - - S310 1.0.0-2.alpha - - -Supported boards: - - - PCA10000 v1.0 (Only for use with Master Emulator) - - PCA10000 v2.1.0 and 2.2.0 - - PCA10001 v2.1.0 and 2.2.0 - - PCA10004 v2.1.0 - - PCA10005 v2.1.0 and 2.2.0 - - -Changes: - - - Moved and renamed SoftDevice header folders: - from nrf51822/Include/ble/softdevice to nrf51822/Include/s110 - from nrf51422/Include/ble/softdevice to nrf51422/Include/s210 - - Added SoftDevice headers for s120 and s310 at: - nrf51822/Include/s120 - nrf51422/Include/s310 - - Moved ANT examples from nrf51422/Board//ant to nrf51422/Board//s210 - - Moved s110 SoftDevice examples from nrf51822/Board//ble to nrf51822/Board//s110 - - Added folder for s310 examples in nrf51422/Board//s310 - - Added folder for s120 SoftDevice examples in nrf51822/Board//s120 - - ANT - - The flash layout settings of all ANT examples have been adapted to suit the new flash layout of S210 SoftDevice. - - - BLE - - Added experimental Multilink (up to 8) Central example which uses s120 SoftDevice. - - Added experimental Heart Rate collector example which uses s120 SoftDevice. - - Added prototype iBeacon example. - - Proprietary - -Fixed issues: - - - NRFFOETT-671: Added support for creating new nRF51 projects in Keil 5. - - ANT - - NRFFOETT-438: The API documentation of S210 SoftDevice is now correctly structured in the SDK documentation. - BLE - - Proprietary - -Known issues: - - - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". - Solution: - - Write new flash algorithm settings to the uvopt file. - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Utilities". - Press "Settings" button to see flashing algorithms. - Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. - Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. - - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. - This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. - Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. - - - ANT - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. - (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) - - NRFFOSDK-2162 - Heart Rate application for PCA10001 possible inconsistent system attributes on power cycle. It is possible that the system attributes on power cycle are not consistent with the ones updated during previous connection. - - Proprietary: - - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 5.0.0 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.72.1.0 - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: embedded workbench for ARM 6.60 - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - Windows 8.0/8.1 - - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. - -Tested with devices: - - - nRF51822 QFAAGC (For others, use SDK 4.x.x) - - nRF51822 QFAAFA (For others, use SDK 4.x.x) - - nRF51422 QFAADA (For others, use SDK 4.x.x) - -Supported SoftDevices: - - - S110 6.0.0-3 Beta - - Expected to be Compatible with SoftDevice S110 V6.0.0 production version - -Supported boards: - - - PCA10000 v1.0 (Only for use with Master Emulator) - - PCA10000 v2.1.0 and 2.2.0 - - PCA10001 v2.1.0 and 2.2.0 - - PCA10004 v2.1.0 - - PCA10005 v2.1.0 - - NOTE: The ANT examples in this release will only work on nRF51422 QFAADA engineering samples. - Currently no official boards/kits exist that work with these examples. - - -Changes: - - - Added pstorage module for handling asynchronous non-volatile memory (flash) access via SoftDevice API - - Existing BLE event handler has been extended into the new SoftDevice handler module. The new SoftDevice handler module allows for fetching SoC, BLE and ANT events - - Restructured documentation - - - ANT - - BLE - - Changes for support of S110 V6.0.0-3 Beta - - Added Apple Notification Center in experimental - - Proprietary - - SPI slave driver and example code added - - Include new ESB library which uses the same peripherals as the S110 SoftDevice - -Fixed issues: - - ANT - - BLE - - Proprietary - -Known issues: - - - Creating a blank project with Keil V5.0 it is not possible to choose the nRF51 series. - Solution: - Start new projects by making a copy of any existing keil project from the SDK - - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. - This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. - Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. - - - ANT - - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. - (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) - - NRFFOSDK-2162 - Heart Rate application for PCA10001 possible inconsistent system attributes on power cycle. It is possible that the system attributes on power cycle are not consistent with the ones updated during previous connection. - - Proprietary: - - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 4.4.2 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.72.1.0 - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: embedded workbench for ARM 6.60 - - N51822 QFAACA on PCA10004 module on nRF6310 motherboard - - N51822 QFAAFA on PCA10005 module on nRF6310 motherboard - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - Windows 8.0/8.1 - - BLE SoftDevice Version : s110_nrf51822_5.2.1 - - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. - -- Supported boards in nRF51 SDK v. 4.4.2: - - PCA10000 v1.0 (Only for use with Master Emulator) - - PCA10000 v2.0.0 - - PCA10001 v1.0 through v2.1.0 - - PCA10003 v1.0 through v2.0.0 - - PCA10004 v1.0 through v2.0.0 - - PCA10005 v1.0 through v2.1.0 - - PCA10006 v1.0 through v2.0.0 - - PCA10007 v1.0 through v2.0.0 - - PCA10014 v1.0 - - PCA10018 v1.0.0 through v1.1.0 - -Changes: - - ANT - None - - BLE - - Removed ble_dfu_send_hex.exe from device_firmware_update experimental folder. Similar feature is now available in latest Master Control Panel application. - - Proprietary - None - -Fixed issues: - - - NRFFOSDK-1750 - Added PAN-11 workaround in PPI, PWM, and Simple PWM motor control examples. - - NRFFOSDK-1633 - Added PAN-56 workaround in TWI master driver. - - ANT - None - - BLE - - NRFFOSDK-1025 - The field max_len in rep_char_add signature in ble_hids.c has been corrected to uint16_t. - - NRFFOSDK-1921 - In case IRK is distrubuted by a peer using public address whitelist is updated for both IRK and address. - - NRFFOSDK-1899 - System attributes re-initialized on rebonding. - - NRFFOSDK-1900 - Removed false detection of DIV collisions. - - NRFFOSDK-1993 - Increased buffer in hci_mem_pool_internal.h fix the serialization examples. - Proprietary - None - -Known issues: - - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. - This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. - Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. - - - ANT - - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. - (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) - - Proprietary: - - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 4.4.1 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.71.2 - - GCC: gcc-arm-embedded 4.7 2013q1 - - IAR: embedded workbench for ARM 6.60 - - N51422 QFAACA on PCA10003 evaluation kit board - - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - BLE SoftDevice Version : s110_nrf51822_5.2.1 - - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1 Preview. - -Changes: - - - DFU documentation improved. - - ANT - None - - BLE - - NRFFOSDK-1759: Example IAR application for Heart Rate Service added. - - NRFFOSDK-1271: Speed and Cadence Control Point added to Cycling Speed and Cadence Service. - - Proprietary - - ESB: Improved tolerance to delayed interrupts. - - -Fixed issues: - - - NRFFOSDK-1592: Risk of losing timer interrupts when the resolution of the timer is very high, e.g. 1 ms resolution, is now fixed. - - ANT - None - - BLE - - NRFFOETT-399: An IRK is added to the bond manager's whitelist only if the address type of the master is 'resolvable'. - - NRFFOETT-552: DTM application is now implementing PCN_083 - - NRFFOSDK-1828: Key refresh was triggering a link failure when re-bonding to a master. This is now fixed. - - NRFFOETT-571: Premature disconnection scenario handling added to bond manager. Previously this was resulting in system attributes of a master to be cleared. - - Proprietary - - ESB: The nrf_esb_tx_failed() callback function was never called when dynamic acknowledgement was used. This is now fixed. - -Known issues: - - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. - This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. - Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. - - - ANT - - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. - (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) - - Proprietary: - - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 4.4.0 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.71.2 - - GCC: gcc-arm-embedded 4.7 2013q1 - - N51422 QFAACA on PCA10003 evaluation kit board - - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - BLE SoftDevice Version : s110_nrf51822_5.2.1 - - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8. - -Changes: - - - Device Firmware Update example released as part of the main SDK. - - Added support for image transfer over BLE. - - HCI Transport Layer used for serial transfer. - - Note: This example is implemented to work on nRF6310 motherboard because it uses Button 7 to enter bootloader mode on reset. - This is because Button 0 and Button 1 are used by other SDK applications as wakeup buttons. - If this example is to be changed to work for evaluation kit board, then this should be taken into consideration. - - PC application examples for performing firmware updates using HCI and BLE added in nrf6310\device_firmware_updates\experimental folder. - - - UICR Configuration example added to the SDK. It can be found in nrf6310\uicr_config_example folder. - - ANT - None - - BLE - - NRFFOETT-507: ble_app_dtm missing bytes on UART fixed. - - NRFFOSDK-73 : HID keyboard application will now send one key press per notification. - - - Proprietary - None - -Fixed issues: - - ANT - None - - BLE - - NRFFOSDK-1432: Buffer overflow issue in ble_bondmngr_sys_attr_store() function fixed. - - NRFFOETT-339: CCCD values (System Atributes) are now restored on reconnection to a known master only after the link is encrypted. - - Proprietary - None - -Known issues: - - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. - - NRFFOSDK-1774: During SDK installation, chosing custom install location for SDK examples will create Start Menu shortcuts that point to Keil installation location. - - NRFFOSDK-1592: There is a risk of losing timer interrupts when the resolution of the timer is very high, e.g. 1 ms resolution. - - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. - This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. - Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. - - - ANT - - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOETT-399 - The bond manager will use distrubted IRK in its whitelist regardless of the type of central's address and should actually use the irk if distributed and if the central's address is not public, and not random_static and not random_private_non_resovable. - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. - (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) - - Proprietary: - - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 4.3.0 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.60 - - GCC: gcc-arm-embedded 4.7 2013q1 - - N51422 QFAACA on PCA10003 evaluation kit board - - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - BLE SoftDevice Version : s110_nrf51822_5.2.0 - -Changes: - - - Supported GCC toolchain switched from CodeSourcery to gcc-arm-embedded. - - New gcc startup file, linker scripts, and makefiles. - - Updated CMSIS header files in Include/gcc to the latest revision (3.20). - - Makefile target "all" now runs "clean" and "debug" targets instead of incremental "release" target. - - nrf.h requires projects to have a define for a chip to enable some needed workarounds. - - SDK examples now support PCA10000 v2.0.0. To make the examples work on the older PCA10000 v1.0, the UART pins need to be remapped in the pca10000.h header file. - For v1.0 - #define RX_PIN_NUMBER 3 - #define TX_PIN_NUMBER 1 - #define CTS_PIN_NUMBER 2 - #define RTS_PIN_NUMBER 0 - For v2.0.0 - #define RX_PIN_NUMBER 11 - #define TX_PIN_NUMBER 9 - #define CTS_PIN_NUMBER 10 - #define RTS_PIN_NUMBER 8 - - ANT - - ANT examples have been updated to support the newest UART API. - BLE - - HCI Transport Layer from Bluetooth Specification v4.0 introduced for BLE S110 Serialized Applications. - - BLE S110 Serialization Examples released as part of the main SDK. - - Updated serialized ble_app_advertising and ble_app_hrs to use app_scheduler. - - Connection Parameter update module : Added possibility to request different connection parameters multiple times. A new event, BLE_CONN_PARAMS_EVT_SUCCEEDED has been created. Event handler implementation needs to take this into account, especially if they were implemented to trigger a disconnect regardless of the type of event. - - Added Makefile and Eclipse project file for ble_app_hrs. - - Changed hard coded flash pages to be FICR CODESIZE dependent. - - Proprietary - - Gazell: - - Added Gazell Pairing Host source code and board example. Backwards compatible with nRF24L Gazell Pairing Device and Host modules. - - Added function nrf_gzll_set_auto_disable(uint32_t num_ticks), to disable Gazell after a number of timeslots. - - Added function nrf_gzll_get_tick_count(). - - Gazell Pairing Device now uses nrf_gzll_get_tick_count() in order to implement a delay. This reduces current consumption. - - Default sync_lifetime value has been increased to 3*channel_table_size*number_of_timeslots_per_channel. This improves performance in high-interference environments. Current users who are satisfied with the performance may wish to maintain the minimum value of 1*channel_table_size*number_of_timeslots_per_channel, in order to avoid any slight increase in current consumption. - - Enhanced ShockBurst: - - ESB PTX now calls nrf_esb_tx_success() callback instead of nrf_esb_tx_failed() for NOACK packets. - - Fix in nrf_esb_set_mode() - - Information concerning backwards compatibility with nRF24L devices has been moved to the User Guide. - -Fixed issues: - - - Examples doing flash writes were not waiting for writes to finish. - - ANT - - NRFFOSDK-1312 - Changed ANTFS_TRANSMIT_POWER define in antfs.h from 0 to 3. The define previously had an incorrect definition which set the power value to -20dBm instead of 0dBm even though the comment indicated 0dBm. - - BLE - - NRFFOETT-402 - DFU Bootloader application in experimental project now sets stack pointer correctly before executing reset vector of application. - - Proprietary - - NRFFOETT-301 - Radio example uses obsolete RADIO_TXPOWER_TXPOWER_Neg40dBm definition. - - Fixed issue in TWI HW driver. Event was not cleared before waiting it to get cleared. - - Floating point ABI used by Makefiles was incorrect. Now using mabi-float=soft. - - Gazell/ESB: Fixed set_mode() functionality. - - Gazell GCC board examples startup and run correctly with the GCC libraries. - - A Gazell Device nows stop the RSSI measurement when no ACK is received, improving the base current consumption. - -Known issues: - - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. - - ANT - - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOETT-399 - The bond manager will use distrubted IRK in its whitelist regardless of the type of central's address and should actually use the irk if distributed and if the central's address is not public, and not random_static and not random_private_non_resovable. - - NRFFOSDK-1432 - A buffer overflow has been discovered in the BLE bond manager upon system attributes store. Workaround, define BLE_BONDMNGR_MAX_BONDED_MASTERS in ble_bondmngr_cfg.h to be 1 higher than the number of bond required by the applicaiton. - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. - (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) - - Proprietary: - - Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 4.2.0 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.60 - - N51422 QFAACA on PCA10003 evaluation kit board - - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - BLE SoftDevice Version : s110_nrf51822_5.1.0 - -Changes: - - ANT - - BLE - - NRFFOSDK-623 - BLE S110 DFU Bootloader prototype added to experimental folder. - - NRFFOSDK-996 - Delete of individual bonds in Bond Manager. API extension. - Validity check of stored bond added to Bond Manager API. - - NRFFOSDK-745 - Extended BLE S110 Serialized API. - Added serialized Heartrate example to exprimental folder. - - Proprietary - -Fixed issues: - - - NRFFOSDK-1015 - nRFgo Display lock up after a reset - - ANT - - BLE - - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed. - - Proprietary - -Known issues: - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYTEM_OFF before flashing a new application. - - ANT - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. - (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) - - Proprietary: - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 4.1.0 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.60 - - N51422 QFAACA on PCA10003 evaluation kit board - - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard - - Windows XP SP3 32 bit - - Windows 7 SP1 64 bit - - BLE SoftDevice Version : s110_nrf51822_5.0.0 - -Changes: - - nRF51 device variant removed from KEIL device database and replaced with nRF51 series specific devices. - - Added nrf6310_experimental folder to the nRF51 SDK which contains examples and modules under development. - - Experimental version of the SoftDevice S110 serialization API with examples. - - Removed obsolete Master Emulator firmware from the release (nrf51822\Board\pca10000\ble\master_emulator\MEFW_nRF51822_firmware.hex). - - Renamed twi_sw_master_example to twi_master_example - ANT - - BLE - - Updated SoftDevice S110 specific documentation to include message sequence charts. - Proprietary - -Fixed issues: - - NRFFOETT-257 - twi_master_clear_bus() functionality fix done. - - NRFFOSDK-953 - twi_hw_master.c functionality fix done. - ANT - - BLE - - NRFFOSDK-758 - Button 1 does not wake up Bluetooth examples applications. To erase bonding information from system-off mode, press both button 0 and button 1. - - Proprietary - -Known issues: - - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". - Solution: - Press ALT+F7 to open "Options for Target" dialog. - Select "Options for Target" -> "Device". - Choose "Nordic nRF51 Series Devices" from the Database list. - Select the variant of the nRF51 chip that is used for the KEIL project target. - - - - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. - Solution: Upgrade J-Link software to version 4.66 or later. - - - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. - Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. - - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - Solution: Wake-up the current application from SYTEM_OFF before flashing a new application. - - ANT - - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. - (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) - - NRFFOSDK-486 - All applications using the bond manager will assert when the maximum number of bonded masters is passed. See proximity application documentation. - - Proprietary: - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 4.0.1 ------------------- - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.60 - - N51422 QFAACA on PCA10006 module on nRF6310 motherboard - - N51822 QFAACA on PCA10001 evaluation kit board - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - - BLE SoftDevice Version : s110_nrf51822_4.0.0-2.beta - -Changes: - - Adressed poor search functionality in the documentation by upgrading used Doxygen version and adding a CHM version of the documentation. - Proprietary - - ESB/Gazell: A hard PLL rampdown is now implemented which shortens the TX to RX switching time to match nRF24L devices. - -Fixed issues: - - NRFFOSDK-801 - Project memory layout was incorrect for S110 4.0.0 targets. - - NRFFOETT-249 - gcc_nrf51_s110.ld had wrong SoftDevice size. - - ANT - - BLE - - NRFFOSDK-807 - Made changes to the default assert handler. - - NRFFOSDK-800 - Bug when switching between BLE and Gazell mode on buttons presses fixed. - - NRFFOETT-225 - DTM didn't work with Tescom TC3000C and R&S CBT. - - NRFFOETT-262 - Evaluation kit BLE examples had button pin pullup resistors disabled. - - NRFFOSDK-804 - Excluded ble_sps.c and ble_sps.h from release as they have not been fully implemented. - - Proprietary - - ESB/Gazell: The peripherals are no longer prepared for use by the nrf_esb_init() and nrf_gzll_init() functions. This is performed in the SystemInit() function. - -Known issues: - - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. - Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51 SDK installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power - - NRFFOSDK-363 - Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode (implies to wake-up the current application from SYTEM_OFF before flashing a new application) - - ANT - - NRFFOSDK-366 - ANT-FS host: download some times fails when downloading large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application - If the bonding information are not erased manually - by pressing button 1 during start-up - the new application might assert. - - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed - See proximity application documentation. - - NRFFOSDK-758 - Button 1 does not wake up Bluetooth examples applications. To erase bonding information from system-off mode, press on both button 0 and button 1. - - NRFFOSDK-759 - Unable to switch to BLE mode from gazell mode in Multiprotocol application - - Proprietary: - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v. 4.0.0 ------------------ - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.60 - - N51422 QFAACA on PCA10006 module on nRF6310 motherboard - - N51822 QFAACA on PCA10001 evaluation kit board - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - -Changes: - - NRFFOSDK-192 - Interrupt driven low power UART module added. - - NRFFOSDK-543 - Set of common modules used by nRF51xxx examples added. - - ANT - - NRFFOSDK-312 - adapt to renaming of SoftDevice S210 V2.0.0 APIs - - BLE - - NRFFOSDK-55 - adapt to renaming of SoftDevice S110 V4.0.0 APIs - - -Fixed issues: - - NRFFOSDK-563 - nRF51 SDK installer - Keil CDB not installing correctly on PC's running Win7 w/Asian Locales (prim: Japanese/Chinese). - - ANT - - NRFFOSDK-484 - HRM TX background pages are not following 65th packet rule according to spec - - BLE - - NRFFOSDK-361 - System attributes are stored in flash only after disconnect. API ble_bondmngr_sys_attr_store to save system attributes while in a connection is now available. - - - -Known issues: - - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. - Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists - - NRFFOSDK-236 - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power - - NRFFOSDK-363 - Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode (implies to wake-up the current application from SYTEM_OFF before flashing a new application) - - ANT - - NRFFOSDK-366 - ANT-FS host: download some times fails when downloading large file. - - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application - If the bonding information are not erased manually - by pressing button 1 during start-up - the new application might assert. - - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed - See proximity application documentation. - - NRFFOSDK-758 - Button 1 does not wake up Bluetooth examples applications. To erase bonding information from system-off mode, press on both button 0 and button 1. - - NRFFOSDK-759 - Unable to switch to BLE mode from gazell mode in Multiprotocol application - - Proprietary: - - ESB/Gazell: Calling nrf_esb_init() or nrf_gzll_init() will disable usage of the GPIOTE peripheral. - - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the - nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the - payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - - Gazell does not support "Low Power Host mode" (Host mode 1). - -======================================================================== - -nRF51 SDK v3.0.0 ------------------ -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.60 - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - -Changes: - - - Merged nRF514 and nRF518 SDKs - - - system_nrf51.c: GPIOTE peripheral turned on during system init. - - ANT - - Added ANT bicycle power-only sensor example - - Added ANT combined bicycle speed and cadence sensor example - - BLE - - Added Direct Test Mode (DTM) source code - - Added Glucose Meter service and example - - Added Health Thermometer service and example - - Added Blood Pressure service and example - - Added Proximity example for evaluation board - - Bond manager and flash module modified to write bonding information in flash while in a connection - -Fixed issues: - BLE - -NRFFOSDK-120 - ble_bondmngr_store_bonded_masters function from the bond manager cannot be used when advertising nor when in a connection - The bonding information are now written while in a connection but not the system attributes information. - - ANT - - Fixed incorrect event time generation in ANT HRM Tx example - - NRFFOSDK-469 - ANT - bicycle power rx: doxygen architecture picture defect - - - NRFFOSDK-470 - ANT - bicycle power tx: doxygen architecture picture defect - - Proprietary: - - twi_hw_master example : Fixed deadlock when stop condition was not issued. (NRFFOETT-167) - - - Bugfix: Polarity of on-air "no_ack" bit inverted to comply with legacy nRF24L01 - hardware ESB. - - -Known issues: - - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. - Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - - NRFFOSDK-236 - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. - - - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power - - - NRFFOSDK-363 - Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode - (implies to wake-up the current application from SYTEM_OFF before flashing a new application) - ANT - - ARCH-506 - ANT-FS host; download could fail when downloading large files. - - - NRFFOSDK-484 - HRM TX background pages are not following 65th packet rule according to spec - - BLE - - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized - - - NRFFOSDK-361 - System attributes are stored in flash only after disconnect. - - - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application - If the bonding information are not erased manually - by pressing button 1 during start-up - the new application might assert. - - - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed - For more information, see proximity application documentation. - - - - Proprietary: - - ESB/Gazell: Calling nrf_esb_init() or nrf_gzll_init() will disable usage of the GPIOTE peripheral. - - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - The legacy examples need to add the following in order to work with the - nRF51 examples: - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - In addition, the legacy PTX example must add code for handling the - payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. - - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - - Gazell does not support "Low Power Host mode" (Host mode 1). - -Notification ANT: - - This is last release that will support N51422 QFAACA (ANT). Next release will contain API changes. - - - - - - -======================================================== -Old release notes from before SDK merge -======================================================== - - -nRF518 SDK v2.0.0 ------------------ - -Following toolchains/devices have been used for testing and verification: - - ARM: MDK-ARM Version 4.60 - - N51822 QFAACA on PCA10000 evaluation kit USB dongle - - N51822 QFAACA on PCA10001 evaluation kit board - - N51822 QFAACA on PCA10004 module on nRF6310 motherboard - - Windows XP SP3 32-bit - - Windows 7 SP1 64-bit - - Bluetooth: - - Bluetooth Low Energy SoftDevice S110_nRF51822_2.0.0_alpha1 - - Gazell / ESB libraries on-air compatible with the following SDKs for legacy nRF24Lxx devices: - - nRFgo SDK 2.3.0 - - nRFready Desktop 1.2.3 - -Changes: - - Bluetooth: - - Adapted examples for updated S110 API (S110_nRF51822_2.0.0_alpha1). - - Added Find Me (Immediate Alert Service as client) to Proximity Application. - - Added Alert Notification (client) service and example. - - Added Cycling Speed and Cadence service and example. - - Added Running Speed and Cadence service and example. - - Bond Manager modified to add Whitelist handling and CRC verification of flash. - - Bond Manager usage added to all examples except for power profiling application. - - Use of Whitelist added to Proximity, HID Mouse and HID Keyboard examples. - - Use of directed advertisement added to HID Mouse and HID Keyboard examples. - - Timer Module refactored. - - Proprietary: - - Added nRF24L series address conversion functions to radio_example. - - Added support for GCC to nRF51 Code Examples, ESB and Gazell examples. - - Examples no longer use deprecated PERPOWER register. - - Disabled "Download to flash" and "Verify Code Download" in JLink debug Download Options. - - All SDK release notes are now in this file. - - Added hardware flow control option to simple_uart. - - Fixed compilation problems with Keil ARM MDK v4.60 and ram retention, temperature and blinky examples. - - debouncer_example, ppi_example and timer_example now explicitly set timer bitmode. - - keil_arm_uv4.lnt include folder changed from C:\Keil\ARM\RV31\INC to C:\Keil\ARM\ARMCC\INC. - - Corrected location of SFR files in UV projects. - - - ESB: ESB PRX transceiver operations are shorted, removing continuous wave transmission and improving speed and current consumption. - - ESB: PRX starts listening immediately after sending an ACK, no longer waiting for the next timeslot. - - ESB: The NOACK bit is changed to an ACK bit to ensure compatibility with L01 radios. The L01 product specification is incorrect, only devices using dynamic ack will see this. - - ESB: esb_is_enabled function added. - - ESB: Disabling CRC checking on PRX/Host side works correctly - - ESB: Added support for controlling the XOSC outside the ESB library - - - Gazell: Added support for controlling the XOSC outside the Gazell library - - GZP: No longer deletes pairing data on gzp_init. Added functions to check if device has pairing data and delete all pairing info from flash. - - GZP: gzp_desktop_emulator example requires only one key press to pair and has been tested to work on SoftDevice. - - GZP: nrf_nvmc_write_bytes correctly iterates through bytes. - -Fixed issues: - - Examples use deprecated PERPOWER register. - - Proprietary: - - When using Keil ARM MDK v4.60 the ram retention, temperature and blinky examples might fail during compilation. - - Gazell and ESB examples point to wrong SFR file (should be SFD\Nordic\nRF51\nRF51822.sfr). - - Bluetooth: - - The buttons on the evaluation board are not debounced. - -Known issues: - - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. - - On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. - Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. - - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. (DRGN-1807) - - Reset button won't work after programing without cycling the target power. (DRGN-1885) - - Flashing a software using SEGGER is possible only when NOT in SYSTEM_OFF mode (implies to wake-up the current application with a button press for example before flashing a new application).(DRGN-1925) - - Bluetooth: - - Only the ..\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\ and ..\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ applications are power optimized.(DRGN-1914) - - ble_bondmngr_store_bonded_masters function from the bond manager cannot be used when advertising nor when in a connection (DRGN-1915) - (flash erase/write prevents the CPU from running which means the stack will not be able to run properly.) - If ble_bondmngr_store_bonded_masters function is called while advertising or in a connection, the behavior is UNDEFINED. - - Proprietary: - - ESB/Gazell: Calling nrf_esb_init() or nrf_gzll_init() will disable usage of the GPIOTE peripheral. In order to use the GPIOTE peripheral, the workaround in PAN 22 must be performed after calling these functions. - - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. - - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. - - - The nRF24Lxx ESB examples found in the legacy nRFready - SDKs do not work out of the box with the nRF51 ESB examples. This is due to: - - The legacy examples do not use "payload in ACK". - - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). - - The examples do not use dynamic payload length. - - The legacy examples need to add the following in order to work with the - nRF51 examples: - - hal_nrf_setup_dynamic_payload(0xFF); - hal_nrf_enable_dynamic_payload(true); - hal_nrf_enable_ack_payload(true); - hal_nrf_set_rf_channel(10); - - In addition, the legacy PTX example must add code for handling the - payloads received in ACK. - - - The Gazell Link Layer examples are not fully "out of the box" compatible - with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx - devices. The timeslot periods and channel tables require adjustment. - - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, - or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects - (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). - - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, - or use the nrf_gzll_set_channel_table() function in the nRF51 projects. - - Gazell does not support "Low Power Host mode" (Host mode 1). - - - - - - - -nRF518 SDK v1.1.1 ------------------ - -Changes: -- Master Control Panel updated to version 3.1.1. Includes fix for issue where pca10000 master emulator devices did not get detected. - -Known issues: -- When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. -- When using Keil ARM MDK v4.60 the ram retention, temperature and blinky examples might fail during compilation and leave an error message like this: - C3900U: Unrecognized option '--asm'. - C3900U: Unrecognized option '--interleave'. - To fix this Click Alt+F7, choose "Listing" tab. Uncheck "C Compiler Listing" -- Previous issues from v1.1.0 does still apply - - - - - - - -nRF518 SDK v1.1.0 ------------------ - -Following toolchains/devices have been used for testing and verification: -- ARM: MDK-ARM Version 4.54 -- N51822 QFAACA on PCA10004 module on nRF6310 motherboard -- N51822 QFAACA on PCA10000 USB dongle -- N51822 QFAACA on PCA10001 board -- Windows XP SP3 32-bit -- Windows 7 SP1 64-bit - -Known issues: -- Examples use depracated PERPOWER register. Future silicon will power up peripherals after reset and PERPOWER register will be removed. -- Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. -- Temperature example does not give sane output values. This is hardware related issue described in -- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. -- On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. - Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. -- Gazell and ESB examples point to wrong SFR file (should be SFD\Nordic\nRF51\nRF51822.sfr). -- Reset button wont work after programing without cycling the target power. Workaround is to update system_nrf51.c with - void SystemInit (void) - { - /* Switch ON both RAM banks */ - NRF_POWER->RESET = POWER_RESET_RESET_Enabled; - NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) | - (POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos); - } - -Bluetooth: - - The button on the evaluation board are not debounced in hardware and the application implementing for it does not debounce the button presses either (using software mechanisms). So there will be additional increments/decrements of heart rate measurement while pressing the buttons. - - - - - -nRF518 SDK v1.0.0 ------------------ - -Following toolchains/devices have been used for testing and verification: -- ARM: MDK-ARM Version 4.54 -- N51822 QFAACA on nRF2752 module on nRF6310 motherboard -- Windows XP SP3 32-bit -- Windows 7 SP1 64-bit -Bluetooth: - - S110 SoftDevice v1.0.0 - - J-Link ARM v4.52b or higher - -This release contains the following: -Bluetooth: - - Complete source code needed for writing applications on top of S110 SoftDevice (BLE Stack) - - Template application that can be used as a starting point to develop custom applications. - - Example application for Heart Rate Service - - Example application for Proximity profile - - Example application for HID Mouse - - Example application for HID Keyboard - - Power profiling application - - Example application using Heart Rate Service for Evaluation Board (PCA10001) - - Multiprotocol application that implements the Heart Rate profile in Bluetooth mode and the Gazell 'device' mode. - - Documentation - -Known issues: -- Examples use depracated PERPOWER register. Future silicon will power up peripherals after reset and PERPOWER register will be removed. -- Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. -- Temperature example does not give sane output values. This is hardware related issue described in -- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. -- On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. - Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. -- Gazell and ESB examples point to wrong SFR file (should be SFD\Nordic\nRF51\nRF51822.sfr). -- Reset button wont work after programing without cycling the target power. Workaround is to update system_nrf51.c with - void SystemInit (void) - { - /* Switch ON both RAM banks */ - NRF_POWER->RESET = POWER_RESET_RESET_Enabled; - NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) | - (POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos); - } -- Spi master function spi_master_init() sends two dummy bytes. This will be removed in a future release. -- timer_example nrf_timer_delay_ms() will not give expected results using parameter values over 65 ms. - -Bluetooth: - - The button on the evaluation board are not debounced in hardware and the application implementing for it does not debounce the button presses either (using software mechanisms). So there will be additional increments/decrements of heart rate measurement while pressing the buttons. - - - - -nRF514 SDK v.1.2.0 ------------------- - -Following toolchains/devices have been used for testing and verification: -- ARM: MDK-ARM Version 4.60 -- N51422 QFAACA on PCA10004 module on nRF6310 motherboard -- N51422 QFAACA on PCA10006 module on nRF6310 motherboard -- N51822 QFAACA on nRF2752 module on nRF6310 motherboard -- N51822 QFAACA on PCA10001 evaluation kit board -- Windows XP SP3 32-bit -- Windows 7 SP1 64-bit - -Changes: -- Added Bicycle Power minimal slave example. -- Added Stride and Distance Monitor minimal slave and master example. -- Removed deprecated PERPOWER register from examples and header files. - -Known issues: -- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. -- On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. - - Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. -- When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. -- Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode (implies to wake-up the current application from SYTEM_OFF before flashing a new application) -- Reset button won't work after programming with Keil without cycling the target power. On the other hand if nrfjprog with -p (pin reset) is used to program the device, reset button will work. -- Using -p option in nrfjprog too heavily might block JLink. This block can be resolved by re-cycling the JLink power. - - -nRF514 SDK v1.1.0 ------------------ - -Following toolchains/devices have been used for testing and verification: -- ARM: MDK-ARM Version 4.54 -- N51422 QFAACA on PCA10001 module -- N51422 QFAACA on a PCA10005 modulea on nRF6310 motherboard - -Known issues: -- When having an application which starts up by putting the chip in SystemOff mode, and wakeup source is not configured correctly, the device cannot be programmed. - Workaround: Use nrfjprog with "recover" option to wipe the application keeping the application in SystemOff mode. -- For PCA10003 examples using UART, the terminal program on the PC has to release the COM port when PCA10003 is power cycled. It is not possible for the PCA10003 to keep a connection up when performing a power cycle. - Workaround: Close terminal program for each time you want to perform a power recycle - -Changes: -- Added examples for PCA10003 Evaluation kit. -- Added nrfjprog.exe - Nordic Semiconductor command line nRF51 programming tool using JLink dll's. -- Added custom system_nrf51422.c in templates folder for handling reset after flashing and turning all peripherals on (except GPIOTE) as described in PAN028. -- Removed references to depricated PERPOWER register in ANT code examples. -- Added compiler flag to the ANT examples, to easier being able to run examples without any UART. -- Modified simple_uart_config() parameters. Added new parameters for flow control -- Added include/boards folder for handling examples targeted for different boards -- Fixed bug in timer_example -- Fixed bug in spi_example - - -nRF514 SDK v1.0.0 ------------------ - -Following toolchains/devices have been used for testing and verification: -- ARM: MDK-ARM Version 4.54 -- N51822 QFAACA on nRF2754 module on nRF6310 motherboard -- Tested on Windows 7 64-bit - -Known issues: -- Examples use depracated PERPOWER register. Future silicon will power up peripherals after reset and PERPOWER register will be removed. -- Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. -- Temperature example does not give sane output values. This is hardware related issue described in -- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. -- Reset button wont work after programing without cycling the target power. Workaround is to update system_nrf51.c with - void SystemInit (void) - { - /* Switch ON both RAM banks */ - NRF_POWER->RESET = POWER_RESET_RESET_Enabled; - NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) | - (POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos); - } -- Spi master function spi_master_init() sends two dummy bytes. This will be removed in a future release. -- timer_example nrf_timer_delay_ms() will not give expected results using parameter values over 65 ms. - -Changes: -- First public release - diff --git a/src/main.c b/src/main.c index 3136a06..f83e476 100644 --- a/src/main.c +++ b/src/main.c @@ -552,7 +552,6 @@ uint32_t tusb_hal_millis(void) /*------------------------------------------------------------------*/ /* SoftDevice Event handler *------------------------------------------------------------------*/ - void ada_ble_task(void* evt_data, uint16_t evt_size); void ada_soc_task(void* evt_data, uint16_t evt_size); @@ -612,6 +611,7 @@ void ada_soc_task(void* evt_data, uint16_t evt_size) if (NRF_SUCCESS == err) { + // from hal_nrf5x.c extern void power_usb_event_handler(uint32_t evt); pstorage_sys_event_handler(soc_evt); diff --git a/src/make_common.mk b/src/make_common.mk index a7a9308..0008e4d 100644 --- a/src/make_common.mk +++ b/src/make_common.mk @@ -14,11 +14,11 @@ VERSION_MAJOR = 6 VERSION_MINOR = 0 VERSION_REVISION = 0 -SDK_PATH = ../../nRF5_SDK_11.0.0_89a8197/components -SDK15_PATH = ./../nRF5_SDK_15.0.0_a53641a/components +SDK_PATH = ../../lib/sdk/components +SDK11_PATH = ../../lib/sdk11/components SRC_PATH = .. -TUSB_PATH = ../../tinyusb/tinyusb +TUSB_PATH = ../../lib/tinyusb/tinyusb SD_NAME = s140 SD_VERSION = 6.0.0 @@ -83,14 +83,22 @@ remduplicates = $(strip $(if $1,$(firstword $1) $(call remduplicates,$(filter-ou #source common to all targets C_SOURCE_FILES += $(SRC_PATH)/main.c C_SOURCE_FILES += $(SRC_PATH)/dfu_ble_svc.c +C_SOURCE_FILES += $(SRC_PATH)/tusb_descriptors.c -C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/bootloader.c -C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/bootloader_settings.c -C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/bootloader_util.c -C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/dfu_init_template.c -C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/dfu_transport_serial.c -C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/dfu_transport_ble.c +# SDK 11 files +C_SOURCE_FILES += $(SDK11_PATH)/libraries/bootloader_dfu/bootloader.c +C_SOURCE_FILES += $(SDK11_PATH)/libraries/bootloader_dfu/bootloader_settings.c +C_SOURCE_FILES += $(SDK11_PATH)/libraries/bootloader_dfu/bootloader_util.c +C_SOURCE_FILES += $(SDK11_PATH)/libraries/bootloader_dfu/dfu_init_template.c +C_SOURCE_FILES += $(SDK11_PATH)/libraries/bootloader_dfu/dfu_transport_serial.c +C_SOURCE_FILES += $(SDK11_PATH)/libraries/bootloader_dfu/dfu_transport_ble.c +C_SOURCE_FILES += $(SDK11_PATH)/drivers_nrf/pstorage/pstorage_raw.c + +C_SOURCE_FILES += $(SDK11_PATH)/ble/ble_services/ble_dfu/ble_dfu.c +C_SOURCE_FILES += $(SDK11_PATH)/ble/ble_services/ble_dis/ble_dis.c + +# Latest SDK files C_SOURCE_FILES += $(SDK_PATH)/libraries/timer/app_timer.c C_SOURCE_FILES += $(SDK_PATH)/libraries/scheduler/app_scheduler.c C_SOURCE_FILES += $(SDK_PATH)/libraries/util/app_error.c @@ -100,26 +108,21 @@ C_SOURCE_FILES += $(SDK_PATH)/libraries/hci/hci_mem_pool.c C_SOURCE_FILES += $(SDK_PATH)/libraries/hci/hci_slip.c C_SOURCE_FILES += $(SDK_PATH)/libraries/hci/hci_transport.c C_SOURCE_FILES += $(SDK_PATH)/libraries/util/nrf_assert.c + C_SOURCE_FILES += $(SDK_PATH)/libraries/uart/app_uart.c +C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/uart/nrf_drv_uart.c C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/common/nrf_drv_common.c -C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/uart/nrf_drv_uart.c -#C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/power/nrf_drv_power.c -C_SOURCE_FILES += $(SDK_PATH)/ble/ble_services/ble_dfu/ble_dfu.c -C_SOURCE_FILES += $(SDK_PATH)/ble/ble_services/ble_dis/ble_dis.c - -C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/pstorage/pstorage_raw.c C_SOURCE_FILES += $(SDK_PATH)/toolchain/system_nrf52840.c -#C_SOURCE_FILES += $(SRC_PATH)/tusb_descriptors.c - -#C_SOURCE_FILES += $(TUSB_PATH)/portable/nordic/nrf5x/dcd_nrf5x.c -#C_SOURCE_FILES += $(TUSB_PATH)/portable/nordic/nrf5x/hal_nrf5x.c -#C_SOURCE_FILES += $(TUSB_PATH)/common/tusb_fifo.c -#C_SOURCE_FILES += $(TUSB_PATH)/device/usbd.c -#C_SOURCE_FILES += $(TUSB_PATH)/class/cdc/cdc_device.c -#C_SOURCE_FILES += $(TUSB_PATH)/tusb.c +# Tinyusb stack +C_SOURCE_FILES += $(TUSB_PATH)/portable/nordic/nrf5x/dcd_nrf5x.c +C_SOURCE_FILES += $(TUSB_PATH)/portable/nordic/nrf5x/hal_nrf5x.c +C_SOURCE_FILES += $(TUSB_PATH)/common/tusb_fifo.c +C_SOURCE_FILES += $(TUSB_PATH)/device/usbd.c +C_SOURCE_FILES += $(TUSB_PATH)/class/cdc/cdc_device.c +C_SOURCE_FILES += $(TUSB_PATH)/tusb.c #****************************************************************************** # Assembly Files @@ -130,10 +133,15 @@ ASM_SOURCE_FILES = $(SDK_PATH)/toolchain/gcc/gcc_startup_nrf52840.S # INCLUDE PATH #****************************************************************************** INC_PATHS += -I$(SRC_PATH)/ - INC_PATHS += -I$(TUSB_PATH)/ -INC_PATHS += -I$(SDK_PATH)/libraries/bootloader_dfu/hci_transport -INC_PATHS += -I$(SDK_PATH)/libraries/bootloader_dfu + +INC_PATHS += -I$(SDK11_PATH)/libraries/bootloader_dfu/hci_transport +INC_PATHS += -I$(SDK11_PATH)/libraries/bootloader_dfu +INC_PATHS += -I$(SDK11_PATH)/drivers_nrf/pstorage +INC_PATHS += -I$(SDK11_PATH)/ble/common +INC_PATHS += -I$(SDK11_PATH)/ble/ble_services/ble_dfu +INC_PATHS += -I$(SDK11_PATH)/ble/ble_services/ble_dis +INC_PATHS += -I$(SDK11_PATH)/libraries/util INC_PATHS += -I$(SDK_PATH)/libraries/timer INC_PATHS += -I$(SDK_PATH)/libraries/scheduler @@ -151,20 +159,17 @@ INC_PATHS += -I$(SDK_PATH)/drivers_nrf/uart INC_PATHS += -I$(SDK_PATH)/drivers_nrf/power INC_PATHS += -I$(SDK_PATH)/drivers_nrf/usbd -INC_PATHS += -I$(SD_PATH)/common -INC_PATHS += -I$(SD_PATH)/$(SD_NAME)/headers -INC_PATHS += -I$(SD_PATH)/$(SD_NAME)/headers/nrf52 - INC_PATHS += -I$(SDK_PATH)/device -INC_PATHS += -I$(SDK_PATH)/drivers_nrf/pstorage INC_PATHS += -I$(SDK_PATH)/toolchain/cmsis/include INC_PATHS += -I$(SDK_PATH)/toolchain/gcc INC_PATHS += -I$(SDK_PATH)/toolchain -INC_PATHS += -I$(SDK_PATH)/ble/common -INC_PATHS += -I$(SDK_PATH)/ble/ble_services/ble_dfu -INC_PATHS += -I$(SDK_PATH)/ble/ble_services/ble_dis + +INC_PATHS += -I$(SD_PATH)/common +INC_PATHS += -I$(SD_PATH)/$(SD_NAME)/headers +INC_PATHS += -I$(SD_PATH)/$(SD_NAME)/headers/nrf52 + OBJECT_DIRECTORY = _build LISTING_DIRECTORY = $(OBJECT_DIRECTORY) diff --git a/src/segger/nrf52840_bootloader.emProject b/src/segger/nrf52840_bootloader.emProject index eb29a0f..9b983b9 100644 --- a/src/segger/nrf52840_bootloader.emProject +++ b/src/segger/nrf52840_bootloader.emProject @@ -19,13 +19,13 @@ arm_target_device_name="nRF52840_xxAA" arm_target_interface_type="SWD" c_preprocessor_definitions="NRF52840_XXAA;__nRF_FAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;NO_VTOR_CONFIG;BOARD_FEATHER52840;BOOTLOADER_VERSION=0x06000001;S140;CONFIG_GPIO_AS_PINRESET;BLE_STACK_SUPPORT_REQD;SWI_DISABLE0;SOFTDEVICE_PRESENT;FLOAT_ABI_HARD;DFU_APP_DATA_RESERVED=7*4096" - c_user_include_directories="$(TusbDir);$(SdkDir);$(SdkDir)/device;$(SdkDir)/toolchain;$(SdkDir)/drivers_nrf/hal;$(SdkDir)/drivers_nrf/systick;$(SdkDir)/drivers_nrf/uart;$(SdkDir)/drivers_nrf/usbd;$(SdkDir)/drivers_nrf/common;$(SdkDir)/drivers_nrf/delay;$(SdkDir)/drivers_nrf/power;$(SdkDir)/drivers_nrf/clock;$(SdkDir)/drivers_nrf/pstorage;$(SdkDir)/external/fprintf;$(SdkDir)/libraries/util;$(SdkDir)/libraries/strerror;$(SdkDir)/libraries/atomic;$(SdkDir)/libraries/balloc;$(SdkDir)/libraries/experimental_log/src;$(SdkDir)/libraries/experimental_log;$(SdkDir)/libraries/experimental_section_vars;$(SdkDir)/libraries/experimental_memobj;$(SdkDir)/libraries/timer;$(SdkDir)/libraries/scheduler;$(SdkDir)/libraries/crc16;$(SdkDir)/libraries/util;$(SdkDir)/libraries/hci/config;$(SdkDir)/libraries/uart;$(SdkDir)/libraries/hci;$(SdkDir)/libraries/bootloader_dfu;$(SdkDir)/libraries/bootloader_dfu/hci_transport;$(SdkDir)/ble/common/;$(SdkDir)/ble/ble_services/ble_dfu;$(SdkDir)/ble/ble_services/ble_dis;$(SdDir)/s140/headers;$(SdDir)/s140/headers/nrf52;$(SdkDir)/toolchain/cmsis/include;../" + c_user_include_directories="../;$(TusbDir);$(SdDir)/s140/headers;$(SdDir)/s140/headers/nrf52;$(Sdk11Dir)/drivers_nrf/pstorage;$(Sdk11Dir)/ble/common/;$(Sdk11Dir)/ble/ble_services/ble_dfu;$(Sdk11Dir)/ble/ble_services/ble_dis;$(Sdk11Dir)/libraries/bootloader_dfu;$(Sdk11Dir)/libraries/bootloader_dfu/hci_transport;$(Sdk11Dir)/libraries/util;$(SdkDir)/toolchain/cmsis/include;$(SdkDir)/device;$(SdkDir)/toolchain;$(SdkDir)/drivers_nrf/hal;$(SdkDir)/drivers_nrf/systick;$(SdkDir)/drivers_nrf/uart;$(SdkDir)/drivers_nrf/usbd;$(SdkDir)/drivers_nrf/common;$(SdkDir)/drivers_nrf/delay;$(SdkDir)/drivers_nrf/power;$(SdkDir)/drivers_nrf/clock;$(SdkDir)/libraries/util;$(SdkDir)/libraries/timer;$(SdkDir)/libraries/scheduler;$(SdkDir)/libraries/crc16;$(SdkDir)/libraries/util;$(SdkDir)/libraries/hci/config;$(SdkDir)/libraries/uart;$(SdkDir)/libraries/hci;$(SdkDir)/external/fprintf;$(SdkDir)/libraries/strerror;$(SdkDir)/libraries/atomic;$(SdkDir)/libraries/balloc;$(SdkDir)/libraries/experimental_log/src;$(SdkDir)/libraries/experimental_log;$(SdkDir)/libraries/experimental_section_vars;$(SdkDir)/libraries/experimental_memobj" debug_register_definition_file="$(ProjectDir)/nrf52840_Registers.xml" debug_target_connection="J-Link" gcc_entry_point="Reset_Handler" linker_memory_map_file="$(ProjectDir)/nRF52840_xxAA_MemoryMap.xml" linker_section_placement_file="$(ProjectDir)/flash_placement.xml" - macros="DeviceHeaderFile=$(PackagesDir)/nRF/CMSIS/Device/Include/nrf.h;DeviceLibraryIdentifier=M4lf;DeviceSystemFile=$(PackagesDir)/nRF/CMSIS/Device/Source/system_nrf52840.c;DeviceVectorsFile=$(PackagesDir)/nRF/Source/ses_nrf52840_Vectors.s;DeviceFamily=nRF;Target=nRF52840_xxAA;Placement=Flash;TusbDir=../../lib/tinyusb/tinyusb;SdkDir=../../nRF5_SDK_11.0.0_89a8197/components;SdDir=../../softdevice/6.0.0" + macros="DeviceHeaderFile=$(PackagesDir)/nRF/CMSIS/Device/Include/nrf.h;DeviceLibraryIdentifier=M4lf;DeviceSystemFile=$(PackagesDir)/nRF/CMSIS/Device/Source/system_nrf52840.c;DeviceVectorsFile=$(PackagesDir)/nRF/Source/ses_nrf52840_Vectors.s;DeviceFamily=nRF;Target=nRF52840_xxAA;Placement=Flash;SdkDir=../../lib/sdk/components;Sdk11Dir=../../lib/sdk11/components;SdDir=../../softdevice/6.0.0;TusbDir=../../lib/tinyusb/tinyusb" project_directory="" project_type="Executable" target_reset_script="Reset();" @@ -49,222 +49,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -328,6 +112,144 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +