270 lines
6.1 KiB
C
270 lines
6.1 KiB
C
/**
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* Copyright (c) 2011 - 2017, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
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* Semiconductor ASA integrated circuit in a product or a software update for
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef _NRF_DELAY_H
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#define _NRF_DELAY_H
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#include "nrf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CLOCK_FREQ_16MHz (16000000UL)
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#ifdef NRF52_SERIES
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#define CPU_FREQ_64MHz
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#endif
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/**
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* @brief Function for delaying execution for number of microseconds.
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*
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* @note NRF52 has instruction cache and because of that delay is not precise.
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*
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* @param number_of_us
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*
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*/
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/*lint -e{438, 522, 40, 10, 563} */
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__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us);
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/**
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* @brief Function for delaying execution for number of miliseconds.
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*
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* @note NRF52 has instruction cache and because of that delay is not precise.
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*
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* @note Function internally calls @ref nrf_delay_us so the maximum delay is the
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* same as in case of @ref nrf_delay_us, approx. 71 minutes.
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*
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* @param number_of_ms
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*
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*/
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/*lint -e{438, 522, 40, 10, 563} */
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__STATIC_INLINE void nrf_delay_ms(uint32_t number_of_ms);
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#if defined ( __CC_ARM )
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__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us)
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{
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if (!number_of_us)
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return;
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__asm
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{
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loop:
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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CMP SystemCoreClock, CLOCK_FREQ_16MHz
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BEQ cond
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NOP
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#ifdef CPU_FREQ_64MHz
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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#endif //CPU_FREQ_64MHz
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cond:
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SUBS number_of_us, #1
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BNE loop
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}
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}
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#elif defined ( _WIN32 ) || defined ( __unix ) || defined( __APPLE__ )
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#ifndef CUSTOM_NRF_DELAY_US
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__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us)
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{}
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#endif
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#elif defined ( __GNUC__ ) || ( __ICCARM__ )
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__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us)
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{
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const uint32_t clock16MHz = CLOCK_FREQ_16MHz;
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if (number_of_us)
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{
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__ASM volatile (
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#if ( defined(__GNUC__) && (__CORTEX_M == (0x00U) ) )
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".syntax unified\n"
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#endif
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"1:\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" CMP %[SystemCoreClock], %[clock16MHz]\n"
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" BEQ.N 2f\n"
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" NOP\n"
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#ifdef CPU_FREQ_64MHz
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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" NOP\n"
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#endif //CPU_FREQ_64MHz
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"2:\n"
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" SUBS %[number_of_us], %[number_of_us], #1\n"
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" BNE.N 1b\n"
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#if ( defined(__GNUC__) && (__CORTEX_M == (0x00U) ) )
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".syntax divided\n"
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#endif
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#if ( __CORTEX_M == (0x00U) )
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// The SUBS instruction in Cortex-M0 is available only in 16-bit encoding,
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// hence it requires a "lo" register (r0-r7) as an operand.
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: [number_of_us] "=l" (number_of_us)
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#else
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: [number_of_us] "=r" (number_of_us)
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#endif
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: [SystemCoreClock] "r" (SystemCoreClock),
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[clock16MHz] "r" (clock16MHz),
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"[number_of_us]" (number_of_us)
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: "cc"
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);
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}
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}
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#endif
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__STATIC_INLINE void nrf_delay_ms(uint32_t number_of_ms)
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{
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nrf_delay_us(1000*number_of_ms);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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