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add files from nrf52832 bootloader project

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hathach 2018-02-07 23:32:49 +07:00
parent ac1f0e7955
commit 9f1d9f321e
186 changed files with 83021 additions and 0 deletions
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LICENSE Normal file
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MIT License
Copyright (c) 2016 Adafruit Industries
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

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nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.c Normal file
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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "ble_dfu.h"
#include "ble_types.h"
#include "ble_gatts.h"
#include "ble_srv_common.h"
#include <stddef.h>
#include "sdk_common.h"
#define MAX_DFU_PKT_LEN 20 /**< Maximum length (in bytes) of the DFU Packet characteristic. */
#define PKT_START_DFU_PARAM_LEN 2 /**< Length (in bytes) of the parameters for Packet Start DFU Request. */
#define PKT_INIT_DFU_PARAM_LEN 2 /**< Length (in bytes) of the parameters for Packet Init DFU Request. */
#define PKT_RCPT_NOTIF_REQ_LEN 3 /**< Length (in bytes) of the Packet Receipt Notification Request. */
#define MAX_PKTS_RCPT_NOTIF_LEN 6 /**< Maximum length (in bytes) of the Packets Receipt Notification. */
#define MAX_RESPONSE_LEN 7 /**< Maximum length (in bytes) of the response to a Control Point command. */
#define MAX_NOTIF_BUFFER_LEN MAX(MAX_PKTS_RCPT_NOTIF_LEN, MAX_RESPONSE_LEN) /**< Maximum length (in bytes) of the buffer needed by DFU Service while sending notifications to peer. */
enum
{
OP_CODE_START_DFU = 1, /**< Value of the Op code field for 'Start DFU' command.*/
OP_CODE_RECEIVE_INIT = 2, /**< Value of the Op code field for 'Initialize DFU parameters' command.*/
OP_CODE_RECEIVE_FW = 3, /**< Value of the Op code field for 'Receive firmware image' command.*/
OP_CODE_VALIDATE = 4, /**< Value of the Op code field for 'Validate firmware' command.*/
OP_CODE_ACTIVATE_N_RESET = 5, /**< Value of the Op code field for 'Activate & Reset' command.*/
OP_CODE_SYS_RESET = 6, /**< Value of the Op code field for 'Reset System' command.*/
OP_CODE_IMAGE_SIZE_REQ = 7, /**< Value of the Op code field for 'Report received image size' command.*/
OP_CODE_PKT_RCPT_NOTIF_REQ = 8, /**< Value of the Op code field for 'Request packet receipt notification.*/
OP_CODE_RESPONSE = 16, /**< Value of the Op code field for 'Response.*/
OP_CODE_PKT_RCPT_NOTIF = 17 /**< Value of the Op code field for 'Packets Receipt Notification'.*/
};
static bool m_is_dfu_service_initialized = false; /**< Variable to check if the DFU service was initialized by the application.*/
static uint8_t m_notif_buffer[MAX_NOTIF_BUFFER_LEN]; /**< Buffer used for sending notifications to peer. */
/**@brief Function for adding DFU Packet characteristic to the BLE Stack.
*
* @param[in] p_dfu DFU Service structure.
*
* @return NRF_SUCCESS on success. Otherwise an error code.
*/
static uint32_t dfu_pkt_char_add(ble_dfu_t * const p_dfu)
{
ble_gatts_char_md_t char_md;
ble_gatts_attr_t attr_char_value;
ble_uuid_t char_uuid;
ble_gatts_attr_md_t attr_md;
memset(&char_md, 0, sizeof(char_md));
char_md.char_props.write_wo_resp = 1;
char_md.p_char_user_desc = NULL;
char_md.p_char_pf = NULL;
char_md.p_user_desc_md = NULL;
char_md.p_cccd_md = NULL;
char_md.p_sccd_md = NULL;
char_uuid.type = p_dfu->uuid_type;
char_uuid.uuid = BLE_DFU_PKT_CHAR_UUID;
memset(&attr_md, 0, sizeof(attr_md));
BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.read_perm);
BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm);
attr_md.vloc = BLE_GATTS_VLOC_STACK;
attr_md.rd_auth = 0;
attr_md.wr_auth = 0;
attr_md.vlen = 1;
memset(&attr_char_value, 0, sizeof(attr_char_value));
attr_char_value.p_uuid = &char_uuid;
attr_char_value.p_attr_md = &attr_md;
attr_char_value.init_len = 0;
attr_char_value.init_offs = 0;
attr_char_value.max_len = MAX_DFU_PKT_LEN;
attr_char_value.p_value = NULL;
return sd_ble_gatts_characteristic_add(p_dfu->service_handle,
&char_md,
&attr_char_value,
&p_dfu->dfu_pkt_handles);
}
/**@brief Function for adding DFU Revision characteristic to the BLE Stack.
*
* @param[in] p_dfu DFU Service structure.
*
* @return NRF_SUCCESS on success. Otherwise an error code.
*/
static uint32_t dfu_rev_char_add(ble_dfu_t * const p_dfu, ble_dfu_init_t const * const p_dfu_init)
{
ble_gatts_char_md_t char_md;
ble_gatts_attr_t attr_char_value;
ble_uuid_t char_uuid;
ble_gatts_attr_md_t attr_md;
memset(&char_md, 0, sizeof(char_md));
char_md.char_props.read = 1;
char_md.p_char_user_desc = NULL;
char_md.p_char_pf = NULL;
char_md.p_user_desc_md = NULL;
char_md.p_cccd_md = NULL;
char_md.p_sccd_md = NULL;
char_uuid.type = p_dfu->uuid_type;
char_uuid.uuid = BLE_DFU_REV_CHAR_UUID;
memset(&attr_md, 0, sizeof(attr_md));
BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.read_perm);
BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.write_perm);
attr_md.vloc = BLE_GATTS_VLOC_STACK;
attr_md.rd_auth = 0;
attr_md.wr_auth = 0;
attr_md.vlen = 1;
memset(&attr_char_value, 0, sizeof(attr_char_value));
attr_char_value.p_uuid = &char_uuid;
attr_char_value.p_attr_md = &attr_md;
attr_char_value.init_len = sizeof(uint16_t);
attr_char_value.init_offs = 0;
attr_char_value.max_len = sizeof(uint16_t);
attr_char_value.p_value = (uint8_t *)&p_dfu_init->revision;
return sd_ble_gatts_characteristic_add(p_dfu->service_handle,
&char_md,
&attr_char_value,
&p_dfu->dfu_rev_handles);
}
/**@brief Function for adding DFU Control Point characteristic to the BLE Stack.
*
* @param[in] p_dfu DFU Service structure.
*
* @return NRF_SUCCESS on success. Otherwise an error code.
*/
static uint32_t dfu_ctrl_pt_add(ble_dfu_t * const p_dfu)
{
ble_gatts_char_md_t char_md;
ble_gatts_attr_t attr_char_value;
ble_uuid_t char_uuid;
ble_gatts_attr_md_t attr_md;
memset(&char_md, 0, sizeof(char_md));
char_md.char_props.write = 1;
char_md.char_props.notify = 1;
char_md.p_char_user_desc = NULL;
char_md.p_char_pf = NULL;
char_md.p_user_desc_md = NULL;
char_md.p_cccd_md = NULL;
char_md.p_sccd_md = NULL;
char_uuid.type = p_dfu->uuid_type;
char_uuid.uuid = BLE_DFU_CTRL_PT_UUID;
memset(&attr_md, 0, sizeof(attr_md));
BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.read_perm);
BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm);
attr_md.vloc = BLE_GATTS_VLOC_STACK;
attr_md.rd_auth = 0;
attr_md.wr_auth = 1;
attr_md.vlen = 1;
memset(&attr_char_value, 0, sizeof(attr_char_value));
attr_char_value.p_uuid = &char_uuid;
attr_char_value.p_attr_md = &attr_md;
attr_char_value.init_len = 0;
attr_char_value.init_offs = 0;
attr_char_value.max_len = BLE_GATT_ATT_MTU_DEFAULT;
attr_char_value.p_value = NULL;
return sd_ble_gatts_characteristic_add(p_dfu->service_handle,
&char_md,
&attr_char_value,
&p_dfu->dfu_ctrl_pt_handles);
}
/**@brief Function for handling the @ref BLE_GAP_EVT_CONNECTED event from the S110 SoftDevice.
*
* @param[in] p_dfu DFU Service Structure.
* @param[in] p_ble_evt Pointer to the event received from BLE stack.
*/
static void on_connect(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
{
p_dfu->conn_handle = p_ble_evt->evt.gap_evt.conn_handle;
}
/**@brief Function for checking if the CCCD of DFU Control point is configured for Notification.
*
* @details This function checks if the CCCD of DFU Control Point characteristic is configured
* for Notification by the DFU Controller.
*
* @param[in] p_dfu DFU Service structure.
*
* @return True if the CCCD of DFU Control Point characteristic is configured for Notification.
* False otherwise.
*/
static bool is_cccd_configured(ble_dfu_t * p_dfu)
{
// Check if the CCCDs are configured.
uint8_t cccd_val_buf[BLE_CCCD_VALUE_LEN];
ble_gatts_value_t gatts_value;
// Initialize value struct.
memset(&gatts_value, 0, sizeof(gatts_value));
gatts_value.len = BLE_CCCD_VALUE_LEN;
gatts_value.offset = 0;
gatts_value.p_value = cccd_val_buf;
// Check the CCCD Value of DFU Control Point.
uint32_t err_code = sd_ble_gatts_value_get(p_dfu->conn_handle,
p_dfu->dfu_ctrl_pt_handles.cccd_handle,
&gatts_value);
if (err_code != NRF_SUCCESS)
{
if (p_dfu->error_handler != NULL)
{
p_dfu->error_handler(err_code);
}
return false;
}
return ble_srv_is_notification_enabled(cccd_val_buf);
}
/**@brief Function for handling a Write event on the Control Point characteristic.
*
* @param[in] p_dfu DFU Service Structure.
* @param[in] p_ble_write_evt Pointer to the write event received from BLE stack.
*
* @return NRF_SUCCESS on successful processing of control point write. Otherwise an error code.
*/
static uint32_t on_ctrl_pt_write(ble_dfu_t * p_dfu, ble_gatts_evt_write_t * p_ble_write_evt)
{
ble_gatts_rw_authorize_reply_params_t auth_reply;
auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE;
auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE;
auth_reply.params.write.update = 1;
auth_reply.params.write.offset = p_ble_write_evt->offset;
auth_reply.params.write.len = p_ble_write_evt->len;
auth_reply.params.write.p_data = p_ble_write_evt->data;
if (!is_cccd_configured(p_dfu))
{
// Send an error response to the peer indicating that the CCCD is improperly configured.
auth_reply.params.write.gatt_status =
BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR;
return (sd_ble_gatts_rw_authorize_reply(p_dfu->conn_handle, &auth_reply));
}
else
{
uint32_t err_code;
auth_reply.params.write.gatt_status = BLE_GATT_STATUS_SUCCESS;
err_code = (sd_ble_gatts_rw_authorize_reply(p_dfu->conn_handle, &auth_reply));
VERIFY_SUCCESS(err_code);
}
ble_dfu_evt_t ble_dfu_evt;
switch (p_ble_write_evt->data[0])
{
case OP_CODE_START_DFU:
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_START;
if (p_ble_write_evt->len < PKT_START_DFU_PARAM_LEN)
{
return ble_dfu_response_send(p_dfu,
(ble_dfu_procedure_t) p_ble_write_evt->data[0],
BLE_DFU_RESP_VAL_OPER_FAILED);
}
ble_dfu_evt.evt.ble_dfu_pkt_write.len = 1;
ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = &(p_ble_write_evt->data[1]);
p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
break;
case OP_CODE_RECEIVE_INIT:
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_RECEIVE_INIT_DATA;
if (p_ble_write_evt->len < PKT_INIT_DFU_PARAM_LEN)
{
return ble_dfu_response_send(p_dfu,
(ble_dfu_procedure_t) p_ble_write_evt->data[0],
BLE_DFU_RESP_VAL_OPER_FAILED);
}
ble_dfu_evt.evt.ble_dfu_pkt_write.len = 1;
ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = &(p_ble_write_evt->data[1]);
p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
break;
case OP_CODE_RECEIVE_FW:
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_RECEIVE_APP_DATA;
p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
break;
case OP_CODE_VALIDATE:
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_VALIDATE;
p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
break;
case OP_CODE_ACTIVATE_N_RESET:
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_ACTIVATE_N_RESET;
p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
break;
case OP_CODE_SYS_RESET:
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_SYS_RESET;
p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
break;
case OP_CODE_PKT_RCPT_NOTIF_REQ:
if (p_ble_write_evt->len < PKT_RCPT_NOTIF_REQ_LEN)
{
return (ble_dfu_response_send(p_dfu,
BLE_DFU_PKT_RCPT_REQ_PROCEDURE,
BLE_DFU_RESP_VAL_NOT_SUPPORTED));
}
ble_dfu_evt.evt.pkt_rcpt_notif_req.num_of_pkts =
uint16_decode(&(p_ble_write_evt->data[1]));
if (ble_dfu_evt.evt.pkt_rcpt_notif_req.num_of_pkts == 0)
{
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PKT_RCPT_NOTIF_DISABLED;
}
else
{
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PKT_RCPT_NOTIF_ENABLED;
}
p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
break;
case OP_CODE_IMAGE_SIZE_REQ:
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_BYTES_RECEIVED_SEND;
p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
break;
default:
// Unsupported op code.
return ble_dfu_response_send(p_dfu,
(ble_dfu_procedure_t) p_ble_write_evt->data[0],
BLE_DFU_RESP_VAL_NOT_SUPPORTED);
}
return NRF_SUCCESS;
}
/**@brief Function for handling the @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event from the S110
* Stack.
*
* @param[in] p_dfu DFU Service Structure.
* @param[in] p_ble_evt Pointer to the event received from BLE stack.
*/
static void on_rw_authorize_req(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
{
ble_gatts_evt_rw_authorize_request_t * p_authorize_request;
p_authorize_request = &(p_ble_evt->evt.gatts_evt.params.authorize_request);
if (
(p_authorize_request->type == BLE_GATTS_AUTHORIZE_TYPE_WRITE)
&&
(p_authorize_request->request.write.handle == p_dfu->dfu_ctrl_pt_handles.value_handle)
&&
(p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op != BLE_GATTS_OP_PREP_WRITE_REQ)
&&
(p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op != BLE_GATTS_OP_EXEC_WRITE_REQ_NOW)
&&
(p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op != BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL)
)
{
uint32_t err_code;
err_code = on_ctrl_pt_write(p_dfu, &(p_authorize_request->request.write));
if (err_code != NRF_SUCCESS && p_dfu->error_handler != NULL)
{
p_dfu->error_handler(err_code);
}
}
}
/**@brief Function for handling the @ref BLE_GATTS_EVT_WRITE event from the S110 SoftDevice.
*
* @param[in] p_dfu DFU Service Structure.
* @param[in] p_ble_evt Pointer to the event received from BLE stack.
*/
static void on_write(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
{
if (p_ble_evt->evt.gatts_evt.params.write.handle == p_dfu->dfu_pkt_handles.value_handle)
{
// DFU Packet written
ble_dfu_evt_t ble_dfu_evt;
ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PACKET_WRITE;
ble_dfu_evt.evt.ble_dfu_pkt_write.len = p_ble_evt->evt.gatts_evt.params.write.len;
ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = p_ble_evt->evt.gatts_evt.params.write.data;
p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
}
}
/**@brief Function for handling the BLE_GAP_EVT_DISCONNECTED event from the S110 SoftDevice.
*
* @param[in] p_dfu DFU Service Structure.
* @param[in] p_ble_evt Pointer to the event received from BLE stack.
*/
static void on_disconnect(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
{
p_dfu->conn_handle = BLE_CONN_HANDLE_INVALID;
}
uint32_t ble_dfu_init(ble_dfu_t * p_dfu, ble_dfu_init_t * p_dfu_init)
{
if ((p_dfu == NULL) || (p_dfu_init == NULL) || (p_dfu_init->evt_handler == NULL))
{
return NRF_ERROR_NULL;
}
p_dfu->conn_handle = BLE_CONN_HANDLE_INVALID;
ble_uuid_t service_uuid;
uint32_t err_code;
const ble_uuid128_t base_uuid128 =
{
{
0x23, 0xD1, 0xBC, 0xEA, 0x5F, 0x78, 0x23, 0x15,
0xDE, 0xEF, 0x12, 0x12, 0x00, 0x00, 0x00, 0x00
}
};
service_uuid.uuid = BLE_DFU_SERVICE_UUID;
err_code = sd_ble_uuid_vs_add(&base_uuid128, &(service_uuid.type));
VERIFY_SUCCESS(err_code);
err_code = sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY,
&service_uuid,
&(p_dfu->service_handle));
VERIFY_SUCCESS(err_code);
p_dfu->uuid_type = service_uuid.type;
err_code = dfu_pkt_char_add(p_dfu);
VERIFY_SUCCESS(err_code);
err_code = dfu_ctrl_pt_add(p_dfu);
VERIFY_SUCCESS(err_code);
err_code = dfu_rev_char_add(p_dfu, p_dfu_init);
VERIFY_SUCCESS(err_code);
p_dfu->evt_handler = p_dfu_init->evt_handler;
if (p_dfu_init->error_handler != NULL)
{
p_dfu->error_handler = p_dfu_init->error_handler;
}
m_is_dfu_service_initialized = true;
return NRF_SUCCESS;
}
void ble_dfu_on_ble_evt(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
{
if ((p_dfu == NULL) || (p_ble_evt == NULL))
{
return;
}
if (p_dfu->evt_handler != NULL)
{
switch (p_ble_evt->header.evt_id)
{
case BLE_GAP_EVT_CONNECTED:
on_connect(p_dfu, p_ble_evt);
break;
case BLE_GATTS_EVT_WRITE:
on_write(p_dfu, p_ble_evt);
break;
case BLE_GAP_EVT_DISCONNECTED:
on_disconnect(p_dfu, p_ble_evt);
break;
case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST:
on_rw_authorize_req(p_dfu, p_ble_evt);
break;
default:
// No implementation needed.
break;
}
}
}
uint32_t ble_dfu_bytes_rcvd_report(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd)
{
if (p_dfu == NULL)
{
return NRF_ERROR_NULL;
}
if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized)
{
return NRF_ERROR_INVALID_STATE;
}
ble_gatts_hvx_params_t hvx_params;
uint16_t index = 0;
// Encode the Op Code.
m_notif_buffer[index++] = OP_CODE_RESPONSE;
// Encode the Reqest Op Code.
m_notif_buffer[index++] = OP_CODE_IMAGE_SIZE_REQ;
// Encode the Response Value.
m_notif_buffer[index++] = (uint8_t)BLE_DFU_RESP_VAL_SUCCESS;
index += uint32_encode(num_of_firmware_bytes_rcvd, &m_notif_buffer[index]);
memset(&hvx_params, 0, sizeof(hvx_params));
hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle;
hvx_params.type = BLE_GATT_HVX_NOTIFICATION;
hvx_params.offset = 0;
hvx_params.p_len = &index;
hvx_params.p_data = m_notif_buffer;
return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params);
}
uint32_t ble_dfu_pkts_rcpt_notify(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd)
{
if (p_dfu == NULL)
{
return NRF_ERROR_NULL;
}
if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized)
{
return NRF_ERROR_INVALID_STATE;
}
ble_gatts_hvx_params_t hvx_params;
uint16_t index = 0;
m_notif_buffer[index++] = OP_CODE_PKT_RCPT_NOTIF;
index += uint32_encode(num_of_firmware_bytes_rcvd, &m_notif_buffer[index]);
memset(&hvx_params, 0, sizeof(hvx_params));
hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle;
hvx_params.type = BLE_GATT_HVX_NOTIFICATION;
hvx_params.offset = 0;
hvx_params.p_len = &index;
hvx_params.p_data = m_notif_buffer;
return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params);
}
uint32_t ble_dfu_response_send(ble_dfu_t * p_dfu,
ble_dfu_procedure_t dfu_proc,
ble_dfu_resp_val_t resp_val)
{
if (p_dfu == NULL)
{
return NRF_ERROR_NULL;
}
if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized)
{
return NRF_ERROR_INVALID_STATE;
}
ble_gatts_hvx_params_t hvx_params;
uint16_t index = 0;
m_notif_buffer[index++] = OP_CODE_RESPONSE;
// Encode the Request Op code
m_notif_buffer[index++] = (uint8_t)dfu_proc;
// Encode the Response Value.
m_notif_buffer[index++] = (uint8_t)resp_val;
memset(&hvx_params, 0, sizeof(hvx_params));
hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle;
hvx_params.type = BLE_GATT_HVX_NOTIFICATION;
hvx_params.offset = 0;
hvx_params.p_len = &index;
hvx_params.p_data = m_notif_buffer;
return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params);
}

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup ble_sdk_srv_dfu Device Firmware Update Service
* @{
* @ingroup ble_sdk_srv
* @brief Device Firmware Update Service
*
* @details The Device Firmware Update (DFU) service is a GATT based service that can be used for
* performing firmware updates over BLE. Note that this implementation uses vendor
* specific UUIDs for service and characteristics and is intended to demonstrate the
* firmware updates over BLE. Refer @ref bledfu_transport_bleservice and @ref
* bledfu_transport_bleprofile for more information on the service and profile respectively.
*/
#ifndef BLE_DFU_H__
#define BLE_DFU_H__
#include <stdint.h>
#include "ble_gatts.h"
#include "ble_gap.h"
#include "ble.h"
#include "ble_srv_common.h"
#define BLE_DFU_SERVICE_UUID 0x1530 /**< The UUID of the DFU Service. */
#define BLE_DFU_PKT_CHAR_UUID 0x1532 /**< The UUID of the DFU Packet Characteristic. */
#define BLE_DFU_CTRL_PT_UUID 0x1531 /**< The UUID of the DFU Control Point. */
#define BLE_DFU_STATUS_REP_UUID 0x1533 /**< The UUID of the DFU Status Report Characteristic. */
#define BLE_DFU_REV_CHAR_UUID 0x1534 /**< The UUID of the DFU Revision Characteristic. */
/**@brief DFU Event type.
*
* @details This enumeration contains the types of events that will be received from the DFU Service.
*/
typedef enum
{
BLE_DFU_START, /**< The event indicating that the peer wants the application to prepare for a new firmware update. */
BLE_DFU_RECEIVE_INIT_DATA, /**< The event indicating that the peer wants the application to prepare to receive init parameters. */
BLE_DFU_RECEIVE_APP_DATA, /**< The event indicating that the peer wants the application to prepare to receive the new firmware image. */
BLE_DFU_VALIDATE, /**< The event indicating that the peer wants the application to validate the newly received firmware image. */
BLE_DFU_ACTIVATE_N_RESET, /**< The event indicating that the peer wants the application to undergo activate new firmware and restart with new valid application */
BLE_DFU_SYS_RESET, /**< The event indicating that the peer wants the application to undergo a reset and start the currently valid application image.*/
BLE_DFU_PKT_RCPT_NOTIF_ENABLED, /**< The event indicating that the peer has enabled packet receipt notifications. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify each time the number of packets indicated by num_of_pkts field in @ref ble_dfu_evt_t is received.*/
BLE_DFU_PKT_RCPT_NOTIF_DISABLED, /**< The event indicating that the peer has disabled the packet receipt notifications.*/
BLE_DFU_PACKET_WRITE, /**< The event indicating that the peer has written a value to the 'DFU Packet' characteristic. The data received from the peer will be present in the @ref BLE_DFU_PACKET_WRITE element contained within @ref ble_dfu_evt_t.*/
BLE_DFU_BYTES_RECEIVED_SEND /**< The event indicating that the peer is requesting for the number of bytes of firmware data last received by the application. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify in response to this event. */
} ble_dfu_evt_type_t;
/**@brief DFU Procedure type.
*
* @details This enumeration contains the types of DFU procedures.
*/
typedef enum
{
BLE_DFU_START_PROCEDURE = 1, /**< DFU Start procedure.*/
BLE_DFU_INIT_PROCEDURE = 2, /**< DFU Initialization procedure.*/
BLE_DFU_RECEIVE_APP_PROCEDURE = 3, /**< Firmware receiving procedure.*/
BLE_DFU_VALIDATE_PROCEDURE = 4, /**< Firmware image validation procedure .*/
BLE_DFU_PKT_RCPT_REQ_PROCEDURE = 8 /**< Packet receipt notification request procedure. */
} ble_dfu_procedure_t;
/**@brief DFU Response value type.
*/
typedef enum
{
BLE_DFU_RESP_VAL_SUCCESS = 1, /**< Success.*/
BLE_DFU_RESP_VAL_INVALID_STATE, /**< Invalid state.*/
BLE_DFU_RESP_VAL_NOT_SUPPORTED, /**< Operation not supported.*/
BLE_DFU_RESP_VAL_DATA_SIZE, /**< Data size exceeds limit.*/
BLE_DFU_RESP_VAL_CRC_ERROR, /**< CRC Error.*/
BLE_DFU_RESP_VAL_OPER_FAILED /**< Operation failed.*/
} ble_dfu_resp_val_t;
/**@brief DFU Packet structure.
*
* @details This structure contains the value of the DFU Packet characteristic as written by the
* peer and the length of the value written. It will be filled by the DFU Service when the
* peer writes to the DFU Packet characteristic.
*/
typedef struct
{
uint8_t * p_data; /**< Pointer to the received packet. This will point to a word aligned memory location.*/
uint8_t len; /**< Length of the packet received. */
} ble_dfu_pkt_write_t;
/**@brief Packet receipt notification request structure.
*
* @details This structure contains the contents of the packet receipt notification request
* sent by the DFU Controller.
*/
typedef struct
{
uint16_t num_of_pkts; /**< The number of packets of firmware data to be received by application before sending the next Packet Receipt Notification to the peer. */
} ble_pkt_rcpt_notif_req_t;
/**@brief DFU Event structure.
*
* @details This structure contains the event generated by the DFU Service based on the data
* received from the peer.
*/
typedef struct
{
ble_dfu_evt_type_t ble_dfu_evt_type; /**< Type of the event.*/
union
{
ble_dfu_pkt_write_t ble_dfu_pkt_write; /**< The DFU packet received. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PACKET_WRITE.*/
ble_pkt_rcpt_notif_req_t pkt_rcpt_notif_req; /**< Packet receipt notification request. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PKT_RCPT_NOTIF_ENABLED.*/
} evt;
} ble_dfu_evt_t;
// Forward declaration of the ble_dfu_t type.
typedef struct ble_dfu_s ble_dfu_t;
/**@brief DFU Service event handler type. */
typedef void (*ble_dfu_evt_handler_t) (ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt);
/**@brief DFU service structure.
*
* @details This structure contains status information related to the service.
*/
struct ble_dfu_s
{
uint16_t conn_handle; /**< Handle of the current connection (as provided by the SoftDevice). This will be BLE_CONN_HANDLE_INVALID when not in a connection. */
uint16_t revision; /**< Handle of DFU Service (as provided by the SoftDevice). */
uint16_t service_handle; /**< Handle of DFU Service (as provided by the SoftDevice). */
uint8_t uuid_type; /**< UUID type assigned for DFU Service by the SoftDevice. */
ble_gatts_char_handles_t dfu_pkt_handles; /**< Handles related to the DFU Packet characteristic. */
ble_gatts_char_handles_t dfu_ctrl_pt_handles; /**< Handles related to the DFU Control Point characteristic. */
ble_gatts_char_handles_t dfu_status_rep_handles; /**< Handles related to the DFU Status Report characteristic. */
ble_gatts_char_handles_t dfu_rev_handles; /**< Handles related to the DFU Revision characteristic. */
ble_dfu_evt_handler_t evt_handler; /**< The event handler to be called when an event is to be sent to the application.*/
ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
};
/**@brief DFU service initialization structure.
*
* @details This structure contains the initialization information for the DFU Service. The
* application needs to fill this structure and pass it to the DFU Service using the
* @ref ble_dfu_init function.
*/
typedef struct
{
uint16_t revision; /**< Revision number to be exposed by the DFU service. */
ble_dfu_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Device Firmware Update Service. */
ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
} ble_dfu_init_t;
/**@brief Function for handling a BLE event.
*
* @details The DFU service expects the application to call this function each time an event
* is received from the SoftDevice. This function processes the event, if it is
* relevant for the DFU service and calls the DFU event handler of the application if
* necessary.
*
* @param[in] p_dfu Pointer to the DFU service structure.
* @param[in] p_ble_evt Pointer to the event received from SoftDevice.
*/
void ble_dfu_on_ble_evt(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt);
/**@brief Function for initializing the DFU service.
*
* @param[out] p_dfu Device Firmware Update service structure. This structure will have to be
* supplied by the application. It will be initialized by this function,
* and will later be used to identify the service instance.
* @param[in] p_dfu_init Information needed to initialize the service.
*
* @return NRF_SUCCESS if the DFU service and its characteristics were successfully added to the
* SoftDevice. Otherwise an error code.
* This function returns NRF_ERROR_NULL if the value of evt_handler in p_dfu_init
* structure provided is NULL or if the pointers supplied as input are NULL.
*/
uint32_t ble_dfu_init(ble_dfu_t * p_dfu, ble_dfu_init_t * p_dfu_init);
/**@brief Function for sending response to a control point command.
*
* @details This function will encode a DFU Control Point response using the given input
* parameters and will send a notification of the same to the peer.
*
* @param[in] p_dfu Pointer to the DFU service structure.
* @param[in] dfu_proc Procedure for which this response is to be sent.
* @param[in] resp_val Response value.
*
* @return NRF_SUCCESS if the DFU Service has successfully requested the SoftDevice to
* send the notification. Otherwise an error code.
* This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
* peer or if the DFU service is not initialized or if the notification of the DFU
* Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
* if the pointer p_dfu is NULL.
*/
uint32_t ble_dfu_response_send(ble_dfu_t * p_dfu,
ble_dfu_procedure_t dfu_proc,
ble_dfu_resp_val_t resp_val);
/**@brief Function for notifying the peer about the number of bytes of firmware data received.
*
* @param[in] p_dfu Pointer to the DFU service structure.
* @param[in] num_of_firmware_bytes_rcvd Number of bytes.
*
* @return NRF_SUCCESS if the DFU Service has successfully requested the SoftDevice to send
* the notification. Otherwise an error code.
* This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
* peer or if the DFU service is not initialized or if the notification of the DFU
* Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
* if the pointer p_dfu is NULL.
*/
uint32_t ble_dfu_bytes_rcvd_report(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd);
/**@brief Function for sending Packet Receipt Notification to the peer.
*
* This function will encode the number of bytes received as input parameter into a
* notification of the control point characteristic and send it to the peer.
*
* @param[in] p_dfu Pointer to the DFU service structure.
* @param[in] num_of_firmware_bytes_rcvd Number of bytes of firmware image received.
*
* @return NRF_SUCCESS if the DFU Service has successfully requested the SoftDevice to send
* the notification. Otherwise an error code.
* This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
* peer or if the DFU service is not initialized or if the notification of the DFU
* Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
* if the pointer p_dfu is NULL.
*/
uint32_t ble_dfu_pkts_rcpt_notify(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd);
#endif // BLE_DFU_H__
/** @} */

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/* Attention!
* To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile
* qualification listings, this section of source code must not be modified.
*/
#include "ble_dis.h"
#include <stdlib.h>
#include <string.h>
#include "app_error.h"
#include "ble_gatts.h"
#include "nordic_common.h"
#include "ble_srv_common.h"
#include "app_util.h"
#define BLE_DIS_SYS_ID_LEN 8 /**< Length of System ID Characteristic Value. */
#define BLE_DIS_PNP_ID_LEN 7 /**< Length of Pnp ID Characteristic Value. */
static uint16_t service_handle;
static ble_gatts_char_handles_t manufact_name_handles;
static ble_gatts_char_handles_t model_num_handles;
static ble_gatts_char_handles_t serial_num_handles;
static ble_gatts_char_handles_t hw_rev_handles;
static ble_gatts_char_handles_t fw_rev_handles;
static ble_gatts_char_handles_t sw_rev_handles;
static ble_gatts_char_handles_t sys_id_handles;
static ble_gatts_char_handles_t reg_cert_data_list_handles;
static ble_gatts_char_handles_t pnp_id_handles;
/**@brief Function for encoding a System ID.
*
* @param[out] p_encoded_buffer Buffer where the encoded data will be written.
* @param[in] p_sys_id System ID to be encoded.
*/
static void sys_id_encode(uint8_t * p_encoded_buffer, const ble_dis_sys_id_t * p_sys_id)
{
APP_ERROR_CHECK_BOOL(p_sys_id != NULL);
APP_ERROR_CHECK_BOOL(p_encoded_buffer != NULL);
p_encoded_buffer[0] = (p_sys_id->manufacturer_id & 0x00000000FF);
p_encoded_buffer[1] = (p_sys_id->manufacturer_id & 0x000000FF00) >> 8;
p_encoded_buffer[2] = (p_sys_id->manufacturer_id & 0x0000FF0000) >> 16;
p_encoded_buffer[3] = (p_sys_id->manufacturer_id & 0x00FF000000) >> 24;
p_encoded_buffer[4] = (p_sys_id->manufacturer_id & 0xFF00000000) >> 32;
p_encoded_buffer[5] = (p_sys_id->organizationally_unique_id & 0x0000FF);
p_encoded_buffer[6] = (p_sys_id->organizationally_unique_id & 0x00FF00) >> 8;
p_encoded_buffer[7] = (p_sys_id->organizationally_unique_id & 0xFF0000) >> 16;
}
/**@brief Function for encoding a PnP ID.
*
* @param[out] p_encoded_buffer Buffer where the encoded data will be written.
* @param[in] p_pnp_id PnP ID to be encoded.
*/
static void pnp_id_encode(uint8_t * p_encoded_buffer, const ble_dis_pnp_id_t * p_pnp_id)
{
uint8_t len = 0;
APP_ERROR_CHECK_BOOL(p_pnp_id != NULL);
APP_ERROR_CHECK_BOOL(p_encoded_buffer != NULL);
p_encoded_buffer[len++] = p_pnp_id->vendor_id_source;
len += uint16_encode(p_pnp_id->vendor_id, &p_encoded_buffer[len]);
len += uint16_encode(p_pnp_id->product_id, &p_encoded_buffer[len]);
len += uint16_encode(p_pnp_id->product_version, &p_encoded_buffer[len]);
APP_ERROR_CHECK_BOOL(len == BLE_DIS_PNP_ID_LEN);
}
/**@brief Function for adding the Characteristic.
*
* @param[in] uuid UUID of characteristic to be added.
* @param[in] p_char_value Initial value of characteristic to be added.
* @param[in] char_len Length of initial value. This will also be the maximum value.
* @param[in] dis_attr_md Security settings of characteristic to be added.
* @param[out] p_handles Handles of new characteristic.
*
* @return NRF_SUCCESS on success, otherwise an error code.
*/
static uint32_t char_add(uint16_t uuid,
uint8_t * p_char_value,
uint16_t char_len,
const ble_srv_security_mode_t * dis_attr_md,
ble_gatts_char_handles_t * p_handles)
{
ble_uuid_t ble_uuid;
ble_gatts_char_md_t char_md;
ble_gatts_attr_t attr_char_value;
ble_gatts_attr_md_t attr_md;
APP_ERROR_CHECK_BOOL(p_char_value != NULL);
APP_ERROR_CHECK_BOOL(char_len > 0);
// The ble_gatts_char_md_t structure uses bit fields. So we reset the memory to zero.
memset(&char_md, 0, sizeof(char_md));
char_md.char_props.read = 1;
char_md.p_char_user_desc = NULL;
char_md.p_char_pf = NULL;
char_md.p_user_desc_md = NULL;
char_md.p_cccd_md = NULL;
char_md.p_sccd_md = NULL;
BLE_UUID_BLE_ASSIGN(ble_uuid, uuid);
memset(&attr_md, 0, sizeof(attr_md));
attr_md.read_perm = dis_attr_md->read_perm;
attr_md.write_perm = dis_attr_md->write_perm;
attr_md.vloc = BLE_GATTS_VLOC_STACK;
attr_md.rd_auth = 0;
attr_md.wr_auth = 0;
attr_md.vlen = 0;
memset(&attr_char_value, 0, sizeof(attr_char_value));
attr_char_value.p_uuid = &ble_uuid;
attr_char_value.p_attr_md = &attr_md;
attr_char_value.init_len = char_len;
attr_char_value.init_offs = 0;
attr_char_value.max_len = char_len;
attr_char_value.p_value = p_char_value;
return sd_ble_gatts_characteristic_add(service_handle, &char_md, &attr_char_value, p_handles);
}
uint32_t ble_dis_init(const ble_dis_init_t * p_dis_init)
{
uint32_t err_code;
ble_uuid_t ble_uuid;
// Add service
BLE_UUID_BLE_ASSIGN(ble_uuid, BLE_UUID_DEVICE_INFORMATION_SERVICE);
err_code = sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY, &ble_uuid, &service_handle);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
// Add characteristics
if (p_dis_init->manufact_name_str.length > 0)
{
err_code = char_add(BLE_UUID_MANUFACTURER_NAME_STRING_CHAR,
p_dis_init->manufact_name_str.p_str,
p_dis_init->manufact_name_str.length,
&p_dis_init->dis_attr_md,
&manufact_name_handles);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
if (p_dis_init->model_num_str.length > 0)
{
err_code = char_add(BLE_UUID_MODEL_NUMBER_STRING_CHAR,
p_dis_init->model_num_str.p_str,
p_dis_init->model_num_str.length,
&p_dis_init->dis_attr_md,
&model_num_handles);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
if (p_dis_init->serial_num_str.length > 0)
{
err_code = char_add(BLE_UUID_SERIAL_NUMBER_STRING_CHAR,
p_dis_init->serial_num_str.p_str,
p_dis_init->serial_num_str.length,
&p_dis_init->dis_attr_md,
&serial_num_handles);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
if (p_dis_init->hw_rev_str.length > 0)
{
err_code = char_add(BLE_UUID_HARDWARE_REVISION_STRING_CHAR,
p_dis_init->hw_rev_str.p_str,
p_dis_init->hw_rev_str.length,
&p_dis_init->dis_attr_md,
&hw_rev_handles);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
if (p_dis_init->fw_rev_str.length > 0)
{
err_code = char_add(BLE_UUID_FIRMWARE_REVISION_STRING_CHAR,
p_dis_init->fw_rev_str.p_str,
p_dis_init->fw_rev_str.length,
&p_dis_init->dis_attr_md,
&fw_rev_handles);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
if (p_dis_init->sw_rev_str.length > 0)
{
err_code = char_add(BLE_UUID_SOFTWARE_REVISION_STRING_CHAR,
p_dis_init->sw_rev_str.p_str,
p_dis_init->sw_rev_str.length,
&p_dis_init->dis_attr_md,
&sw_rev_handles);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
if (p_dis_init->p_sys_id != NULL)
{
uint8_t encoded_sys_id[BLE_DIS_SYS_ID_LEN];
sys_id_encode(encoded_sys_id, p_dis_init->p_sys_id);
err_code = char_add(BLE_UUID_SYSTEM_ID_CHAR,
encoded_sys_id,
BLE_DIS_SYS_ID_LEN,
&p_dis_init->dis_attr_md,
&sys_id_handles);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
if (p_dis_init->p_reg_cert_data_list != NULL)
{
err_code = char_add(BLE_UUID_IEEE_REGULATORY_CERTIFICATION_DATA_LIST_CHAR,
p_dis_init->p_reg_cert_data_list->p_list,
p_dis_init->p_reg_cert_data_list->list_len,
&p_dis_init->dis_attr_md,
&reg_cert_data_list_handles);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
if (p_dis_init->p_pnp_id != NULL)
{
uint8_t encoded_pnp_id[BLE_DIS_PNP_ID_LEN];
pnp_id_encode(encoded_pnp_id, p_dis_init->p_pnp_id);
err_code = char_add(BLE_UUID_PNP_ID_CHAR,
encoded_pnp_id,
BLE_DIS_PNP_ID_LEN,
&p_dis_init->dis_attr_md,
&pnp_id_handles);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
return NRF_SUCCESS;
}

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup ble_sdk_srv_dis Device Information Service
* @{
* @ingroup ble_sdk_srv
* @brief Device Information Service module.
*
* @details This module implements the Device Information Service.
* During initialization it adds the Device Information Service to the BLE stack database.
* It then encodes the supplied information, and adds the curresponding characteristics.
*
* @note Attention!
* To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
* qualification listings, this section of source code must not be modified.
*/
#ifndef BLE_DIS_H__
#define BLE_DIS_H__
#include <stdint.h>
#include "ble_srv_common.h"
/** @defgroup DIS_VENDOR_ID_SRC_VALUES Vendor ID Source values
* @{
*/
#define BLE_DIS_VENDOR_ID_SRC_BLUETOOTH_SIG 1 /**< Vendor ID assigned by Bluetooth SIG. */
#define BLE_DIS_VENDOR_ID_SRC_USB_IMPL_FORUM 2 /**< Vendor ID assigned by USB Implementer's Forum. */
/** @} */
/**@brief System ID parameters */
typedef struct
{
uint64_t manufacturer_id; /**< Manufacturer ID. Only 5 LSOs shall be used. */
uint32_t organizationally_unique_id; /**< Organizationally unique ID. Only 3 LSOs shall be used. */
} ble_dis_sys_id_t;
/**@brief IEEE 11073-20601 Regulatory Certification Data List Structure */
typedef struct
{
uint8_t * p_list; /**< Pointer the byte array containing the encoded opaque structure based on IEEE 11073-20601 specification. */
uint8_t list_len; /**< Length of the byte array. */
} ble_dis_reg_cert_data_list_t;
/**@brief PnP ID parameters */
typedef struct
{
uint8_t vendor_id_source; /**< Vendor ID Source. see @ref DIS_VENDOR_ID_SRC_VALUES. */
uint16_t vendor_id; /**< Vendor ID. */
uint16_t product_id; /**< Product ID. */
uint16_t product_version; /**< Product Version. */
} ble_dis_pnp_id_t;
/**@brief Device Information Service init structure. This contains all possible characteristics
* needed for initialization of the service.
*/
typedef struct
{
ble_srv_utf8_str_t manufact_name_str; /**< Manufacturer Name String. */
ble_srv_utf8_str_t model_num_str; /**< Model Number String. */
ble_srv_utf8_str_t serial_num_str; /**< Serial Number String. */
ble_srv_utf8_str_t hw_rev_str; /**< Hardware Revision String. */
ble_srv_utf8_str_t fw_rev_str; /**< Firmware Revision String. */
ble_srv_utf8_str_t sw_rev_str; /**< Software Revision String. */
ble_dis_sys_id_t * p_sys_id; /**< System ID. */
ble_dis_reg_cert_data_list_t * p_reg_cert_data_list; /**< IEEE 11073-20601 Regulatory Certification Data List. */
ble_dis_pnp_id_t * p_pnp_id; /**< PnP ID. */
ble_srv_security_mode_t dis_attr_md; /**< Initial Security Setting for Device Information Characteristics. */
} ble_dis_init_t;
/**@brief Function for initializing the Device Information Service.
*
* @details This call allows the application to initialize the device information service.
* It adds the DIS service and DIS characteristics to the database, using the initial
* values supplied through the p_dis_init parameter. Characteristics which are not to be
* added, shall be set to NULL in p_dis_init.
*
* @param[in] p_dis_init The structure containing the values of characteristics needed by the
* service.
*
* @return NRF_SUCCESS on successful initialization of service.
*/
uint32_t ble_dis_init(const ble_dis_init_t * p_dis_init);
#endif // BLE_DIS_H__
/** @} */

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "ble_advdata.h"
#include "ble_gap.h"
#include "ble_srv_common.h"
#include "sdk_common.h"
// NOTE: For now, Security Manager Out of Band Flags (OOB) are omitted from the advertising data.
// Types of LE Bluetooth Device Address AD type
#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_PUBLIC 0UL
#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_RANDOM 1UL
static uint32_t tk_value_encode(ble_advdata_tk_value_t * p_tk_value,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
int8_t i;
// Check for buffer overflow.
if (((*p_offset) + AD_TYPE_TK_VALUE_SIZE) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
// Encode LE Role.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_TK_VALUE_DATA_SIZE);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
for (i = AD_TYPE_TK_VALUE_DATA_SIZE - 1; i >= 0; i--, (*p_offset)++)
{
p_encoded_data[*p_offset] = p_tk_value->tk[i];
}
return NRF_SUCCESS;
}
static uint32_t le_role_encode(ble_advdata_le_role_t le_role,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
// Check for buffer overflow.
if (((*p_offset) + AD_TYPE_LE_ROLE_SIZE) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
// Encode LE Role.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_LE_ROLE_DATA_SIZE);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_LE_ROLE;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
switch(le_role)
{
case BLE_ADVDATA_ROLE_ONLY_PERIPH:
p_encoded_data[*p_offset] = 0;
break;
case BLE_ADVDATA_ROLE_ONLY_CENTRAL:
p_encoded_data[*p_offset] = 1;
break;
case BLE_ADVDATA_ROLE_BOTH_PERIPH_PREFERRED:
p_encoded_data[*p_offset] = 2;
break;
case BLE_ADVDATA_ROLE_BOTH_CENTRAL_PREFERRED:
p_encoded_data[*p_offset] = 3;
break;
default:
return NRF_ERROR_INVALID_PARAM;
}
*p_offset += AD_TYPE_LE_ROLE_DATA_SIZE;
return NRF_SUCCESS;
}
static uint32_t ble_device_addr_encode(uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
uint32_t err_code;
ble_gap_addr_t device_addr;
// Check for buffer overflow.
if (((*p_offset) + AD_TYPE_BLE_DEVICE_ADDR_SIZE) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
// Get BLE address
err_code = sd_ble_gap_addr_get(&device_addr);
VERIFY_SUCCESS(err_code);
// Encode LE Bluetooth Device Address
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE +
AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
memcpy(&p_encoded_data[*p_offset], &device_addr.addr[0], BLE_GAP_ADDR_LEN);
*p_offset += BLE_GAP_ADDR_LEN;
if(BLE_GAP_ADDR_TYPE_PUBLIC == device_addr.addr_type)
{
p_encoded_data[*p_offset] = AD_TYPE_BLE_DEVICE_ADDR_TYPE_PUBLIC;
}
else
{
p_encoded_data[*p_offset] = AD_TYPE_BLE_DEVICE_ADDR_TYPE_RANDOM;
}
*p_offset += AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE;
return NRF_SUCCESS;
}
static uint32_t name_encode(const ble_advdata_t * p_advdata,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
uint32_t err_code;
uint16_t rem_adv_data_len;
uint16_t actual_length;
uint8_t adv_data_format;
// Validate parameters
if((BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) && (0 == p_advdata->short_name_len))
{
return NRF_ERROR_INVALID_PARAM;
}
// Check for buffer overflow.
if ( (((*p_offset) + ADV_AD_DATA_OFFSET) > max_size) ||
( (BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) &&
(((*p_offset) + ADV_AD_DATA_OFFSET + p_advdata->short_name_len) > max_size)))
{
return NRF_ERROR_DATA_SIZE;
}
rem_adv_data_len = max_size - (*p_offset) - ADV_AD_DATA_OFFSET;
actual_length = rem_adv_data_len;
// Get GAP device name and length
err_code = sd_ble_gap_device_name_get(&p_encoded_data[(*p_offset) + ADV_AD_DATA_OFFSET],
&actual_length);
VERIFY_SUCCESS(err_code);
// Check if device intend to use short name and it can fit available data size.
if ((p_advdata->name_type == BLE_ADVDATA_FULL_NAME) && (actual_length <= rem_adv_data_len))
{
// Complete device name can fit, setting Complete Name in Adv Data.
adv_data_format = BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME;
}
else
{
// Else short name needs to be used. Or application has requested use of short name.
adv_data_format = BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME;
// If application has set a preference on the short name size, it needs to be considered,
// else fit what can be fit.
if ((BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) &&
(p_advdata->short_name_len <= rem_adv_data_len))
{
// Short name fits available size.
actual_length = p_advdata->short_name_len;
}
// Else whatever can fit the data buffer will be packed.
else
{
actual_length = rem_adv_data_len;
}
}
// There is only 1 byte intended to encode length which is (actual_length + ADV_AD_TYPE_FIELD_SIZE)
if(actual_length > (0x00FF - ADV_AD_TYPE_FIELD_SIZE))
{
return NRF_ERROR_DATA_SIZE;
}
// Complete name field in encoded data.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + actual_length);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = adv_data_format;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
*p_offset += actual_length;
return NRF_SUCCESS;
}
static uint32_t appearance_encode(uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
uint32_t err_code;
uint16_t appearance;
// Check for buffer overflow.
if (((*p_offset) + AD_TYPE_APPEARANCE_SIZE) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
// Get GAP appearance field.
err_code = sd_ble_gap_appearance_get(&appearance);
VERIFY_SUCCESS(err_code);
// Encode Length, AD Type and Appearance.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_APPEARANCE_DATA_SIZE);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_APPEARANCE;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
*p_offset += uint16_encode(appearance, &p_encoded_data[*p_offset]);
return NRF_SUCCESS;
}
static uint32_t flags_encode(int8_t flags,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
// Check for buffer overflow.
if (((*p_offset) + AD_TYPE_FLAGS_SIZE) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
// Encode flags.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_FLAGS_DATA_SIZE);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_FLAGS;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
p_encoded_data[*p_offset] = flags;
*p_offset += AD_TYPE_FLAGS_DATA_SIZE;
return NRF_SUCCESS;
}
static uint32_t sec_mgr_oob_flags_encode(uint8_t oob_flags,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
// Check for buffer overflow.
if (((*p_offset) + AD_TYPE_OOB_FLAGS_SIZE) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
// Encode flags.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_OOB_FLAGS_DATA_SIZE);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
p_encoded_data[*p_offset] = oob_flags;
*p_offset += AD_TYPE_OOB_FLAGS_DATA_SIZE;
return NRF_SUCCESS;
}
static uint32_t tx_power_level_encode(int8_t tx_power_level,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
// Check for buffer overflow.
if (((*p_offset) + AD_TYPE_TX_POWER_LEVEL_SIZE) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
// Encode TX Power Level.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE +
AD_TYPE_TX_POWER_LEVEL_DATA_SIZE);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_TX_POWER_LEVEL;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
p_encoded_data[*p_offset] = tx_power_level;
*p_offset += AD_TYPE_TX_POWER_LEVEL_DATA_SIZE;
return NRF_SUCCESS;
}
static uint32_t uuid_list_sized_encode(const ble_advdata_uuid_list_t * p_uuid_list,
uint8_t adv_type,
uint8_t uuid_size,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
int i;
bool is_heading_written = false;
uint16_t start_pos = *p_offset;
uint16_t length;
for (i = 0; i < p_uuid_list->uuid_cnt; i++)
{
uint32_t err_code;
uint8_t encoded_size;
ble_uuid_t uuid = p_uuid_list->p_uuids[i];
// Find encoded uuid size.
err_code = sd_ble_uuid_encode(&uuid, &encoded_size, NULL);
VERIFY_SUCCESS(err_code);
// Check size.
if (encoded_size == uuid_size)
{
uint8_t heading_bytes = (is_heading_written) ? 0 : ADV_AD_DATA_OFFSET;
// Check for buffer overflow
if (((*p_offset) + encoded_size + heading_bytes) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
if (!is_heading_written)
{
// Write AD structure heading.
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = adv_type;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
is_heading_written = true;
}
// Write UUID.
err_code = sd_ble_uuid_encode(&uuid, &encoded_size, &p_encoded_data[*p_offset]);
VERIFY_SUCCESS(err_code);
*p_offset += encoded_size;
}
}
if (is_heading_written)
{
// Write length.
length = (*p_offset) - (start_pos + ADV_LENGTH_FIELD_SIZE);
// There is only 1 byte intended to encode length
if(length > 0x00FF)
{
return NRF_ERROR_DATA_SIZE;
}
p_encoded_data[start_pos] = (uint8_t)length;
}
return NRF_SUCCESS;
}
static uint32_t uuid_list_encode(const ble_advdata_uuid_list_t * p_uuid_list,
uint8_t adv_type_16,
uint8_t adv_type_128,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
uint32_t err_code;
// Encode 16 bit UUIDs.
err_code = uuid_list_sized_encode(p_uuid_list,
adv_type_16,
sizeof(uint16_le_t),
p_encoded_data,
p_offset,
max_size);
VERIFY_SUCCESS(err_code);
// Encode 128 bit UUIDs.
err_code = uuid_list_sized_encode(p_uuid_list,
adv_type_128,
sizeof(ble_uuid128_t),
p_encoded_data,
p_offset,
max_size);
VERIFY_SUCCESS(err_code);
return NRF_SUCCESS;
}
static uint32_t conn_int_check(const ble_advdata_conn_int_t *p_conn_int)
{
// Check Minimum Connection Interval.
if ((p_conn_int->min_conn_interval < 0x0006) ||
(
(p_conn_int->min_conn_interval > 0x0c80) &&
(p_conn_int->min_conn_interval != 0xffff)
)
)
{
return NRF_ERROR_INVALID_PARAM;
}
// Check Maximum Connection Interval.
if ((p_conn_int->max_conn_interval < 0x0006) ||
(
(p_conn_int->max_conn_interval > 0x0c80) &&
(p_conn_int->max_conn_interval != 0xffff)
)
)
{
return NRF_ERROR_INVALID_PARAM;
}
// Make sure Minimum Connection Interval is not bigger than Maximum Connection Interval.
if ((p_conn_int->min_conn_interval != 0xffff) &&
(p_conn_int->max_conn_interval != 0xffff) &&
(p_conn_int->min_conn_interval > p_conn_int->max_conn_interval)
)
{
return NRF_ERROR_INVALID_PARAM;
}
return NRF_SUCCESS;
}
static uint32_t conn_int_encode(const ble_advdata_conn_int_t * p_conn_int,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
uint32_t err_code;
// Check for buffer overflow.
if (((*p_offset) + AD_TYPE_CONN_INT_SIZE) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
// Check parameters.
err_code = conn_int_check(p_conn_int);
VERIFY_SUCCESS(err_code);
// Encode Length and AD Type.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_CONN_INT_DATA_SIZE);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
// Encode Minimum and Maximum Connection Intervals.
*p_offset += uint16_encode(p_conn_int->min_conn_interval, &p_encoded_data[*p_offset]);
*p_offset += uint16_encode(p_conn_int->max_conn_interval, &p_encoded_data[*p_offset]);
return NRF_SUCCESS;
}
static uint32_t manuf_specific_data_encode(const ble_advdata_manuf_data_t * p_manuf_sp_data,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
uint32_t data_size = AD_TYPE_MANUF_SPEC_DATA_ID_SIZE + p_manuf_sp_data->data.size;
// Check for buffer overflow.
if (((*p_offset) + ADV_AD_DATA_OFFSET + data_size) > max_size)
{
return NRF_ERROR_DATA_SIZE;
}
// There is only 1 byte intended to encode length which is (data_size + ADV_AD_TYPE_FIELD_SIZE)
if(data_size > (0x00FF - ADV_AD_TYPE_FIELD_SIZE))
{
return NRF_ERROR_DATA_SIZE;
}
// Encode Length and AD Type.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + data_size);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
// Encode Company Identifier.
*p_offset += uint16_encode(p_manuf_sp_data->company_identifier, &p_encoded_data[*p_offset]);
// Encode additional manufacturer specific data.
if (p_manuf_sp_data->data.size > 0)
{
if (p_manuf_sp_data->data.p_data == NULL)
{
return NRF_ERROR_INVALID_PARAM;
}
memcpy(&p_encoded_data[*p_offset], p_manuf_sp_data->data.p_data, p_manuf_sp_data->data.size);
*p_offset += p_manuf_sp_data->data.size;
}
return NRF_SUCCESS;
}
// Implemented only for 16-bit UUIDs
static uint32_t service_data_encode(const ble_advdata_t * p_advdata,
uint8_t * p_encoded_data,
uint16_t * p_offset,
uint16_t max_size)
{
uint8_t i;
// Check parameter consistency.
if (p_advdata->p_service_data_array == NULL)
{
return NRF_ERROR_INVALID_PARAM;
}
for (i = 0; i < p_advdata->service_data_count; i++)
{
ble_advdata_service_data_t * p_service_data;
uint32_t data_size;
p_service_data = &p_advdata->p_service_data_array[i];
// For now implemented only for 16-bit UUIDs
data_size = AD_TYPE_SERV_DATA_16BIT_UUID_SIZE + p_service_data->data.size;
// There is only 1 byte intended to encode length which is (data_size + ADV_AD_TYPE_FIELD_SIZE)
if(data_size > (0x00FF - ADV_AD_TYPE_FIELD_SIZE))
{
return NRF_ERROR_DATA_SIZE;
}
// Encode Length and AD Type.
p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + data_size);
*p_offset += ADV_LENGTH_FIELD_SIZE;
p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_SERVICE_DATA;
*p_offset += ADV_AD_TYPE_FIELD_SIZE;
// Encode service 16-bit UUID.
*p_offset += uint16_encode(p_service_data->service_uuid, &p_encoded_data[*p_offset]);
// Encode additional service data.
if (p_service_data->data.size > 0)
{
if (p_service_data->data.p_data == NULL)
{
return NRF_ERROR_INVALID_PARAM;
}
memcpy(&p_encoded_data[*p_offset], p_service_data->data.p_data, p_service_data->data.size);
*p_offset += p_service_data->data.size;
}
}
return NRF_SUCCESS;
}
uint32_t adv_data_encode(ble_advdata_t const * const p_advdata,
uint8_t * const p_encoded_data,
uint16_t * const p_len)
{
uint32_t err_code = NRF_SUCCESS;
uint16_t max_size = *p_len;
*p_len = 0;
//Encode Security Manager OOB Flags
if (p_advdata->p_sec_mgr_oob_flags != NULL)
{
err_code = sec_mgr_oob_flags_encode(*p_advdata->p_sec_mgr_oob_flags,
p_encoded_data,
p_len,
max_size);
VERIFY_SUCCESS(err_code);
}
// Encode Security Manager TK value
if (NULL != p_advdata->p_tk_value)
{
err_code = tk_value_encode(p_advdata->p_tk_value, p_encoded_data, p_len, max_size);
VERIFY_SUCCESS(err_code);
}
// Encode LE Role
if (BLE_ADVDATA_ROLE_NOT_PRESENT != p_advdata->le_role)
{
err_code = le_role_encode(p_advdata->le_role, p_encoded_data, p_len, max_size);
VERIFY_SUCCESS(err_code);
}
// Encode LE Bluetooth Device Address
if (p_advdata->include_ble_device_addr)
{
err_code = ble_device_addr_encode(p_encoded_data, p_len, max_size);
VERIFY_SUCCESS(err_code);
}
// Encode appearance.
if (p_advdata->include_appearance)
{
err_code = appearance_encode(p_encoded_data, p_len, max_size);
VERIFY_SUCCESS(err_code);
}
//Encode Flags
if(p_advdata->flags != 0 )
{
err_code = flags_encode(p_advdata->flags, p_encoded_data, p_len, max_size);
VERIFY_SUCCESS(err_code);
}
// Encode TX power level.
if (p_advdata->p_tx_power_level != NULL)
{
err_code = tx_power_level_encode(*p_advdata->p_tx_power_level,
p_encoded_data,
p_len,
max_size);
VERIFY_SUCCESS(err_code);
}
// Encode 'more available' uuid list.
if (p_advdata->uuids_more_available.uuid_cnt > 0)
{
err_code = uuid_list_encode(&p_advdata->uuids_more_available,
BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE,
BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE,
p_encoded_data,
p_len,
max_size);
VERIFY_SUCCESS(err_code);
}
// Encode 'complete' uuid list.
if (p_advdata->uuids_complete.uuid_cnt > 0)
{
err_code = uuid_list_encode(&p_advdata->uuids_complete,
BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE,
BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE,
p_encoded_data,
p_len,
max_size);
VERIFY_SUCCESS(err_code);
}
// Encode 'solicited service' uuid list.
if (p_advdata->uuids_solicited.uuid_cnt > 0)
{
err_code = uuid_list_encode(&p_advdata->uuids_solicited,
BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT,
BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT,
p_encoded_data,
p_len,
max_size);
VERIFY_SUCCESS(err_code);
}
// Encode Slave Connection Interval Range.
if (p_advdata->p_slave_conn_int != NULL)
{
err_code = conn_int_encode(p_advdata->p_slave_conn_int, p_encoded_data, p_len, max_size);
VERIFY_SUCCESS(err_code);
}
// Encode Manufacturer Specific Data.
if (p_advdata->p_manuf_specific_data != NULL)
{
err_code = manuf_specific_data_encode(p_advdata->p_manuf_specific_data,
p_encoded_data,
p_len,
max_size);
VERIFY_SUCCESS(err_code);
}
// Encode Service Data.
if (p_advdata->service_data_count > 0)
{
err_code = service_data_encode(p_advdata, p_encoded_data, p_len, max_size);
VERIFY_SUCCESS(err_code);
}
// Encode name. WARNING: it is encoded last on purpose since too long device name is truncated.
if (p_advdata->name_type != BLE_ADVDATA_NO_NAME)
{
err_code = name_encode(p_advdata, p_encoded_data, p_len, max_size);
VERIFY_SUCCESS(err_code);
}
return err_code;
}
static uint32_t advdata_check(const ble_advdata_t * p_advdata)
{
// Flags must be included in advertising data, and the BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED flag must be set.
if (
((p_advdata->flags & BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) == 0)
)
{
return NRF_ERROR_INVALID_PARAM;
}
return NRF_SUCCESS;
}
static uint32_t srdata_check(const ble_advdata_t * p_srdata)
{
// Flags shall not be included in the scan response data.
if (p_srdata->flags)
{
return NRF_ERROR_INVALID_PARAM;
}
return NRF_SUCCESS;
}
uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata)
{
uint32_t err_code;
uint16_t len_advdata = BLE_GAP_ADV_MAX_SIZE;
uint16_t len_srdata = BLE_GAP_ADV_MAX_SIZE;
uint8_t encoded_advdata[BLE_GAP_ADV_MAX_SIZE];
uint8_t encoded_srdata[BLE_GAP_ADV_MAX_SIZE];
uint8_t * p_encoded_advdata;
uint8_t * p_encoded_srdata;
// Encode advertising data (if supplied).
if (p_advdata != NULL)
{
err_code = advdata_check(p_advdata);
VERIFY_SUCCESS(err_code);
err_code = adv_data_encode(p_advdata, encoded_advdata, &len_advdata);
VERIFY_SUCCESS(err_code);
p_encoded_advdata = encoded_advdata;
}
else
{
p_encoded_advdata = NULL;
len_advdata = 0;
}
// Encode scan response data (if supplied).
if (p_srdata != NULL)
{
err_code = srdata_check(p_srdata);
VERIFY_SUCCESS(err_code);
err_code = adv_data_encode(p_srdata, encoded_srdata, &len_srdata);
VERIFY_SUCCESS(err_code);
p_encoded_srdata = encoded_srdata;
}
else
{
p_encoded_srdata = NULL;
len_srdata = 0;
}
// Pass encoded advertising data and/or scan response data to the stack.
return sd_ble_gap_adv_data_set(p_encoded_advdata, len_advdata, p_encoded_srdata, len_srdata);
}

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup ble_sdk_lib_advdata Advertising and Scan Response Data Encoder
* @{
* @ingroup ble_sdk_lib
* @brief Functions for encoding data in the Advertising and Scan Response Data format,
* and for passing the data to the stack.
*/
#ifndef BLE_ADVDATA_H__
#define BLE_ADVDATA_H__
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "ble.h"
#include "app_util.h"
#define ADV_LENGTH_FIELD_SIZE 1UL /**< Advertising Data and Scan Response format contains 1 octet for the length. */
#define ADV_AD_TYPE_FIELD_SIZE 1UL /**< Advertising Data and Scan Response format contains 1 octet for the AD type. */
#define ADV_AD_DATA_OFFSET (ADV_LENGTH_FIELD_SIZE + \
ADV_AD_TYPE_FIELD_SIZE) /**< Offset for the AD data field of the Advertising Data and Scan Response format. */
#define AD_TYPE_TK_VALUE_DATA_SIZE (sizeof(ble_advdata_tk_value_t)) /**< Data size (in octets) of the Security Manager TK value AD type. */
#define AD_TYPE_TK_VALUE_SIZE (ADV_AD_DATA_OFFSET + \
AD_TYPE_TK_VALUE_DATA_SIZE) /**< Size (in octets) of the Security Manager TK value AD type. */
#define AD_TYPE_LE_ROLE_DATA_SIZE 1UL /**< Data size (in octets) of the LE Bluetooth Device Address AD type. */
#define AD_TYPE_LE_ROLE_SIZE (ADV_AD_DATA_OFFSET + \
AD_TYPE_LE_ROLE_DATA_SIZE) /**< Size (in octets) of the LE Bluetooth Device Address AD type. */
#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE 1UL /**< Data size (in octets) of the Address type of the LE Bluetooth Device Address AD type. */
#define AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE (BLE_GAP_ADDR_LEN + \
AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE) /**< Data size (in octets) of the LE Bluetooth Device Address AD type. */
#define AD_TYPE_BLE_DEVICE_ADDR_SIZE (ADV_AD_DATA_OFFSET + \
AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE) /**< Size (in octets) of the LE Bluetooth Device Address AD type. */
#define AD_TYPE_APPEARANCE_DATA_SIZE 2UL /**< Data size (in octets) of the Appearance AD type. */
#define AD_TYPE_APPEARANCE_SIZE (ADV_AD_DATA_OFFSET + \
AD_TYPE_APPEARANCE_DATA_SIZE) /**< Size (in octets) of the Appearance AD type. */
#define AD_TYPE_FLAGS_DATA_SIZE 1UL /**< Data size (in octets) of the Flags AD type. */
#define AD_TYPE_FLAGS_SIZE (ADV_AD_DATA_OFFSET + \
AD_TYPE_FLAGS_DATA_SIZE) /**< Size (in octets) of the Flags AD type. */
#define AD_TYPE_TX_POWER_LEVEL_DATA_SIZE 1UL /**< Data size (in octets) of the TX Power Level AD type. */
#define AD_TYPE_TX_POWER_LEVEL_SIZE (ADV_AD_DATA_OFFSET + \
AD_TYPE_TX_POWER_LEVEL_DATA_SIZE) /**< Size (in octets) of the TX Power Level AD type. */
#define AD_TYPE_CONN_INT_DATA_SIZE 4UL /**< Data size (in octets) of the Slave Connection Interval Range AD type. */
#define AD_TYPE_CONN_INT_SIZE (ADV_AD_DATA_OFFSET + \
AD_TYPE_CONN_INT_DATA_SIZE) /**< Data size (in octets) of the Slave Connection Interval Range AD type. */
#define AD_TYPE_MANUF_SPEC_DATA_ID_SIZE 2UL /**< Size (in octets) of the Company Identifier Code, which is a part of the Manufacturer Specific Data AD type. */
#define AD_TYPE_SERV_DATA_16BIT_UUID_SIZE 2UL /**< Size (in octets) of the 16-bit UUID, which is a part of the Service Data AD type. */
#define AD_TYPE_OOB_FLAGS_DATA_SIZE 1UL /**< Data size (in octets) of the Security Manager OOB Flags AD type. */
#define AD_TYPE_OOB_FLAGS_SIZE (ADV_AD_DATA_OFFSET + \
AD_TYPE_OOB_FLAGS_DATA_SIZE) /**< Size (in octets) of the Security Manager OOB Flags AD type. */
#define AD_TYPE_SEC_MGR_OOB_FLAG_SET 1U /**< Security Manager OOB Flag set. Flag selection is done using _POS defines */
#define AD_TYPE_SEC_MGR_OOB_FLAG_CLEAR 0U /**< Security Manager OOB Flag clear. Flag selection is done using _POS defines */
#define AD_TYPE_SEC_MGR_OOB_FLAG_OOB_DATA_PRESENT_POS 0UL /**< Security Manager OOB Data Present Flag position. */
#define AD_TYPE_SEC_MGR_OOB_FLAG_OOB_LE_SUPPORTED_POS 1UL /**< Security Manager OOB Low Energy Supported Flag position. */
#define AD_TYPE_SEC_MGR_OOB_FLAG_SIM_LE_AND_EP_POS 2UL /**< Security Manager OOB Simultaneous LE and BR/EDR to Same Device Capable Flag position. */
#define AD_TYPE_SEC_MGR_OOB_ADDRESS_TYPE_PUBLIC 0UL /**< Security Manager OOB Public Address type. */
#define AD_TYPE_SEC_MGR_OOB_ADDRESS_TYPE_RANDOM 1UL /**< Security Manager OOB Random Address type. */
#define AD_TYPE_SEC_MGR_OOB_FLAG_ADDRESS_TYPE_POS 3UL /**< Security Manager OOB Address type Flag (0 = Public Address, 1 = Random Address) position. */
/**@brief Security Manager TK value. */
typedef struct
{
uint8_t tk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing TK value. */
} ble_advdata_tk_value_t;
/**@brief Advertising data LE Role types. This enumeration contains the options available for the LE role inside
* the advertising data. */
typedef enum
{
BLE_ADVDATA_ROLE_NOT_PRESENT = 0, /**< LE Role AD structure not present. */
BLE_ADVDATA_ROLE_ONLY_PERIPH, /**< Only Peripheral Role supported. */
BLE_ADVDATA_ROLE_ONLY_CENTRAL, /**< Only Central Role supported. */
BLE_ADVDATA_ROLE_BOTH_PERIPH_PREFERRED, /**< Peripheral and Central Role supported. Peripheral Role preferred for connection establishment. */
BLE_ADVDATA_ROLE_BOTH_CENTRAL_PREFERRED /**< Peripheral and Central Role supported. Central Role preferred for connection establishment */
} ble_advdata_le_role_t;
/**@brief Advertising data name type. This enumeration contains the options available for the device name inside
* the advertising data. */
typedef enum
{
BLE_ADVDATA_NO_NAME, /**< Include no device name in advertising data. */
BLE_ADVDATA_SHORT_NAME, /**< Include short device name in advertising data. */
BLE_ADVDATA_FULL_NAME /**< Include full device name in advertising data. */
} ble_advdata_name_type_t;
/**@brief UUID list type. */
typedef struct
{
uint16_t uuid_cnt; /**< Number of UUID entries. */
ble_uuid_t * p_uuids; /**< Pointer to UUID array entries. */
} ble_advdata_uuid_list_t;
/**@brief Connection interval range structure. */
typedef struct
{
uint16_t min_conn_interval; /**< Minimum connection interval, in units of 1.25 ms, range 6 to 3200 (7.5 ms to 4 s). */
uint16_t max_conn_interval; /**< Maximum connection interval, in units of 1.25 ms, range 6 to 3200 (7.5 ms to 4 s). The value 0xFFFF indicates no specific maximum. */
} ble_advdata_conn_int_t;
/**@brief Manufacturer specific data structure. */
typedef struct
{
uint16_t company_identifier; /**< Company identifier code. */
uint8_array_t data; /**< Additional manufacturer specific data. */
} ble_advdata_manuf_data_t;
/**@brief Service data structure. */
typedef struct
{
uint16_t service_uuid; /**< Service UUID. */
uint8_array_t data; /**< Additional service data. */
} ble_advdata_service_data_t;
/**@brief Advertising data structure. This structure contains all options and data needed for encoding and
* setting the advertising data. */
typedef struct
{
ble_advdata_name_type_t name_type; /**< Type of device name. */
uint8_t short_name_len; /**< Length of short device name (if short type is specified). */
bool include_appearance; /**< Determines if Appearance shall be included. */
uint8_t flags; /**< Advertising data Flags field. */
int8_t * p_tx_power_level; /**< TX Power Level field. */
ble_advdata_uuid_list_t uuids_more_available; /**< List of UUIDs in the 'More Available' list. */
ble_advdata_uuid_list_t uuids_complete; /**< List of UUIDs in the 'Complete' list. */
ble_advdata_uuid_list_t uuids_solicited; /**< List of solicited UUIDs. */
ble_advdata_conn_int_t * p_slave_conn_int; /**< Slave Connection Interval Range. */
ble_advdata_manuf_data_t * p_manuf_specific_data; /**< Manufacturer specific data. */
ble_advdata_service_data_t * p_service_data_array; /**< Array of Service data structures. */
uint8_t service_data_count; /**< Number of Service data structures. */
bool include_ble_device_addr; /**< Determines if LE Bluetooth Device Address shall be included. */
ble_advdata_le_role_t le_role; /**< LE Role field. Included when different from @ref BLE_ADVDATA_ROLE_NOT_PRESENT. @warning This field can be used only for NFC. For BLE advertising, set it to NULL. */
ble_advdata_tk_value_t * p_tk_value; /**< Security Manager TK value field. Included when different from NULL. @warning This field can be used only for NFC. For BLE advertising, set it to NULL.*/
uint8_t * p_sec_mgr_oob_flags; /**< Security Manager Out Of Band Flags field. Included when different from NULL. @warning This field can be used only for NFC. For BLE advertising, set it to NULL.*/
} ble_advdata_t;
/**@brief Function for encoding data in the Advertising and Scan Response data format
* (AD structures).
*
* @details This function encodes data into the Advertising and Scan Response data format
* (AD structures) based on the selections in the supplied structures. This function can be used to
* create a payload of Advertising packet or Scan Response packet, or a payload of NFC
* message intended for initiating the Out-of-Band pairing.
*
* @param[in] p_advdata Pointer to the structure for specifying the content of encoded data.
* @param[out] p_encoded_data Pointer to the buffer where encoded data will be returned.
* @param[in,out] p_len \c in: Size of \p p_encoded_data buffer.
* \c out: Length of encoded data.
*
* @retval NRF_SUCCESS If the operation was successful.
* @retval NRF_ERROR_INVALID_PARAM If the operation failed because a wrong parameter was provided in \p p_advdata.
* @retval NRF_ERROR_DATA_SIZE If the operation failed because not all the requested data could fit into the
* provided buffer or some encoded AD structure is too long and its
* length cannot be encoded with one octet.
*
* @warning This API may override the application's request to use the long name and use a short name
* instead. This truncation will occur in case the long name does not fit the provided buffer size.
* The application can specify a preferred short name length if truncation is required.
* For example, if the complete device name is ABCD_HRMonitor, the application can specify the short name
* length to be 8, so that the short device name appears as ABCD_HRM instead of ABCD_HRMo or ABCD_HRMoni
* if the available size for the short name is 9 or 12 respectively, to have a more appropriate short name.
* However, it should be noted that this is just a preference that the application can specify, and
* if the preference is too large to fit in the provided buffer, the name can be truncated further.
*/
uint32_t adv_data_encode(ble_advdata_t const * const p_advdata,
uint8_t * const p_encoded_data,
uint16_t * const p_len);
/**@brief Function for encoding and setting the advertising data and/or scan response data.
*
* @details This function encodes advertising data and/or scan response data based on the selections
* in the supplied structures, and passes the encoded data to the stack.
*
* @param[in] p_advdata Structure for specifying the content of the advertising data.
* Set to NULL if advertising data is not to be set.
* @param[in] p_srdata Structure for specifying the content of the scan response data.
* Set to NULL if scan response data is not to be set.
*
* @retval NRF_SUCCESS If the operation was successful.
* @retval NRF_ERROR_INVALID_PARAM If the operation failed because a wrong parameter was provided in \p p_advdata.
* @retval NRF_ERROR_DATA_SIZE If the operation failed because not all the requested data could fit into the
* advertising packet. The maximum size of the advertisement packet
* is @ref BLE_GAP_ADV_MAX_SIZE.
*
* @warning This API may override the application's request to use the long name and use a short name
* instead. This truncation will occur in case the long name does not fit the provided buffer size.
* The application can specify a preferred short name length if truncation is required.
* For example, if the complete device name is ABCD_HRMonitor, the application can specify the short name
* length to be 8, so that the short device name appears as ABCD_HRM instead of ABCD_HRMo or ABCD_HRMoni
* if the available size for the short name is 9 or 12 respectively, to have a more appropriate short name.
* However, it should be noted that this is just a preference that the application can specify, and
* if the preference is too large to fit in the provided buffer, the name can be truncated further.
*/
uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata);
#endif // BLE_ADVDATA_H__
/** @} */

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "ble_conn_params.h"
#include <stdlib.h>
#include "nordic_common.h"
#include "ble_hci.h"
#include "app_timer.h"
#include "ble_srv_common.h"
#include "app_util.h"
static ble_conn_params_init_t m_conn_params_config; /**< Configuration as specified by the application. */
static ble_gap_conn_params_t m_preferred_conn_params; /**< Connection parameters preferred by the application. */
static uint8_t m_update_count; /**< Number of Connection Parameter Update messages that has currently been sent. */
static uint16_t m_conn_handle; /**< Current connection handle. */
static ble_gap_conn_params_t m_current_conn_params; /**< Connection parameters received in the most recent Connect event. */
APP_TIMER_DEF(m_conn_params_timer_id); /**< Connection parameters timer. */
static bool m_change_param = false;
static bool is_conn_params_ok(ble_gap_conn_params_t * p_conn_params)
{
// Check if interval is within the acceptable range.
// NOTE: Using max_conn_interval in the received event data because this contains
// the client's connection interval.
if (
(p_conn_params->max_conn_interval >= m_preferred_conn_params.min_conn_interval)
&&
(p_conn_params->max_conn_interval <= m_preferred_conn_params.max_conn_interval)
)
{
return true;
}
else
{
return false;
}
}
static void update_timeout_handler(void * p_context)
{
UNUSED_PARAMETER(p_context);
if (m_conn_handle != BLE_CONN_HANDLE_INVALID)
{
// Check if we have reached the maximum number of attempts
m_update_count++;
if (m_update_count <= m_conn_params_config.max_conn_params_update_count)
{
uint32_t err_code;
// Parameters are not ok, send connection parameters update request.
err_code = sd_ble_gap_conn_param_update(m_conn_handle, &m_preferred_conn_params);
if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
{
m_conn_params_config.error_handler(err_code);
}
}
else
{
m_update_count = 0;
// Negotiation failed, disconnect automatically if this has been configured
if (m_conn_params_config.disconnect_on_fail)
{
uint32_t err_code;
err_code = sd_ble_gap_disconnect(m_conn_handle, BLE_HCI_CONN_INTERVAL_UNACCEPTABLE);
if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
{
m_conn_params_config.error_handler(err_code);
}
}
// Notify the application that the procedure has failed
if (m_conn_params_config.evt_handler != NULL)
{
ble_conn_params_evt_t evt;
evt.evt_type = BLE_CONN_PARAMS_EVT_FAILED;
m_conn_params_config.evt_handler(&evt);
}
}
}
}
uint32_t ble_conn_params_init(const ble_conn_params_init_t * p_init)
{
uint32_t err_code;
m_conn_params_config = *p_init;
m_change_param = false;
if (p_init->p_conn_params != NULL)
{
m_preferred_conn_params = *p_init->p_conn_params;
// Set the connection params in stack
err_code = sd_ble_gap_ppcp_set(&m_preferred_conn_params);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
else
{
// Fetch the connection params from stack
err_code = sd_ble_gap_ppcp_get(&m_preferred_conn_params);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
}
m_conn_handle = BLE_CONN_HANDLE_INVALID;
m_update_count = 0;
return app_timer_create(&m_conn_params_timer_id,
APP_TIMER_MODE_SINGLE_SHOT,
update_timeout_handler);
}
uint32_t ble_conn_params_stop(void)
{
return app_timer_stop(m_conn_params_timer_id);
}
static void conn_params_negotiation(void)
{
// Start negotiation if the received connection parameters are not acceptable
if (!is_conn_params_ok(&m_current_conn_params))
{
uint32_t err_code;
uint32_t timeout_ticks;
if (m_change_param)
{
// Notify the application that the procedure has failed
if (m_conn_params_config.evt_handler != NULL)
{
ble_conn_params_evt_t evt;
evt.evt_type = BLE_CONN_PARAMS_EVT_FAILED;
m_conn_params_config.evt_handler(&evt);
}
}
else
{
if (m_update_count == 0)
{
// First connection parameter update
timeout_ticks = m_conn_params_config.first_conn_params_update_delay;
}
else
{
timeout_ticks = m_conn_params_config.next_conn_params_update_delay;
}
err_code = app_timer_start(m_conn_params_timer_id, timeout_ticks, NULL);
if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
{
m_conn_params_config.error_handler(err_code);
}
}
}
else
{
// Notify the application that the procedure has succeded
if (m_conn_params_config.evt_handler != NULL)
{
ble_conn_params_evt_t evt;
evt.evt_type = BLE_CONN_PARAMS_EVT_SUCCEEDED;
m_conn_params_config.evt_handler(&evt);
}
}
m_change_param = false;
}
static void on_connect(ble_evt_t * p_ble_evt)
{
// Save connection parameters
m_conn_handle = p_ble_evt->evt.gap_evt.conn_handle;
m_current_conn_params = p_ble_evt->evt.gap_evt.params.connected.conn_params;
m_update_count = 0; // Connection parameter negotiation should re-start every connection
// Check if we shall handle negotiation on connect
if (m_conn_params_config.start_on_notify_cccd_handle == BLE_GATT_HANDLE_INVALID)
{
conn_params_negotiation();
}
}
static void on_disconnect(ble_evt_t * p_ble_evt)
{
uint32_t err_code;
m_conn_handle = BLE_CONN_HANDLE_INVALID;
// Stop timer if running
m_update_count = 0; // Connection parameters updates should happen during every connection
err_code = app_timer_stop(m_conn_params_timer_id);
if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
{
m_conn_params_config.error_handler(err_code);
}
}
static void on_write(ble_evt_t * p_ble_evt)
{
ble_gatts_evt_write_t * p_evt_write = &p_ble_evt->evt.gatts_evt.params.write;
// Check if this the correct CCCD
if (
(p_evt_write->handle == m_conn_params_config.start_on_notify_cccd_handle)
&&
(p_evt_write->len == 2)
)
{
// Check if this is a 'start notification'
if (ble_srv_is_notification_enabled(p_evt_write->data))
{
// Do connection parameter negotiation if necessary
conn_params_negotiation();
}
else
{
uint32_t err_code;
// Stop timer if running
err_code = app_timer_stop(m_conn_params_timer_id);
if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
{
m_conn_params_config.error_handler(err_code);
}
}
}
}
static void on_conn_params_update(ble_evt_t * p_ble_evt)
{
// Copy the parameters
m_current_conn_params = p_ble_evt->evt.gap_evt.params.conn_param_update.conn_params;
conn_params_negotiation();
}
void ble_conn_params_on_ble_evt(ble_evt_t * p_ble_evt)
{
switch (p_ble_evt->header.evt_id)
{
case BLE_GAP_EVT_CONNECTED:
on_connect(p_ble_evt);
break;
case BLE_GAP_EVT_DISCONNECTED:
on_disconnect(p_ble_evt);
break;
case BLE_GATTS_EVT_WRITE:
on_write(p_ble_evt);
break;
case BLE_GAP_EVT_CONN_PARAM_UPDATE:
on_conn_params_update(p_ble_evt);
break;
default:
// No implementation needed.
break;
}
}
uint32_t ble_conn_params_change_conn_params(ble_gap_conn_params_t * new_params)
{
uint32_t err_code;
m_preferred_conn_params = *new_params;
// Set the connection params in stack
err_code = sd_ble_gap_ppcp_set(&m_preferred_conn_params);
if (err_code == NRF_SUCCESS)
{
if (!is_conn_params_ok(&m_current_conn_params))
{
m_change_param = true;
err_code = sd_ble_gap_conn_param_update(m_conn_handle, &m_preferred_conn_params);
m_update_count = 1;
}
else
{
// Notify the application that the procedure has succeded
if (m_conn_params_config.evt_handler != NULL)
{
ble_conn_params_evt_t evt;
evt.evt_type = BLE_CONN_PARAMS_EVT_SUCCEEDED;
m_conn_params_config.evt_handler(&evt);
}
err_code = NRF_SUCCESS;
}
}
return err_code;
}

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup ble_sdk_lib_conn_params Connection Parameters Negotiation
* @{
* @ingroup ble_sdk_lib
* @brief Module for initiating and executing a connection parameters negotiation procedure.
*/
#ifndef BLE_CONN_PARAMS_H__
#define BLE_CONN_PARAMS_H__
#include <stdint.h>
#include "ble.h"
#include "ble_srv_common.h"
/**@brief Connection Parameters Module event type. */
typedef enum
{
BLE_CONN_PARAMS_EVT_FAILED , /**< Negotiation procedure failed. */
BLE_CONN_PARAMS_EVT_SUCCEEDED /**< Negotiation procedure succeeded. */
} ble_conn_params_evt_type_t;
/**@brief Connection Parameters Module event. */
typedef struct
{
ble_conn_params_evt_type_t evt_type; /**< Type of event. */
} ble_conn_params_evt_t;
/**@brief Connection Parameters Module event handler type. */
typedef void (*ble_conn_params_evt_handler_t) (ble_conn_params_evt_t * p_evt);
/**@brief Connection Parameters Module init structure. This contains all options and data needed for
* initialization of the connection parameters negotiation module. */
typedef struct
{
ble_gap_conn_params_t * p_conn_params; /**< Pointer to the connection parameters desired by the application. When calling ble_conn_params_init, if this parameter is set to NULL, the connection parameters will be fetched from host. */
uint32_t first_conn_params_update_delay; /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (in number of timer ticks). */
uint32_t next_conn_params_update_delay; /**< Time between each call to sd_ble_gap_conn_param_update after the first (in number of timer ticks). Recommended value 30 seconds as per BLUETOOTH SPECIFICATION Version 4.0. */
uint8_t max_conn_params_update_count; /**< Number of attempts before giving up the negotiation. */
uint16_t start_on_notify_cccd_handle; /**< If procedure is to be started when notification is started, set this to the handle of the corresponding CCCD. Set to BLE_GATT_HANDLE_INVALID if procedure is to be started on connect event. */
bool disconnect_on_fail; /**< Set to TRUE if a failed connection parameters update shall cause an automatic disconnection, set to FALSE otherwise. */
ble_conn_params_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Connection Parameters. */
ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
} ble_conn_params_init_t;
/**@brief Function for initializing the Connection Parameters module.
*
* @note If the negotiation procedure should be triggered when notification/indication of
* any characteristic is enabled by the peer, then this function must be called after
* having initialized the services.
*
* @param[in] p_init This contains information needed to initialize this module.
*
* @return NRF_SUCCESS on successful initialization, otherwise an error code.
*/
uint32_t ble_conn_params_init(const ble_conn_params_init_t * p_init);
/**@brief Function for stopping the Connection Parameters module.
*
* @details This function is intended to be used by the application to clean up the connection
* parameters update module. This will stop the connection parameters update timer if
* running, thereby preventing any impending connection parameters update procedure. This
* function must be called by the application when it needs to clean itself up (for
* example, before disabling the bluetooth SoftDevice) so that an unwanted timer expiry
* event can be avoided.
*
* @return NRF_SUCCESS on successful initialization, otherwise an error code.
*/
uint32_t ble_conn_params_stop(void);
/**@brief Function for changing the current connection parameters to a new set.
*
* @details Use this function to change the connection parameters to a new set of parameter
* (ie different from the ones given at init of the module).
* This function is usefull for scenario where most of the time the application
* needs a relatively big connection interval, and just sometimes, for a temporary
* period requires shorter connection interval, for example to transfer a higher
* amount of data.
* If the given parameters does not match the current connection's parameters
* this function initiates a new negotiation.
*
* @param[in] new_params This contains the new connections parameters to setup.
*
* @return NRF_SUCCESS on successful initialization, otherwise an error code.
*/
uint32_t ble_conn_params_change_conn_params(ble_gap_conn_params_t *new_params);
/**@brief Function for handling the Application's BLE Stack events.
*
* @details Handles all events from the BLE stack that are of interest to this module.
*
* @param[in] p_ble_evt The event received from the BLE stack.
*/
void ble_conn_params_on_ble_evt(ble_evt_t * p_ble_evt);
#endif // BLE_CONN_PARAMS_H__
/** @} */

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/* Attention!
* To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile
* qualification listings, this section of source code must not be modified.
*/
#include "ble_srv_common.h"
#include <string.h>
#include "nordic_common.h"
#include "app_error.h"
#include "ble.h"
uint8_t ble_srv_report_ref_encode(uint8_t * p_encoded_buffer,
const ble_srv_report_ref_t * p_report_ref)
{
uint8_t len = 0;
p_encoded_buffer[len++] = p_report_ref->report_id;
p_encoded_buffer[len++] = p_report_ref->report_type;
APP_ERROR_CHECK_BOOL(len == BLE_SRV_ENCODED_REPORT_REF_LEN);
return len;
}
void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii)
{
p_utf8->length = (uint16_t)strlen(p_ascii);
p_utf8->p_str = (uint8_t *)p_ascii;
}
/**@brief Function for setting security requirements of a characteristic.
*
* @param[in] level required security level.
* @param[out] p_perm Characteristic security requirements.
*
* @return encoded security level and security mode.
*/
static inline void set_security_req(security_req_t level, ble_gap_conn_sec_mode_t * p_perm)
{
BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm);
switch (level)
{
case SEC_NO_ACCESS:
BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm);
break;
case SEC_OPEN:
BLE_GAP_CONN_SEC_MODE_SET_OPEN(p_perm);
break;
case SEC_JUST_WORKS:
BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(p_perm);
break;
case SEC_MITM:
BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(p_perm);
break;
case SEC_SIGNED:
BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(p_perm);
break;
case SEC_SIGNED_MITM:
BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(p_perm);
break;
}
return;
}
uint32_t characteristic_add(uint16_t service_handle,
ble_add_char_params_t * p_char_props,
ble_gatts_char_handles_t * p_char_handle)
{
ble_gatts_char_md_t char_md;
ble_gatts_attr_t attr_char_value;
ble_uuid_t char_uuid;
ble_gatts_attr_md_t attr_md;
ble_gatts_attr_md_t user_descr_attr_md;
ble_gatts_attr_md_t cccd_md;
if (p_char_props->uuid_type == 0)
{
char_uuid.type = BLE_UUID_TYPE_BLE;
}
else
{
char_uuid.type = p_char_props->uuid_type;
}
char_uuid.uuid = p_char_props->uuid;
memset(&attr_md, 0, sizeof(ble_gatts_attr_md_t));
set_security_req(p_char_props->read_access, &attr_md.read_perm);
set_security_req(p_char_props->write_access, & attr_md.write_perm);
attr_md.rd_auth = (p_char_props->is_defered_read ? 1 : 0);
attr_md.wr_auth = (p_char_props->is_defered_write ? 1 : 0);
attr_md.vlen = (p_char_props->is_var_len ? 1 : 0);
attr_md.vloc = (p_char_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK);
memset(&char_md, 0, sizeof(ble_gatts_char_md_t));
if ((p_char_props->char_props.notify == 1)||(p_char_props->char_props.indicate == 1))
{
memset(&cccd_md, 0, sizeof(cccd_md));
set_security_req(p_char_props->cccd_write_access, &cccd_md.write_perm);
BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm);
cccd_md.vloc = BLE_GATTS_VLOC_STACK;
char_md.p_cccd_md = &cccd_md;
}
char_md.char_props = p_char_props->char_props;
memset(&attr_char_value, 0, sizeof(ble_gatts_attr_t));
attr_char_value.p_uuid = &char_uuid;
attr_char_value.p_attr_md = &attr_md;
attr_char_value.max_len = p_char_props->max_len;
if (p_char_props->p_init_value != NULL)
{
attr_char_value.init_len = p_char_props->init_len;
attr_char_value.p_value = p_char_props->p_init_value;
}
if (p_char_props->p_user_descr != NULL)
{
memset(&user_descr_attr_md, 0, sizeof(ble_gatts_attr_md_t));
char_md.char_user_desc_max_size = p_char_props->p_user_descr->max_size;
char_md.char_user_desc_size = p_char_props->p_user_descr->size;
char_md.p_char_user_desc = p_char_props->p_user_descr->p_char_user_desc;
char_md.p_user_desc_md = &user_descr_attr_md;
set_security_req(p_char_props->p_user_descr->read_access, &user_descr_attr_md.read_perm);
set_security_req(p_char_props->p_user_descr->write_access, &user_descr_attr_md.write_perm);
user_descr_attr_md.rd_auth = (p_char_props->p_user_descr->is_defered_read ? 1 : 0);
user_descr_attr_md.wr_auth = (p_char_props->p_user_descr->is_defered_write ? 1 : 0);
user_descr_attr_md.vlen = (p_char_props->p_user_descr->is_var_len ? 1 : 0);
user_descr_attr_md.vloc = (p_char_props->p_user_descr->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK);
}
if (p_char_props->p_presentation_format != NULL)
{
char_md.p_char_pf = p_char_props->p_presentation_format;
}
return sd_ble_gatts_characteristic_add(service_handle,
&char_md,
&attr_char_value,
p_char_handle);
}
uint32_t descriptor_add(uint16_t char_handle,
ble_add_descr_params_t * p_descr_props,
uint16_t * p_descr_handle)
{
ble_gatts_attr_t descr_params;
ble_uuid_t desc_uuid;
ble_gatts_attr_md_t attr_md;
memset(&descr_params, 0, sizeof(descr_params));
if (p_descr_props->uuid_type == 0)
{
desc_uuid.type = BLE_UUID_TYPE_BLE;
}
else
{
desc_uuid.type = p_descr_props->uuid_type;
}
desc_uuid.uuid = p_descr_props->uuid;
descr_params.p_uuid = &desc_uuid;
set_security_req(p_descr_props->read_access, &attr_md.read_perm);
set_security_req(p_descr_props->write_access,&attr_md.write_perm);
attr_md.rd_auth = (p_descr_props->is_defered_read ? 1 : 0);
attr_md.wr_auth = (p_descr_props->is_defered_write ? 1 : 0);
attr_md.vlen = (p_descr_props->is_var_len ? 1 : 0);
attr_md.vloc = (p_descr_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK);
descr_params.p_attr_md = &attr_md;
descr_params.init_len = p_descr_props->init_len;
descr_params.init_offs = p_descr_props->init_offs;
descr_params.max_len = p_descr_props->max_len;
descr_params.p_value = p_descr_props->p_value;
return sd_ble_gatts_descriptor_add(char_handle, &descr_params, p_descr_handle);
}

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup ble_sdk_srv_common Common service definitions
* @{
* @ingroup ble_sdk_srv
* @brief Constants, type definitions, and functions that are common to all services.
*/
#ifndef BLE_SRV_COMMON_H__
#define BLE_SRV_COMMON_H__
#include <stdint.h>
#include <stdbool.h>
#include "ble_types.h"
#include "app_util.h"
#include "ble.h"
#include "ble_gap.h"
#include "ble_gatt.h"
/** @defgroup UUID_SERVICES Service UUID definitions
* @{ */
#define BLE_UUID_ALERT_NOTIFICATION_SERVICE 0x1811 /**< Alert Notification service UUID. */
#define BLE_UUID_BATTERY_SERVICE 0x180F /**< Battery service UUID. */
#define BLE_UUID_BLOOD_PRESSURE_SERVICE 0x1810 /**< Blood Pressure service UUID. */
#define BLE_UUID_CURRENT_TIME_SERVICE 0x1805 /**< Current Time service UUID. */
#define BLE_UUID_CYCLING_SPEED_AND_CADENCE 0x1816 /**< Cycling Speed and Cadence service UUID. */
#define BLE_UUID_LOCATION_AND_NAVIGATION_SERVICE 0x1819 /**< Location and Navigation service UUID. */
#define BLE_UUID_DEVICE_INFORMATION_SERVICE 0x180A /**< Device Information service UUID. */
#define BLE_UUID_GLUCOSE_SERVICE 0x1808 /**< Glucose service UUID. */
#define BLE_UUID_HEALTH_THERMOMETER_SERVICE 0x1809 /**< Health Thermometer service UUID. */
#define BLE_UUID_HEART_RATE_SERVICE 0x180D /**< Heart Rate service UUID. */
#define BLE_UUID_HUMAN_INTERFACE_DEVICE_SERVICE 0x1812 /**< Human Interface Device service UUID. */
#define BLE_UUID_IMMEDIATE_ALERT_SERVICE 0x1802 /**< Immediate Alert service UUID. */
#define BLE_UUID_LINK_LOSS_SERVICE 0x1803 /**< Link Loss service UUID. */
#define BLE_UUID_NEXT_DST_CHANGE_SERVICE 0x1807 /**< Next Dst Change service UUID. */
#define BLE_UUID_PHONE_ALERT_STATUS_SERVICE 0x180E /**< Phone Alert Status service UUID. */
#define BLE_UUID_REFERENCE_TIME_UPDATE_SERVICE 0x1806 /**< Reference Time Update service UUID. */
#define BLE_UUID_RUNNING_SPEED_AND_CADENCE 0x1814 /**< Running Speed and Cadence service UUID. */
#define BLE_UUID_SCAN_PARAMETERS_SERVICE 0x1813 /**< Scan Parameters service UUID. */
#define BLE_UUID_TX_POWER_SERVICE 0x1804 /**< TX Power service UUID. */
#define BLE_UUID_IPSP_SERVICE 0x1820 /**< Internet Protocol Support service UUID. */
#define BLE_UUID_BMS_SERVICE 0x181E /**< BOND MANAGEMENT service UUID*/
#define BLE_UUID_CGM_SERVICE 0x181F /**< Contiunous Glucose Monitoring service UUID*/
#define BLE_UUID_PLX_SERVICE 0x1822 /**< Pulse Oximeter Service UUID*/
/** @} */
/** @defgroup UUID_CHARACTERISTICS Characteristic UUID definitions
* @{ */
#define BLE_UUID_REMOVABLE_CHAR 0x2A3A /**< Removable characteristic UUID. */
#define BLE_UUID_SERVICE_REQUIRED_CHAR 0x2A3B /**< Service Required characteristic UUID. */
#define BLE_UUID_ALERT_CATEGORY_ID_CHAR 0x2A43 /**< Alert Category Id characteristic UUID. */
#define BLE_UUID_ALERT_CATEGORY_ID_BIT_MASK_CHAR 0x2A42 /**< Alert Category Id Bit Mask characteristic UUID. */
#define BLE_UUID_ALERT_LEVEL_CHAR 0x2A06 /**< Alert Level characteristic UUID. */
#define BLE_UUID_ALERT_NOTIFICATION_CONTROL_POINT_CHAR 0x2A44 /**< Alert Notification Control Point characteristic UUID. */
#define BLE_UUID_ALERT_STATUS_CHAR 0x2A3F /**< Alert Status characteristic UUID. */
#define BLE_UUID_BATTERY_LEVEL_CHAR 0x2A19 /**< Battery Level characteristic UUID. */
#define BLE_UUID_BLOOD_PRESSURE_FEATURE_CHAR 0x2A49 /**< Blood Pressure Feature characteristic UUID. */
#define BLE_UUID_BLOOD_PRESSURE_MEASUREMENT_CHAR 0x2A35 /**< Blood Pressure Measurement characteristic UUID. */
#define BLE_UUID_BODY_SENSOR_LOCATION_CHAR 0x2A38 /**< Body Sensor Location characteristic UUID. */
#define BLE_UUID_BOOT_KEYBOARD_INPUT_REPORT_CHAR 0x2A22 /**< Boot Keyboard Input Report characteristic UUID. */
#define BLE_UUID_BOOT_KEYBOARD_OUTPUT_REPORT_CHAR 0x2A32 /**< Boot Keyboard Output Report characteristic UUID. */
#define BLE_UUID_BOOT_MOUSE_INPUT_REPORT_CHAR 0x2A33 /**< Boot Mouse Input Report characteristic UUID. */
#define BLE_UUID_CURRENT_TIME_CHAR 0x2A2B /**< Current Time characteristic UUID. */
#define BLE_UUID_DATE_TIME_CHAR 0x2A08 /**< Date Time characteristic UUID. */
#define BLE_UUID_DAY_DATE_TIME_CHAR 0x2A0A /**< Day Date Time characteristic UUID. */
#define BLE_UUID_DAY_OF_WEEK_CHAR 0x2A09 /**< Day Of Week characteristic UUID. */
#define BLE_UUID_DST_OFFSET_CHAR 0x2A0D /**< Dst Offset characteristic UUID. */
#define BLE_UUID_EXACT_TIME_256_CHAR 0x2A0C /**< Exact Time 256 characteristic UUID. */
#define BLE_UUID_FIRMWARE_REVISION_STRING_CHAR 0x2A26 /**< Firmware Revision String characteristic UUID. */
#define BLE_UUID_GLUCOSE_FEATURE_CHAR 0x2A51 /**< Glucose Feature characteristic UUID. */
#define BLE_UUID_GLUCOSE_MEASUREMENT_CHAR 0x2A18 /**< Glucose Measurement characteristic UUID. */
#define BLE_UUID_GLUCOSE_MEASUREMENT_CONTEXT_CHAR 0x2A34 /**< Glucose Measurement Context characteristic UUID. */
#define BLE_UUID_HARDWARE_REVISION_STRING_CHAR 0x2A27 /**< Hardware Revision String characteristic UUID. */
#define BLE_UUID_HEART_RATE_CONTROL_POINT_CHAR 0x2A39 /**< Heart Rate Control Point characteristic UUID. */
#define BLE_UUID_HEART_RATE_MEASUREMENT_CHAR 0x2A37 /**< Heart Rate Measurement characteristic UUID. */
#define BLE_UUID_HID_CONTROL_POINT_CHAR 0x2A4C /**< Hid Control Point characteristic UUID. */
#define BLE_UUID_HID_INFORMATION_CHAR 0x2A4A /**< Hid Information characteristic UUID. */
#define BLE_UUID_IEEE_REGULATORY_CERTIFICATION_DATA_LIST_CHAR 0x2A2A /**< IEEE Regulatory Certification Data List characteristic UUID. */
#define BLE_UUID_INTERMEDIATE_CUFF_PRESSURE_CHAR 0x2A36 /**< Intermediate Cuff Pressure characteristic UUID. */
#define BLE_UUID_INTERMEDIATE_TEMPERATURE_CHAR 0x2A1E /**< Intermediate Temperature characteristic UUID. */
#define BLE_UUID_LOCAL_TIME_INFORMATION_CHAR 0x2A0F /**< Local Time Information characteristic UUID. */
#define BLE_UUID_MANUFACTURER_NAME_STRING_CHAR 0x2A29 /**< Manufacturer Name String characteristic UUID. */
#define BLE_UUID_MEASUREMENT_INTERVAL_CHAR 0x2A21 /**< Measurement Interval characteristic UUID. */
#define BLE_UUID_MODEL_NUMBER_STRING_CHAR 0x2A24 /**< Model Number String characteristic UUID. */
#define BLE_UUID_UNREAD_ALERT_CHAR 0x2A45 /**< Unread Alert characteristic UUID. */
#define BLE_UUID_NEW_ALERT_CHAR 0x2A46 /**< New Alert characteristic UUID. */
#define BLE_UUID_PNP_ID_CHAR 0x2A50 /**< PNP Id characteristic UUID. */
#define BLE_UUID_PROTOCOL_MODE_CHAR 0x2A4E /**< Protocol Mode characteristic UUID. */
#define BLE_UUID_RECORD_ACCESS_CONTROL_POINT_CHAR 0x2A52 /**< Record Access Control Point characteristic UUID. */
#define BLE_UUID_REFERENCE_TIME_INFORMATION_CHAR 0x2A14 /**< Reference Time Information characteristic UUID. */
#define BLE_UUID_REPORT_CHAR 0x2A4D /**< Report characteristic UUID. */
#define BLE_UUID_REPORT_MAP_CHAR 0x2A4B /**< Report Map characteristic UUID. */
#define BLE_UUID_RINGER_CONTROL_POINT_CHAR 0x2A40 /**< Ringer Control Point characteristic UUID. */
#define BLE_UUID_RINGER_SETTING_CHAR 0x2A41 /**< Ringer Setting characteristic UUID. */
#define BLE_UUID_SCAN_INTERVAL_WINDOW_CHAR 0x2A4F /**< Scan Interval Window characteristic UUID. */
#define BLE_UUID_SCAN_REFRESH_CHAR 0x2A31 /**< Scan Refresh characteristic UUID. */
#define BLE_UUID_SERIAL_NUMBER_STRING_CHAR 0x2A25 /**< Serial Number String characteristic UUID. */
#define BLE_UUID_SOFTWARE_REVISION_STRING_CHAR 0x2A28 /**< Software Revision String characteristic UUID. */
#define BLE_UUID_SUPPORTED_NEW_ALERT_CATEGORY_CHAR 0x2A47 /**< Supported New Alert Category characteristic UUID. */
#define BLE_UUID_SUPPORTED_UNREAD_ALERT_CATEGORY_CHAR 0x2A48 /**< Supported Unread Alert Category characteristic UUID. */
#define BLE_UUID_SYSTEM_ID_CHAR 0x2A23 /**< System Id characteristic UUID. */
#define BLE_UUID_TEMPERATURE_MEASUREMENT_CHAR 0x2A1C /**< Temperature Measurement characteristic UUID. */
#define BLE_UUID_TEMPERATURE_TYPE_CHAR 0x2A1D /**< Temperature Type characteristic UUID. */
#define BLE_UUID_TIME_ACCURACY_CHAR 0x2A12 /**< Time Accuracy characteristic UUID. */
#define BLE_UUID_TIME_SOURCE_CHAR 0x2A13 /**< Time Source characteristic UUID. */
#define BLE_UUID_TIME_UPDATE_CONTROL_POINT_CHAR 0x2A16 /**< Time Update Control Point characteristic UUID. */
#define BLE_UUID_TIME_UPDATE_STATE_CHAR 0x2A17 /**< Time Update State characteristic UUID. */
#define BLE_UUID_TIME_WITH_DST_CHAR 0x2A11 /**< Time With Dst characteristic UUID. */
#define BLE_UUID_TIME_ZONE_CHAR 0x2A0E /**< Time Zone characteristic UUID. */
#define BLE_UUID_TX_POWER_LEVEL_CHAR 0x2A07 /**< TX Power Level characteristic UUID. */
#define BLE_UUID_CSC_FEATURE_CHAR 0x2A5C /**< Cycling Speed and Cadence Feature characteristic UUID. */
#define BLE_UUID_CSC_MEASUREMENT_CHAR 0x2A5B /**< Cycling Speed and Cadence Measurement characteristic UUID. */
#define BLE_UUID_RSC_FEATURE_CHAR 0x2A54 /**< Running Speed and Cadence Feature characteristic UUID. */
#define BLE_UUID_SC_CTRLPT_CHAR 0x2A55 /**< Speed and Cadence Control Point UUID. */
#define BLE_UUID_RSC_MEASUREMENT_CHAR 0x2A53 /**< Running Speed and Cadence Measurement characteristic UUID. */
#define BLE_UUID_SENSOR_LOCATION_CHAR 0x2A5D /**< Sensor Location characteristic UUID. */
#define BLE_UUID_EXTERNAL_REPORT_REF_DESCR 0x2907 /**< External Report Reference descriptor UUID. */
#define BLE_UUID_REPORT_REF_DESCR 0x2908 /**< Report Reference descriptor UUID. */
#define BLE_UUID_LN_FEATURE_CHAR 0x2A6A /**< Location Navigation Service, Feature characteristic UUID. */
#define BLE_UUID_LN_POSITION_QUALITY_CHAR 0x2A69 /**< Location Navigation Service, Position quality UUID. */
#define BLE_UUID_LN_LOCATION_AND_SPEED_CHAR 0x2A67 /**< Location Navigation Service, Location and Speed characteristic UUID. */
#define BLE_UUID_LN_NAVIGATION_CHAR 0x2A68 /**< Location Navigation Service, Navigation characteristic UUID. */
#define BLE_UUID_LN_CONTROL_POINT_CHAR 0x2A6B /**< Location Navigation Service, Control point characteristic UUID. */
#define BLE_UUID_BMS_CTRLPT 0x2AA4 /**< BMS Control Point characteristic UUID. */
#define BLE_UUID_BMS_FEATURE 0x2AA5 /**< BMS Feature characteristic UUID. */
#define BLE_UUID_CGM_MEASUREMENT 0x2AA7 /**< CGM Service, Measurement characteristic UUID*/
#define BLE_UUID_CGM_FEATURE 0x2AA8 /**< CGM Service, Feature characteristic UUID*/
#define BLE_UUID_CGM_STATUS 0x2AA9 /**< CGM Service, Status characteristic UUID*/
#define BLE_UUID_CGM_SESSION_START_TIME 0x2AAA /**< CGM Service, session start time characteristic UUID*/
#define BLE_UUID_CGM_SESSION_RUN_TIME 0x2AAB /**< CGM Service, session run time characteristic UUID*/
#define BLE_UUID_CGM_SPECIFIC_OPS_CTRLPT 0x2AAC /**< CGM Service, specific ops ctrlpt characteristic UUID*/
#define BLE_UUID_PLX_SPOT_CHECK_MEAS 0x2A5E /**< PLX Service, spot check measurement characteristic UUID*/
#define BLE_UUID_PLX_CONTINUOUS_MEAS 0x2A5F /**< PLX Service, continuous measurement characteristic UUID*/
#define BLE_UUID_PLX_FEATURES 0x2A60 /**< PLX Service, feature characteristic UUID*/
/** @} */
/** @defgroup ALERT_LEVEL_VALUES Definitions for the Alert Level characteristic values
* @{ */
#define BLE_CHAR_ALERT_LEVEL_NO_ALERT 0x00 /**< No Alert. */
#define BLE_CHAR_ALERT_LEVEL_MILD_ALERT 0x01 /**< Mild Alert. */
#define BLE_CHAR_ALERT_LEVEL_HIGH_ALERT 0x02 /**< High Alert. */
/** @} */
#define BLE_SRV_ENCODED_REPORT_REF_LEN 2 /**< The length of an encoded Report Reference Descriptor. */
#define BLE_CCCD_VALUE_LEN 2 /**< The length of a CCCD value. */
/**@brief Type definition for error handler function that will be called in case of an error in
* a service or a service library module. */
typedef void (*ble_srv_error_handler_t) (uint32_t nrf_error);
/**@brief Value of a Report Reference descriptor.
*
* @details This is mapping information that maps the parent characteristic to the Report ID(s) and
* Report Type(s) defined within a Report Map characteristic.
*/
typedef struct
{
uint8_t report_id; /**< Non-zero value if there is more than one instance of the same Report Type */
uint8_t report_type; /**< Type of Report characteristic (see @ref BLE_HIDS_REPORT_TYPE) */
} ble_srv_report_ref_t;
/**@brief UTF-8 string data type.
*
* @note The type can only hold a pointer to the string data (i.e. not the actual data).
*/
typedef struct
{
uint16_t length; /**< String length. */
uint8_t * p_str; /**< String data. */
} ble_srv_utf8_str_t;
/**@brief Security settings structure.
* @details This structure contains the security options needed during initialization of the
* service.
*/
typedef struct
{
ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */
ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */
} ble_srv_security_mode_t;
/**@brief Security settings structure.
* @details This structure contains the security options needed during initialization of the
* service. It can be used when the characteristics contains a CCCD.
*/
typedef struct
{
ble_gap_conn_sec_mode_t cccd_write_perm; /**< Write permissions for Client Characteristic Configuration Descriptor. */
ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */
ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */
} ble_srv_cccd_security_mode_t;
/**@brief Function for decoding a CCCD value, and then testing if notification is
* enabled.
*
* @param[in] p_encoded_data Buffer where the encoded CCCD is stored.
*
* @retval TRUE If notification is enabled.
* @retval FALSE Otherwise.
*/
static __INLINE bool ble_srv_is_notification_enabled(uint8_t const * p_encoded_data)
{
uint16_t cccd_value = uint16_decode(p_encoded_data);
return ((cccd_value & BLE_GATT_HVX_NOTIFICATION) != 0);
}
/**@brief Function for decoding a CCCD value, and then testing if indication is
* enabled.
*
* @param[in] p_encoded_data Buffer where the encoded CCCD is stored.
*
* @retval TRUE If indication is enabled.
* @retval FALSE Otherwise.
*/
static __INLINE bool ble_srv_is_indication_enabled(uint8_t const * p_encoded_data)
{
uint16_t cccd_value = uint16_decode(p_encoded_data);
return ((cccd_value & BLE_GATT_HVX_INDICATION) != 0);
}
/**@brief Function for encoding a Report Reference Descriptor.
*
* @param[in] p_encoded_buffer The buffer of the encoded data.
* @param[in] p_report_ref Report Reference value to be encoded.
*
* @return Length of the encoded data.
*/
uint8_t ble_srv_report_ref_encode(uint8_t * p_encoded_buffer,
const ble_srv_report_ref_t * p_report_ref);
/**@brief Function for making a UTF-8 structure refer to an ASCII string.
*
* @param[out] p_utf8 UTF-8 structure to be set.
* @param[in] p_ascii ASCII string to be referred to.
*/
void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii);
/**@brief Security Access enumeration.
* @details This enumeration gives the possible requirements for accessing a characteristic value.
*/
typedef enum
{
SEC_NO_ACCESS = 0, /**< Not possible to access. */
SEC_OPEN = 1, /**< Access open. */
SEC_JUST_WORKS = 2, /**< Access possible with 'Just Works' security at least. */
SEC_MITM = 3, /**< Access possible with 'MITM' security at least. */
SEC_SIGNED = 4, /**< Access possible with 'signed' security at least. */
SEC_SIGNED_MITM = 5 /**< Access possible with 'signed and MITM' security at least. */
}security_req_t;
/**@brief Characteristic User Descriptor parameters.
* @details This structure contains the parameters for User Descriptor.
*/
typedef struct
{
uint16_t max_size; /**< Maximum size of the user descriptor*/
uint16_t size; /**< Size of the user descriptor*/
uint8_t *p_char_user_desc; /**< User descriptor content, pointer to a UTF-8 encoded string (non-NULL terminated)*/
bool is_var_len; /**< Indicates if the user descriptor has variable length.*/
ble_gatt_char_props_t char_props; /**< user descriptor properties.*/
bool is_defered_read; /**< Indicate if deferred read operations are supported.*/
bool is_defered_write; /**< Indicate if deferred write operations are supported.*/
security_req_t read_access; /**< Security requirement for reading the user descriptor.*/
security_req_t write_access; /**< Security requirement for writing the user descriptor.*/
bool is_value_user; /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/
}ble_add_char_user_desc_t;
/**@brief Add characteristic parameters structure.
* @details This structure contains the parameters needed to use the @ref characteristic_add function.
*/
typedef struct
{
uint16_t uuid; /**< Characteristic UUID (16 bits UUIDs).*/
uint8_t uuid_type; /**< Base UUID. If 0, the Bluetooth SIG UUID will be used. Otherwise, this should be a value returned by @ref sd_ble_uuid_vs_add when adding the base UUID.*/
uint16_t max_len; /**< Maximum length of the characteristic value.*/
uint16_t init_len; /**< Initial length of the characteristic value.*/
uint8_t * p_init_value; /**< Initial encoded value of the characteristic.*/
bool is_var_len; /**< Indicates if the characteristic value has variable length.*/
ble_gatt_char_props_t char_props; /**< Characteristic properties.*/
bool is_defered_read; /**< Indicate if deferred read operations are supported.*/
bool is_defered_write; /**< Indicate if deferred write operations are supported.*/
security_req_t read_access; /**< Security requirement for reading the characteristic value.*/
security_req_t write_access; /**< Security requirement for writing the characteristic value.*/
security_req_t cccd_write_access; /**< Security requirement for writing the characteristic's CCCD.*/
bool is_value_user; /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/
ble_add_char_user_desc_t *p_user_descr; /**< Pointer to user descriptor if needed*/
ble_gatts_char_pf_t *p_presentation_format; /**< Pointer to characteristic format if needed*/
} ble_add_char_params_t;
/**@brief Add descriptor parameters structure.
* @details This structure contains the parameters needed to use the @ref descriptor_add function.
*/
typedef struct
{
uint16_t uuid; /**< descriptor UUID (16 bits UUIDs).*/
uint8_t uuid_type; /**< Base UUID. If 0, the Bluetooth SIG UUID will be used. Otherwise, this should be a value returned by @ref sd_ble_uuid_vs_add when adding the base UUID.*/
bool is_defered_read; /**< Indicate if deferred read operations are supported.*/
bool is_defered_write; /**< Indicate if deferred write operations are supported.*/
bool is_var_len; /**< Indicates if the descriptor value has variable length.*/
security_req_t read_access; /**< Security requirement for reading the descriptor value.*/
security_req_t write_access; /**< Security requirement for writing the descriptor value.*/
bool is_value_user; /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/
uint16_t init_len; /**< Initial descriptor value length in bytes. */
uint16_t init_offs; /**< Initial descriptor value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */
uint16_t max_len; /**< Maximum descriptor value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */
uint8_t* p_value; /**< Pointer to the value of the descriptor*/
} ble_add_descr_params_t;
/**@brief Function for adding a characteristic to a given service.
*
* If no pointer is given for the initial value,
* the initial length parameter will be ignored and the initial length will be 0.
*
* @param[in] service_handle Handle of the service to which the characteristic is to be added.
* @param[in] p_char_props Information needed to add the characteristic.
* @param[out] p_char_handle Handle of the added characteristic.
*
* @retval NRF_SUCCESS If the characteristic was added successfully. Otherwise, an error code is returned.
*/
uint32_t characteristic_add(uint16_t service_handle,
ble_add_char_params_t * p_char_props,
ble_gatts_char_handles_t * p_char_handle);
/**@brief Function for adding a characteristic's descriptor to a given characteristic.
*
* @param[in] char_handle Handle of the characteristic to which the descriptor is to be added, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
* @param[in] p_descr_props Information needed to add the descriptor.
* @param[out] p_descr_handle Handle of the added descriptor.
*
* @retval NRF_SUCCESS If the characteristic was added successfully. Otherwise, an error code is returned.
*/
uint32_t descriptor_add(uint16_t char_handle,
ble_add_descr_params_t * p_descr_props,
uint16_t * p_descr_handle);
#endif // BLE_SRV_COMMON_H__
/** @} */

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/* Copyright (c) 2015, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _COMPILER_ABSTRACTION_H
#define _COMPILER_ABSTRACTION_H
/*lint ++flb "Enter library region" */
#if defined ( __CC_ARM )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
#define GET_SP() __current_sp()
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
/* Not defined for IAR since it requires a new line to work, and C preprocessor does not allow that. */
#ifndef __ALIGN
#define __ALIGN(n)
#endif
#define GET_SP() __get_SP()
#elif defined ( __GNUC__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __attribute__((aligned(n)))
#endif
#define GET_SP() gcc_current_sp()
static inline unsigned int gcc_current_sp(void)
{
register unsigned sp __ASM("sp");
return sp;
}
#elif defined ( __TASKING__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
#define GET_SP() __get_MSP()
#endif
/*lint --flb "Leave library region" */
#endif

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/* Copyright (c) 2015, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_H
#define NRF_H
/* MDK version */
#define MDK_MAJOR_VERSION 8
#define MDK_MINOR_VERSION 5
#define MDK_MICRO_VERSION 0
#if defined(_WIN32)
/* Do not include nrf51 specific files when building for PC host */
//#elif defined(__unix)
/* Do not include nrf51 specific files when building for PC host */
#elif defined(__APPLE__)
/* Do not include nrf51 specific files when building for PC host */
#else
/* Family selection for family includes. */
#if defined (NRF51)
#include "nrf51.h"
#include "nrf51_bitfields.h"
#include "nrf51_deprecated.h"
#elif defined (NRF52)
#include "nrf52.h"
#include "nrf52_bitfields.h"
#include "nrf51_to_nrf52.h"
#include "nrf52_name_change.h"
#else
#error "Device family must be defined. See nrf.h."
#endif /* NRF51, NRF52 */
#include "compiler_abstraction.h"
#endif /* _WIN32 || __unix || __APPLE__ */
#endif /* NRF_H */

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/* Copyright (c) 2015, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF51_TO_NRF52_H
#define NRF51_TO_NRF52_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices.
* It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
* functionality is gone, there old names are not define, so compilation will fail. Note that also includes macros
* from the nrf51_deprecated.h file. */
/* IRQ */
/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
#define UART0_IRQHandler UARTE0_UART0_IRQHandler
#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define ADC_IRQHandler SAADC_IRQHandler
#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler
#define SWI0_IRQHandler SWI0_EGU0_IRQHandler
#define SWI1_IRQHandler SWI1_EGU1_IRQHandler
#define SWI2_IRQHandler SWI2_EGU2_IRQHandler
#define SWI3_IRQHandler SWI3_EGU3_IRQHandler
#define SWI4_IRQHandler SWI4_EGU4_IRQHandler
#define SWI5_IRQHandler SWI5_EGU5_IRQHandler
#define UART0_IRQn UARTE0_UART0_IRQn
#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
#define ADC_IRQn SAADC_IRQn
#define LPCOMP_IRQn COMP_LPCOMP_IRQn
#define SWI0_IRQn SWI0_EGU0_IRQn
#define SWI1_IRQn SWI1_EGU1_IRQn
#define SWI2_IRQn SWI2_EGU2_IRQn
#define SWI3_IRQn SWI3_EGU3_IRQn
#define SWI4_IRQn SWI4_EGU4_IRQn
#define SWI5_IRQn SWI5_EGU5_IRQn
/* UICR */
/* Register RBPCONF was renamed to APPROTECT. */
#define RBPCONF APPROTECT
#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos
#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk
#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled
#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled
/* GPIO */
/* GPIO port was renamed to P0. */
#define NRF_GPIO NRF_P0
#define NRF_GPIO_BASE NRF_P0_BASE
/* SPIS */
/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
#define PSELSCK PSEL.SCK
#define PSELMISO PSEL.MISO
#define PSELMOSI PSEL.MOSI
#define PSELCSN PSEL.CSN
/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
#define RXDPTR RXD.PTR
#define MAXRX RXD.MAXCNT
#define AMOUNTRX RXD.AMOUNT
#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos
#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk
#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos
#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk
/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
#define TXDPTR TXD.PTR
#define MAXTX TXD.MAXCNT
#define AMOUNTTX TXD.AMOUNT
#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos
#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk
#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
/* MPU */
/* Part of MPU module was renamed BPROT, while the rest was eliminated. */
#define NRF_MPU NRF_BPROT
/* Register DISABLEINDEBUG macros were affected. */
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled
/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */
#define PROTENSET0 CONFIG0
#define PROTENSET1 CONFIG1
#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos
#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk
#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled
#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled
#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled
#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos
#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk
#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled
#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled
#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled
#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos
#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk
#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled
#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled
#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled
#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos
#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk
#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled
#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled
#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled
#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos
#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk
#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled
#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled
#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled
#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos
#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk
#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled
#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled
#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled
#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos
#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk
#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled
#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled
#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled
#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos
#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk
#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled
#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled
#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled
#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos
#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk
#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled
#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled
#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled
#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos
#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk
#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled
#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled
#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled
#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos
#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk
#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled
#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled
#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled
#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos
#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk
#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled
#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled
#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled
#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos
#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk
#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled
#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled
#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled
#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos
#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk
#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled
#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled
#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled
#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos
#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk
#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled
#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled
#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled
#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos
#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk
#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled
#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled
#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled
#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos
#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk
#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled
#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled
#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled
#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos
#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk
#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled
#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled
#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled
#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos
#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk
#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled
#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled
#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled
#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos
#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk
#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled
#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled
#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled
#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos
#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk
#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled
#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled
#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled
#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos
#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk
#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled
#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled
#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled
#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos
#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk
#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled
#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled
#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled
#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos
#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk
#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled
#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled
#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled
#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos
#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk
#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled
#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled
#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled
#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos
#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk
#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled
#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled
#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled
#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos
#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk
#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled
#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled
#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled
#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos
#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk
#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled
#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled
#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled
#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos
#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk
#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled
#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled
#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled
#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos
#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk
#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled
#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled
#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled
#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos
#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk
#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled
#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled
#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled
#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos
#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk
#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled
#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled
#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled
#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos
#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk
#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled
#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled
#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled
#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos
#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk
#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled
#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled
#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled
#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos
#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk
#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled
#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled
#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled
#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos
#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk
#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled
#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled
#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled
#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos
#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk
#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled
#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled
#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled
#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos
#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk
#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled
#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled
#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled
#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos
#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk
#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled
#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled
#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled
#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos
#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk
#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled
#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled
#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled
#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos
#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk
#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled
#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled
#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled
#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos
#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk
#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled
#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled
#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled
#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos
#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk
#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled
#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled
#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled
#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos
#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk
#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled
#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled
#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled
#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos
#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk
#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled
#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled
#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled
#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos
#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk
#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled
#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled
#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled
#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos
#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk
#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled
#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled
#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled
#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos
#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk
#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled
#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled
#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled
#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos
#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk
#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled
#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled
#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled
#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos
#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk
#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled
#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled
#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled
#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos
#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk
#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled
#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled
#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled
#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos
#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk
#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled
#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled
#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled
#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos
#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk
#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled
#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled
#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled
#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos
#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk
#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled
#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled
#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled
#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos
#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk
#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled
#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled
#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled
#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos
#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk
#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled
#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled
#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled
#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos
#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk
#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled
#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled
#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled
#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos
#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk
#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled
#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled
#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled
#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos
#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk
#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled
#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled
#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled
#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos
#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk
#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled
#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled
#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled
#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos
#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk
#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled
#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled
#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled
#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos
#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk
#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled
#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled
#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled
#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos
#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk
#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled
#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled
#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled
#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos
#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk
#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled
#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled
#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled
/* From nrf51_deprecated.h */
/* NVMC */
/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
#define ERASEPROTECTEDPAGE ERASEPCR0
/* IRQ */
/* COMP module was eliminated. Adapted to nrf52 headers. */
#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler
#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn
/* RADIO */
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
/* FICR */
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
#define DEVICEID0 DEVICEID[0]
#define DEVICEID1 DEVICEID[1]
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
#define ER0 ER[0]
#define ER1 ER[1]
#define ER2 ER[2]
#define ER3 ER[3]
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
#define IR0 IR[0]
#define IR1 IR[1]
#define IR2 IR[2]
#define IR3 IR[3]
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
#define DEVICEADDR0 DEVICEADDR[0]
#define DEVICEADDR1 DEVICEADDR[1]
/* PPI */
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
#define TASKS_CHG0EN TASKS_CHG[0].EN
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
#define TASKS_CHG1EN TASKS_CHG[1].EN
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
#define TASKS_CHG2EN TASKS_CHG[2].EN
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
#define TASKS_CHG3EN TASKS_CHG[3].EN
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
#define CH0_EEP CH[0].EEP
#define CH0_TEP CH[0].TEP
#define CH1_EEP CH[1].EEP
#define CH1_TEP CH[1].TEP
#define CH2_EEP CH[2].EEP
#define CH2_TEP CH[2].TEP
#define CH3_EEP CH[3].EEP
#define CH3_TEP CH[3].TEP
#define CH4_EEP CH[4].EEP
#define CH4_TEP CH[4].TEP
#define CH5_EEP CH[5].EEP
#define CH5_TEP CH[5].TEP
#define CH6_EEP CH[6].EEP
#define CH6_TEP CH[6].TEP
#define CH7_EEP CH[7].EEP
#define CH7_TEP CH[7].TEP
#define CH8_EEP CH[8].EEP
#define CH8_TEP CH[8].TEP
#define CH9_EEP CH[9].EEP
#define CH9_TEP CH[9].TEP
#define CH10_EEP CH[10].EEP
#define CH10_TEP CH[10].TEP
#define CH11_EEP CH[11].EEP
#define CH11_TEP CH[11].TEP
#define CH12_EEP CH[12].EEP
#define CH12_TEP CH[12].TEP
#define CH13_EEP CH[13].EEP
#define CH13_TEP CH[13].TEP
#define CH14_EEP CH[14].EEP
#define CH14_TEP CH[14].TEP
#define CH15_EEP CH[15].EEP
#define CH15_TEP CH[15].TEP
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
#define CHG0 CHG[0]
#define CHG1 CHG[1]
#define CHG2 CHG[2]
#define CHG3 CHG[3]
/* All bitfield macros for the CHGx registers therefore changed name. */
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
/*lint --flb "Leave library region" */
#endif /* NRF51_TO_NRF52_H */

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/* Copyright (c) 2015, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF52_NAME_CHANGE_H
#define NRF52_NAME_CHANGE_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and
* nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
*/
/* I2S */
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
/*lint --flb "Leave library region" */
#endif /* NRF52_NAME_CHANGE_H */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stddef.h>
#include "nrf_drv_common.h"
#include "nrf_assert.h"
#include "app_util_platform.h"
#ifdef SOFTDEVICE_PRESENT
#include "nrf_soc.h"
#endif
#if PERIPHERAL_RESOURCE_SHARING_ENABLED
typedef struct {
nrf_drv_irq_handler_t handler;
bool acquired;
} shared_resource_t;
// SPIM0, SPIS0, SPI0, TWIM0, TWIS0, TWI0
#if (SPI0_ENABLED || SPIS0_ENABLED || TWI0_ENABLED || TWIS0_ENABLED)
#define SERIAL_BOX_0_IN_USE
// [this checking may need a different form in unit tests, hence macro]
#ifndef IS_SERIAL_BOX_0
#define IS_SERIAL_BOX_0(p_per_base) (p_per_base == NRF_SPI0)
#endif
static shared_resource_t m_serial_box_0 = { .acquired = false };
void SPI0_TWI0_IRQHandler(void)
{
ASSERT(m_serial_box_0.handler);
m_serial_box_0.handler();
}
#endif // (SPI0_ENABLED || SPIS0_ENABLED || TWI0_ENABLED || TWIS0_ENABLED)
// SPIM1, SPIS1, SPI1, TWIM1, TWIS1, TWI1
#if (SPI1_ENABLED || SPIS1_ENABLED || TWI1_ENABLED || TWIS1_ENABLED)
#define SERIAL_BOX_1_IN_USE
// [this checking may need a different form in unit tests, hence macro]
#ifndef IS_SERIAL_BOX_1
#define IS_SERIAL_BOX_1(p_per_base) (p_per_base == NRF_SPI1)
#endif
static shared_resource_t m_serial_box_1 = { .acquired = false };
void SPI1_TWI1_IRQHandler(void)
{
ASSERT(m_serial_box_1.handler);
m_serial_box_1.handler();
}
#endif // (SPI1_ENABLED || SPIS1_ENABLED || TWI1_ENABLED || TWIS1_ENABLED)
// SPIM2, SPIS2, SPI2
#if (SPI2_ENABLED || SPIS2_ENABLED)
#define SERIAL_BOX_2_IN_USE
// [this checking may need a different form in unit tests, hence macro]
#ifndef IS_SERIAL_BOX_2
#define IS_SERIAL_BOX_2(p_per_base) (p_per_base == NRF_SPI2)
#endif
static shared_resource_t m_serial_box_2 = { .acquired = false };
void SPIM2_SPIS2_SPI2_IRQHandler(void)
{
ASSERT(m_serial_box_2.handler);
m_serial_box_2.handler();
}
#endif // (SPI2_ENABLED || SPIS2_ENABLED)
// COMP, LPCOMP
#if (COMP_ENABLED || LPCOMP_ENABLED)
#define COMP_LPCOMP_IN_USE
#ifndef IS_COMP_LPCOMP
#define IS_COMP_LPCOMP(p_per_base) ((p_per_base) == NRF_LPCOMP)
#endif
static shared_resource_t m_comp_lpcomp = { .acquired = false };
void LPCOMP_IRQHandler(void)
{
ASSERT(m_comp_lpcomp.handler);
m_comp_lpcomp.handler();
}
#endif // (COMP_ENABLED || LPCOMP_ENABLED)
#if defined(SERIAL_BOX_0_IN_USE) || \
defined(SERIAL_BOX_1_IN_USE) || \
defined(SERIAL_BOX_2_IN_USE) || \
defined(COMP_LPCOMP_IN_USE)
static ret_code_t acquire_shared_resource(shared_resource_t * p_resource,
nrf_drv_irq_handler_t handler)
{
bool busy = false;
CRITICAL_REGION_ENTER();
if (p_resource->acquired)
{
busy = true;
}
else
{
p_resource->acquired = true;
}
CRITICAL_REGION_EXIT();
if (busy)
{
return NRF_ERROR_BUSY;
}
p_resource->handler = handler;
return NRF_SUCCESS;
}
#endif
ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base,
nrf_drv_irq_handler_t handler)
{
#ifdef SERIAL_BOX_0_IN_USE
if (IS_SERIAL_BOX_0(p_per_base))
{
return acquire_shared_resource(&m_serial_box_0, handler);
}
#endif
#ifdef SERIAL_BOX_1_IN_USE
if (IS_SERIAL_BOX_1(p_per_base))
{
return acquire_shared_resource(&m_serial_box_1, handler);
}
#endif
#ifdef SERIAL_BOX_2_IN_USE
if (IS_SERIAL_BOX_2(p_per_base))
{
return acquire_shared_resource(&m_serial_box_2, handler);
}
#endif
#ifdef COMP_LPCOMP_IN_USE
if (IS_COMP_LPCOMP(p_per_base))
{
return acquire_shared_resource(&m_comp_lpcomp, handler);
}
#endif
return NRF_ERROR_INVALID_PARAM;
}
void nrf_drv_common_per_res_release(void const * p_per_base)
{
#ifdef SERIAL_BOX_0_IN_USE
if (IS_SERIAL_BOX_0(p_per_base))
{
m_serial_box_0.acquired = false;
}
else
#endif
#ifdef SERIAL_BOX_1_IN_USE
if (IS_SERIAL_BOX_1(p_per_base))
{
m_serial_box_1.acquired = false;
}
else
#endif
#ifdef SERIAL_BOX_2_IN_USE
if (IS_SERIAL_BOX_2(p_per_base))
{
m_serial_box_2.acquired = false;
}
else
#endif
#ifdef COMP_LPCOMP_IN_USE
if (IS_COMP_LPCOMP(p_per_base))
{
m_comp_lpcomp.acquired = false;
}
else
#endif
{}
}
#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority)
{
#ifdef SOFTDEVICE_PRESENT
ASSERT((priority == APP_IRQ_PRIORITY_LOW) || (priority == APP_IRQ_PRIORITY_HIGH));
#endif
NVIC_SetPriority(IRQn, priority);
NVIC_ClearPendingIRQ(IRQn);
NVIC_EnableIRQ(IRQn);
}

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_DRV_COMMON_H__
#define NRF_DRV_COMMON_H__
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "sdk_errors.h"
#include "nrf_drv_config.h"
/**
* @brief Offset of event registers in every peripheral instance
*
* This is the offset where event registers start in the every peripheral.
*/
#define NRF_DRV_COMMON_EVREGS_OFFSET 0x100U
/**
* @brief Driver state.
*/
typedef enum
{
NRF_DRV_STATE_UNINITIALIZED, /**< Uninitialized. */
NRF_DRV_STATE_INITIALIZED, /**< Initialized but powered off. */
NRF_DRV_STATE_POWERED_ON
} nrf_drv_state_t;
/**
* @brief Driver power state selection.
*/
typedef enum
{
NRF_DRV_PWR_CTRL_ON, /**< Power on request. */
NRF_DRV_PWR_CTRL_OFF /**< Power off request. */
} nrf_drv_pwr_ctrl_t;
/**
* @brief IRQ handler type.
*/
typedef void (*nrf_drv_irq_handler_t)(void);
#if PERIPHERAL_RESOURCE_SHARING_ENABLED
/**
* @brief Function for acquiring shared peripheral resources associated with
* the specified peripheral.
*
* Certain resources and registers are shared among peripherals that have
* the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0).
* Only one of them can be utilized at a given time. This function reserves
* proper resources to be used by the specified peripheral.
* If PERIPHERAL_RESOURCE_SHARING_ENABLED is set to a non-zero value, IRQ
* handlers for peripherals that are sharing resources with others are
* implemented by the nrf_drv_common module instead of individual drivers.
* The drivers must then specify their interrupt handling routines and
* register them by using this function.
*
* @param[in] p_per_base Requested peripheral base pointer.
* @param[in] handler Interrupt handler to register. May be NULL
* if interrupts are not used for the peripheral.
*
* @retval NRF_SUCCESS If resources were acquired successfully.
* @retval NRF_ERROR_BUSY If resources were already acquired.
* @retval NRF_ERROR_INVALID_PARAM If the specified peripheral is not enabled
* or the peripheral does not share resources
* with other peripherals.
*/
ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base,
nrf_drv_irq_handler_t handler);
/**
* @brief Function for releasing shared resources reserved previously by
* @ref nrf_drv_common_per_res_acquire() for the specified peripheral.
*
* @param[in] p_per_base Requested peripheral base pointer.
*/
void nrf_drv_common_per_res_release(void const * p_per_base);
#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
/**
* @brief Function sets priority and enables NVIC interrupt
*
* @note Function checks if correct priority is used when softdevice is present
*
* @param[in] IRQn Interrupt id
* @param[in] priority Interrupt priority
*/
void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority);
/**
* @brief Function disables NVIC interrupt
*
* @param[in] IRQn Interrupt id
*/
__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn);
/**
* @brief Convert bit position to event code
*
* Function for converting the bit position in INTEN register to event code
* that is equivalent to the offset of the event register from the beginning
* of peripheral instance.
*
* For example the result of this function can be casted directly to
* the types like @ref nrf_twis_event_t or @ref nrf_rng_events_t...
*
* @param bit Bit position in INTEN register
* @return Event code to be casted to the right enum type or to be used in functions like
* @ref nrf_rng_event_get
*
* @sa nrf_drv_event_to_bitpos
*/
__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit);
/**
* @brief Convert event code to bit position
*
* This function can be used to get bit position in INTEN register from event code.
*
* @param event Event code that may be casted from enum values from types like
* @ref nrf_twis_event_t or @ref nrf_rng_events_t
* @return Bit position in INTEN register that corresponds to the given code.
*
* @sa nrf_drv_bitpos_to_event
*/
__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event);
/**
* @brief Get interrupt number connected with given instance
*
* Function returns interrupt number for a given instance of any peripheral.
* @param[in] pinst Pointer to peripheral registry
* @return Interrupt number
*/
__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst);
/**
* @brief Check if given object is in RAM
*
* Function for analyzing if given location is placed in RAM.
* This function is used to determine if we have address that can be supported by EasyDMA.
* @param[in] ptr Pointer to the object
* @retval true Object is located in RAM
* @retval false Object is not located in RAM
*/
__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn)
{
NVIC_DisableIRQ(IRQn);
}
__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit)
{
return NRF_DRV_COMMON_EVREGS_OFFSET + bit * sizeof(uint32_t);
}
__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event)
{
return (event - NRF_DRV_COMMON_EVREGS_OFFSET) / sizeof(uint32_t);
}
__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst)
{
uint8_t ret = (uint8_t)((uint32_t)pinst>>12U);
return (IRQn_Type) ret;
}
__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr)
{
return ((((uintptr_t)ptr) & 0xE0000000u) == 0x20000000u);
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_DRV_COMMON_H__

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_DRV_CONFIG_H
#define NRF_DRV_CONFIG_H
/**
* Provide a non-zero value here in applications that need to use several
* peripherals with the same ID that are sharing certain resources
* (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
* simultaneously. Therefore, this definition allows to initialize the driver
* for another peripheral from a given group only after the previously used one
* is uninitialized. Normally, this is not possible, because interrupt handlers
* are implemented in individual drivers.
* This functionality requires a more complicated interrupt handling and driver
* initialization, hence it is not always desirable to use it.
*/
#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0
/* CLOCK */
#define CLOCK_ENABLED 0
#if (CLOCK_ENABLED == 1)
#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#endif
/* GPIOTE */
#define GPIOTE_ENABLED 0
#if (GPIOTE_ENABLED == 1)
#define GPIOTE_CONFIG_USE_SWI_EGU false
#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
#endif
/* TIMER */
#define TIMER0_ENABLED 0
#if (TIMER0_ENABLED == 1)
#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define TIMER0_INSTANCE_INDEX 0
#endif
#define TIMER1_ENABLED 0
#if (TIMER1_ENABLED == 1)
#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
#endif
#define TIMER2_ENABLED 0
#if (TIMER2_ENABLED == 1)
#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
#endif
#define TIMER3_ENABLED 0
#if (TIMER3_ENABLED == 1)
#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
#endif
#define TIMER4_ENABLED 0
#if (TIMER4_ENABLED == 1)
#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
#endif
#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
/* RTC */
#define RTC0_ENABLED 0
#if (RTC0_ENABLED == 1)
#define RTC0_CONFIG_FREQUENCY 32678
#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define RTC0_CONFIG_RELIABLE false
#define RTC0_INSTANCE_INDEX 0
#endif
#define RTC1_ENABLED 0
#if (RTC1_ENABLED == 1)
#define RTC1_CONFIG_FREQUENCY 32768
#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define RTC1_CONFIG_RELIABLE false
#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
#endif
#define RTC2_ENABLED 0
#if (RTC2_ENABLED == 1)
#define RTC2_CONFIG_FREQUENCY 32768
#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define RTC2_CONFIG_RELIABLE false
#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
#endif
#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
#define NRF_MAXIMUM_LATENCY_US 2000
/* RNG */
#define RNG_ENABLED 0
#if (RNG_ENABLED == 1)
#define RNG_CONFIG_ERROR_CORRECTION true
#define RNG_CONFIG_POOL_SIZE 8
#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#endif
/* PWM */
#define PWM0_ENABLED 0
#if (PWM0_ENABLED == 1)
#define PWM0_CONFIG_OUT0_PIN 2
#define PWM0_CONFIG_OUT1_PIN 3
#define PWM0_CONFIG_OUT2_PIN 4
#define PWM0_CONFIG_OUT3_PIN 5
#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
#define PWM0_CONFIG_TOP_VALUE 1000
#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
#define PWM0_INSTANCE_INDEX 0
#endif
#define PWM1_ENABLED 0
#if (PWM1_ENABLED == 1)
#define PWM1_CONFIG_OUT0_PIN 2
#define PWM1_CONFIG_OUT1_PIN 3
#define PWM1_CONFIG_OUT2_PIN 4
#define PWM1_CONFIG_OUT3_PIN 5
#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
#define PWM1_CONFIG_TOP_VALUE 1000
#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
#endif
#define PWM2_ENABLED 0
#if (PWM2_ENABLED == 1)
#define PWM2_CONFIG_OUT0_PIN 2
#define PWM2_CONFIG_OUT1_PIN 3
#define PWM2_CONFIG_OUT2_PIN 4
#define PWM2_CONFIG_OUT3_PIN 5
#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
#define PWM2_CONFIG_TOP_VALUE 1000
#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
#endif
#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
/* SPI */
#define SPI0_ENABLED 0
#if (SPI0_ENABLED == 1)
#define SPI0_USE_EASY_DMA 0
#define SPI0_CONFIG_SCK_PIN 2
#define SPI0_CONFIG_MOSI_PIN 3
#define SPI0_CONFIG_MISO_PIN 4
#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define SPI0_INSTANCE_INDEX 0
#endif
#define SPI1_ENABLED 0
#if (SPI1_ENABLED == 1)
#define SPI1_USE_EASY_DMA 0
#define SPI1_CONFIG_SCK_PIN 2
#define SPI1_CONFIG_MOSI_PIN 3
#define SPI1_CONFIG_MISO_PIN 4
#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
#endif
#define SPI2_ENABLED 0
#if (SPI2_ENABLED == 1)
#define SPI2_USE_EASY_DMA 0
#define SPI2_CONFIG_SCK_PIN 2
#define SPI2_CONFIG_MOSI_PIN 3
#define SPI2_CONFIG_MISO_PIN 4
#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
#endif
#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
/* SPIS */
#define SPIS0_ENABLED 0
#if (SPIS0_ENABLED == 1)
#define SPIS0_CONFIG_SCK_PIN 2
#define SPIS0_CONFIG_MOSI_PIN 3
#define SPIS0_CONFIG_MISO_PIN 4
#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define SPIS0_INSTANCE_INDEX 0
#endif
#define SPIS1_ENABLED 0
#if (SPIS1_ENABLED == 1)
#define SPIS1_CONFIG_SCK_PIN 2
#define SPIS1_CONFIG_MOSI_PIN 3
#define SPIS1_CONFIG_MISO_PIN 4
#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
#endif
#define SPIS2_ENABLED 0
#if (SPIS2_ENABLED == 1)
#define SPIS2_CONFIG_SCK_PIN 2
#define SPIS2_CONFIG_MOSI_PIN 3
#define SPIS2_CONFIG_MISO_PIN 4
#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
#endif
#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
/* UART */
#define UART0_ENABLED 0
#if (UART0_ENABLED == 1)
#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
#define UART0_CONFIG_PSEL_TXD 0
#define UART0_CONFIG_PSEL_RXD 0
#define UART0_CONFIG_PSEL_CTS 0
#define UART0_CONFIG_PSEL_RTS 0
#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#ifdef NRF52
#define UART0_CONFIG_USE_EASY_DMA false
//Compile time flag
#define UART_EASY_DMA_SUPPORT 1
#define UART_LEGACY_SUPPORT 1
#endif //NRF52
#endif
#define TWI0_ENABLED 0
#if (TWI0_ENABLED == 1)
#define TWI0_USE_EASY_DMA 0
#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
#define TWI0_CONFIG_SCL 0
#define TWI0_CONFIG_SDA 1
#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define TWI0_INSTANCE_INDEX 0
#endif
#define TWI1_ENABLED 0
#if (TWI1_ENABLED == 1)
#define TWI1_USE_EASY_DMA 0
#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
#define TWI1_CONFIG_SCL 0
#define TWI1_CONFIG_SDA 1
#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
#endif
#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
/* TWIS */
#define TWIS0_ENABLED 0
#if (TWIS0_ENABLED == 1)
#define TWIS0_CONFIG_ADDR0 0
#define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
#define TWIS0_CONFIG_SCL 0
#define TWIS0_CONFIG_SDA 1
#define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define TWIS0_INSTANCE_INDEX 0
#endif
#define TWIS1_ENABLED 0
#if (TWIS1_ENABLED == 1)
#define TWIS1_CONFIG_ADDR0 0
#define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
#define TWIS1_CONFIG_SCL 0
#define TWIS1_CONFIG_SDA 1
#define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
#endif
#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
/* For more documentation see nrf_drv_twis.h file */
#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
/* For more documentation see nrf_drv_twis.h file */
#define TWIS_NO_SYNC_MODE 0
/* QDEC */
#define QDEC_ENABLED 0
#if (QDEC_ENABLED == 1)
#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
#define QDEC_CONFIG_PIO_A 1
#define QDEC_CONFIG_PIO_B 2
#define QDEC_CONFIG_PIO_LED 3
#define QDEC_CONFIG_LEDPRE 511
#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define QDEC_CONFIG_DBFEN false
#define QDEC_CONFIG_SAMPLE_INTEN false
#endif
/* ADC */
#define ADC_ENABLED 0
#if (ADC_ENABLED == 1)
#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#endif
/* SAADC */
#define SAADC_ENABLED 0
#if (SAADC_ENABLED == 1)
#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#endif
/* PDM */
#define PDM_ENABLED 0
#if (PDM_ENABLED == 1)
#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#endif
/* COMP */
#define COMP_ENABLED 0
#if (COMP_ENABLED == 1)
#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
#endif
/* LPCOMP */
#define LPCOMP_ENABLED 0
#if (LPCOMP_ENABLED == 1)
#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
#endif
/* WDT */
#define WDT_ENABLED 0
#if (WDT_ENABLED == 1)
#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
#define WDT_CONFIG_RELOAD_VALUE 2000
#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
#endif
/* SWI EGU */
#ifdef NRF52
#define EGU_ENABLED 0
#endif
/* I2S */
#define I2S_ENABLED 0
#if (I2S_ENABLED == 1)
#define I2S_CONFIG_SCK_PIN 22
#define I2S_CONFIG_LRCK_PIN 23
#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
#define I2S_CONFIG_SDOUT_PIN 24
#define I2S_CONFIG_SDIN_PIN 25
#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
#endif
#include "nrf_drv_config_validation.h"
#endif // NRF_DRV_CONFIG_H

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_DRV_CONFIG_VALIDATION_H
#define NRF_DRV_CONFIG_VALIDATION_H
#ifdef NRF52
#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
((SPI0_ENABLED + SPIS0_ENABLED + TWI0_ENABLED + TWIS0_ENABLED) > 1)
#error "Peripherals overlap. SPI0, SPIS0, TWI0, TWIS0 - only one of these can be enabled."
#endif
#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
((SPI1_ENABLED + SPIS1_ENABLED + TWI1_ENABLED + TWIS1_ENABLED) > 1)
#error "Peripherals overlap. SPI1, SPIS1, TWI1, TWIS1 - only one of these can be enabled."
#endif
#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
((SPI2_ENABLED + SPIS2_ENABLED) > 1)
#error "Peripherals overlap. SPI2, SPIS2 - only one of these can be enabled."
#endif
#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
((COMP_ENABLED + LPCOMP_ENABLED) > 1)
#error "COMP and LPCOMP cannot be enabled together. Peripherals overlap."
#endif
#else //NRF51
#if (TWIS0_ENABLED + TWIS1_ENABLED) > 0
#error "TWIS not present in nRF51."
#endif
#if SPIS0_ENABLED > 0
#error "SPIS0 instance not present in nRF51."
#endif
#if (SPI2_ENABLED + SPIS2_ENABLED) > 0
#error "SPI2/SPIS2 instance not present in nRF51."
#endif
#if RTC2_ENABLED
#error "RTC2 not present in NRF51."
#endif
#if (TIMER3_ENABLED + TIMER4_ENABLED) > 0
#error "TIMER3 and TIMER4 not present in nRF51."
#endif
#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
((SPI0_ENABLED + TWI0_ENABLED) > 1)
#error "Peripherals overlap. SPI0, TWI0 - only one of these can be enabled."
#endif
#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
((SPI1_ENABLED + SPIS1_ENABLED + TWI1_ENABLED) > 1)
#error "Peripherals overlap. SPI1, SPIS1, TWI1 - only one of these can be enabled."
#endif
#if SAADC_ENABLED > 0
#error "SAADC not present in nRF51."
#endif
#if I2S_ENABLED > 0
#error "I2S not present in nRF51."
#endif
#if COMP_ENABLED > 0
#error "COMP not present in nRF51."
#endif
#endif //NRF51
#endif // NRF_DRV_CONFIG_VALIDATION_H

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stdio.h>
#include "compiler_abstraction.h"
#include "nrf.h"
#include "nrf_delay.h"
/*lint --e{438} "Variable not used" */
void nrf_delay_ms(uint32_t volatile number_of_ms)
{
while(number_of_ms != 0)
{
number_of_ms--;
nrf_delay_us(999);
}
}

242
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#ifndef _NRF_DELAY_H
#define _NRF_DELAY_H
#include "nrf.h"
/**
* @brief Function for delaying execution for number of microseconds.
*
* @note NRF52 has instruction cache and because of that delay is not precise.
*
* @param number_of_ms
*/
/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
#if defined ( __CC_ARM )
static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
{
loop
SUBS R0, R0, #1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
#ifdef NRF52
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
#endif
BNE loop
BX LR
}
#elif defined ( __ICCARM__ )
static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
{
__ASM (
"loop:\n\t"
" SUBS R0, R0, #1\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
#ifdef NRF52
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
#endif
" BNE.n loop\n\t");
}
#elif defined ( _WIN32 ) /*|| defined ( __unix )*/ || defined( __APPLE__ )
__STATIC_INLINE void nrf_delay_us(uint32_t volatile number_of_us);
#ifndef CUSTOM_NRF_DELAY_US
__STATIC_INLINE void nrf_delay_us(uint32_t volatile number_of_us)
{}
#endif
#elif defined ( __GNUC__ )
static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline));
static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
{
register uint32_t delay __ASM ("r0") = number_of_us;
__ASM volatile (
#ifdef NRF51
".syntax unified\n"
#endif
"1:\n"
" SUBS %0, %0, #1\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
#ifdef NRF52
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
#endif
" BNE 1b\n"
#ifdef NRF51
".syntax divided\n"
#endif
: "+r" (delay));
}
#endif
void nrf_delay_ms(uint32_t volatile number_of_ms);
#endif

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @file
* @brief ADC HAL implementation
*/
#include "nrf_adc.h"
#ifndef NRF52
/**
* @brief Function for configuring ADC.
*
* This function powers on ADC and configures it. ADC is in DISABLE state after configuration,
* so it should be enabled before using it.
*
* @param[in] config Requested configuration.
*/
void nrf_adc_configure(nrf_adc_config_t * config)
{
uint32_t config_reg = 0;
config_reg |= ((uint32_t)config->resolution << ADC_CONFIG_RES_Pos) & ADC_CONFIG_RES_Msk;
config_reg |= ((uint32_t)config->scaling << ADC_CONFIG_INPSEL_Pos) & ADC_CONFIG_INPSEL_Msk;
config_reg |= ((uint32_t)config->reference << ADC_CONFIG_REFSEL_Pos) & ADC_CONFIG_REFSEL_Msk;
if (config->reference & ADC_CONFIG_EXTREFSEL_Msk)
{
config_reg |= config->reference & ADC_CONFIG_EXTREFSEL_Msk;
}
/* select input */
nrf_adc_input_select(NRF_ADC_CONFIG_INPUT_DISABLED);
/* set new configuration keeping selected input */
NRF_ADC->CONFIG = config_reg | (NRF_ADC->CONFIG & ADC_CONFIG_PSEL_Msk);
}
/**
* @brief Blocking function for executing single ADC conversion.
*
* This function selects the desired input, starts a single conversion,
* waits for it to finish, and returns the result.
* ADC is left in STOP state, the given input is selected.
* This function does not check if ADC is initialized and powered.
*
* @param[in] input Requested input to be selected.
*
* @return Conversion result
*/
int32_t nrf_adc_convert_single(nrf_adc_config_input_t input)
{
int32_t val;
nrf_adc_input_select(input);
nrf_adc_start();
while (!nrf_adc_conversion_finished())
{
}
nrf_adc_conversion_event_clean();
val = nrf_adc_result_get();
nrf_adc_stop();
return val;
}
#endif

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_ADC_H_
#define NRF_ADC_H_
/**
* @defgroup nrf_adc_hal ADC HAL
* @{
* @ingroup nrf_adc
* @brief @tagAPI51 Hardware access layer for managing the analog-to-digital converter (ADC).
*/
#include <stdbool.h>
#include <stddef.h>
#include "nrf.h"
#ifndef NRF52
/**
* @enum nrf_adc_config_resolution_t
* @brief Resolution of the analog-to-digital converter.
*/
/**
* @brief ADC interrupts.
*/
typedef enum
{
NRF_ADC_INT_END_MASK = ADC_INTENSET_END_Msk, /**< ADC interrupt on END event. */
} nrf_adc_int_mask_t;
typedef enum
{
NRF_ADC_CONFIG_RES_8BIT = ADC_CONFIG_RES_8bit, /**< 8 bit resolution. */
NRF_ADC_CONFIG_RES_9BIT = ADC_CONFIG_RES_9bit, /**< 9 bit resolution. */
NRF_ADC_CONFIG_RES_10BIT = ADC_CONFIG_RES_10bit, /**< 10 bit resolution. */
} nrf_adc_config_resolution_t;
/**
* @enum nrf_adc_config_scaling_t
* @brief Scaling factor of the analog-to-digital conversion.
*/
typedef enum
{
NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE = ADC_CONFIG_INPSEL_AnalogInputNoPrescaling, /**< Full scale input. */
NRF_ADC_CONFIG_SCALING_INPUT_TWO_THIRDS = ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling, /**< 2/3 scale input. */
NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD = ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling, /**< 1/3 scale input. */
NRF_ADC_CONFIG_SCALING_SUPPLY_TWO_THIRDS = ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling, /**< 2/3 of supply. */
NRF_ADC_CONFIG_SCALING_SUPPLY_ONE_THIRD = ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling /**< 1/3 of supply. */
} nrf_adc_config_scaling_t;
/**
* @enum nrf_adc_config_reference_t
* @brief Reference selection of the analog-to-digital converter.
*/
typedef enum
{
NRF_ADC_CONFIG_REF_VBG = ADC_CONFIG_REFSEL_VBG, /**< 1.2 V reference. */
NRF_ADC_CONFIG_REF_SUPPLY_ONE_HALF = ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling, /**< 1/2 of power supply. */
NRF_ADC_CONFIG_REF_SUPPLY_ONE_THIRD = ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling, /**< 1/3 of power supply. */
NRF_ADC_CONFIG_REF_EXT_REF0 = ADC_CONFIG_REFSEL_External |
ADC_CONFIG_EXTREFSEL_AnalogReference0 <<
ADC_CONFIG_EXTREFSEL_Pos, /**< External reference 0. */
NRF_ADC_CONFIG_REF_EXT_REF1 = ADC_CONFIG_REFSEL_External |
ADC_CONFIG_EXTREFSEL_AnalogReference1 << ADC_CONFIG_EXTREFSEL_Pos, /**< External reference 0. */
} nrf_adc_config_reference_t;
/**
* @enum nrf_adc_config_input_t
* @brief Input selection of the analog-to-digital converter.
*/
typedef enum
{
NRF_ADC_CONFIG_INPUT_DISABLED = ADC_CONFIG_PSEL_Disabled, /**< No input selected. */
NRF_ADC_CONFIG_INPUT_0 = ADC_CONFIG_PSEL_AnalogInput0, /**< Input 0. */
NRF_ADC_CONFIG_INPUT_1 = ADC_CONFIG_PSEL_AnalogInput1, /**< Input 1. */
NRF_ADC_CONFIG_INPUT_2 = ADC_CONFIG_PSEL_AnalogInput2, /**< Input 2. */
NRF_ADC_CONFIG_INPUT_3 = ADC_CONFIG_PSEL_AnalogInput3, /**< Input 3. */
NRF_ADC_CONFIG_INPUT_4 = ADC_CONFIG_PSEL_AnalogInput4, /**< Input 4. */
NRF_ADC_CONFIG_INPUT_5 = ADC_CONFIG_PSEL_AnalogInput5, /**< Input 5. */
NRF_ADC_CONFIG_INPUT_6 = ADC_CONFIG_PSEL_AnalogInput6, /**< Input 6. */
NRF_ADC_CONFIG_INPUT_7 = ADC_CONFIG_PSEL_AnalogInput7, /**< Input 7. */
} nrf_adc_config_input_t;
/**
* @enum nrf_adc_task_t
* @brief Analog-to-digital converter tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_ADC_TASK_START = offsetof(NRF_ADC_Type, TASKS_START), /**< ADC start sampling task. */
NRF_ADC_TASK_STOP = offsetof(NRF_ADC_Type, TASKS_STOP) /**< ADC stop sampling task. */
/*lint -restore*/
} nrf_adc_task_t;
/**
* @enum nrf_adc_event_t
* @brief Analog-to-digital converter events.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
/*lint -save -e30*/
NRF_ADC_EVENT_END = offsetof(NRF_ADC_Type, EVENTS_END) /**< End of conversion event. */
/*lint -restore*/
} nrf_adc_event_t;
/**@brief Analog-to-digital converter configuration. */
typedef struct
{
nrf_adc_config_resolution_t resolution; /**< ADC resolution. */
nrf_adc_config_scaling_t scaling; /**< ADC scaling factor. */
nrf_adc_config_reference_t reference; /**< ADC reference. */
} nrf_adc_config_t;
/** Default ADC configuration. */
#define NRF_ADC_CONFIG_DEFAULT { NRF_ADC_CONFIG_RES_10BIT, \
NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD, \
NRF_ADC_CONFIG_REF_VBG }
/**
* @brief Function for configuring ADC.
*
* This function powers on the analog-to-digital converter and configures it.
* After the configuration, the ADC is in DISABLE state and must be
* enabled before using it.
*
* @param[in] config Configuration parameters.
*/
void nrf_adc_configure(nrf_adc_config_t * config);
/**
* @brief Blocking function for executing a single ADC conversion.
*
* This function selects the desired input, starts a single conversion,
* waits for it to finish, and returns the result.
* After the input is selected, the analog-to-digital converter
* is left in STOP state.
* The function does not check if the ADC is initialized and powered.
*
* @param[in] input Input to be selected.
*
* @return Conversion result.
*/
int32_t nrf_adc_convert_single(nrf_adc_config_input_t input);
/**
* @brief Function for selecting ADC input.
*
* This function selects the active input of ADC. Ensure that
* the ADC is powered on and in IDLE state before calling this function.
*
* @param[in] input Input to be selected.
*/
__STATIC_INLINE void nrf_adc_input_select(nrf_adc_config_input_t input)
{
NRF_ADC->CONFIG =
((uint32_t)input << ADC_CONFIG_PSEL_Pos) | (NRF_ADC->CONFIG & ~ADC_CONFIG_PSEL_Msk);
if (input != NRF_ADC_CONFIG_INPUT_DISABLED)
{
NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos;
}
else
{
NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos;
}
}
/**
* @brief Function for retrieving the ADC conversion result.
*
* This function retrieves and returns the last analog-to-digital conversion result.
*
* @return Last conversion result.
*/
__STATIC_INLINE int32_t nrf_adc_result_get(void)
{
return (int32_t)NRF_ADC->RESULT;
}
/**
* @brief Function for checking whether the ADC is busy.
*
* This function checks whether the analog-to-digital converter is busy with a conversion.
*
* @retval true If the ADC is busy.
* @retval false If the ADC is not busy.
*/
__STATIC_INLINE bool nrf_adc_is_busy(void)
{
return ( (NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) == ADC_BUSY_BUSY_Msk);
}
/**
* @brief Function for getting the ADC's enabled interrupts.
*
* @param[in] mask Mask of interrupts to check.
*
* @return State of the interrupts selected by the mask.
*
* @sa nrf_adc_int_enable()
* @sa nrf_adc_int_disable()
*/
__STATIC_INLINE uint32_t nrf_adc_int_get(uint32_t mask)
{
return (NRF_ADC->INTENSET & mask); // when read this register will return the value of INTEN.
}
/**
* @brief Function for starting conversion.
*
* @sa nrf_adc_stop()
*
*/
__STATIC_INLINE void nrf_adc_start(void)
{
NRF_ADC->TASKS_START = 1;
}
/**
* @brief Function for stopping conversion.
*
* If the analog-to-digital converter is in inactive state, power consumption is reduced.
*
* @sa nrf_adc_start()
*
*/
__STATIC_INLINE void nrf_adc_stop(void)
{
NRF_ADC->TASKS_STOP = 1;
}
/**
* @brief Function for checking if the requested ADC conversion has ended.
*
* @retval true If the task has finished.
* @retval false If the task is still running.
*/
__STATIC_INLINE bool nrf_adc_conversion_finished(void)
{
return ((bool)NRF_ADC->EVENTS_END);
}
/**
* @brief Function for clearing the conversion END event.
*/
__STATIC_INLINE void nrf_adc_conversion_event_clean(void)
{
NRF_ADC->EVENTS_END = 0;
}
/**
* @brief Function for getting the address of an ADC task register.
*
* @param[in] adc_task ADC task.
*
* @return Address of the specified ADC task.
*/
__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task);
/**
* @brief Function for getting the address of a specific ADC event register.
*
* @param[in] adc_event ADC event.
*
* @return Address of the specified ADC event.
*/
__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event);
/**
* @brief Function for setting the CONFIG register in ADC.
*
* @param[in] configuration Value to be written to the CONFIG register.
*/
__STATIC_INLINE void nrf_adc_config_set(uint32_t configuration);
/**
* @brief Function for clearing an ADC event.
*
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event);
/**
* @brief Function for checking state of an ADC event.
*
* @param[in] event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] int_mask Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_adc_int_enable_check(nrf_adc_int_mask_t int_mask);
/**
* @brief Function for activating a specific ADC task.
*
* @param[in] task Task to activate.
*/
__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task);
/**
* @brief Function for enabling ADC.
*
*/
__STATIC_INLINE void nrf_adc_enable(void);
/**
* @brief Function for disabling ADC.
*
*/
__STATIC_INLINE void nrf_adc_disable(void);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task)
{
return (uint32_t)((uint8_t *)NRF_ADC + adc_task);
}
__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event)
{
return (uint32_t)((uint8_t *)NRF_ADC + adc_event);
}
__STATIC_INLINE void nrf_adc_config_set(uint32_t configuration)
{
NRF_ADC->CONFIG = configuration;
}
__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event)
{
*((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event);
}
__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask)
{
NRF_ADC->INTENSET = int_mask;
}
__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask)
{
NRF_ADC->INTENCLR = int_mask;
}
__STATIC_INLINE bool nrf_adc_int_enable_check(nrf_adc_int_mask_t int_mask)
{
return (bool)(NRF_ADC->INTENSET & int_mask);
}
__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task)
{
*((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE void nrf_adc_enable(void)
{
NRF_ADC->ENABLE = 1;
}
__STATIC_INLINE void nrf_adc_disable(void)
{
NRF_ADC->ENABLE = 0;
}
#endif
#endif /* NRF52 */
/**
*@}
**/
#endif /* NRF_ADC_H_ */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_CLOCK_H__
#define NRF_CLOCK_H__
#include <stddef.h>
#include <stdbool.h>
#include "nrf.h"
/**
* @defgroup nrf_clock_hal Clock HAL
* @{
* @ingroup nrf_clock
* @brief Hardware access layer for managing the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK).
*/
#define NRF_CLOCK_TASK_TRIGGER (1UL)
#define NRF_CLOCK_EVENT_CLEAR (0UL)
/**
* @brief Low-frequency clock sources.
* @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers.
*/
typedef enum
{
NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */
NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth /**< Internal 32 kHz synthesizer from HFCLK system clock. */
} nrf_clock_lfclk_t;
/**
* @brief High-frequency clock sources.
*/
typedef enum
{
NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_RC, /**< Internal 16 MHz RC oscillator. */
NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */
} nrf_clock_hfclk_t;
/**
* @brief Trigger status of task LFCLKSTART/HFCLKSTART.
* @details Used by LFCLKRUN and HFCLKRUN registers.
*/
typedef enum
{
NRF_CLOCK_START_TASK_NOT_TRIGGERED = CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */
NRF_CLOCK_START_TASK_TRIGGERED = CLOCK_LFCLKRUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */
} nrf_clock_start_task_status_t;
/**
* @brief Crystal frequency selection.
*/
typedef enum
{
#ifdef NRF51
NRF_CLOCK_XTALFREQ_Default = CLOCK_XTALFREQ_XTALFREQ_16MHz, /**< Default. 32 MHz. */
NRF_CLOCK_XTALFREQ_16MHz = CLOCK_XTALFREQ_XTALFREQ_16MHz, /**< 16 MHz crystal. */
NRF_CLOCK_XTALFREQ_32MHz = CLOCK_XTALFREQ_XTALFREQ_32MHz /**< 32 MHz crystal. */
#elif defined NRF52
NRF_CLOCK_XTALFREQ_Default, /**< Default. 64MHz. */
#endif
} nrf_clock_xtalfreq_t;
/**
* @brief Interrupts.
*/
typedef enum
{
NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */
NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */
NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */
NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk /**< Interrupt on CTTO event. */
} nrf_clock_int_mask_t;
/**
* @brief Tasks.
*
* @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running.
* The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/
NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source.*/
NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source.*/
NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source.*/
NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator.*/
NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer.*/
NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer.*/
} nrf_clock_task_t; /*lint -restore */
/**
* @brief Events.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/
NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/
NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed.*/
NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO) /**< Calibration timer time-out.*/
} nrf_clock_event_t; /*lint -restore */
/**
* @brief Function for enabling a specific interrupt.
*
* @param[in] int_mask Interrupt.
*/
__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask);
/**
* @brief Function for disabling a specific interrupt.
*
* @param[in] int_mask Interrupt.
*/
__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask);
/**
* @brief Function for retrieving the state of a specific interrupt.
*
* @param[in] int_mask Interrupt.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask);
/**
* @brief Function for retrieving the address of a specific task.
* @details This function can be used by the PPI module.
*
* @param[in] task Task.
*
* @return Address of the requested task register.
*/
__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task);
/**
* @brief Function for setting a specific task.
*
* @param[in] task Task.
*/
__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task);
/**
* @brief Function for retrieving the address of a specific event.
* @details This function can be used by the PPI module.
*
* @param[in] event Event.
*
* @return Address of the requested event register.
*/
__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event);
/**
* @brief Function for clearing a specific event.
*
* @param[in] event Event.
*/
__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event);
/**
* @brief Function for retrieving the state of a specific event.
*
* @param[in] event Event.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event);
/**
* @brief Function for changing the low-frequency clock source.
* @details This function cannot be called when the low-frequency clock is running.
*
* @param[in] source New low-frequency clock source.
*
*/
__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source);
/**
* @brief Function for retrieving the selected source for the low-frequency clock.
*
* @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the selected source for the low-frequency clock.
* @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the selected source for the low-frequency clock.
* @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the selected source for the low-frequency clock.
*/
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void);
/**
* @brief Function for retrieving the active source of the low-frequency clock.
*
* @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the active source of the low-frequency clock.
* @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the active source of the low-frequency clock.
* @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the active source of the low-frequency clock.
*/
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void);
/**
* @brief Function for retrieving the clock source for the LFCLK clock when the task LKCLKSTART is triggered.
*
* @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is running and generating the LFCLK clock.
* @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is running and generating the LFCLK clock.
* @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is running and generating the LFCLK clock.
*/
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void);
/**
* @brief Function for retrieving the state of the LFCLK clock.
*
* @retval false If the LFCLK clock is not running.
* @retval true If the LFCLK clock is running.
*/
__STATIC_INLINE bool nrf_clock_lf_is_running(void);
/**
* @brief Function for retrieving the trigger status of the task LFCLKSTART.
*
* @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task LFCLKSTART has not been triggered.
* @retval NRF_CLOCK_START_TASK_TRIGGERED If the task LFCLKSTART has been triggered.
*/
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void);
/**
* @brief Function for retrieving the active source of the high-frequency clock.
*
* @retval NRF_CLOCK_HFCLK_LOW_ACCURACY If the internal 16 MHz RC oscillator is the active source of the high-frequency clock.
* @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY If an external 16 MHz/32 MHz crystal oscillator is the active source of the high-frequency clock.
*/
__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void);
/**
* @brief Function for retrieving the state of the HFCLK clock.
*
* @param[in] clk_src Clock source to be checked.
*
* @retval false If the HFCLK clock is not running.
* @retval true If the HFCLK clock is running.
*/
__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src);
/**
* @brief Function for retrieving the trigger status of the task HFCLKSTART.
*
* @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task HFCLKSTART has not been triggered.
* @retval NRF_CLOCK_START_TASK_TRIGGERED If the task HFCLKSTART has been triggered.
*/
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void);
/**
* @brief Function for retrieving the frequency selection of the external crystal.
*
* @retval NRF_CLOCK_XTALFREQ_16MHz If a 16 MHz crystal is used as source for the HFCLK oscillator.
* @retval NRF_CLOCK_XTALFREQ_32MHz If a 32 MHz crystal is used as source for the HFCLK oscillator.
*/
__STATIC_INLINE nrf_clock_xtalfreq_t nrf_clock_xtalfreq_get(void);
/**
* @brief Function for changing the frequency selection of the external crystal.
*
* @param[in] xtalfreq New frequency selection for the external crystal.
*/
__STATIC_INLINE void nrf_clock_xtalfreq_set(nrf_clock_xtalfreq_t xtalfreq);
/**
* @brief Function for changing the calibration timer interval.
*
* @param[in] interval New calibration timer interval in 0.25 s resolution (range: 0.25 seconds to 31.75 seconds).
*/
__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask)
{
NRF_CLOCK->INTENSET = int_mask;
}
__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask)
{
NRF_CLOCK->INTENCLR = int_mask;
}
__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask)
{
return (bool)(NRF_CLOCK->INTENCLR & int_mask);
}
__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task)
{
return ((uint32_t )NRF_CLOCK + task);
}
__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task)
{
*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = NRF_CLOCK_TASK_TRIGGER;
}
__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event)
{
return ((uint32_t)NRF_CLOCK + event);
}
__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event)
{
*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = NRF_CLOCK_EVENT_CLEAR;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event));
(void)dummy;
#endif
}
__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event)
{
return (bool)*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event));
}
__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source)
{
NRF_CLOCK->LFCLKSRC =
(uint32_t)((source << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk);
}
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void)
{
return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRC &
CLOCK_LFCLKSRC_SRC_Msk) >> CLOCK_LFCLKSRC_SRC_Pos);
}
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void)
{
return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSTAT &
CLOCK_LFCLKSTAT_SRC_Msk) >> CLOCK_LFCLKSTAT_SRC_Pos);
}
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void)
{
return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRCCOPY &
CLOCK_LFCLKSRCCOPY_SRC_Msk) >> CLOCK_LFCLKSRCCOPY_SRC_Pos);
}
__STATIC_INLINE bool nrf_clock_lf_is_running(void)
{
return ((NRF_CLOCK->LFCLKSTAT &
CLOCK_LFCLKSTAT_STATE_Msk) >> CLOCK_LFCLKSTAT_STATE_Pos);
}
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void)
{
return (nrf_clock_start_task_status_t)((NRF_CLOCK->LFCLKRUN &
CLOCK_LFCLKRUN_STATUS_Msk) >>
CLOCK_LFCLKRUN_STATUS_Pos);
}
__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void)
{
return (nrf_clock_hfclk_t)((NRF_CLOCK->HFCLKSTAT &
CLOCK_HFCLKSTAT_SRC_Msk) >> CLOCK_HFCLKSTAT_SRC_Pos);
}
__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src)
{
return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) ==
(CLOCK_HFCLKSTAT_STATE_Msk | (clk_src << CLOCK_HFCLKSTAT_SRC_Pos));
}
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void)
{
return (nrf_clock_start_task_status_t)((NRF_CLOCK->HFCLKRUN &
CLOCK_HFCLKRUN_STATUS_Msk) >>
CLOCK_HFCLKRUN_STATUS_Pos);
}
__STATIC_INLINE nrf_clock_xtalfreq_t nrf_clock_xtalfreq_get(void)
{
#ifdef NRF51
return (nrf_clock_xtalfreq_t)((NRF_CLOCK->XTALFREQ &
CLOCK_XTALFREQ_XTALFREQ_Msk) >> CLOCK_XTALFREQ_XTALFREQ_Pos);
#elif defined NRF52
return NRF_CLOCK_XTALFREQ_Default;
#endif
}
__STATIC_INLINE void nrf_clock_xtalfreq_set(nrf_clock_xtalfreq_t xtalfreq)
{
#ifdef NRF51
NRF_CLOCK->XTALFREQ =
(uint32_t)((xtalfreq << CLOCK_XTALFREQ_XTALFREQ_Pos) & CLOCK_XTALFREQ_XTALFREQ_Msk);
#elif defined NRF52
return;
#endif
}
__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval)
{
NRF_CLOCK->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk);
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/**
*@}
**/
#endif // NRF_CLOCK_H__

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @file
* @brief COMP HAL API.
*/
#ifndef NRF_COMP_H_
#define NRF_COMP_H_
/**
* @defgroup nrf_comp_hal COMP HAL
* @{
* @ingroup nrf_comp
* @brief @tagAPI52 Hardware access layer for managing the Comparator (COMP).
*/
#include "nrf.h"
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
/**
* @enum nrf_comp_input_t
* @brief COMP analog pin selection.
*/
typedef enum
{
NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */
NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */
NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */
NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */
NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */
NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */
NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */
NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7 /*!< AIN7 selected as analog input. */
}nrf_comp_input_t;
/**
* @enum nrf_comp_ref_t
* @brief COMP reference selection.
*/
typedef enum
{
NRF_COMP_REF_Int1V2 = COMP_REFSEL_REFSEL_Int1V2, /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V). */
NRF_COMP_REF_Int1V8 = COMP_REFSEL_REFSEL_Int1V8, /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V). */
NRF_COMP_REF_Int2V4 = COMP_REFSEL_REFSEL_Int2V4, /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V). */
NRF_COMP_REF_VDD = COMP_REFSEL_REFSEL_VDD, /*!< VREF = VDD. */
NRF_COMP_REF_ARef = COMP_REFSEL_REFSEL_ARef /*!< VREF = AREF (VDD >= VREF >= AREFMIN). */
}nrf_comp_ref_t;
/**
* @enum nrf_comp_ext_ref_t
* @brief COMP external analog reference selection.
*/
typedef enum
{
NRF_COMP_EXT_REF_0 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference0, /*!< Use AIN0 as external analog reference. */
NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 /*!< Use AIN1 as external analog reference. */
}nrf_comp_ext_ref_t;
/**
* @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP.
*/
typedef struct
{
uint8_t th_down; /*!< THDOWN value. */
uint8_t th_up; /*!< THUP value. */
}nrf_comp_th_t;
/**
* @enum nrf_comp_main_mode_t
* @brief COMP main operation mode.
*/
typedef enum
{
NRF_COMP_MAIN_MODE_SE = COMP_MODE_MAIN_SE, /*!< Single ended mode. */
NRF_COMP_MAIN_MODE_Diff = COMP_MODE_MAIN_Diff /*!< Differential mode. */
}nrf_comp_main_mode_t;
/**
* @enum nrf_comp_sp_mode_t
* @brief COMP speed and power mode.
*/
typedef enum
{
NRF_COMP_SP_MODE_Low = COMP_MODE_SP_Low, /*!< Low power mode. */
NRF_COMP_SP_MODE_Normal = COMP_MODE_SP_Normal, /*!< Normal mode. */
NRF_COMP_SP_MODE_High = COMP_MODE_SP_High /*!< High speed mode. */
}nrf_comp_sp_mode_t;
/**
* @enum nrf_comp_hyst_t
* @brief COMP comparator hysteresis.
*/
typedef enum
{
NRF_COMP_HYST_NoHyst = COMP_HYST_HYST_NoHyst, /*!< Comparator hysteresis disabled. */
NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV /*!< Comparator hysteresis enabled. */
}nrf_comp_hyst_t;
/**
* @brief COMP current source selection on analog input.
*/
typedef enum
{
NRF_COMP_ISOURCE_Off = COMP_ISOURCE_ISOURCE_Off, /*!< Current source disabled. */
NRF_COMP_ISOURCE_Ien2uA5 = COMP_ISOURCE_ISOURCE_Ien2mA5, /*!< Current source enabled (+/- 2.5 uA). */
NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA, /*!< Current source enabled (+/- 5 uA). */
NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA /*!< Current source enabled (+/- 10 uA). */
}nrf_isource_t;
/**
* @enum nrf_comp_task_t
* @brief COMP tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_COMP_TASK_START = offsetof(NRF_COMP_Type, TASKS_START), /*!< COMP start sampling task. */
NRF_COMP_TASK_STOP = offsetof(NRF_COMP_Type, TASKS_STOP), /*!< COMP stop sampling task. */
NRF_COMP_TASK_SAMPLE = offsetof(NRF_COMP_Type, TASKS_SAMPLE) /*!< Sample comparator value. */
/*lint -restore*/
}nrf_comp_task_t;
/**
* @enum nrf_comp_event_t
* @brief COMP events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_COMP_EVENT_READY = offsetof(NRF_COMP_Type, EVENTS_READY), /*!< COMP is ready and output is valid. */
NRF_COMP_EVENT_DOWN = offsetof(NRF_COMP_Type, EVENTS_DOWN), /*!< Input voltage crossed the threshold going down. */
NRF_COMP_EVENT_UP = offsetof(NRF_COMP_Type, EVENTS_UP), /*!< Input voltage crossed the threshold going up. */
NRF_COMP_EVENT_CROSS = offsetof(NRF_COMP_Type, EVENTS_CROSS) /*!< Input voltage crossed the threshold in any direction. */
/*lint -restore*/
}nrf_comp_event_t;
/**
* @brief COMP reference configuration.
*/
typedef struct
{
nrf_comp_ref_t reference; /*!< COMP reference selection. */
nrf_comp_ext_ref_t external; /*!< COMP external analog reference selection. */
}nrf_comp_ref_conf_t;
/**
* @brief Function for enabling the COMP peripheral.
*/
__STATIC_INLINE void nrf_comp_enable(void);
/**
* @brief Function for disabling the COMP peripheral.
*/
__STATIC_INLINE void nrf_comp_disable(void);
/**
* @brief Function for checking if the COMP peripheral is enabled.
*
* @retval true If the COMP peripheral is enabled.
* @retval false If the COMP peripheral is not enabled.
*/
__STATIC_INLINE bool nrf_comp_enable_check(void);
/**
* @brief Function for setting the reference source.
*
* @param[in] reference COMP reference selection.
*/
__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference);
/**
* @brief Function for setting the external analog reference source.
*
* @param[in] ext_ref COMP external analog reference selection.
*/
__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref);
/**
* @brief Function for setting threshold voltages.
*
* @param[in] threshold COMP VDOWN and VUP thresholds.
*/
__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold);
/**
* @brief Function for setting the main mode.
*
* @param[in] main_mode COMP main operation mode.
*/
__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode);
/**
* @brief Function for setting the speed mode.
*
* @param[in] speed_mode COMP speed and power mode.
*/
__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode);
/**
* @brief Function for setting the hysteresis.
*
* @param[in] hyst COMP comparator hysteresis.
*/
__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst);
/**
* @brief Function for setting the current source on the analog input.
*
* @param[in] isource COMP current source selection on analog input.
*/
__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource);
/**
* @brief Function for selecting the active input of the COMP.
*
* @param[in] input Input to be selected.
*/
__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input);
/**
* @brief Function for getting the last COMP compare result.
*
* @return The last compare result. If 0, then VIN+ < VIN-. If 1, then VIN+ > VIN-.
*
* @note If VIN+ == VIN-, the return value depends on the previous result.
*/
__STATIC_INLINE uint32_t nrf_comp_result_get(void);
/**
* @brief Function for enabling interrupts from COMP.
*
* @param[in] comp_int_mask Mask of interrupts to be enabled.
*
* @sa nrf_comp_int_enable_check()
*/
__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask);
/**
* @brief Function for disabling interrupts from COMP.
*
* @param[in] comp_int_mask Mask of interrupts to be disabled.
*
* @sa nrf_comp_int_enable_check()
*/
__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask);
/**
* @brief Function for getting the enabled interrupts of COMP.
*
* @param[in] comp_int_mask Mask of interrupts to be checked.
*
* @retval true If any interrupts of the specified mask are enabled.
*/
__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask);
/**
* @brief Function for getting the address of a specific COMP task register.
*
* @param[in] comp_task COMP task.
*
* @return Address of the specified COMP task.
*/
__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task);
/**
* @brief Function for getting the address of a specific COMP event register.
*
* @param[in] comp_event COMP event.
*
* @return Address of the specified COMP event.
*/
__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event);
/**
* @brief Function for setting COMP shorts.
*
* @param[in] comp_short_mask COMP shorts by mask.
*
*/
__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask);
/**
* @brief Function for clearing COMP shorts by mask.
*
* @param[in] comp_short_mask COMP shorts to be cleared.
*
*/
__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask);
/**
* @brief Function for setting a specific COMP task.
*
* @param[in] comp_task COMP task to be set.
*
*/
__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task);
/**
* @brief Function for clearing a specific COMP event.
*
* @param[in] comp_event COMP event to be cleared.
*
*/
__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event);
/**
* @brief Function for getting the state of a specific COMP event.
*
* @retval true If the specified COMP event is active.
*
*/
__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_comp_enable(void)
{
NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Enabled << COMP_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_comp_disable(void)
{
NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Disabled << COMP_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE bool nrf_comp_enable_check(void)
{
return ((NRF_COMP->ENABLE) & COMP_ENABLE_ENABLE_Enabled);
}
__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference)
{
NRF_COMP->REFSEL = (reference << COMP_REFSEL_REFSEL_Pos);
}
__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref)
{
NRF_COMP->EXTREFSEL = (ext_ref << COMP_EXTREFSEL_EXTREFSEL_Pos);
}
__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold)
{
NRF_COMP->TH =
((threshold.th_down << COMP_TH_THDOWN_Pos) & COMP_TH_THDOWN_Msk) |
((threshold.th_up << COMP_TH_THUP_Pos) & COMP_TH_THUP_Msk);
}
__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode)
{
NRF_COMP->MODE |= (main_mode << COMP_MODE_MAIN_Pos);
}
__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode)
{
NRF_COMP->MODE |= (speed_mode << COMP_MODE_SP_Pos);
}
__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst)
{
NRF_COMP->HYST = (hyst << COMP_HYST_HYST_Pos) & COMP_HYST_HYST_Msk;
}
__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource)
{
NRF_COMP->ISOURCE = (isource << COMP_ISOURCE_ISOURCE_Pos) & COMP_ISOURCE_ISOURCE_Msk;
}
__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input)
{
NRF_COMP->PSEL = ((uint32_t)input << COMP_PSEL_PSEL_Pos);
}
__STATIC_INLINE uint32_t nrf_comp_result_get(void)
{
return (uint32_t)NRF_COMP->RESULT;
}
__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask)
{
NRF_COMP->INTENSET = comp_int_mask;
}
__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask)
{
NRF_COMP->INTENCLR = comp_int_mask;
}
__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask)
{
return (NRF_COMP->INTENSET & comp_int_mask); // when read this register will return the value of INTEN.
}
__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task)
{
return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_task);
}
__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event)
{
return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event);
}
__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask)
{
NRF_COMP->SHORTS |= comp_short_mask;
}
__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask)
{
NRF_COMP->SHORTS &= ~comp_short_mask;
}
__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_task) ) = 1;
}
__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)comp_event) ) = 0;
}
__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event)
{
return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_event));
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/**
*@}
**/
#endif // NRF_COMP_H_

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
* $LastChangedRevision: 25419 $
*/
/**
* @file
* @brief Implementation of AES ECB driver
*/
//lint -e438
#include <stdlib.h>
#include <stdbool.h>
#include <string.h>
#include "nrf.h"
#include "nrf_ecb.h"
static uint8_t ecb_data[48]; ///< ECB data structure for RNG peripheral to access.
static uint8_t* ecb_key; ///< Key: Starts at ecb_data
static uint8_t* ecb_cleartext; ///< Cleartext: Starts at ecb_data + 16 bytes.
static uint8_t* ecb_ciphertext; ///< Ciphertext: Starts at ecb_data + 32 bytes.
bool nrf_ecb_init(void)
{
ecb_key = ecb_data;
ecb_cleartext = ecb_data + 16;
ecb_ciphertext = ecb_data + 32;
NRF_ECB->ECBDATAPTR = (uint32_t)ecb_data;
return true;
}
bool nrf_ecb_crypt(uint8_t * dest_buf, const uint8_t * src_buf)
{
uint32_t counter = 0x1000000;
if(src_buf != ecb_cleartext)
{
memcpy(ecb_cleartext,src_buf,16);
}
NRF_ECB->EVENTS_ENDECB = 0;
NRF_ECB->TASKS_STARTECB = 1;
while(NRF_ECB->EVENTS_ENDECB == 0)
{
counter--;
if(counter == 0)
{
return false;
}
}
NRF_ECB->EVENTS_ENDECB = 0;
if(dest_buf != ecb_ciphertext)
{
memcpy(dest_buf,ecb_ciphertext,16);
}
return true;
}
void nrf_ecb_set_key(const uint8_t * key)
{
memcpy(ecb_key,key,16);
}

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is confidential property of Nordic
* Semiconductor ASA.Terms and conditions of usage are described in detail
* in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
* $LastChangedRevision: 13999 $
*/
/**
* @file
* @brief ECB driver API.
*/
#ifndef NRF_ECB_H__
#define NRF_ECB_H__
/**
* @defgroup nrf_ecb AES ECB encryption
* @{
* @ingroup nrf_drivers
* @brief Driver for the AES Electronic Code Book (ECB) peripheral.
*
* To encrypt and decrypt data, the peripheral must first be powered on
* using @ref nrf_ecb_init. Next, the key must be set using @ref nrf_ecb_set_key.
*/
#include <stdint.h>
/**
* @brief Function for initializing and powering on the ECB peripheral.
*
* This function allocates memory for the ECBDATAPTR.
* @retval true If initialization was successful.
* @retval false If powering on failed.
*/
bool nrf_ecb_init(void);
/**
* @brief Function for encrypting and decrypting 16-byte data using current key.
*
* This function avoids unnecessary copying of data if the parameters point to the
* correct locations in the ECB data structure.
*
* @param dst Result of encryption/decryption. 16 bytes will be written.
* @param src Source with 16-byte data to be encrypted/decrypted.
*
* @retval true If the encryption operation completed.
* @retval false If the encryption operation did not complete.
*/
bool nrf_ecb_crypt(uint8_t * dst, const uint8_t * src);
/**
* @brief Function for setting the key to be used for encryption and decryption.
*
* @param key Pointer to the key. 16 bytes will be read.
*/
void nrf_ecb_set_key(const uint8_t * key);
#endif // NRF_ECB_H__
/** @} */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_EGU_H__
#define NRF_EGU_H__
#ifndef NRF52
#error EGU is not supported on your chip.
#endif
/**
* @defgroup nrf_egu EGU (Event Generator Unit) abstraction
* @{
* @ingroup nrf_drivers
* @brief @tagAPI52 EGU (Event Generator Unit) module functions.
*
*/
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "nrf_assert.h"
#include "nrf.h"
#define NRF_EGU_COUNT 6 /**< Number of EGU instances. */
#define NRF_EGU_CHANNEL_COUNT 16 /**< Number of channels per EGU instance. */
/**
* @enum nrf_egu_task_t
* @brief EGU tasks.
*/
typedef enum
{
/*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_EGU_TASK_TRIGGER0 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]), /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */
NRF_EGU_TASK_TRIGGER1 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]), /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */
NRF_EGU_TASK_TRIGGER2 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]), /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */
NRF_EGU_TASK_TRIGGER3 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[3]), /**< Trigger 3 for triggering the corresponding TRIGGERED[3] event. */
NRF_EGU_TASK_TRIGGER4 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[4]), /**< Trigger 4 for triggering the corresponding TRIGGERED[4] event. */
NRF_EGU_TASK_TRIGGER5 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[5]), /**< Trigger 5 for triggering the corresponding TRIGGERED[5] event. */
NRF_EGU_TASK_TRIGGER6 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[6]), /**< Trigger 6 for triggering the corresponding TRIGGERED[6] event. */
NRF_EGU_TASK_TRIGGER7 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[7]), /**< Trigger 7 for triggering the corresponding TRIGGERED[7] event. */
NRF_EGU_TASK_TRIGGER8 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[8]), /**< Trigger 8 for triggering the corresponding TRIGGERED[8] event. */
NRF_EGU_TASK_TRIGGER9 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[9]), /**< Trigger 9 for triggering the corresponding TRIGGERED[9] event. */
NRF_EGU_TASK_TRIGGER10 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[10]), /**< Trigger 10 for triggering the corresponding TRIGGERED[10] event. */
NRF_EGU_TASK_TRIGGER11 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[11]), /**< Trigger 11 for triggering the corresponding TRIGGERED[11] event. */
NRF_EGU_TASK_TRIGGER12 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[12]), /**< Trigger 12 for triggering the corresponding TRIGGERED[12] event. */
NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */
NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */
NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15]) /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */
/*lint -restore*/
} nrf_egu_task_t;
/**
* @enum nrf_egu_event_t
* @brief EGU events.
*/
typedef enum
{
/*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_EGU_EVENT_TRIGGERED0 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]), /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */
NRF_EGU_EVENT_TRIGGERED1 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]), /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */
NRF_EGU_EVENT_TRIGGERED2 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]), /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */
NRF_EGU_EVENT_TRIGGERED3 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[3]), /**< Event number 3 generated by triggering the corresponding TRIGGER[3] task. */
NRF_EGU_EVENT_TRIGGERED4 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[4]), /**< Event number 4 generated by triggering the corresponding TRIGGER[4] task. */
NRF_EGU_EVENT_TRIGGERED5 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[5]), /**< Event number 5 generated by triggering the corresponding TRIGGER[5] task. */
NRF_EGU_EVENT_TRIGGERED6 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[6]), /**< Event number 6 generated by triggering the corresponding TRIGGER[6] task. */
NRF_EGU_EVENT_TRIGGERED7 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[7]), /**< Event number 7 generated by triggering the corresponding TRIGGER[7] task. */
NRF_EGU_EVENT_TRIGGERED8 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[8]), /**< Event number 8 generated by triggering the corresponding TRIGGER[8] task. */
NRF_EGU_EVENT_TRIGGERED9 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[9]), /**< Event number 9 generated by triggering the corresponding TRIGGER[9] task. */
NRF_EGU_EVENT_TRIGGERED10 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[10]), /**< Event number 10 generated by triggering the corresponding TRIGGER[10] task. */
NRF_EGU_EVENT_TRIGGERED11 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[11]), /**< Event number 11 generated by triggering the corresponding TRIGGER[11] task. */
NRF_EGU_EVENT_TRIGGERED12 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[12]), /**< Event number 12 generated by triggering the corresponding TRIGGER[12] task. */
NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */
NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */
NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15]) /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */
/*lint -restore*/
} nrf_egu_event_t;
/**
* @enum nrf_egu_int_mask_t
* @brief EGU interrupts.
*/
typedef enum
{
NRF_EGU_INT_TRIGGERED0 = EGU_INTENSET_TRIGGERED0_Msk, /**< Interrupt on EVENTS_TRIGGERED[0] event. */
NRF_EGU_INT_TRIGGERED1 = EGU_INTENSET_TRIGGERED1_Msk, /**< Interrupt on EVENTS_TRIGGERED[1] event. */
NRF_EGU_INT_TRIGGERED2 = EGU_INTENSET_TRIGGERED2_Msk, /**< Interrupt on EVENTS_TRIGGERED[2] event. */
NRF_EGU_INT_TRIGGERED3 = EGU_INTENSET_TRIGGERED3_Msk, /**< Interrupt on EVENTS_TRIGGERED[3] event. */
NRF_EGU_INT_TRIGGERED4 = EGU_INTENSET_TRIGGERED4_Msk, /**< Interrupt on EVENTS_TRIGGERED[4] event. */
NRF_EGU_INT_TRIGGERED5 = EGU_INTENSET_TRIGGERED5_Msk, /**< Interrupt on EVENTS_TRIGGERED[5] event. */
NRF_EGU_INT_TRIGGERED6 = EGU_INTENSET_TRIGGERED6_Msk, /**< Interrupt on EVENTS_TRIGGERED[6] event. */
NRF_EGU_INT_TRIGGERED7 = EGU_INTENSET_TRIGGERED7_Msk, /**< Interrupt on EVENTS_TRIGGERED[7] event. */
NRF_EGU_INT_TRIGGERED8 = EGU_INTENSET_TRIGGERED8_Msk, /**< Interrupt on EVENTS_TRIGGERED[8] event. */
NRF_EGU_INT_TRIGGERED9 = EGU_INTENSET_TRIGGERED9_Msk, /**< Interrupt on EVENTS_TRIGGERED[9] event. */
NRF_EGU_INT_TRIGGERED10 = EGU_INTENSET_TRIGGERED10_Msk, /**< Interrupt on EVENTS_TRIGGERED[10] event. */
NRF_EGU_INT_TRIGGERED11 = EGU_INTENSET_TRIGGERED11_Msk, /**< Interrupt on EVENTS_TRIGGERED[11] event. */
NRF_EGU_INT_TRIGGERED12 = EGU_INTENSET_TRIGGERED12_Msk, /**< Interrupt on EVENTS_TRIGGERED[12] event. */
NRF_EGU_INT_TRIGGERED13 = EGU_INTENSET_TRIGGERED13_Msk, /**< Interrupt on EVENTS_TRIGGERED[13] event. */
NRF_EGU_INT_TRIGGERED14 = EGU_INTENSET_TRIGGERED14_Msk, /**< Interrupt on EVENTS_TRIGGERED[14] event. */
NRF_EGU_INT_TRIGGERED15 = EGU_INTENSET_TRIGGERED15_Msk, /**< Interrupt on EVENTS_TRIGGERED[15] event. */
NRF_EGU_INT_ALL = 0xFFFFuL
} nrf_egu_int_mask_t;
/**
* @brief Function for triggering a specific EGU task.
*
* @param NRF_EGUx EGU instance.
* @param egu_task EGU task.
*/
__STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task)
{
*((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task)) = 0x1UL;
}
/**
* @brief Function for returning the address of a specific EGU task register.
*
* @param NRF_EGUx EGU instance.
* @param egu_task EGU task.
*/
__STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx,
nrf_egu_task_t egu_task)
{
return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task);
}
/**
* @brief Function for returning the address of a specific EGU TRIGGER task register.
*
* @param NRF_EGUx EGU instance.
* @param channel Channel number.
*/
__STATIC_INLINE uint32_t * nrf_egu_task_trigger_addres_get(NRF_EGU_Type * NRF_EGUx,
uint8_t channel)
{
ASSERT(channel < NRF_EGU_CHANNEL_COUNT);
return (uint32_t*)&NRF_EGUx->TASKS_TRIGGER[channel];
}
/**
* @brief Function for returning the specific EGU TRIGGER task.
*
* @param channel Channel number.
*/
__STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(uint8_t channel)
{
ASSERT(channel <= NRF_EGU_CHANNEL_COUNT);
return (nrf_egu_task_t)((uint32_t) NRF_EGU_TASK_TRIGGER0 + (channel * sizeof(uint32_t)));
}
/**
* @brief Function for returning the state of a specific EGU event.
*
* @param NRF_EGUx EGU instance.
* @param egu_event EGU event to check.
*/
__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx,
nrf_egu_event_t egu_event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event);
}
/**
* @brief Function for clearing a specific EGU event.
*
* @param NRF_EGUx EGU instance.
* @param egu_event EGU event to clear.
*/
__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx,
nrf_egu_event_t egu_event)
{
*((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event)) = 0x0UL;
}
/**
* @brief Function for returning the address of a specific EGU event register.
*
* @param NRF_EGUx EGU instance.
* @param egu_event EGU event.
*/
__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx,
nrf_egu_event_t egu_event)
{
return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event);
}
/**
* @brief Function for returning the address of a specific EGU TRIGGERED event register.
*
* @param NRF_EGUx EGU instance.
* @param channel Channel number.
*/
__STATIC_INLINE uint32_t * nrf_egu_event_triggered_addres_get(NRF_EGU_Type * NRF_EGUx,
uint8_t channel)
{
ASSERT(channel < NRF_EGU_CHANNEL_COUNT);
return (uint32_t*)&NRF_EGUx->EVENTS_TRIGGERED[channel];
}
/**
* @brief Function for returning the specific EGU TRIGGERED event.
*
* @param channel Channel number.
*/
__STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(uint8_t channel)
{
ASSERT(channel < NRF_EGU_CHANNEL_COUNT);
return (nrf_egu_event_t)((uint32_t) NRF_EGU_EVENT_TRIGGERED0 + (channel * sizeof(uint32_t)));
}
/**
* @brief Function for enabling one or more specific EGU interrupts.
*
* @param NRF_EGUx EGU instance.
* @param egu_int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
{
NRF_EGUx->INTENSET = egu_int_mask;
}
/**
* @brief Function for retrieving the state of one or more EGU interrupts.
*
* @param NRF_EGUx EGU instance.
* @param egu_int_mask Interrupts to check.
*
* @retval true If all of the specified interrupts are enabled.
* @retval false If at least one of the specified interrupts is disabled.
*/
__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
{
return (bool)(NRF_EGUx->INTENSET & egu_int_mask);
}
/**
* @brief Function for disabling one or more specific EGU interrupts.
*
* @param NRF_EGUx EGU instance.
* @param egu_int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
{
NRF_EGUx->INTENCLR = egu_int_mask;
}
/**
* @brief Function for retrieving one or more specific EGU interrupts.
*
* @param channel Channel number.
*
* @returns EGU interrupt mask.
*/
__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(uint8_t channel)
{
ASSERT(channel < NRF_EGU_CHANNEL_COUNT);
return (nrf_egu_int_mask_t)((uint32_t) (EGU_INTENSET_TRIGGERED0_Msk << channel));
}
/** @} */
#endif

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_GPIO_H__
#define NRF_GPIO_H__
#include "nrf.h"
#include <stdbool.h>
/**
* @defgroup nrf_gpio GPIO abstraction
* @{
* @ingroup nrf_drivers
* @brief GPIO pin abstraction and port abstraction for reading and writing byte-wise to GPIO ports.
*
* Here, the GPIO ports are defined as follows:
* - Port 0 -> pin 0-7
* - Port 1 -> pin 8-15
* - Port 2 -> pin 16-23
* - Port 3 -> pin 24-31
*/
#define NUMBER_OF_PINS 32
/**
* @brief Enumerator used for selecting between port 0 - 3.
*/
typedef enum
{
NRF_GPIO_PORT_SELECT_PORT0 = 0, ///< Port 0 (GPIO pin 0-7)
NRF_GPIO_PORT_SELECT_PORT1, ///< Port 1 (GPIO pin 8-15)
NRF_GPIO_PORT_SELECT_PORT2, ///< Port 2 (GPIO pin 16-23)
NRF_GPIO_PORT_SELECT_PORT3, ///< Port 3 (GPIO pin 24-31)
} nrf_gpio_port_select_t;
/**
* @brief Enumerator used for setting the direction of a GPIO port.
*/
typedef enum
{
NRF_GPIO_PORT_DIR_OUTPUT, ///< Output
NRF_GPIO_PORT_DIR_INPUT ///< Input
} nrf_gpio_port_dir_t;
/**
* @brief Pin direction definitions.
*/
typedef enum
{
NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input
NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output
} nrf_gpio_pin_dir_t;
/**
* @brief Connection of input buffer
*/
typedef enum
{
NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer
NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer
} nrf_gpio_pin_input_t;
/**
* @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration
*/
typedef enum
{
NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pullup resistor disabled
NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pulldown resistor enabled
NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pullup resistor enabled
} nrf_gpio_pin_pull_t;
/**
* @brief Enumerator used for selecting output drive mode
*/
typedef enum
{
NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'
NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High drive '0', standard '1'
NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high drive '1'
NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high 'drive '1''
NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'
NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high drive '1'
NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0'. disconnect '1'
NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High drive '0', disconnect '1'
} nrf_gpio_pin_drive_t;
/**
* @brief Enumerator used for selecting the pin to sense high or low level on the pin input.
*/
typedef enum
{
NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level.
NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
} nrf_gpio_pin_sense_t;
/**
* @brief Function for configuring the GPIO pin range as outputs with normal drive strength.
* This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
*
* @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
*
* @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
*
* @note For configuring only one pin as output use @ref nrf_gpio_cfg_output
* Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output.
*/
__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
/**
* @brief Function for configuring the GPIO pin range as inputs with given initial value set, hiding inner details.
* This function can be used to configure pin range as simple input.
*
* @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
*
* @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
*
* @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high)
*
* @note For configuring only one pin as input use @ref nrf_gpio_cfg_input
* Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable
*/
__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config);
/**
* @brief Pin configuration function
*
* The main pin configuration function.
* This function allows to set any aspect in PIN_CNF register.
* @param pin_number Specifies the pin number (allowed values 0-31).
* @param dir Pin direction
* @param input Connect or disconnect input buffer
* @param pull Pull configuration
* @param drive Drive configuration
* @param sense Pin sensing mechanism
*/
__STATIC_INLINE void nrf_gpio_cfg(
uint32_t pin_number,
nrf_gpio_pin_dir_t dir,
nrf_gpio_pin_input_t input,
nrf_gpio_pin_pull_t pull,
nrf_gpio_pin_drive_t drive,
nrf_gpio_pin_sense_t sense);
/**
* @brief Function for configuring the given GPIO pin number as output with given initial value set, hiding inner details.
* This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
*
* @param pin_number specifies the pin number (allowed values 0-31)
*
* @note Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output.
*/
__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
/**
* @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details.
* This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
*
* @param pin_number Specifies the pin number (allowed values 0-30).
* @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high).
*
* @note Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable
*/
__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
/**
* @brief Function for reseting pin configuration to its default state.
*
* @param pin_number Specifies the pin number (allowed values 0-31).
*/
__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
/**
* @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
*
* @param pin_number Specifies the pin number (allowed values 0-31).
*
*/
__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
/**
* @brief Function for disconnecting input for the given GPIO.
*
* @param pin_number Specifies the pin number (allowed values 0-31).
*
*/
__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
/**
* @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details.
* This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
* Sense capability on the pin is configurable, and input is connected to buffer so that the GPIO->IN register is readable.
*
* @param pin_number Specifies the pin number (allowed values 0-30).
* @param pull_config State of the pin pull resistor (no pull, pulled down or pulled high).
* @param sense_config Sense level of the pin (no sense, sense low or sense high).
*/
__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config);
/**
* @brief Function for configuring sense level for the given GPIO.
*
* @param pin_number Specifies the pin number of gpio pin numbers to be configured (allowed values 0-30).
* @param sense_config Sense configuration.
*
*/
__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config);
/**
* @brief Function for setting the direction for a GPIO pin.
*
* @param pin_number specifies the pin number (0-31) for which to
* set the direction.
*
* @param direction specifies the direction
*/
__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
/**
* @brief Function for setting a GPIO pin.
*
* Note that the pin must be configured as an output for this
* function to have any effect.
*
* @param pin_number Specifies the pin number (0-31) to set.
*/
__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
/**
* @brief Function for setting GPIO pins.
*
* Note that the pins must be configured as outputs for this
* function to have any effect.
*
* @param pin_mask Specifies the pins to set.
*/
__STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask);
/**
* @brief Function for clearing a GPIO pin.
*
* Note that the pin must be configured as an output for this
* function to have any effect.
*
* @param pin_number Specifies the pin number (0-31) to clear.
*/
__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
/**
* @brief Function for clearing GPIO pins.
*
* Note that the pins must be configured as outputs for this
* function to have any effect.
*
* @param pin_mask Specifies the pins to clear.
*/
__STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask);
/**
* @brief Function for toggling a GPIO pin.
*
* Note that the pin must be configured as an output for this
* function to have any effect.
*
* @param pin_number Specifies the pin number (0-31) to toggle.
*/
__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
/**
* @brief Function for toggling GPIO pins.
*
* Note that the pins must be configured as outputs for this
* function to have any effect.
*
* @param pin_mask Specifies the pins to toggle.
*/
__STATIC_INLINE void nrf_gpio_pins_toggle(uint32_t pin_mask);
/**
* @brief Function for writing a value to a GPIO pin.
*
* Note that the pin must be configured as an output for this
* function to have any effect.
*
* @param pin_number specifies the pin number (0-31) to
* write.
*
* @param value specifies the value to be written to the pin.
* @arg 0 clears the pin
* @arg >=1 sets the pin.
*/
__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
/**
* @brief Function for reading the input level of a GPIO pin.
*
* Note that the pin must have input connected for the value
* returned from this function to be valid.
*
* @param pin_number specifies the pin number (0-31) to
* read.
*
* @return
* @retval 0 if the pin input level is low.
* @retval 1 if the pin input level is high.
* @retval > 1 should never occur.
*/
__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
/**
* @brief Function for reading the input level of all GPIO pins.
*
* Note that the pin must have input connected for the value
* returned from this function to be valid.
*
* @retval Status of input of all pins
*/
__STATIC_INLINE uint32_t nrf_gpio_pins_read(void);
/**
* @brief Function for reading the sense configuration of a GPIO pin.
*
* @param pin_number specifies the pin number (0-31) to
* read.
*
* @retval Sense configuration
*/
__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
/**
* @brief Generic function for writing a single byte of a 32 bit word at a given
* address.
*
* This function should not be called from outside the nrf_gpio
* abstraction layer.
*
* @param word_address is the address of the word to be written.
*
* @param byte_no is the word byte number (0-3) to be written.
*
* @param value is the value to be written to byte "byte_no" of word
* at address "word_address"
*/
__STATIC_INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value);
/**
* @brief Generic function for reading a single byte of a 32 bit word at a given
* address.
*
* This function should not be called from outside the nrf_gpio
* abstraction layer.
*
* @param word_address is the address of the word to be read.
*
* @param byte_no is the byte number (0-3) of the word to be read.
*
* @return byte "byte_no" of word at address "word_address".
*/
__STATIC_INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no);
/**
* @brief Function for setting the direction of a port.
*
* @param port is the port for which to set the direction.
*
* @param dir direction to be set for this port.
*/
__STATIC_INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir);
/**
* @brief Function for reading a GPIO port.
*
* @param port is the port to read.
*
* @return the input value on this port.
*/
__STATIC_INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port);
/**
* @brief Function for writing to a GPIO port.
*
* @param port is the port to write.
*
* @param value is the value to write to this port.
*
* @sa nrf_gpio_port_dir_set()
*/
__STATIC_INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value);
/**
* @brief Function for setting individual pins on GPIO port.
*
* @param port is the port for which to set the pins.
*
* @param set_mask is a mask specifying which pins to set. A bit
* set to 1 indicates that the corresponding port pin shall be
* set.
*
* @sa nrf_gpio_port_dir_set()
*/
__STATIC_INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask);
/**
* @brief Function for clearing individual pins on GPIO port.
*
* @param port is the port for which to clear the pins.
*
* @param clr_mask is a mask specifying which pins to clear. A bit
* set to 1 indicates that the corresponding port pin shall be
* cleared.
*
* @sa nrf_gpio_port_dir_set()
*/
__STATIC_INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
{
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
for (; pin_range_start <= pin_range_end; pin_range_start++)
{
nrf_gpio_cfg_output(pin_range_start);
}
}
__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config)
{
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
for (; pin_range_start <= pin_range_end; pin_range_start++)
{
nrf_gpio_cfg_input(pin_range_start, pull_config);
}
}
__STATIC_INLINE void nrf_gpio_cfg(
uint32_t pin_number,
nrf_gpio_pin_dir_t dir,
nrf_gpio_pin_input_t input,
nrf_gpio_pin_pull_t pull,
nrf_gpio_pin_drive_t drive,
nrf_gpio_pin_sense_t sense)
{
NRF_GPIO->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
| ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos)
| ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)
| ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
| ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
}
__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
{
nrf_gpio_cfg(
pin_number,
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_NOSENSE);
}
__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
{
nrf_gpio_cfg(
pin_number,
NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_CONNECT,
pull_config,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_NOSENSE);
}
__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
{
nrf_gpio_cfg(
pin_number,
NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_NOSENSE);
}
__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
{
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
NRF_GPIO->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
}
__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
{
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
NRF_GPIO->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
}
__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config)
{
nrf_gpio_cfg(
pin_number,
NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_CONNECT,
pull_config,
NRF_GPIO_PIN_S0S1,
sense_config);
}
__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config)
{
/*lint -e{845} // A zero has been given as right argument to operator '|'" */
//uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
NRF_GPIO->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk;
NRF_GPIO->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos);
}
__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
{
if(direction == NRF_GPIO_PIN_DIR_INPUT)
{
nrf_gpio_cfg(
pin_number,
NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_CONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_NOSENSE);
}
else
{
NRF_GPIO->DIRSET = (1UL << pin_number);
}
}
__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
{
NRF_GPIO->OUTSET = (1UL << pin_number);
}
__STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask)
{
NRF_GPIO->OUTSET = pin_mask;
}
__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
{
NRF_GPIO->OUTCLR = (1UL << pin_number);
}
__STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask)
{
NRF_GPIO->OUTCLR = pin_mask;
}
__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
{
nrf_gpio_pins_toggle(1UL << pin_number);
}
__STATIC_INLINE void nrf_gpio_pins_toggle(uint32_t pin_mask)
{
uint32_t pins_state = NRF_GPIO->OUT;
NRF_GPIO->OUTSET = (~pins_state & pin_mask);
NRF_GPIO->OUTCLR = ( pins_state & pin_mask);
}
__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
{
if (value == 0)
{
nrf_gpio_pin_clear(pin_number);
}
else
{
nrf_gpio_pin_set(pin_number);
}
}
__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
{
return ((NRF_GPIO->IN >> pin_number) & 1UL);
}
__STATIC_INLINE uint32_t nrf_gpio_pins_read(void)
{
return NRF_GPIO->IN;
}
__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
{
return (nrf_gpio_pin_sense_t)((NRF_GPIO->PIN_CNF[pin_number] & GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
}
__STATIC_INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value)
{
*((volatile uint8_t*)(word_address) + byte_no) = value;
}
__STATIC_INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no)
{
return (*((const volatile uint8_t*)(word_address) + byte_no));
}
__STATIC_INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir)
{
if (dir == NRF_GPIO_PORT_DIR_OUTPUT)
{
nrf_gpio_word_byte_write(&NRF_GPIO->DIRSET, port, 0xFF);
}
else
{
nrf_gpio_range_cfg_input(port*8, (port+1)*8-1, NRF_GPIO_PIN_NOPULL);
}
}
__STATIC_INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port)
{
return nrf_gpio_word_byte_read(&NRF_GPIO->IN, port);
}
__STATIC_INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value)
{
nrf_gpio_word_byte_write(&NRF_GPIO->OUT, port, value);
}
__STATIC_INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask)
{
nrf_gpio_word_byte_write(&NRF_GPIO->OUTSET, port, set_mask);
}
__STATIC_INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask)
{
nrf_gpio_word_byte_write(&NRF_GPIO->OUTCLR, port, clr_mask);
}
#endif //SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#endif

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nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpiote.h Normal file
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_GPIOTE_H__
#define NRF_GPIOTE_H__
#include "nrf.h"
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
/**
* @defgroup nrf_gpiote_abs GPIOTE abstraction
* @{
* @ingroup nrf_gpiote
* @brief GPIOTE abstraction for configuration of channels.
*/
#ifdef NRF51
#define NUMBER_OF_GPIO_TE 4
#elif defined(NRF52)
#define NUMBER_OF_GPIO_TE 8
#else
#error "Chip family not specified"
#endif
/**
* @enum nrf_gpiote_polarity_t
* @brief Polarity for the GPIOTE channel.
*/
typedef enum
{
NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high.
NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low.
NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle ///< Toggle.
} nrf_gpiote_polarity_t;
/**
* @enum nrf_gpiote_outinit_t
* @brief Initial output value for the GPIOTE channel.
*/
typedef enum
{
NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high.
NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High ///< High to low.
} nrf_gpiote_outinit_t;
/**
* @brief Tasks.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_GPIOTE_TASKS_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/
NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/
NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/
NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/
#if (NUMBER_OF_GPIO_TE == 8)
NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/
NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/
NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/
NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/
#endif
#ifdef NRF52
NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/
NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/
NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/
NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/
NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/
NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/
NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/
NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/
NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/
NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/
NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/
NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/
NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/
NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/
NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/
NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/
#endif
/*lint -restore*/
} nrf_gpiote_tasks_t;
/**
* @brief Events.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_GPIOTE_EVENTS_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/
NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/
NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/
NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/
#if (NUMBER_OF_GPIO_TE == 8)
NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/
NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/
NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/
NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/
#endif
NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event.*/
/*lint -restore*/
} nrf_gpiote_events_t;
/**
* @enum nrf_gpiote_int_t
* @brief GPIOTE interrupts.
*/
typedef enum
{
NRF_GPIOTE_INT_IN0_MASK = GPIOTE_INTENSET_IN0_Msk, /**< GPIOTE interrupt from IN0. */
NRF_GPIOTE_INT_IN1_MASK = GPIOTE_INTENSET_IN1_Msk, /**< GPIOTE interrupt from IN1. */
NRF_GPIOTE_INT_IN2_MASK = GPIOTE_INTENSET_IN2_Msk, /**< GPIOTE interrupt from IN2. */
NRF_GPIOTE_INT_IN3_MASK = GPIOTE_INTENSET_IN3_Msk, /**< GPIOTE interrupt from IN3. */
#if (NUMBER_OF_GPIO_TE == 8)
NRF_GPIOTE_INT_IN4_MASK = GPIOTE_INTENSET_IN4_Msk, /**< GPIOTE interrupt from IN4. */
NRF_GPIOTE_INT_IN5_MASK = GPIOTE_INTENSET_IN5_Msk, /**< GPIOTE interrupt from IN5. */
NRF_GPIOTE_INT_IN6_MASK = GPIOTE_INTENSET_IN6_Msk, /**< GPIOTE interrupt from IN6. */
NRF_GPIOTE_INT_IN7_MASK = GPIOTE_INTENSET_IN7_Msk, /**< GPIOTE interrupt from IN7. */
#endif
NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */
} nrf_gpiote_int_t;
#if (NUMBER_OF_GPIO_TE == 4)
#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK)
#elif (NUMBER_OF_GPIO_TE == 8)
#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\
NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\
NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK)
#else
#error "Unexpected number of GPIO Tasks and Events"
#endif
/**
* @brief Function for activating a specific GPIOTE task.
*
* @param[in] task Task.
*/
__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task);
/**
* @brief Function for getting the address of a specific GPIOTE task.
*
* @param[in] task Task.
*
* @returns Address.
*/
__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task);
/**
* @brief Function for getting the state of a specific GPIOTE event.
*
* @param[in] event Event.
*/
__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event);
/**
* @brief Function for clearing a specific GPIOTE event.
*
* @param[in] event Event.
*/
__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event);
/**
* @brief Function for getting the address of a specific GPIOTE event.
*
* @param[in] event Event.
*
* @return Address
*/
__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event);
/**@brief Function for enabling interrupts.
*
* @param[in] mask Interrupt mask to be enabled.
*/
__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask);
/**@brief Function for disabling interrupts.
*
* @param[in] mask Interrupt mask to be disabled.
*/
__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask);
/**@brief Function for checking if interrupts are enabled.
*
* @param[in] mask Mask of interrupt flags to check.
*
* @return Mask with enabled interrupts.
*/
__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask);
/**@brief Function for enabling a GPIOTE event.
*
* @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx);
/**@brief Function for disabling a GPIOTE event.
*
* @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx);
/**@brief Function for configuring a GPIOTE event.
*
* @param[in] idx Task-Event index.
* @param[in] pin Pin associated with event.
* @param[in] polarity Transition that should generate an event.
*/
__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin,
nrf_gpiote_polarity_t polarity);
/**@brief Function for getting the pin associated with a GPIOTE event.
*
* @param[in] idx Task-Event index.
*
* @return Pin number.
*/
__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx);
/**@brief Function for getting the polarity associated with a GPIOTE event.
*
* @param[in] idx Task-Event index.
*
* @return Polarity.
*/
__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx);
/**@brief Function for enabling a GPIOTE task.
*
* @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx);
/**@brief Function for disabling a GPIOTE task.
*
* @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx);
/**@brief Function for configuring a GPIOTE task.
* @note Function is not configuring mode field so task is disabled after this function is called.
*
* @param[in] idx Task-Event index.
* @param[in] pin Pin associated with event.
* @param[in] polarity Transition that should generate an event.
* @param[in] init_val Initial value of pin.
*/
__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
nrf_gpiote_polarity_t polarity,
nrf_gpiote_outinit_t init_val);
/**@brief Function for forcing a specific state on the pin connected to GPIOTE.
*
* @param[in] idx Task-Event index.
* @param[in] init_val Pin state.
*/
__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val);
/**@brief Function for resetting a GPIOTE task event configuration to the default state.
*
* @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task)
{
*(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task)
{
return ((uint32_t)NRF_GPIOTE + task);
}
__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event)
{
return (*(uint32_t *)nrf_gpiote_event_addr_get(event) == 0x1UL) ? true : false;
}
__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event)
{
*(uint32_t *)nrf_gpiote_event_addr_get(event) = 0;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_addr_get(event));
(void)dummy;
#endif
}
__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event)
{
return ((uint32_t)NRF_GPIOTE + event);
}
__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask)
{
NRF_GPIOTE->INTENSET = mask;
}
__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask)
{
NRF_GPIOTE->INTENCLR = mask;
}
__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask)
{
return (NRF_GPIOTE->INTENSET & mask);
}
__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx)
{
NRF_GPIOTE->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
}
__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx)
{
NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
}
__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, nrf_gpiote_polarity_t polarity)
{
NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk);
NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) |
((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}
__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx)
{
return ((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_PSEL_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
}
__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx)
{
return (nrf_gpiote_polarity_t)((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos);
}
__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx)
{
uint32_t final_config = NRF_GPIOTE->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task;
/* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
correct state in GPIOTE but not in the OUT register. */
/* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */
NRF_GPIOTE->CONFIG[idx] = final_config | ((31 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk);
__NOP();
__NOP();
__NOP();
NRF_GPIOTE->CONFIG[idx] = final_config;
}
__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx)
{
NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task;
}
__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
nrf_gpiote_polarity_t polarity,
nrf_gpiote_outinit_t init_val)
{
NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PSEL_Msk |
GPIOTE_CONFIG_POLARITY_Msk |
GPIOTE_CONFIG_OUTINIT_Msk);
NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) |
((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}
__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val)
{
NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk)
| ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}
__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx)
{
NRF_GPIOTE->CONFIG[idx] = 0;
}
#endif //SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#endif

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @defgroup nrf_i2s_hal I2S HAL
* @{
* @ingroup nrf_i2s
*
* @brief @tagAPI52 Hardware access layer for managing the Inter-IC Sound (I2S) peripheral.
*/
#ifndef NRF_I2S_H__
#define NRF_I2S_H__
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "nrf.h"
/**
* @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set
* function call to specify that a given I2S signal (SDOUT, SDIN, or MCK)
* shall not be connected to a physical pin.
*/
#define NRF_I2S_PIN_NOT_CONNECTED 0xFFFFFFFF
/**
* @brief I2S tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled.
NRF_I2S_TASK_STOP = offsetof(NRF_I2S_Type, TASKS_STOP) ///< Stops I2S transfer. Also stops the MCK generator.
/*lint -restore*/
} nrf_i2s_task_t;
/**
* @brief I2S events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double-buffers.
NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double-buffers.
NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED) ///< I2S transfer stopped.
/*lint -restore*/
} nrf_i2s_event_t;
/**
* @brief I2S interrupts.
*/
typedef enum
{
NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event.
NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk ///< Interrupt on STOPPED event.
} nrf_i2s_int_mask_t;
/**
* @brief I2S modes of operation.
*/
typedef enum
{
NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode.
NRF_I2S_MODE_SLAVE = I2S_CONFIG_MODE_MODE_Slave ///< Slave mode.
} nrf_i2s_mode_t;
/**
* @brief I2S master clock generator settings.
*/
typedef enum
{
NRF_I2S_MCK_DISABLED = 0, ///< MCK disabled.
// [conversion to 'int' needed to prevent compilers from complaining
// that the provided value (0x80000000UL) is out of range of "int"]
NRF_I2S_MCK_32MDIV2 = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz.
NRF_I2S_MCK_32MDIV3 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3, ///< 32 MHz / 3 = 10.6666667 MHz.
NRF_I2S_MCK_32MDIV4 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4, ///< 32 MHz / 4 = 8.0 MHz.
NRF_I2S_MCK_32MDIV5 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5, ///< 32 MHz / 5 = 6.4 MHz.
NRF_I2S_MCK_32MDIV6 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6, ///< 32 MHz / 6 = 5.3333333 MHz.
NRF_I2S_MCK_32MDIV8 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, ///< 32 MHz / 8 = 4.0 MHz.
NRF_I2S_MCK_32MDIV10 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, ///< 32 MHz / 10 = 3.2 MHz.
NRF_I2S_MCK_32MDIV11 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11, ///< 32 MHz / 11 = 2.9090909 MHz.
NRF_I2S_MCK_32MDIV15 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15, ///< 32 MHz / 15 = 2.1333333 MHz.
NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz.
NRF_I2S_MCK_32MDIV21 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21, ///< 32 MHz / 21 = 1.5238095 MHz.
NRF_I2S_MCK_32MDIV23 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23, ///< 32 MHz / 23 = 1.3913043 MHz.
NRF_I2S_MCK_32MDIV31 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31, ///< 32 MHz / 31 = 1.0322581 MHz.
NRF_I2S_MCK_32MDIV42 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42, ///< 32 MHz / 42 = 0.7619048 MHz.
NRF_I2S_MCK_32MDIV63 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63, ///< 32 MHz / 63 = 0.5079365 MHz.
NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 ///< 32 MHz / 125 = 0.256 MHz.
} nrf_i2s_mck_t;
/**
* @brief I2S MCK/LRCK ratios.
*/
typedef enum
{
NRF_I2S_RATIO_32X = I2S_CONFIG_RATIO_RATIO_32X, ///< LRCK = MCK / 32.
NRF_I2S_RATIO_48X = I2S_CONFIG_RATIO_RATIO_48X, ///< LRCK = MCK / 48.
NRF_I2S_RATIO_64X = I2S_CONFIG_RATIO_RATIO_64X, ///< LRCK = MCK / 64.
NRF_I2S_RATIO_96X = I2S_CONFIG_RATIO_RATIO_96X, ///< LRCK = MCK / 96.
NRF_I2S_RATIO_128X = I2S_CONFIG_RATIO_RATIO_128X, ///< LRCK = MCK / 128.
NRF_I2S_RATIO_192X = I2S_CONFIG_RATIO_RATIO_192X, ///< LRCK = MCK / 192.
NRF_I2S_RATIO_256X = I2S_CONFIG_RATIO_RATIO_256X, ///< LRCK = MCK / 256.
NRF_I2S_RATIO_384X = I2S_CONFIG_RATIO_RATIO_384X, ///< LRCK = MCK / 384.
NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X ///< LRCK = MCK / 512.
} nrf_i2s_ratio_t;
/**
* @brief I2S sample widths.
*/
typedef enum
{
NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit.
NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit ///< 24 bit.
} nrf_i2s_swidth_t;
/**
* @brief I2S alignments of sample within a frame.
*/
typedef enum
{
NRF_I2S_ALIGN_LEFT = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned.
NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned.
} nrf_i2s_align_t;
/**
* @brief I2S frame formats.
*/
typedef enum
{
NRF_I2S_FORMAT_I2S = I2S_CONFIG_FORMAT_FORMAT_I2S, ///< Original I2S format.
NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left- or right-aligned) format.
} nrf_i2s_format_t;
/**
* @brief I2S enabled channels.
*/
typedef enum
{
NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo.
NRF_I2S_CHANNELS_LEFT = I2S_CONFIG_CHANNELS_CHANNELS_Left, ///< Left only.
NRF_I2S_CHANNELS_RIGHT = I2S_CONFIG_CHANNELS_CHANNELS_Right ///< Right only.
} nrf_i2s_channels_t;
/**
* @brief Function for activating a specific I2S task.
*
* @param[in] p_i2s I2S instance.
* @param[in] task Task to activate.
*/
__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s,
nrf_i2s_task_t task);
/**
* @brief Function for getting the address of a specific I2S task register.
*
* @param[in] p_i2s I2S instance.
* @param[in] task Requested task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s,
nrf_i2s_task_t task);
/**
* @brief Function for clearing a specific I2S event.
*
* @param[in] p_i2s I2S instance.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s,
nrf_i2s_event_t event);
/**
* @brief Function for checking the state of a specific I2S event.
*
* @param[in] p_i2s I2S instance.
* @param[in] event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s,
nrf_i2s_event_t event);
/**
* @brief Function for getting the address of a specific I2S event register.
*
* @param[in] p_i2s I2S instance.
* @param[in] event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s,
nrf_i2s_event_t event);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_i2s I2S instance.
* @param[in] mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_i2s I2S instance.
* @param[in] mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_i2s I2S instance.
* @param[in] i2s_int Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s,
nrf_i2s_int_mask_t i2s_int);
/**
* @brief Function for enabling the I2S peripheral.
*
* @param[in] p_i2s I2S instance.
*/
__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s);
/**
* @brief Function for disabling the I2S peripheral.
*
* @param[in] p_i2s I2S instance.
*/
__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s);
/**
* @brief Function for configuring I2S pins.
*
* Usage of the SDOUT, SDIN, and MCK signals is optional.
* If a given signal is not needed, pass the @ref NRF_I2S_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_i2s I2S instance.
* @param[in] sck_pin SCK pin number.
* @param[in] lrck_pin LRCK pin number.
* @param[in] mck_pin MCK pin number.
* @param[in] sdout_pin SDOUT pin number.
* @param[in] sdin_pin SDIN pin number.
*/
__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s,
uint32_t sck_pin,
uint32_t lrck_pin,
uint32_t mck_pin,
uint32_t sdout_pin,
uint32_t sdin_pin);
/**
* @brief Function for setting the I2S peripheral configuration.
*
* @param[in] p_i2s I2S instance.
* @param[in] mode Mode of operation (master or slave).
* @param[in] format I2S frame format.
* @param[in] alignment Alignment of sample within a frame.
* @param[in] sample_width Sample width.
* @param[in] channels Enabled channels.
* @param[in] mck_setup Master clock generator setup.
* @param[in] ratio MCK/LRCK ratio.
*
* @retval true If the configuration has been set successfully.
* @retval false If the requested configuration is not allowed.
*/
__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s,
nrf_i2s_mode_t mode,
nrf_i2s_format_t format,
nrf_i2s_align_t alignment,
nrf_i2s_swidth_t sample_width,
nrf_i2s_channels_t channels,
nrf_i2s_mck_t mck_setup,
nrf_i2s_ratio_t ratio);
/**
* @brief Function for setting up the I2S transfer.
*
* This function sets up the RX and TX buffers and enables reception and/or
* transmission accordingly. If the transfer in a given direction is not
* required, pass NULL instead of the pointer to the corresponding buffer.
*
* @param[in] p_i2s I2S instance.
* @param[in] size Size of the buffers (in 32-bit words).
* @param[in] p_rx_buffer Pointer to the receive buffer.
* Pass NULL to disable reception.
* @param[in] p_tx_buffer Pointer to the transmit buffer.
* Pass NULL to disable transmission.
*/
__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s,
uint16_t size,
uint32_t * p_rx_buffer,
uint32_t const * p_tx_buffer);
/**
* @brief Function for setting the pointer to the receive buffer.
*
* @note The size of the buffer can be set only by calling
* @ref nrf_i2s_transfer_set.
*
* @param[in] p_i2s I2S instance.
* @param[in] p_buffer Pointer to the receive buffer.
*/
__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s,
uint32_t * p_buffer);
/**
* @brief Function for getting the pointer to the receive buffer.
*
* @param[in] p_i2s I2S instance.
*
* @return Pointer to the receive buffer.
*/
__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s);
/**
* @brief Function for setting the pointer to the transmit buffer.
*
* @note The size of the buffer can be set only by calling
* @ref nrf_i2s_transfer_set.
*
* @param[in] p_i2s I2S instance.
* @param[in] p_buffer Pointer to the transmit buffer.
*/
__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s,
uint32_t const * p_buffer);
/**
* @brief Function for getting the pointer to the transmit buffer.
*
* @param[in] p_i2s I2S instance.
*
* @return Pointer to the transmit buffer.
*/
__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s,
nrf_i2s_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s,
nrf_i2s_task_t task)
{
return ((uint32_t)p_i2s + (uint32_t)task);
}
__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s,
nrf_i2s_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s,
nrf_i2s_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event);
}
__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s,
nrf_i2s_event_t event)
{
return ((uint32_t)p_i2s + (uint32_t)event);
}
__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask)
{
p_i2s->INTENSET = mask;
}
__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask)
{
p_i2s->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s,
nrf_i2s_int_mask_t i2s_int)
{
return (bool)(p_i2s->INTENSET & i2s_int);
}
__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s)
{
p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Enabled << I2S_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s)
{
p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Disabled << I2S_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s,
uint32_t sck_pin,
uint32_t lrck_pin,
uint32_t mck_pin,
uint32_t sdout_pin,
uint32_t sdin_pin)
{
p_i2s->PSEL.SCK = sck_pin;
p_i2s->PSEL.LRCK = lrck_pin;
p_i2s->PSEL.MCK = mck_pin;
p_i2s->PSEL.SDOUT = sdout_pin;
p_i2s->PSEL.SDIN = sdin_pin;
}
__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s,
nrf_i2s_mode_t mode,
nrf_i2s_format_t format,
nrf_i2s_align_t alignment,
nrf_i2s_swidth_t sample_width,
nrf_i2s_channels_t channels,
nrf_i2s_mck_t mck_setup,
nrf_i2s_ratio_t ratio)
{
if (mode == NRF_I2S_MODE_MASTER)
{
// The MCK/LRCK ratio shall be a multiple of 2 * sample width.
if (((sample_width == NRF_I2S_SWIDTH_16BIT) &&
(ratio == NRF_I2S_RATIO_48X))
||
((sample_width == NRF_I2S_SWIDTH_24BIT) &&
((ratio == NRF_I2S_RATIO_32X) ||
(ratio == NRF_I2S_RATIO_64X) ||
(ratio == NRF_I2S_RATIO_128X) ||
(ratio == NRF_I2S_RATIO_256X) ||
(ratio == NRF_I2S_RATIO_512X))))
{
return false;
}
}
p_i2s->CONFIG.MODE = mode;
p_i2s->CONFIG.FORMAT = format;
p_i2s->CONFIG.ALIGN = alignment;
p_i2s->CONFIG.SWIDTH = sample_width;
p_i2s->CONFIG.CHANNELS = channels;
p_i2s->CONFIG.RATIO = ratio;
if (mck_setup == NRF_I2S_MCK_DISABLED)
{
p_i2s->CONFIG.MCKEN =
(I2S_CONFIG_MCKEN_MCKEN_Disabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
}
else
{
p_i2s->CONFIG.MCKFREQ = mck_setup;
p_i2s->CONFIG.MCKEN =
(I2S_CONFIG_MCKEN_MCKEN_Enabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
}
return true;
}
__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s,
uint16_t size,
uint32_t * p_buffer_rx,
uint32_t const * p_buffer_tx)
{
p_i2s->RXTXD.MAXCNT = size;
nrf_i2s_rx_buffer_set(p_i2s, p_buffer_rx);
p_i2s->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0;
nrf_i2s_tx_buffer_set(p_i2s, p_buffer_tx);
p_i2s->CONFIG.TXEN = (p_buffer_tx != NULL) ? 1 : 0;
}
__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s,
uint32_t * p_buffer)
{
p_i2s->RXD.PTR = (uint32_t)p_buffer;
}
__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s)
{
return (uint32_t *)(p_i2s->RXD.PTR);
}
__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s,
uint32_t const * p_buffer)
{
p_i2s->TXD.PTR = (uint32_t)p_buffer;
}
__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s)
{
return (uint32_t *)(p_i2s->TXD.PTR);
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_I2S_H__
/** @} */

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @file
* @brief LPCOMP HAL API.
*/
#ifndef NRF_LPCOMP_H_
#define NRF_LPCOMP_H_
/**
* @defgroup nrf_lpcomp_hal LPCOMP HAL
* @{
* @ingroup nrf_lpcomp
* @brief Hardware access layer for managing the Low Power Comparator (LPCOMP).
*/
#include "nrf.h"
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
/**
* @enum nrf_lpcomp_ref_t
* @brief LPCOMP reference selection.
*/
typedef enum
{
#ifdef NRF51
NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling, /**< Use supply with a 1/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling, /**< Use supply with a 2/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling, /**< Use supply with a 3/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling, /**< Use supply with a 4/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling, /**< Use supply with a 5/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling, /**< Use supply with a 6/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling, /**< Use supply with a 7/8 prescaler as reference. */
#elif defined NRF52
NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, /**< Use supply with a 1/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, /**< Use supply with a 2/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, /**< Use supply with a 3/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, /**< Use supply with a 4/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, /**< Use supply with a 5/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, /**< Use supply with a 6/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, /**< Use supply with a 7/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_1_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 1/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_3_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 3/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_5_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 5/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_7_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 7/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_9_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 9/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_11_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 11/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_13_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 13/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_15_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 15/16 prescaler as reference. */
#endif
NRF_LPCOMP_REF_EXT_REF0 = LPCOMP_REFSEL_REFSEL_ARef |
(LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), /**< External reference 0. */
NRF_LPCOMP_CONFIG_REF_EXT_REF1 = LPCOMP_REFSEL_REFSEL_ARef |
(LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 << 16), /**< External reference 1. */
} nrf_lpcomp_ref_t;
/**
* @enum nrf_lpcomp_input_t
* @brief LPCOMP input selection.
*/
typedef enum
{
NRF_LPCOMP_INPUT_0 = LPCOMP_PSEL_PSEL_AnalogInput0, /**< Input 0. */
NRF_LPCOMP_INPUT_1 = LPCOMP_PSEL_PSEL_AnalogInput1, /**< Input 1. */
NRF_LPCOMP_INPUT_2 = LPCOMP_PSEL_PSEL_AnalogInput2, /**< Input 2. */
NRF_LPCOMP_INPUT_3 = LPCOMP_PSEL_PSEL_AnalogInput3, /**< Input 3. */
NRF_LPCOMP_INPUT_4 = LPCOMP_PSEL_PSEL_AnalogInput4, /**< Input 4. */
NRF_LPCOMP_INPUT_5 = LPCOMP_PSEL_PSEL_AnalogInput5, /**< Input 5. */
NRF_LPCOMP_INPUT_6 = LPCOMP_PSEL_PSEL_AnalogInput6, /**< Input 6. */
NRF_LPCOMP_INPUT_7 = LPCOMP_PSEL_PSEL_AnalogInput7 /**< Input 7. */
} nrf_lpcomp_input_t;
/**
* @enum nrf_lpcomp_detect_t
* @brief LPCOMP detection type selection.
*/
typedef enum
{
NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, /**< Generate ANADETEC on crossing, both upwards and downwards crossing. */
NRF_LPCOMP_DETECT_UP = LPCOMP_ANADETECT_ANADETECT_Up, /**< Generate ANADETEC on upwards crossing only. */
NRF_LPCOMP_DETECT_DOWN = LPCOMP_ANADETECT_ANADETECT_Down /**< Generate ANADETEC on downwards crossing only. */
} nrf_lpcomp_detect_t;
/**
* @enum nrf_lpcomp_task_t
* @brief LPCOMP tasks.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_LPCOMP_TASK_START = offsetof(NRF_LPCOMP_Type, TASKS_START), /**< LPCOMP start sampling task. */
NRF_LPCOMP_TASK_STOP = offsetof(NRF_LPCOMP_Type, TASKS_STOP), /**< LPCOMP stop sampling task. */
NRF_LPCOMP_TASK_SAMPLE = offsetof(NRF_LPCOMP_Type, TASKS_SAMPLE) /**< Sample comparator value. */
} nrf_lpcomp_task_t; /*lint -restore*/
/**
* @enum nrf_lpcomp_event_t
* @brief LPCOMP events.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_LPCOMP_EVENT_READY = offsetof(NRF_LPCOMP_Type, EVENTS_READY), /**< LPCOMP is ready and output is valid. */
NRF_LPCOMP_EVENT_DOWN = offsetof(NRF_LPCOMP_Type, EVENTS_DOWN), /**< Input voltage crossed the threshold going down. */
NRF_LPCOMP_EVENT_UP = offsetof(NRF_LPCOMP_Type, EVENTS_UP), /**< Input voltage crossed the threshold going up. */
NRF_LPCOMP_EVENT_CROSS = offsetof(NRF_LPCOMP_Type, EVENTS_CROSS) /**< Input voltage crossed the threshold in any direction. */
} nrf_lpcomp_event_t; /*lint -restore*/
/**
* @enum nrf_lpcomp_short_mask_t
* @brief LPCOMP shorts masks.
*/
typedef enum
{
NRF_LPCOMP_SHORT_CROSS_STOP_MASK = LPCOMP_SHORTS_CROSS_STOP_Msk, /*!< Short between CROSS event and STOP task. */
NRF_LPCOMP_SHORT_UP_STOP_MASK = LPCOMP_SHORTS_UP_STOP_Msk, /*!< Short between UP event and STOP task. */
NRF_LPCOMP_SHORT_DOWN_STOP_MASK = LPCOMP_SHORTS_DOWN_STOP_Msk, /*!< Short between DOWN event and STOP task. */
NRF_LPCOMP_SHORT_READY_STOP_MASK = LPCOMP_SHORTS_READY_STOP_Msk, /*!< Short between READY event and STOP task. */
NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Short between READY event and SAMPLE task. */
} nrf_lpcomp_short_mask_t;
/** @brief LPCOMP configuration. */
typedef struct
{
nrf_lpcomp_ref_t reference; /**< LPCOMP reference. */
nrf_lpcomp_detect_t detection; /**< LPCOMP detection type. */
} nrf_lpcomp_config_t;
/** Default LPCOMP configuration. */
#define NRF_LPCOMP_CONFIG_DEFAULT { NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT, NRF_LPCOMP_DETECT_DOWN }
/**
* @brief Function for configuring LPCOMP.
*
* This function powers on LPCOMP and configures it. LPCOMP is in DISABLE state after configuration,
* so it must be enabled before using it. All shorts are inactive, events are cleared, and LPCOMP is stopped.
*
* @param[in] p_config Configuration.
*/
__STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config)
{
NRF_LPCOMP->TASKS_STOP = 1;
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
NRF_LPCOMP->REFSEL =
(p_config->reference << LPCOMP_REFSEL_REFSEL_Pos) & LPCOMP_REFSEL_REFSEL_Msk;
//If external source is choosen extract analog reference index.
if ((p_config->reference & LPCOMP_REFSEL_REFSEL_ARef)==LPCOMP_REFSEL_REFSEL_ARef)
{
uint32_t extref = p_config->reference >> 16;
NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) & LPCOMP_EXTREFSEL_EXTREFSEL_Msk;
}
NRF_LPCOMP->ANADETECT =
(p_config->detection << LPCOMP_ANADETECT_ANADETECT_Pos) & LPCOMP_ANADETECT_ANADETECT_Msk;
NRF_LPCOMP->SHORTS = 0;
NRF_LPCOMP->INTENCLR = LPCOMP_INTENCLR_CROSS_Msk | LPCOMP_INTENCLR_UP_Msk |
LPCOMP_INTENCLR_DOWN_Msk | LPCOMP_INTENCLR_READY_Msk;
}
/**
* @brief Function for selecting the LPCOMP input.
*
* This function selects the active input of LPCOMP.
*
* @param[in] input Input to be selected.
*/
__STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input)
{
uint32_t lpcomp_enable_state = NRF_LPCOMP->ENABLE;
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
NRF_LPCOMP->PSEL =
((uint32_t)input << LPCOMP_PSEL_PSEL_Pos) | (NRF_LPCOMP->PSEL & ~LPCOMP_PSEL_PSEL_Msk);
NRF_LPCOMP->ENABLE = lpcomp_enable_state;
}
/**
* @brief Function for enabling the Low Power Comparator.
*
* This function enables LPCOMP.
*
*/
__STATIC_INLINE void nrf_lpcomp_enable(void)
{
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos;
NRF_LPCOMP->EVENTS_READY = 0;
NRF_LPCOMP->EVENTS_DOWN = 0;
NRF_LPCOMP->EVENTS_UP = 0;
NRF_LPCOMP->EVENTS_CROSS = 0;
}
/**
* @brief Function for disabling the Low Power Comparator.
*
* This function disables LPCOMP.
*
*/
__STATIC_INLINE void nrf_lpcomp_disable(void)
{
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
}
/**
* @brief Function for getting the last LPCOMP compare result.
*
* @return The last compare result. If 0 then VIN+ < VIN-, if 1 then the opposite.
*/
__STATIC_INLINE uint32_t nrf_lpcomp_result_get(void)
{
return (uint32_t)NRF_LPCOMP->RESULT;
}
/**
* @brief Function for enabling interrupts from LPCOMP.
*
* @param[in] lpcomp_int_mask Mask of interrupts to be enabled.
*
* @sa nrf_lpcomp_int_disable()
* @sa nrf_lpcomp_int_enable_check()
*/
__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t lpcomp_int_mask)
{
NRF_LPCOMP->INTENSET = lpcomp_int_mask;
}
/**
* @brief Function for disabling interrupts from LPCOMP.
*
* @param[in] lpcomp_int_mask Mask of interrupts to be disabled.
*
* @sa nrf_lpcomp_int_enable()
* @sa nrf_lpcomp_int_enable_check()
*/
__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask)
{
NRF_LPCOMP->INTENCLR = lpcomp_int_mask;
}
/**
* @brief Function for getting the enabled interrupts of LPCOMP.
*
* @param[in] lpcomp_int_mask Mask of interrupts to be checked.
*
* @retval true If any of interrupts of the specified mask are enabled.
*
* @sa nrf_lpcomp_int_enable()
* @sa nrf_lpcomp_int_disable()
*/
__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t lpcomp_int_mask)
{
return (NRF_LPCOMP->INTENSET & lpcomp_int_mask); // when read this register will return the value of INTEN.
}
/**
* @brief Function for getting the address of a specific LPCOMP task register.
*
* @param[in] lpcomp_task LPCOMP task.
*
* @return The address of the specified LPCOMP task.
*/
__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t lpcomp_task)
{
return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_task);
}
/**
* @brief Function for getting the address of a specific LPCOMP event register.
*
* @param[in] lpcomp_event LPCOMP event.
*
* @return The address of the specified LPCOMP event.
*/
__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t lpcomp_event)
{
return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event);
}
/**
* @brief Function for setting LPCOMP shorts.
*
* @param[in] lpcomp_short_mask LPCOMP shorts by mask.
*
*/
__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t lpcomp_short_mask)
{
NRF_LPCOMP->SHORTS |= lpcomp_short_mask;
}
/**
* @brief Function for clearing LPCOMP shorts by mask.
*
* @param[in] lpcomp_short_mask LPCOMP shorts to be cleared.
*
*/
__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t lpcomp_short_mask)
{
NRF_LPCOMP->SHORTS &= ~lpcomp_short_mask;
}
/**
* @brief Function for setting a specific LPCOMP task.
*
* @param[in] lpcomp_task LPCOMP task to be set.
*
*/
__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t lpcomp_task)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_task) ) = 1;
}
/**
* @brief Function for clearing a specific LPCOMP event.
*
* @param[in] lpcomp_event LPCOMP event to be cleared.
*
*/
__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t lpcomp_event)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event) ) = 0;
}
/**
* @brief Function for getting the state of a specific LPCOMP event.
*
* @retval true If the specified LPCOMP event is active.
*
*/
__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t lpcomp_event)
{
return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event));
}
/**
*@}
**/
#endif /* NRF_LPCOMP_H_ */

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
* $LastChangedRevision: 17685 $
*/
/**
*@file
*@brief NMVC driver implementation
*/
#include <stdbool.h>
#include "nrf.h"
#include "nrf_nvmc.h"
void nrf_nvmc_page_erase(uint32_t address)
{
// Enable erase.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
// Erase the page
NRF_NVMC->ERASEPAGE = address;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
}
void nrf_nvmc_write_byte(uint32_t address, uint8_t value)
{
uint32_t byte_shift = address & (uint32_t)0x03;
uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in.
uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3)));
value32 = value32 + ((uint32_t)value << (byte_shift << 3));
// Enable write.
NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
*(uint32_t*)address32 = value32;
while(NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
{
}
}
void nrf_nvmc_write_word(uint32_t address, uint32_t value)
{
// Enable write.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
}
*(uint32_t*)address = value;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
}
void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes)
{
uint32_t i;
for(i=0;i<num_bytes;i++)
{
nrf_nvmc_write_byte(address+i,src[i]);
}
}
void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words)
{
uint32_t i;
// Enable write.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
for(i=0;i<num_words;i++)
{
((uint32_t*)address)[i] = src[i];
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
}

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is confidential property of Nordic
* Semiconductor ASA.Terms and conditions of usage are described in detail
* in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
* $LastChangedRevision: 17685 $
*/
/**
* @file
* @brief NMVC driver API.
*/
#ifndef NRF_NVMC_H__
#define NRF_NVMC_H__
#include <stdint.h>
/**
* @defgroup nrf_nvmc Non-volatile memory controller
* @{
* @ingroup nrf_drivers
* @brief Driver for the NVMC peripheral.
*
* This driver allows writing to the non-volatile memory (NVM) regions
* of the chip. In order to write to NVM the controller must be powered
* on and the relevant page must be erased.
*
*/
/**
* @brief Erase a page in flash. This is required before writing to any
* address in the page.
*
* @param address Start address of the page.
*/
void nrf_nvmc_page_erase(uint32_t address);
/**
* @brief Write a single byte to flash.
*
* The function reads the word containing the byte, and then
* rewrites the entire word.
*
* @param address Address to write to.
* @param value Value to write.
*/
void nrf_nvmc_write_byte(uint32_t address , uint8_t value);
/**
* @brief Write a 32-bit word to flash.
* @param address Address to write to.
* @param value Value to write.
*/
void nrf_nvmc_write_word(uint32_t address, uint32_t value);
/**
* @brief Write consecutive bytes to flash.
*
* @param address Address to write to.
* @param src Pointer to data to copy from.
* @param num_bytes Number of bytes in src to write.
*/
void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes);
/**
* @brief Write consecutive words to flash.
*
* @param address Address to write to.
* @param src Pointer to data to copy from.
* @param num_words Number of bytes in src to write.
*/
void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words);
#endif // NRF_NVMC_H__
/** @} */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_PDM_H_
#define NRF_PDM_H_
/**
* @defgroup nrf_pdm_hal PDM HAL
* @{
* @ingroup nrf_pdm
*
* @brief @tagAPI52 Hardware abstraction layer for accessing the pulse density modulation (PDM) peripheral.
*/
#include <stdbool.h>
#include <stddef.h>
#include "nrf.h"
#include "nrf_assert.h"
#define NRF_PDM_GAIN_MINIMUM 0x00
#define NRF_PDM_GAIN_DEFAULT 0x28
#define NRF_PDM_GAIN_MAXIMUM 0x50
typedef uint8_t nrf_pdm_gain_t;
/**
* @brief PDM tasks.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_PDM_TASK_START = offsetof(NRF_PDM_Type, TASKS_START), ///< Starts continuous PDM transfer.
NRF_PDM_TASK_STOP = offsetof(NRF_PDM_Type, TASKS_STOP) ///< Stops PDM transfer.
} nrf_pdm_task_t;
/**
* @brief PDM events.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_PDM_EVENT_STARTED = offsetof(NRF_PDM_Type, EVENTS_STARTED), ///< PDM transfer has started.
NRF_PDM_EVENT_STOPPED = offsetof(NRF_PDM_Type, EVENTS_STOPPED), ///< PDM transfer has finished.
NRF_PDM_EVENT_END = offsetof(NRF_PDM_Type, EVENTS_END) ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM.
} nrf_pdm_event_t;
/**
* @brief PDM interrupt masks.
*/
typedef enum
{
NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
NRF_PDM_INT_END = PDM_INTENSET_END_Msk ///< Interrupt on EVENTS_END event.
} nrf_pdm_int_mask_t;
/**
* @brief PDM clock frequency.
*/
typedef enum
{
NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K, ///< PDM_CLK = 1.000 MHz.
NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default, ///< PDM_CLK = 1.032 MHz.
NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K ///< PDM_CLK = 1.067 MHz.
} nrf_pdm_freq_t;
/**
* @brief PDM operation mode.
*/
typedef enum
{
NRF_PDM_MODE_STEREO = PDM_MODE_OPERATION_Stereo, ///< Sample and store one pair (Left + Right) of 16-bit samples per RAM word.
NRF_PDM_MODE_MONO = PDM_MODE_OPERATION_Mono ///< Sample and store two successive Left samples (16 bit each) per RAM word.
} nrf_pdm_mode_t;
/**
* @brief PDM sampling mode.
*/
typedef enum
{
NRF_PDM_EDGE_LEFTFALLING = PDM_MODE_EDGE_LeftFalling, ///< Left (or mono) is sampled on falling edge of PDM_CLK.
NRF_PDM_EDGE_LEFTRISING = PDM_MODE_EDGE_LeftRising ///< Left (or mono) is sampled on rising edge of PDM_CLK.
} nrf_pdm_edge_t;
/**
* @brief Function for triggering a PDM task.
*
* @param[in] pdm_task PDM task.
*/
__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t pdm_task)
{
*((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_task)) = 0x1UL;
}
/**
* @brief Function for getting the address of a PDM task register.
*
* @param[in] pdm_task PDM task.
*
* @return Address of the specified PDM task.
*/
__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t pdm_task)
{
return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)pdm_task);
}
/**
* @brief Function for getting the state of a PDM event.
*
* @param[in] pdm_event PDM event.
*
* @return State of the specified PDM event.
*/
__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t pdm_event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
}
/**
* @brief Function for clearing a PDM event.
*
* @param[in] pdm_event PDM event.
*/
__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t pdm_event)
{
*((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)) = 0x0UL;
}
/**
* @brief Function for getting the address of a PDM event register.
*
* @param[in] pdm_event PDM event.
*
* @return Address of the specified PDM event.
*/
__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t pdm_event)
{
return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
}
/**
* @brief Function for enabling PDM interrupts.
*
* @param[in] pdm_int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_pdm_int_enable(uint32_t pdm_int_mask)
{
NRF_PDM->INTENSET = pdm_int_mask;
}
/**
* @brief Function for retrieving the state of PDM interrupts.
*
* @param[in] pdm_int_mask Interrupts to check.
*
* @retval true If all specified interrupts are enabled.
* @retval false If at least one of the given interrupts is not enabled.
*/
__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t pdm_int_mask)
{
return (bool)(NRF_PDM->INTENSET & pdm_int_mask);
}
/**
* @brief Function for disabling interrupts.
*
* @param pdm_int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_pdm_int_disable(uint32_t pdm_int_mask)
{
NRF_PDM->INTENCLR = pdm_int_mask;
}
/**
* @brief Function for enabling the PDM peripheral.
*
* The PDM peripheral must be enabled before use.
*/
__STATIC_INLINE void nrf_pdm_enable(void)
{
NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos);
}
/**
* @brief Function for disabling the PDM peripheral.
*/
__STATIC_INLINE void nrf_pdm_disable(void)
{
NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Disabled << PDM_ENABLE_ENABLE_Pos);
}
/**
* @brief Function for checking if the PDM peripheral is enabled.
*
* @retval true If the PDM peripheral is enabled.
* @retval false If the PDM peripheral is not enabled.
*/
__STATIC_INLINE bool nrf_pdm_enable_check(void)
{
return (NRF_PDM->ENABLE == (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos));
}
/**
* @brief Function for setting the PDM operation mode.
*
* @param[in] pdm_mode PDM operation mode.
* @param[in] pdm_edge PDM sampling mode.
*/
__STATIC_INLINE void nrf_pdm_mode_set(nrf_pdm_mode_t pdm_mode, nrf_pdm_edge_t pdm_edge)
{
NRF_PDM->MODE = ((pdm_mode << PDM_MODE_OPERATION_Pos) & PDM_MODE_OPERATION_Msk)
| ((pdm_edge << PDM_MODE_EDGE_Pos) & PDM_MODE_EDGE_Msk);
}
/**
* @brief Function for getting the PDM operation mode.
*
* @param[out] p_pdm_mode PDM operation mode.
* @param[out] p_pdm_edge PDM sampling mode.
*/
__STATIC_INLINE void nrf_pdm_mode_get(nrf_pdm_mode_t * p_pdm_mode, nrf_pdm_edge_t * p_pdm_edge)
{
uint32_t mode = NRF_PDM->MODE;
*p_pdm_mode = (nrf_pdm_mode_t)((mode & PDM_MODE_OPERATION_Msk ) >> PDM_MODE_OPERATION_Pos);
*p_pdm_edge = (nrf_pdm_edge_t)((mode & PDM_MODE_EDGE_Msk ) >> PDM_MODE_EDGE_Pos);
}
/**
* @brief Function for setting the PDM clock frequency.
*
* @param[in] pdm_freq PDM clock frequency.
*/
__STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq)
{
NRF_PDM->PDMCLKCTRL = ((pdm_freq << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
}
/**
* @brief Function for getting the PDM clock frequency.
*/
__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void)
{
return (nrf_pdm_freq_t) ((NRF_PDM->PDMCLKCTRL << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
}
/**
* @brief Function for setting up the PDM pins.
*
* @param[in] psel_clk CLK pin number.
* @param[in] psel_din DIN pin number.
*/
__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din)
{
NRF_PDM->PSEL.CLK = ((psel_clk << PDM_PSEL_CLK_PIN_Pos) & PDM_PSEL_CLK_PIN_Msk)
| ((PDM_PSEL_CLK_CONNECT_Connected << PDM_PSEL_CLK_CONNECT_Pos) & PDM_PSEL_CLK_CONNECT_Msk);
NRF_PDM->PSEL.DIN = ((psel_din << PDM_PSEL_DIN_PIN_Pos) & PDM_PSEL_DIN_PIN_Msk)
| ((PDM_PSEL_DIN_CONNECT_Connected << PDM_PSEL_CLK_CONNECT_Pos) & PDM_PSEL_DIN_CONNECT_Msk);
}
/**
* @brief Function for disconnecting the PDM pins.
*/
__STATIC_INLINE void nrf_pdm_psel_disconnect()
{
NRF_PDM->PSEL.CLK = ((PDM_PSEL_CLK_CONNECT_Disconnected << PDM_PSEL_CLK_CONNECT_Pos)
& PDM_PSEL_CLK_CONNECT_Msk);
NRF_PDM->PSEL.DIN = ((PDM_PSEL_DIN_CONNECT_Disconnected << PDM_PSEL_DIN_CONNECT_Pos)
& PDM_PSEL_DIN_CONNECT_Msk);
}
/**
* @brief Function for setting the PDM gain.
*
* @param[in] gain_l Left channel gain.
* @param[in] gain_r Right channel gain.
*/
__STATIC_INLINE void nrf_pdm_gain_set(nrf_pdm_gain_t gain_l, nrf_pdm_gain_t gain_r)
{
NRF_PDM->GAINL = gain_l;
NRF_PDM->GAINR = gain_r;
}
/**
* @brief Function for getting the PDM gain.
*
* @param[out] p_gain_l Left channel gain.
* @param[out] p_gain_r Right channel gain.
*/
__STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t * p_gain_r)
{
*p_gain_l = NRF_PDM->GAINL;
*p_gain_r = NRF_PDM->GAINR;
}
/**
* @brief Function for setting the PDM sample buffer.
*
* @param[in] p_buffer Pointer to the RAM address where samples should be written with EasyDMA.
* @param[in] num Number of samples to allocate memory for in EasyDMA mode.
*
* The amount of allocated RAM depends on the operation mode.
* - For stereo mode: N 32-bit words.
* - For mono mode: Ceil(N/2) 32-bit words.
*/
__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num)
{
NRF_PDM->SAMPLE.PTR = (uint32_t)p_buffer;
NRF_PDM->SAMPLE.MAXCNT = num;
}
/**
* @brief Function for getting the current PDM sample buffer address.
*
* @return Pointer to the current sample buffer.
*/
__STATIC_INLINE uint32_t * nrf_pdm_buffer_get()
{
return (uint32_t *)NRF_PDM->SAMPLE.PTR;
}
/**
*@}
**/
#endif /* NRF_PDM_H_ */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_PPI_H__
#define NRF_PPI_H__
#include <stddef.h>
#include "nrf.h"
/**
* @defgroup nrf_ppi_hal PPI HAL
* @{
* @ingroup nrf_ppi
* @brief Hardware access layer for setting up Programmable Peripheral Interconnect (PPI) channels.
*/
#define NRF_PPI_TASK_SET (1UL)
/**
* @enum nrf_ppi_channel_t
* @brief PPI channels.
*/
typedef enum
{
NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */
NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */
NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */
NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */
NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */
NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */
NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */
NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */
NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */
NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */
NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */
NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */
NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */
NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
#ifdef NRF52
NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */
NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */
#endif
NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */
NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */
NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */
NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */
NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */
NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */
NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */
NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */
NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */
NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */
NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */
NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */
} nrf_ppi_channel_t;
/**
* @enum nrf_ppi_channel_group_t
* @brief PPI channel groups.
*/
typedef enum
{
NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
#ifdef NRF52
NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
#endif
} nrf_ppi_channel_group_t;
/**
* @enum nrf_ppi_channel_include_t
* @brief Definition of which PPI channels belong to a group.
*/
typedef enum
{
NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */
NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */
} nrf_ppi_channel_include_t;
/**
* @enum nrf_ppi_channel_enable_t
* @brief Definition if a PPI channel is enabled.
*/
typedef enum
{
NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */
NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */
} nrf_ppi_channel_enable_t;
/**
* @enum nrf_ppi_task_t
* @brief PPI tasks.
*/
typedef enum
{
/*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0 */
NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */
NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1 */
NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */
NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2 */
NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */
NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3 */
NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */
#ifdef NRF52
NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4 */
NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */
NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5 */
NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5 */
#endif
/*lint -restore*/
} nrf_ppi_task_t;
/**
* @brief Function for enabling a given PPI channel.
*
* @details This function enables only one channel.
*
* @param[in] channel Channel to enable.
*
* */
__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel)
{
NRF_PPI->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel);
}
/**
* @brief Function for disabling a given PPI channel.
*
* @details This function disables only one channel.
*
* @param[in] channel Channel to disable.
*/
__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel)
{
NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel);
}
/**
* @brief Function for checking if a given PPI channel is enabled.
*
* @details This function checks only one channel.
*
* @param[in] channel Channel to check.
*
* @retval NRF_PPI_CHANNEL_ENABLED If the channel is enabled.
* @retval NRF_PPI_CHANNEL_DISABLED If the channel is not enabled.
*
*/
__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel)
{
if (NRF_PPI->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel)))
{
return NRF_PPI_CHANNEL_ENABLED;
}
else
{
return NRF_PPI_CHANNEL_DISABLED;
}
}
/**
* @brief Function for disabling all PPI channels.
*/
__STATIC_INLINE void nrf_ppi_channel_disable_all(void)
{
NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
}
/**
* @brief Function for disabling multiple PPI channels.
*
* @param[in] mask Channel mask.
*/
__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask)
{
NRF_PPI->CHENCLR = mask;
}
/**
* @brief Function for setting up event and task endpoints for a given PPI channel.
*
* @param[in] eep Event register address.
*
* @param[in] tep Task register address.
*
* @param[in] channel Channel to which the given endpoints are assigned.
*/
__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
uint32_t eep,
uint32_t tep)
{
NRF_PPI->CH[(uint32_t) channel].EEP = eep;
NRF_PPI->CH[(uint32_t) channel].TEP = tep;
}
#ifdef NRF52
/**
* @brief Function for setting up task endpoint for a given PPI fork.
*
* @param[in] fork_tep Task register address.
*
* @param[in] channel Channel to which the given fork endpoint is assigned.
*/
__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
uint32_t fork_tep)
{
NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep;
}
/**
* @brief Function for setting up event and task endpoints for a given PPI channel and fork.
*
* @param[in] eep Event register address.
*
* @param[in] tep Task register address.
*
* @param[in] fork_tep Fork task register address (register value).
*
* @param[in] channel Channel to which the given endpoints are assigned.
*/
__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,
uint32_t eep,
uint32_t tep,
uint32_t fork_tep)
{
nrf_ppi_channel_endpoint_setup(channel, eep, tep);
nrf_ppi_fork_endpoint_setup(channel, fork_tep);
}
#endif
/**
* @brief Function for including a PPI channel in a channel group.
*
* @details This function adds only one channel to the group.
*
* @param[in] channel Channel to be included in the group.
*
* @param[in] channel_group Channel group.
*
*/
__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel,
nrf_ppi_channel_group_t channel_group)
{
NRF_PPI->CHG[(uint32_t) channel_group] =
NRF_PPI->CHG[(uint32_t) channel_group] | (PPI_CHG_CH0_Included << ((uint32_t) channel));
}
/**
* @brief Function for including multiple PPI channels in a channel group.
*
* @details This function adds all specified channels to the group.
*
* @param[in] channel_mask Channels to be included in the group.
*
* @param[in] channel_group Channel group.
*
*/
__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask,
nrf_ppi_channel_group_t channel_group)
{
NRF_PPI->CHG[(uint32_t) channel_group] =
NRF_PPI->CHG[(uint32_t) channel_group] | (channel_mask);
}
/**
* @brief Function for removing a PPI channel from a channel group.
*
* @details This function removes only one channel from the group.
*
* @param[in] channel Channel to be removed from the group.
*
* @param[in] channel_group Channel group.
*/
__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel,
nrf_ppi_channel_group_t channel_group)
{
NRF_PPI->CHG[(uint32_t) channel_group] =
NRF_PPI->CHG[(uint32_t) channel_group] & ~(PPI_CHG_CH0_Included << ((uint32_t) channel));
}
/**
* @brief Function for removing multiple PPI channels from a channel group.
*
* @details This function removes all specified channels from the group.
*
* @param[in] channel_mask Channels to be removed from the group.
*
* @param[in] channel_group Channel group.
*/
__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask,
nrf_ppi_channel_group_t channel_group)
{
NRF_PPI->CHG[(uint32_t) channel_group] =
NRF_PPI->CHG[(uint32_t) channel_group] & ~(channel_mask);
}
/**
* @brief Function for removing all PPI channels from a channel group.
*
* @param[in] group Channel group.
*
*/
__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group)
{
NRF_PPI->CHG[(uint32_t) group] = 0;
}
/**
* @brief Function for enabling a channel group.
*
* @param[in] group Channel group.
*
*/
__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group)
{
NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET;
}
/**
* @brief Function for disabling a channel group.
*
* @param[in] group Channel group.
*
*/
__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group)
{
NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET;
}
/**
* @brief Function for setting a PPI task.
*
* @param[in] ppi_task PPI task to set.
*/
__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task)
{
*((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET;
}
/**
* @brief Function for returning the address of a specific PPI task register.
*
* @param[in] ppi_task PPI task.
*/
__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task)
{
return (uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task);
}
/**
* @brief Function for returning the PPI enable task address of a specific group.
*
* @param[in] group PPI group.
*/
__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group)
{
return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].EN;
}
/**
* @brief Function for returning the PPI disable task address of a specific group.
*
* @param[in] group PPI group.
*/
__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group)
{
return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS;
}
/**
*@}
**/
/*lint --flb "Leave library region" */
#endif // NRF_PPI_H__

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @defgroup nrf_pwm_hal PWM HAL
* @{
* @ingroup nrf_pwm
*
* @brief @tagAPI52 Hardware access layer for managing the Pulse Width Modulation (PWM)
* peripheral.
*/
#ifndef NRF_PWM_H__
#define NRF_PWM_H__
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "nrf.h"
#include "nrf_assert.h"
/**
* @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
* function call to specify that a given output channel shall not be
* connected to a physical pin.
*/
#define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
/**
* @brief Number of channels in each PWM instance.
*/
#define NRF_PWM_CHANNEL_COUNT 4
/**
* @brief PWM tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
/*lint -restore*/
} nrf_pwm_task_t;
/**
* @brief PWM events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the requested number of times.
/*lint -restore*/
} nrf_pwm_event_t;
/**
* @brief PWM interrupts.
*/
typedef enum
{
NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event.
NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event.
NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event.
NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event.
NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
} nrf_pwm_int_mask_t;
/**
* @brief PWM shortcuts.
*/
typedef enum
{
NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task.
NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
} nrf_pwm_short_mask_t;
/**
* @brief PWM modes of operation.
*/
typedef enum
{
NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
} nrf_pwm_mode_t;
/**
* @brief PWM base clock frequencies.
*/
typedef enum
{
NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz.
NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz.
NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz.
NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
} nrf_pwm_clk_t;
/**
* @brief PWM decoder load modes.
*
* The selected mode determines how the sequence data is read from RAM and
* spread to the compare registers.
*/
typedef enum
{
NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3).
NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
} nrf_pwm_dec_load_t;
/**
* @brief PWM decoder next step modes.
*
* The selected mode determines when the next value from the active sequence
* is loaded.
*/
typedef enum
{
NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
} nrf_pwm_dec_step_t;
/**
* @brief Type used for defining duty cycle values for a sequence
* loaded in @ref NRF_PWM_LOAD_COMMON mode.
*/
typedef uint16_t nrf_pwm_values_common_t;
/**
* @brief Structure for defining duty cycle values for a sequence
* loaded in @ref NRF_PWM_LOAD_GROUPED mode.
*/
typedef struct {
uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
} nrf_pwm_values_grouped_t;
/**
* @brief Structure for defining duty cycle values for a sequence
* loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
*/
typedef struct
{
uint16_t channel_0; ///< Duty cycle value for channel 0.
uint16_t channel_1; ///< Duty cycle value for channel 1.
uint16_t channel_2; ///< Duty cycle value for channel 2.
uint16_t channel_3; ///< Duty cycle value for channel 3.
} nrf_pwm_values_individual_t;
/**
* @brief Structure for defining duty cycle values for a sequence
* loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
*/
typedef struct {
uint16_t channel_0; ///< Duty cycle value for channel 0.
uint16_t channel_1; ///< Duty cycle value for channel 1.
uint16_t channel_2; ///< Duty cycle value for channel 2.
uint16_t counter_top; ///< Top value for the pulse generator counter.
} nrf_pwm_values_wave_form_t;
/**
* @brief Union grouping pointers to arrays of duty cycle values applicable to
* various loading modes.
*/
typedef union {
nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
uint16_t const * p_raw; ///< Pointer providing raw access to the values.
} nrf_pwm_values_t;
/**
* @brief Structure for defining a sequence of PWM duty cycles.
*
* When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
* provided duty cycle values are not copied. The @p values pointer is stored
* in the peripheral's internal register, and the values are loaded from RAM
* during the sequence playback. Therefore, you must ensure that the values
* do not change before and during the sequence playback (for example,
* the values cannot be placed in a local variable that is allocated on stack).
* If the sequence is played in a loop and the values should be updated
* before the next iteration, it is safe to modify them when the corresponding
* event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
* or @ref NRF_PWM_EVENT_SEQEND1, respectively).
*
* @note The @p repeats and @p end_delay values (which are written to the
* SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
* respectively) are ignored at the end of a complex sequence
* playback, indicated by the LOOPSDONE event.
* See the @linkProductSpecification52 for more information.
*/
typedef struct
{
nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
/**< This field is defined as an union of pointers
* to provide a convenient way to define duty
* cycle values in various loading modes
* (see @ref nrf_pwm_dec_load_t).
* In each value, the most significant bit (15)
* determines the polarity of the output and the
* others (14-0) compose the 15-bit value to be
* compared with the pulse generator counter. */
uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
uint32_t repeats; ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
} nrf_pwm_sequence_t;
/**
* @brief Helper macro for calculating the number of 16-bit values in specified
* array of duty cycle values.
*/
#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array)/sizeof(uint16_t))
/**
* @brief Function for activating a specific PWM task.
*
* @param[in] p_pwm PWM instance.
* @param[in] task Task to activate.
*/
__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_pwm,
nrf_pwm_task_t task);
/**
* @brief Function for getting the address of a specific PWM task register.
*
* @param[in] p_pwm PWM instance.
* @param[in] task Requested task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_pwm,
nrf_pwm_task_t task);
/**
* @brief Function for clearing a specific PWM event.
*
* @param[in] p_pwm PWM instance.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_pwm,
nrf_pwm_event_t event);
/**
* @brief Function for checking the state of a specific PWM event.
*
* @param[in] p_pwm PWM instance.
* @param[in] event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_pwm,
nrf_pwm_event_t event);
/**
* @brief Function for getting the address of a specific PWM event register.
*
* @param[in] p_pwm PWM instance.
* @param[in] event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_pwm,
nrf_pwm_event_t event);
/**
* @brief Function for enabling specified shortcuts.
*
* @param[in] p_pwm PWM instance.
* @param[in] pwm_shorts_mask Shortcuts to enable.
*/
__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_pwm,
uint32_t pwm_shorts_mask);
/**
* @brief Function for disabling specified shortcuts.
*
* @param[in] p_pwm PWM instance.
* @param[in] pwm_shorts_mask Shortcuts to disable.
*/
__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_pwm,
uint32_t pwm_shorts_mask);
/**
* @brief Function for setting the configuration of PWM shortcuts.
*
* @param[in] p_pwm PWM instance.
* @param[in] pwm_shorts_mask Shortcuts configuration to set.
*/
__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_pwm,
uint32_t pwm_shorts_mask);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_pwm PWM instance.
* @param[in] pwm_int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_pwm,
uint32_t pwm_int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_pwm PWM instance.
* @param[in] pwm_int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_pwm,
uint32_t pwm_int_mask);
/**
* @brief Function for setting the configuration of PWM interrupts.
*
* @param[in] p_pwm PWM instance.
* @param[in] pwm_int_mask Interrupts configuration to set.
*/
__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_pwm,
uint32_t pwm_int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_pwm PWM instance.
* @param[in] pwm_int Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_pwm,
nrf_pwm_int_mask_t pwm_int);
/**
* @brief Function for enabling the PWM peripheral.
*
* @param[in] p_pwm PWM instance.
*/
__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_pwm);
/**
* @brief Function for disabling the PWM peripheral.
*
* @param[in] p_pwm PWM instance.
*/
__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_pwm);
/**
* @brief Function for assigning pins to PWM output channels.
*
* Usage of all PWM output channels is optional. If a given channel is not
* needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
* number.
*
* @param[in] p_pwm PWM instance.
* @param[in] out_pins Array with pin numbers for individual PWM output channels.
*/
__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_pwm,
uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
/**
* @brief Function for configuring the PWM peripheral.
*
* @param[in] p_pwm PWM instance.
* @param[in] base_clock Base clock frequency.
* @param[in] mode Operating mode of the pulse generator counter.
* @param[in] top_value Value up to which the pulse generator counter counts.
*/
__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_pwm,
nrf_pwm_clk_t base_clock,
nrf_pwm_mode_t mode,
uint16_t top_value);
/**
* @brief Function for defining a sequence of PWM duty cycles.
*
* @param[in] p_pwm PWM instance.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] p_seq Pointer to the sequence definition.
*/
__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
nrf_pwm_sequence_t const * p_seq);
/**
* @brief Function for modifying the pointer to the duty cycle values
* in the specified sequence.
*
* @param[in] p_pwm PWM instance.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] p_values Pointer to an array with duty cycle values.
*/
__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
uint16_t const * p_values);
/**
* @brief Function for modifying the total number of duty cycle values
* in the specified sequence.
*
* @param[in] p_pwm PWM instance.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] length Number of duty cycle values.
*/
__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
uint16_t length);
/**
* @brief Function for modifying the additional number of PWM periods spent
* on each duty cycle value in the specified sequence.
*
* @param[in] p_pwm PWM instance.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] refresh Number of additional PWM periods for each duty cycle value.
*/
__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
uint32_t refresh);
/**
* @brief Function for modifying the additional time added after the sequence
* is played.
*
* @param[in] p_pwm PWM instance.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] end_delay Number of PWM periods added at the end of the sequence.
*/
__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
uint32_t end_delay);
/**
* @brief Function for setting the mode of loading sequence data from RAM
* and advancing the sequence.
*
* @param[in] p_pwm PWM instance.
* @param[in] dec_load Mode of loading sequence data from RAM.
* @param[in] dec_step Mode of advancing the active sequence.
*/
__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_pwm,
nrf_pwm_dec_load_t dec_load,
nrf_pwm_dec_step_t dec_step);
/**
* @brief Function for setting the number of times the sequence playback
* should be performed.
*
* This function applies to two-sequence playback (concatenated sequence 0 and 1).
* A single sequence can be played back only once.
*
* @param[in] p_pwm PWM instance.
* @param[in] loop_count Number of times to perform the sequence playback.
*/
__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_pwm,
uint16_t loop_count);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_pwm,
nrf_pwm_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_pwm,
nrf_pwm_task_t task)
{
return ((uint32_t)p_pwm + (uint32_t)task);
}
__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_pwm,
nrf_pwm_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_pwm,
nrf_pwm_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)event);
}
__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_pwm,
nrf_pwm_event_t event)
{
return ((uint32_t)p_pwm + (uint32_t)event);
}
__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_pwm,
uint32_t pwm_shorts_mask)
{
p_pwm->SHORTS |= pwm_shorts_mask;
}
__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_pwm,
uint32_t pwm_shorts_mask)
{
p_pwm->SHORTS &= ~(pwm_shorts_mask);
}
__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_pwm,
uint32_t pwm_shorts_mask)
{
p_pwm->SHORTS = pwm_shorts_mask;
}
__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_pwm,
uint32_t pwm_int_mask)
{
p_pwm->INTENSET = pwm_int_mask;
}
__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_pwm,
uint32_t pwm_int_mask)
{
p_pwm->INTENCLR = pwm_int_mask;
}
__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_pwm,
uint32_t pwm_int_mask)
{
p_pwm->INTEN = pwm_int_mask;
}
__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_pwm,
nrf_pwm_int_mask_t pwm_int)
{
return (bool)(p_pwm->INTENSET & pwm_int);
}
__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_pwm)
{
p_pwm->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_pwm)
{
p_pwm->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_pwm,
uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
{
uint8_t i;
for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
{
p_pwm->PSEL.OUT[i] = out_pins[i];
}
}
__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_pwm,
nrf_pwm_clk_t base_clock,
nrf_pwm_mode_t mode,
uint16_t top_value)
{
ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
p_pwm->PRESCALER = base_clock;
p_pwm->MODE = mode;
p_pwm->COUNTERTOP = top_value;
}
__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
nrf_pwm_sequence_t const * p_seq)
{
ASSERT(p_seq != NULL);
nrf_pwm_seq_ptr_set( p_pwm, seq_id, p_seq->values.p_raw);
nrf_pwm_seq_cnt_set( p_pwm, seq_id, p_seq->length);
nrf_pwm_seq_refresh_set( p_pwm, seq_id, p_seq->repeats);
nrf_pwm_seq_end_delay_set(p_pwm, seq_id, p_seq->end_delay);
}
__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
uint16_t const * p_values)
{
ASSERT(seq_id <= 1);
ASSERT(p_values != NULL);
p_pwm->SEQ[seq_id].PTR = (uint32_t)p_values;
}
__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
uint16_t length)
{
ASSERT(seq_id <= 1);
ASSERT(length != 0);
ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
p_pwm->SEQ[seq_id].CNT = length;
}
__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
uint32_t refresh)
{
ASSERT(seq_id <= 1);
ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
p_pwm->SEQ[seq_id].REFRESH = refresh;
}
__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_pwm,
uint8_t seq_id,
uint32_t end_delay)
{
ASSERT(seq_id <= 1);
ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
p_pwm->SEQ[seq_id].ENDDELAY = end_delay;
}
__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_pwm,
nrf_pwm_dec_load_t dec_load,
nrf_pwm_dec_step_t dec_step)
{
p_pwm->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
}
__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_pwm,
uint16_t loop_count)
{
p_pwm->LOOP = loop_count;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_PWM_H__
/** @} */

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_QDEC_H__
#define NRF_QDEC_H__
#include <stddef.h>
#include "nrf_error.h"
#include "nrf.h"
/*lint ++flb "Enter library region" */
/**
* @defgroup nrf_qdec_hal QDEC HAL
* @{
* @ingroup nrf_qdec
* @brief Hardware access layer for accessing the quadrature decoder (QDEC) peripheral.
*/
/**
* @enum nrf_qdec_task_t
* @brief QDEC tasks.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_QDEC_TASK_START = offsetof(NRF_QDEC_Type, TASKS_START), /**< Starting the quadrature decoder. */
NRF_QDEC_TASK_STOP = offsetof(NRF_QDEC_Type, TASKS_STOP), /**< Stopping the quadrature decoder. */
NRF_QDEC_TASK_READCLRACC = offsetof(NRF_QDEC_Type, TASKS_READCLRACC) /**< Reading and clearing ACC and ACCDBL registers. */
} nrf_qdec_task_t;
/**
* @enum nrf_qdec_event_t
* @brief QDEC events.
*/
typedef enum
{
NRF_QDEC_EVENT_SAMPLERDY = offsetof(NRF_QDEC_Type, EVENTS_SAMPLERDY), /**< Event generated for every new sample. */
NRF_QDEC_EVENT_REPORTRDY = offsetof(NRF_QDEC_Type, EVENTS_REPORTRDY), /**< Event generated for every new report. */
NRF_QDEC_EVENT_ACCOF = offsetof(NRF_QDEC_Type, EVENTS_ACCOF) /**< Event generated for every accumulator overflow. */
} nrf_qdec_event_t; /*lint -restore */
/**
* @enum nrf_qdec_short_mask_t
* @brief QDEC shortcuts.
*/
typedef enum
{
NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK = QDEC_SHORTS_REPORTRDY_READCLRACC_Msk, /**< Shortcut between REPORTRDY event and READCLRACC task. */
NRF_QDEC_SHORT_SAMPLERDY_STOP_MASK = QDEC_SHORTS_SAMPLERDY_STOP_Msk /**< Shortcut between SAMPLERDY event and STOP task. */
} nrf_qdec_short_mask_t;
/**
* @enum nrf_qdec_int_mask_t
* @brief QDEC interrupts.
*/
typedef enum
{
NRF_QDEC_INT_SAMPLERDY_MASK = QDEC_INTENSET_SAMPLERDY_Msk, /**< Mask for enabling or disabling an interrupt on SAMPLERDY event. */
NRF_QDEC_INT_REPORTRDY_MASK = QDEC_INTENSET_REPORTRDY_Msk, /**< Mask for enabling or disabling an interrupt on REPORTRDY event. */
NRF_QDEC_INT_ACCOF_MASK = QDEC_INTENSET_ACCOF_Msk /**< Mask for enabling or disabling an interrupt on ACCOF event. */
} nrf_qdec_int_mask_t;
/**
* @enum nrf_qdec_enable_t
* @brief States of the enable bit.
*/
typedef enum
{
NRF_QDEC_DISABLE = QDEC_ENABLE_ENABLE_Disabled, /**< Mask for disabling the QDEC periperal. When disabled, the QDEC decoder pins are not active. */
NRF_QDEC_ENABLE = QDEC_ENABLE_ENABLE_Enabled /**< Mask for enabling the QDEC periperal. When enabled, the QDEC pins are active. */
} nrf_qdec_enable_t;
/**
* @enum nrf_qdec_dbfen_t
* @brief States of the debounce filter enable bit.
*/
typedef enum
{
NRF_QDEC_DBFEN_DISABLE = QDEC_DBFEN_DBFEN_Disabled, /**< Mask for disabling the debounce filter. */
NRF_QDEC_DBFEN_ENABLE = QDEC_DBFEN_DBFEN_Enabled /**< Mask for enabling the debounce filter. */
} nrf_qdec_dbfen_t;
/**
* @enum nrf_qdec_ledpol_t
* @brief Active LED polarity.
*/
typedef enum
{
NRF_QDEC_LEPOL_ACTIVE_LOW = QDEC_LEDPOL_LEDPOL_ActiveLow, /**< QDEC LED active on output pin low. */
NRF_QDEC_LEPOL_ACTIVE_HIGH = QDEC_LEDPOL_LEDPOL_ActiveHigh /**< QDEC LED active on output pin high. */
} nrf_qdec_ledpol_t;
/**
* @enum nrf_qdec_sampleper_t
* @brief Available sampling periods.
*/
typedef enum
{
NRF_QDEC_SAMPLEPER_128us = QDEC_SAMPLEPER_SAMPLEPER_128us, /**< QDEC sampling period 128 microseconds. */
NRF_QDEC_SAMPLEPER_256us = QDEC_SAMPLEPER_SAMPLEPER_256us, /**< QDEC sampling period 256 microseconds. */
NRF_QDEC_SAMPLEPER_512us = QDEC_SAMPLEPER_SAMPLEPER_512us, /**< QDEC sampling period 512 microseconds. */
NRF_QDEC_SAMPLEPER_1024us = QDEC_SAMPLEPER_SAMPLEPER_1024us, /**< QDEC sampling period 1024 microseconds. */
NRF_QDEC_SAMPLEPER_2048us = QDEC_SAMPLEPER_SAMPLEPER_2048us, /**< QDEC sampling period 2048 microseconds. */
NRF_QDEC_SAMPLEPER_4096us = QDEC_SAMPLEPER_SAMPLEPER_4096us, /**< QDEC sampling period 4096 microseconds. */
NRF_QDEC_SAMPLEPER_8192us = QDEC_SAMPLEPER_SAMPLEPER_8192us, /**< QDEC sampling period 8192 microseconds. */
NRF_QDEC_SAMPLEPER_16384us = QDEC_SAMPLEPER_SAMPLEPER_16384us /**< QDEC sampling period 16384 microseconds. */
} nrf_qdec_sampleper_t;
/**
* @enum nrf_qdec_reportper_t
* @brief Available report periods.
*/
typedef enum
{
NRF_QDEC_REPORTPER_10 = QDEC_REPORTPER_REPORTPER_10Smpl, /**< QDEC report period 10 samples. */
NRF_QDEC_REPORTPER_40 = QDEC_REPORTPER_REPORTPER_40Smpl, /**< QDEC report period 40 samples. */
NRF_QDEC_REPORTPER_80 = QDEC_REPORTPER_REPORTPER_80Smpl, /**< QDEC report period 80 samples. */
NRF_QDEC_REPORTPER_120 = QDEC_REPORTPER_REPORTPER_120Smpl, /**< QDEC report period 120 samples. */
NRF_QDEC_REPORTPER_160 = QDEC_REPORTPER_REPORTPER_160Smpl, /**< QDEC report period 160 samples. */
NRF_QDEC_REPORTPER_200 = QDEC_REPORTPER_REPORTPER_200Smpl, /**< QDEC report period 200 samples. */
NRF_QDEC_REPORTPER_240 = QDEC_REPORTPER_REPORTPER_240Smpl, /**< QDEC report period 240 samples. */
NRF_QDEC_REPORTPER_280 = QDEC_REPORTPER_REPORTPER_280Smpl, /**< QDEC report period 280 samples. */
NRF_QDEC_REPORTPER_DISABLED /**< QDEC reporting disabled. */
} nrf_qdec_reportper_t;
/**
* @brief Function for enabling QDEC.
*/
__STATIC_INLINE void nrf_qdec_enable(void)
{
NRF_QDEC->ENABLE = NRF_QDEC_ENABLE;
}
/**
* @brief Function for disabling QDEC.
*/
__STATIC_INLINE void nrf_qdec_disable(void)
{
NRF_QDEC->ENABLE = NRF_QDEC_DISABLE;
}
/**
* @brief Function for returning the enable state of QDEC.
* @return State of the register.
*/
__STATIC_INLINE uint32_t nrf_qdec_enable_get(void)
{
return NRF_QDEC->ENABLE;
}
/**
* @brief Function for enabling QDEC interrupts by mask.
* @param[in] qdec_int_mask Sources of the interrupts to enable.
*/
__STATIC_INLINE void nrf_qdec_int_enable(uint32_t qdec_int_mask)
{
NRF_QDEC->INTENSET = qdec_int_mask; // writing 0 has no effect
}
/**
* @brief Function for disabling QDEC interrupts by mask.
* @param[in] qdec_int_mask Sources of the interrupts to disable.
*
*/
__STATIC_INLINE void nrf_qdec_int_disable(uint32_t qdec_int_mask)
{
NRF_QDEC->INTENCLR = qdec_int_mask; // writing 0 has no effect
}
/**
* @brief Function for getting the enabled interrupts of the QDEC.
*/
__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t qdec_int_mask)
{
return NRF_QDEC->INTENSET & qdec_int_mask; // when read this register will return the value of INTEN.
}
/**
* @brief Function for enabling the debouncing filter of the QED.
*/
__STATIC_INLINE void nrf_qdec_dbfen_enable(void)
{
NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_ENABLE;
}
/**
* @brief Function for disabling the debouncing filter of the QED.
*/
__STATIC_INLINE void nrf_qdec_dbfen_disable(void)
{
NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_DISABLE;
}
/**
* @brief Function for getting the state of the QDEC's debouncing filter.
* @retval NRF_QDEC_DBFEN_DISABLE If the debouncing filter is disabled.
* @retval NRF_QDEC_DBFEN_ENABLE If the debouncing filter is enabled.
*/
__STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void)
{
return NRF_QDEC->DBFEN;
}
/**
* @brief Function for assigning QDEC pins.
* @param[in] psela Pin number.
* @param[in] pselb Pin number.
* @param[in] pselled Pin number.
*/
__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled)
{
#ifdef NRF51
NRF_QDEC->PSELA = psela;
NRF_QDEC->PSELB = pselb;
NRF_QDEC->PSELLED = pselled;
#elif defined NRF52
NRF_QDEC->PSEL.A = psela;
NRF_QDEC->PSEL.B = pselb;
NRF_QDEC->PSEL.LED = pselled;
#endif
}
/**
* @brief Function for setting a specific QDEC task.
* @param[in] qdec_task QDEC task to be set.
*/
__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task) ) = 1;
}
/**
* @brief Function for retrieving the address of a QDEC task register.
* @param[in] qdec_task QDEC task.
*/
__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t qdec_task)
{
return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task);
}
/**
* @brief Function for clearing a specific QDEC event.
* @param[in] qdec_event QDEC event to clear.
*/
__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t qdec_event)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event) ) = 0;
}
/**
* @brief Function for retrieving the state of a specific QDEC event.
* @return State of the QDEC event.
*/
__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t qdec_event)
{
return *(volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event);
}
/**
* @brief Function for retrieving the address of a specific QDEC event register.
* @param[in] qdec_event QDEC event.
* @return Address of the specified QDEC event.
*/
__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t qdec_event)
{
return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event);
}
/**
* @brief Function for setting QDEC shortcuts.
* @param[in] qdec_short_mask QDEC shortcut by mask.
*/
__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t qdec_short_mask)
{
NRF_QDEC->SHORTS |= qdec_short_mask;
}
/**
* @brief Function for clearing shortcuts of the QDEC by mask.
* @param[in] qdec_short_mask QDEC shortcute to be cleared.
*/
__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t qdec_short_mask)
{
NRF_QDEC->SHORTS &= ~qdec_short_mask;
}
/**
* @brief Function for retrieving the value of QDEC's SAMPLEPER register.
* @return Value of the SAMPLEPER register.
*/
__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void)
{
return NRF_QDEC->SAMPLEPER;
}
/**
* @brief Function for converting the value of QDEC's SAMPLE PERIOD to microseconds.
* @retval sampling period in microseconds.
*/
__STATIC_INLINE uint32_t nrf_qdec_sampleper_to_value(uint32_t sampleper)
{
return (1 << (7+sampleper));
}
/**
* @brief Function for setting the value of QDEC's SAMPLEPER register.
* @param[in] sample_per Sampling period.
*/
__STATIC_INLINE void nrf_qdec_sampleper_set(nrf_qdec_sampleper_t sample_per)
{
NRF_QDEC->SAMPLEPER = sample_per;
}
/**
* @brief Function for retrieving the value of QDEC's SAMPLE register.
* @return Value of the SAMPLE register.
*/
__STATIC_INLINE int32_t nrf_qdec_sample_get(void)
{
return NRF_QDEC->SAMPLE;
}
/**
* @brief Function for retrieving the value of QDEC's ACC register.
* @return Value of the ACC register.
*/
__STATIC_INLINE int32_t nrf_qdec_acc_get(void)
{
return NRF_QDEC->ACC;
}
/**
* @brief Function for retrieving the value of QDEC's ACCREAD register.
* @return Value of the ACCREAD register.
*/
__STATIC_INLINE int32_t nrf_qdec_accread_get(void)
{
return NRF_QDEC->ACCREAD;
}
/**
* @brief Function for retrieving the value of QDEC's ACCDBL register.
* @return Value of the ACCDBL register.
*/
__STATIC_INLINE uint32_t nrf_qdec_accdbl_get(void)
{
return NRF_QDEC->ACCDBL;
}
/**
* @brief Function for retrieving the value of QDEC's ACCDBLREAD register.
* @return Value of the ACCDBLREAD register.
*/
__STATIC_INLINE uint32_t nrf_qdec_accdblread_get(void)
{
return NRF_QDEC->ACCDBLREAD;
}
/**
* @brief Function for setting how long the LED is switched on before sampling.
* @param[in] time_us Time (in microseconds) how long the LED is switched on before sampling.
*/
__STATIC_INLINE void nrf_qdec_ledpre_set(uint32_t time_us)
{
NRF_QDEC->LEDPRE = time_us;
}
/**
* @brief Function for retrieving how long the LED is switched on before sampling.
* @retval time_us Time (in microseconds) how long the LED is switched on before sampling.
*/
__STATIC_INLINE uint32_t nrf_qdec_ledpre_get(void)
{
return NRF_QDEC->LEDPRE;
}
/**
* @brief Function for setting the report period (in samples).
* @param[in] reportper Number of samples.
*/
__STATIC_INLINE void nrf_qdec_reportper_set(nrf_qdec_reportper_t reportper)
{
NRF_QDEC->REPORTPER = reportper;
}
/**
* @brief Function for retrieving the report period.
* @retval reportper Number of samples as encoded in the register.
*/
__STATIC_INLINE uint32_t nrf_qdec_reportper_reg_get(void)
{
return NRF_QDEC->REPORTPER;
}
/**
* @brief Function for retrieving the value of QDEC's SAMPLEPER register.
* @param [in] reportper Reportper to be converted to amount of samples per report.
*/
__STATIC_INLINE uint32_t nrf_qdec_reportper_to_value(uint32_t reportper)
{
return (reportper == NRF_QDEC_REPORTPER_10) ? 10 : reportper*40;
}
/**
* @brief Function for setting the active level for the LED.
* @param[in] pol Active level for the LED.
*/
__STATIC_INLINE void nrf_qdec_ledpol_set(nrf_qdec_ledpol_t pol)
{
NRF_QDEC->LEDPOL = pol;
}
/**
* @brief Function for retrieving the active level for the LED.
* @return Active level for the LED.
*/
__STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void)
{
return NRF_QDEC->LEDPOL;
}
/**
*@}
**/
/*lint --flb "Leave library region" */
#endif

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @file
* @brief RNG HAL API.
*/
#ifndef NRF_RNG_H__
#define NRF_RNG_H__
/**
* @defgroup nrf_rng_hal RNG HAL
* @{
* @ingroup nrf_rng
* @brief Hardware access layer for managing the random number generator (RNG).
*/
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include "nrf.h"
#define NRF_RNG_TASK_SET (1UL)
#define NRF_RNG_EVENT_CLEAR (0UL)
/**
* @enum nrf_rng_task_t
* @brief RNG tasks.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_RNG_TASK_START = offsetof(NRF_RNG_Type, TASKS_START), /**< Start the random number generator. */
NRF_RNG_TASK_STOP = offsetof(NRF_RNG_Type, TASKS_STOP) /**< Stop the random number generator. */
} nrf_rng_task_t; /*lint -restore */
/**
* @enum nrf_rng_event_t
* @brief RNG events.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_RNG_EVENT_VALRDY = offsetof(NRF_RNG_Type, EVENTS_VALRDY) /**< New random number generated event. */
} nrf_rng_event_t; /*lint -restore */
/**
* @enum nrf_rng_int_mask_t
* @brief RNG interrupts.
*/
typedef enum
{
NRF_RNG_INT_VALRDY_MASK = RNG_INTENSET_VALRDY_Msk /**< Mask for enabling or disabling an interrupt on VALRDY event. */
} nrf_rng_int_mask_t;
/**
* @enum nrf_rng_short_mask_t
* @brief Types of RNG shortcuts.
*/
typedef enum
{
NRF_RNG_SHORT_VALRDY_STOP_MASK = RNG_SHORTS_VALRDY_STOP_Msk /**< Mask for setting shortcut between EVENT_VALRDY and TASK_STOP. */
} nrf_rng_short_mask_t;
/**
* @brief Function for enabling interrupts.
*
* @param[in] rng_int_mask Mask of interrupts.
*/
__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask)
{
NRF_RNG->INTENSET = rng_int_mask;
}
/**
* @brief Function for disabling interrupts.
*
* @param[in] rng_int_mask Mask of interrupts.
*/
__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask)
{
NRF_RNG->INTENCLR = rng_int_mask;
}
/**
* @brief Function for getting the state of a specific interrupt.
*
* @param[in] rng_int_mask Interrupt.
*
* @retval true If the interrupt is not enabled.
* @retval false If the interrupt is enabled.
*/
__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask)
{
return (bool)(NRF_RNG->INTENCLR & rng_int_mask);
}
/**
* @brief Function for getting the address of a specific task.
*
* This function can be used by the PPI module.
*
* @param[in] rng_task Task.
*/
__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task)
{
return (uint32_t *)((uint8_t *)NRF_RNG + rng_task);
}
/**
* @brief Function for setting a specific task.
*
* @param[in] rng_task Task.
*/
__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task)
{
*((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_task)) = NRF_RNG_TASK_SET;
}
/**
* @brief Function for getting address of a specific event.
*
* This function can be used by the PPI module.
*
* @param[in] rng_event Event.
*/
__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event)
{
return (uint32_t *)((uint8_t *)NRF_RNG + rng_event);
}
/**
* @brief Function for clearing a specific event.
*
* @param[in] rng_event Event.
*/
__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event)
{
*((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)) = NRF_RNG_EVENT_CLEAR;
}
/**
* @brief Function for getting the state of a specific event.
*
* @param[in] rng_event Event.
*
* @retval true If the event is not set.
* @retval false If the event is set.
*/
__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event)
{
return (bool)*((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event));
}
/**
* @brief Function for setting shortcuts.
*
* @param[in] rng_short_mask Mask of shortcuts.
*
*/
__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask)
{
NRF_RNG->SHORTS |= rng_short_mask;
}
/**
* @brief Function for clearing shortcuts.
*
* @param[in] rng_short_mask Mask of shortcuts.
*
*/
__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask)
{
NRF_RNG->SHORTS &= ~rng_short_mask;
}
/**
* @brief Function for getting the previously generated random value.
*
* @return Previously generated random value.
*/
__STATIC_INLINE uint8_t nrf_rng_random_value_get(void)
{
return (uint8_t)(NRF_RNG->VALUE & RNG_VALUE_VALUE_Msk);
}
/**
* @brief Function for enabling digital error correction.
*/
__STATIC_INLINE void nrf_rng_error_correction_enable(void)
{
NRF_RNG->CONFIG |= RNG_CONFIG_DERCEN_Msk;
}
/**
* @brief Function for disabling digital error correction.
*/
__STATIC_INLINE void nrf_rng_error_correction_disable(void)
{
NRF_RNG->CONFIG &= ~RNG_CONFIG_DERCEN_Msk;
}
/**
*@}
**/
#endif /* NRF_RNG_H__ */

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @file
* @brief RTC HAL API.
*/
#ifndef NRF_RTC_H
#define NRF_RTC_H
/**
* @defgroup nrf_rtc_hal RTC HAL
* @{
* @ingroup nrf_rtc
* @brief Hardware access layer for managing the real time counter (RTC).
*/
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include "nrf.h"
#include "nrf_assert.h"
/**
* @brief Macro for getting the number of compare channels available
* in a given RTC instance.
*/
#ifdef NRF51
#define NRF_RTC_CC_CHANNEL_COUNT(id) 4
#else
#define NRF_RTC_CC_CHANNEL_COUNT(id) ((id) == 0 ? 3 : 4)
#endif
#define RTC_INPUT_FREQ 32768 /**< Input frequency of the RTC instance. */
/**< Macro for wrapping values to RTC capacity. */
#define RTC_WRAP(val) (val & RTC_COUNTER_COUNTER_Msk)
#define RTC_CHANNEL_INT_MASK(ch) ((uint32_t)NRF_RTC_INT_COMPARE0_MASK << ch)
#define RTC_CHANNEL_EVENT_ADDR(ch) (nrf_rtc_event_t)(NRF_RTC_EVENT_COMPARE_0 + ch*sizeof(uint32_t))
/**
* @enum nrf_rtc_task_t
* @brief RTC tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_RTC_TASK_START = offsetof(NRF_RTC_Type,TASKS_START), /**< Start. */
NRF_RTC_TASK_STOP = offsetof(NRF_RTC_Type,TASKS_STOP), /**< Stop. */
NRF_RTC_TASK_CLEAR = offsetof(NRF_RTC_Type,TASKS_CLEAR), /**< Clear. */
NRF_RTC_TASK_TRIGGER_OVERFLOW = offsetof(NRF_RTC_Type,TASKS_TRIGOVRFLW),/**< Trigger overflow. */
/*lint -restore*/
} nrf_rtc_task_t;
/**
* @enum nrf_rtc_event_t
* @brief RTC events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_RTC_EVENT_TICK = offsetof(NRF_RTC_Type,EVENTS_TICK), /**< Tick event. */
NRF_RTC_EVENT_OVERFLOW = offsetof(NRF_RTC_Type,EVENTS_OVRFLW), /**< Overflow event. */
NRF_RTC_EVENT_COMPARE_0 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[0]), /**< Compare 0 event. */
NRF_RTC_EVENT_COMPARE_1 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[1]), /**< Compare 1 event. */
NRF_RTC_EVENT_COMPARE_2 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[2]), /**< Compare 2 event. */
NRF_RTC_EVENT_COMPARE_3 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[3]) /**< Compare 3 event. */
/*lint -restore*/
} nrf_rtc_event_t;
/**
* @enum nrf_rtc_int_t
* @brief RTC interrupts.
*/
typedef enum
{
NRF_RTC_INT_TICK_MASK = RTC_INTENSET_TICK_Msk, /**< RTC interrupt from tick event. */
NRF_RTC_INT_OVERFLOW_MASK = RTC_INTENSET_OVRFLW_Msk, /**< RTC interrupt from overflow event. */
NRF_RTC_INT_COMPARE0_MASK = RTC_INTENSET_COMPARE0_Msk, /**< RTC interrupt from compare event on channel 0. */
NRF_RTC_INT_COMPARE1_MASK = RTC_INTENSET_COMPARE1_Msk, /**< RTC interrupt from compare event on channel 1. */
NRF_RTC_INT_COMPARE2_MASK = RTC_INTENSET_COMPARE2_Msk, /**< RTC interrupt from compare event on channel 2. */
NRF_RTC_INT_COMPARE3_MASK = RTC_INTENSET_COMPARE3_Msk /**< RTC interrupt from compare event on channel 3. */
} nrf_rtc_int_t;
/**@brief Function for setting a compare value for a channel.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] ch Channel.
* @param[in] cc_val Compare value to set.
*/
__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val);
/**@brief Function for returning the compare value for a channel.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] ch Channel.
*
* @return COMPARE[ch] value.
*/
__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch);
/**@brief Function for enabling interrupts.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] mask Interrupt mask to be enabled.
*/
__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask);
/**@brief Function for disabling interrupts.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] mask Interrupt mask to be disabled.
*/
__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask);
/**@brief Function for checking if interrupts are enabled.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] mask Mask of interrupt flags to check.
*
* @return Mask with enabled interrupts.
*/
__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask);
/**@brief Function for returning the status of currently enabled interrupts.
*
* @param[in] p_rtc Pointer to the instance register structure.
*
* @return Value in INTEN register.
*/
__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc);
/**@brief Function for checking if an event is pending.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] event Address of the event.
*
* @return Mask of pending events.
*/
__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
/**@brief Function for clearing an event.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
/**@brief Function for returning a counter value.
*
* @param[in] p_rtc Pointer to the instance register structure.
*
* @return Counter value.
*/
__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc);
/**@brief Function for setting a prescaler value.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] val Value to set the prescaler to.
*/
__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val);
/**@brief Function for returning the address of an event.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] event Requested event.
*
* @return Address of the requested event register.
*/
__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
/**@brief Function for returning the address of a task.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] task Requested task.
*
* @return Address of the requested task register.
*/
__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task);
/**@brief Function for starting a task.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] task Requested task.
*/
__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task);
/**@brief Function for enabling events.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] mask Mask of event flags to enable.
*/
__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask);
/**@brief Function for disabling an event.
*
* @param[in] p_rtc Pointer to the instance register structure.
* @param[in] event Requested event.
*/
__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t event);
/**
*@}
**/
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val)
{
p_rtc->CC[ch] = cc_val;
}
__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch)
{
return p_rtc->CC[ch];
}
__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask)
{
p_rtc->INTENSET = mask;
}
__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask)
{
p_rtc->INTENCLR = mask;
}
__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask)
{
return (p_rtc->INTENSET & mask);
}
__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc)
{
return p_rtc->INTENSET;
}
__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
{
return *(volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event);
}
__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)) = 0;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc)
{
return p_rtc->COUNTER;
}
__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val)
{
ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos));
p_rtc->PRESCALER = val;
}
__STATIC_INLINE uint32_t rtc_prescaler_get(NRF_RTC_Type * p_rtc)
{
return p_rtc->PRESCALER;
}
__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
{
return (uint32_t)p_rtc + event;
}
__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task)
{
return (uint32_t)p_rtc + task;
}
__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task)
{
*(__IO uint32_t *)((uint32_t)p_rtc + task) = 1;
}
__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask)
{
p_rtc->EVTENSET = mask;
}
__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t mask)
{
p_rtc->EVTENCLR = mask;
}
#endif
#endif /* NRF_RTC_H */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @file
* @brief SAADC HAL implementation
*/
#include "nrf_saadc.h"
void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config)
{
NRF_SAADC->CH[channel].CONFIG =
((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk)
| ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk)
| ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk)
| ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk)
| ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk)
| ((config->mode << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk);
nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n);
return;
}

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_SAADC_H_
#define NRF_SAADC_H_
/**
* @defgroup nrf_saadc_hal SAADC HAL
* @{
* @ingroup nrf_saadc
*
* @brief @tagAPI52 Hardware access layer for accessing the SAADC peripheral.
*/
#include <stdbool.h>
#include <stddef.h>
#include "nrf.h"
#include "nrf_assert.h"
#define NRF_SAADC_CHANNEL_COUNT 8
/**
* @brief Resolution of the analog-to-digital converter.
*/
typedef enum
{
NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution.
NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution.
NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution.
NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution.
} nrf_saadc_resolution_t;
/**
* @brief Input selection for the analog-to-digital converter.
*/
typedef enum
{
NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected.
NRF_SAADC_INPUT_AIN0 = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0).
NRF_SAADC_INPUT_AIN1 = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1).
NRF_SAADC_INPUT_AIN2 = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2).
NRF_SAADC_INPUT_AIN3 = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3).
NRF_SAADC_INPUT_AIN4 = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4).
NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5).
NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6).
NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7).
NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD ///< VDD as input.
} nrf_saadc_input_t;
/**
* @brief Analog-to-digital converter oversampling mode.
*/
typedef enum
{
NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling.
NRF_SAADC_OVERSAMPLE_2X = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x, ///< Oversample 2x.
NRF_SAADC_OVERSAMPLE_4X = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x, ///< Oversample 4x.
NRF_SAADC_OVERSAMPLE_8X = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x, ///< Oversample 8x.
NRF_SAADC_OVERSAMPLE_16X = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x, ///< Oversample 16x.
NRF_SAADC_OVERSAMPLE_32X = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x, ///< Oversample 32x.
NRF_SAADC_OVERSAMPLE_64X = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x, ///< Oversample 64x.
NRF_SAADC_OVERSAMPLE_128X = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x.
NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x.
} nrf_saadc_oversample_t;
/**
* @brief Analog-to-digital converter channel resistor control.
*/
typedef enum
{
NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder.
NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND.
NRF_SAADC_RESISTOR_PULLUP = SAADC_CH_CONFIG_RESP_Pullup, ///< Pull-up to VDD.
NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2 ///< Set input at VDD/2.
} nrf_saadc_resistor_t;
/**
* @brief Gain factor of the analog-to-digital converter input.
*/
typedef enum
{
NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6.
NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5.
NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4.
NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3.
NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2.
NRF_SAADC_GAIN1 = SAADC_CH_CONFIG_GAIN_Gain1, ///< Gain factor 1.
NRF_SAADC_GAIN2 = SAADC_CH_CONFIG_GAIN_Gain2, ///< Gain factor 2.
NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4.
} nrf_saadc_gain_t;
/**
* @brief Reference selection for the analog-to-digital converter.
*/
typedef enum
{
NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference (0.6 V).
NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference.
} nrf_saadc_reference_t;
/**
* @brief Analog-to-digital converter acquisition time.
*/
typedef enum
{
NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us.
NRF_SAADC_ACQTIME_5US = SAADC_CH_CONFIG_TACQ_5us, ///< 5 us.
NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us.
NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us.
NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us.
NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us.
} nrf_saadc_acqtime_t;
/**
* @brief Analog-to-digital converter channel mode.
*/
typedef enum
{
NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single ended, PSELN will be ignored, negative input to ADC shorted to GND.
NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode.
} nrf_saadc_mode_t;
/**
* @brief Analog-to-digital converter tasks.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM.
NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled.
NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any on-going conversion.
NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration.
} nrf_saadc_task_t;
/**
* @brief Analog-to-digital converter events.
*/
typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
{
NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started.
NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer.
NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete.
NRF_SAADC_EVENT_STOPPED = offsetof(NRF_SAADC_Type, EVENTS_STOPPED), ///< The ADC has stopped.
NRF_SAADC_EVENT_CH0_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH), ///< Last result is equal or above CH[0].LIMIT.HIGH.
NRF_SAADC_EVENT_CH0_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL), ///< Last result is equal or below CH[0].LIMIT.LOW.
NRF_SAADC_EVENT_CH1_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH), ///< Last result is equal or above CH[1].LIMIT.HIGH.
NRF_SAADC_EVENT_CH1_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL), ///< Last result is equal or below CH[1].LIMIT.LOW.
NRF_SAADC_EVENT_CH2_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH), ///< Last result is equal or above CH[2].LIMIT.HIGH.
NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW.
NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH.
NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW.
NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH.
NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW.
NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH.
NRF_SAADC_EVENT_CH5_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL), ///< Last result is equal or below CH[5].LIMIT.LOW.
NRF_SAADC_EVENT_CH6_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH), ///< Last result is equal or above CH[6].LIMIT.HIGH.
NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW.
NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH.
NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW.
} nrf_saadc_event_t;
/**
* @brief Analog-to-digital converter interrupt masks.
*/
typedef enum
{
NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event.
NRF_SAADC_INT_STOPPED = SAADC_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event.
NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event.
NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event.
NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event.
NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event.
NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event.
NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event.
NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event.
NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event.
NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event.
NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event.
NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event.
NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event.
NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event.
NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event.
NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event.
NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts.
} nrf_saadc_int_mask_t;
/**
* @brief Analog-to-digital converter value limit type.
*/
typedef enum
{
NRF_SAADC_LIMIT_LOW = 0,
NRF_SAADC_LIMIT_HIGH = 1
} nrf_saadc_limit_t;
typedef int16_t nrf_saadc_value_t; ///< Type of a single ADC conversion result.
/**
* @brief Analog-to-digital converter configuration structure.
*/
typedef struct
{
nrf_saadc_resolution_t resolution;
nrf_saadc_oversample_t oversample;
nrf_saadc_value_t * buffer;
uint32_t buffer_size;
} nrf_saadc_config_t;
/**
* @brief Analog-to-digital converter channel configuration structure.
*/
typedef struct
{
nrf_saadc_resistor_t resistor_p;
nrf_saadc_resistor_t resistor_n;
nrf_saadc_gain_t gain;
nrf_saadc_reference_t reference;
nrf_saadc_acqtime_t acq_time;
nrf_saadc_mode_t mode;
nrf_saadc_input_t pin_p;
nrf_saadc_input_t pin_n;
} nrf_saadc_channel_config_t;
/**
* @brief Function for triggering a specific SAADC task.
*
* @param[in] saadc_task SAADC task.
*/
__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task)
{
*((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task)) = 0x1UL;
}
/**
* @brief Function for getting the address of a specific SAADC task register.
*
* @param[in] saadc_task SAADC task.
*
* @return Address of the specified SAADC task.
*/
__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task)
{
return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task);
}
/**
* @brief Function for getting the state of a specific SAADC event.
*
* @param[in] saadc_event SAADC event.
*
* @return State of the specified SAADC event.
*/
__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
}
/**
* @brief Function for clearing the specific SAADC event.
*
* @param[in] saadc_event SAADC event.
*/
__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event)
{
*((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)) = 0x0UL;
}
/**
* @brief Function for getting the address of a specific SAADC event register.
*
* @param[in] saadc_event SAADC event.
*
* @return Address of the specified SAADC event.
*/
__STATIC_INLINE volatile uint32_t * nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event)
{
return (volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
}
/**
* @brief Function for getting the address of a specific SAADC limit event register.
*
* @param[in] channel Channel number.
* @param[in] limit_type Low limit or high limit.
*
* @return Address of the specified SAADC limit event.
*/
__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type)
{
ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
if (limit_type == NRF_SAADC_LIMIT_HIGH)
{
return &NRF_SAADC->EVENTS_CH[channel].LIMITH;
}
else
{
return &NRF_SAADC->EVENTS_CH[channel].LIMITL;
}
}
/**
* @brief Function for getting the SAADC channel monitoring limit events.
*
* @param[in] channel Channel number.
* @param[in] limit_type Low limit or high limit.
*/
__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type)
{
if (limit_type == NRF_SAADC_LIMIT_HIGH)
{
return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITH +
(uint32_t) (NRF_SAADC_EVENT_CH1_LIMITH - NRF_SAADC_EVENT_CH0_LIMITH)
* (uint32_t) channel );
}
else
{
return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITL +
(uint32_t) (NRF_SAADC_EVENT_CH1_LIMITL - NRF_SAADC_EVENT_CH0_LIMITL)
* (uint32_t) channel );
}
}
/**
* @brief Function for configuring the input pins for a specific SAADC channel.
*
* @param[in] channel Channel number.
* @param[in] pselp Positive input.
* @param[in] pseln Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode.
*/
__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
nrf_saadc_input_t pselp,
nrf_saadc_input_t pseln)
{
NRF_SAADC->CH[channel].PSELN = pseln;
NRF_SAADC->CH[channel].PSELP = pselp;
}
/**
* @brief Function for setting the SAADC channel monitoring limits.
*
* @param[in] channel Channel number.
* @param[in] low Low limit.
* @param[in] high High limit.
*/
__STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low, int16_t high)
{
NRF_SAADC->CH[channel].LIMIT = (
(((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk)
| (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk));
}
/**
* @brief Function for enabling specified SAADC interrupts.
*
* @param[in] saadc_int_mask Interrupt(s) to enable.
*/
__STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask)
{
NRF_SAADC->INTENSET = saadc_int_mask;
}
/**
* @brief Function for retrieving the state of specified SAADC interrupts.
*
* @param[in] saadc_int_mask Interrupt(s) to check.
*
* @retval true If all specified interrupts are enabled.
* @retval false If at least one of the given interrupts is not enabled.
*/
__STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask)
{
return (bool)(NRF_SAADC->INTENSET & saadc_int_mask);
}
/**
* @brief Function for disabling specified interrupts.
*
* @param saadc_int_mask Interrupt(s) to disable.
*/
__STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask)
{
NRF_SAADC->INTENCLR = saadc_int_mask;
}
/**
* @brief Function for generating masks for SAADC channel limit interrupts.
*
* @param[in] channel SAADC channel number.
* @param[in] limit_type Limit type.
*
* @returns Interrupt mask.
*/
__STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type)
{
ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ? NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
return mask << (channel * 2);
}
/**
* @brief Function for checking whether the SAADC is busy.
*
* This function checks whether the analog-to-digital converter is busy with a conversion.
*
* @retval true If the SAADC is busy.
* @retval false If the SAADC is not busy.
*/
__STATIC_INLINE bool nrf_saadc_busy_check(void)
{
//return ((NRF_SAADC->STATUS & SAADC_STATUS_STATUS_Msk) == SAADC_STATUS_STATUS_Msk);
//simplified for performance
return NRF_SAADC->STATUS;
}
/**
* @brief Function for enabling the SAADC.
*
* The analog-to-digital converter must be enabled before use.
*/
__STATIC_INLINE void nrf_saadc_enable(void)
{
NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos);
}
/**
* @brief Function for disabling the SAADC.
*/
__STATIC_INLINE void nrf_saadc_disable(void)
{
NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos);
}
/**
* @brief Function for checking if the SAADC is enabled.
*
* @retval true If the SAADC is enabled.
* @retval false If the SAADC is not enabled.
*/
__STATIC_INLINE bool nrf_saadc_enable_check(void)
{
//simplified for performance
return NRF_SAADC->ENABLE;
}
/**
* @brief Function for initializing the SAADC result buffer.
*
* @param[in] buffer Pointer to the result buffer.
* @param[in] num Size of buffer in words.
*/
__STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * buffer, uint32_t num)
{
NRF_SAADC->RESULT.PTR = (uint32_t)buffer;
NRF_SAADC->RESULT.MAXCNT = num;
}
/**
* @brief Function for getting the number of buffer words transferred since last START operation.
*
* @returns Number of words transferred.
*/
__STATIC_INLINE uint16_t nrf_saadc_amount_get(void)
{
return NRF_SAADC->RESULT.AMOUNT;
}
/**
* @brief Function for setting the SAADC sample resolution.
*
* @param[in] resolution Bit resolution.
*/
__STATIC_INLINE void nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution)
{
NRF_SAADC->RESOLUTION = resolution;
}
/**
* @brief Function for configuring the oversampling feature.
*
* @param[in] oversample Oversampling mode.
*/
__STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample)
{
NRF_SAADC->OVERSAMPLE = oversample;
}
/**
* @brief Function for getting the oversampling feature configuration.
*
* @return Oversampling configuration.
*/
__STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void)
{
return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE;
}
/**
* @brief Function for initializing the SAADC channel.
*
* @param[in] channel Channel number.
* @param[in] config Pointer to the channel configuration structure.
*/
void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config);
/**
*@}
**/
#endif /* NRF_SAADC_H_ */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @defgroup nrf_spi_hal SPI HAL
* @{
* @ingroup nrf_spi_master
*
* @brief Hardware access layer for accessing the SPI peripheral.
*/
#ifndef NRF_SPI_H__
#define NRF_SPI_H__
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "nrf.h"
/**
* @brief This value can be used as a parameter for the @ref nrf_spi_pins_set
* function to specify that a given SPI signal (SCK, MOSI, or MISO)
* shall not be connected to a physical pin.
*/
#define NRF_SPI_PIN_NOT_CONNECTED 0xFFFFFFFF
/**
* @brief SPI events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_SPI_EVENT_READY = offsetof(NRF_SPI_Type, EVENTS_READY) ///< TXD byte sent and RXD byte received.
/*lint -restore*/
} nrf_spi_event_t;
/**
* @brief SPI interrupts.
*/
typedef enum
{
NRF_SPI_INT_READY_MASK = SPI_INTENSET_READY_Msk ///< Interrupt on READY event.
} nrf_spi_int_mask_t;
/**
* @brief SPI data rates.
*/
typedef enum
{
NRF_SPI_FREQ_125K = SPI_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
NRF_SPI_FREQ_250K = SPI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
NRF_SPI_FREQ_500K = SPI_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
NRF_SPI_FREQ_1M = SPI_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
NRF_SPI_FREQ_2M = SPI_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
NRF_SPI_FREQ_4M = SPI_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
// [conversion to 'int' needed to prevent compilers from complaining
// that the provided value (0x80000000UL) is out of range of "int"]
NRF_SPI_FREQ_8M = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
} nrf_spi_frequency_t;
/**
* @brief SPI modes.
*/
typedef enum
{
NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock.
NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock.
NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock.
NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock.
} nrf_spi_mode_t;
/**
* @brief SPI bit orders.
*/
typedef enum
{
NRF_SPI_BIT_ORDER_MSB_FIRST = SPI_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
NRF_SPI_BIT_ORDER_LSB_FIRST = SPI_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
} nrf_spi_bit_order_t;
/**
* @brief Function for clearing a specific SPI event.
*
* @param[in] p_spi SPI instance.
* @param[in] spi_event Event to clear.
*/
__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_spi,
nrf_spi_event_t spi_event);
/**
* @brief Function for checking the state of a specific SPI event.
*
* @param[in] p_spi SPI instance.
* @param[in] spi_event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_spi,
nrf_spi_event_t spi_event);
/**
* @brief Function for getting the address of a specific SPI event register.
*
* @param[in] p_spi SPI instance.
* @param[in] spi_event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_spi,
nrf_spi_event_t spi_event);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_spi SPI instance.
* @param[in] spi_int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_spi,
uint32_t spi_int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_spi SPI instance.
* @param[in] spi_int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_spi,
uint32_t spi_int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_spi SPI instance.
* @param[in] spi_int Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_spi,
nrf_spi_int_mask_t spi_int);
/**
* @brief Function for enabling the SPI peripheral.
*
* @param[in] p_spi SPI instance.
*/
__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_spi);
/**
* @brief Function for disabling the SPI peripheral.
*
* @param[in] p_spi SPI instance.
*/
__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_spi);
/**
* @brief Function for configuring SPI pins.
*
* If a given signal is not needed, pass the @ref NRF_SPI_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_spi SPI instance.
* @param[in] sck_pin SCK pin number.
* @param[in] mosi_pin MOSI pin number.
* @param[in] miso_pin MISO pin number.
*/
__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_spi,
uint32_t sck_pin,
uint32_t mosi_pin,
uint32_t miso_pin);
/**
* @brief Function for writing data to the SPI transmitter register.
*
* @param[in] p_spi SPI instance.
* @param[in] data TX data to send.
*/
__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_spi, uint8_t data);
/**
* @brief Function for reading data from the SPI receiver register.
*
* @param[in] p_spi SPI instance.
*
* @return RX data received.
*/
__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_spi);
/**
* @brief Function for setting the SPI master data rate.
*
* @param[in] p_spi SPI instance.
* @param[in] frequency SPI frequency.
*/
__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_spi,
nrf_spi_frequency_t frequency);
/**
* @brief Function for setting the SPI configuration.
*
* @param[in] p_spi SPI instance.
* @param[in] spi_mode SPI mode.
* @param[in] spi_bit_order SPI bit order.
*/
__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_spi,
nrf_spi_mode_t spi_mode,
nrf_spi_bit_order_t spi_bit_order);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_spi,
nrf_spi_event_t spi_event)
{
*((volatile uint32_t *)((uint8_t *)p_spi + (uint32_t)spi_event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_spi,
nrf_spi_event_t spi_event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_spi + (uint32_t)spi_event);
}
__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_spi,
nrf_spi_event_t spi_event)
{
return (uint32_t *)((uint8_t *)p_spi + (uint32_t)spi_event);
}
__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_spi,
uint32_t spi_int_mask)
{
p_spi->INTENSET = spi_int_mask;
}
__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_spi,
uint32_t spi_int_mask)
{
p_spi->INTENCLR = spi_int_mask;
}
__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_spi,
nrf_spi_int_mask_t spi_int)
{
return (bool)(p_spi->INTENSET & spi_int);
}
__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_spi)
{
p_spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_spi)
{
p_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_spi,
uint32_t sck_pin,
uint32_t mosi_pin,
uint32_t miso_pin)
{
p_spi->PSELSCK = sck_pin;
p_spi->PSELMOSI = mosi_pin;
p_spi->PSELMISO = miso_pin;
}
__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_spi, uint8_t data)
{
p_spi->TXD = data;
}
__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_spi)
{
return p_spi->RXD;
}
__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_spi,
nrf_spi_frequency_t frequency)
{
p_spi->FREQUENCY = frequency;
}
__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_spi,
nrf_spi_mode_t spi_mode,
nrf_spi_bit_order_t spi_bit_order)
{
uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ?
SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst);
switch (spi_mode)
{
default:
case NRF_SPI_MODE_0:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
(SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;
case NRF_SPI_MODE_1:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
(SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;
case NRF_SPI_MODE_2:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) |
(SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;
case NRF_SPI_MODE_3:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) |
(SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;
}
p_spi->CONFIG = config;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_SPI_H__
/** @} */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @defgroup nrf_spim_hal SPIM HAL
* @{
* @ingroup nrf_spi_master
*
* @brief Hardware access layer for accessing the SPIM peripheral.
*/
#ifndef NRF_SPIM_H__
#define NRF_SPIM_H__
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "nrf.h"
/**
* @brief This value can be used as a parameter for the @ref nrf_spim_pins_set
* function to specify that a given SPI signal (SCK, MOSI, or MISO)
* shall not be connected to a physical pin.
*/
#define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF
/**
* @brief SPIM tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction.
NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction.
NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction.
NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME) ///< Resume SPI transaction.
/*lint -restore*/
} nrf_spim_task_t;
/**
* @brief SPIM events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped.
NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached.
#ifdef NRF52
NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END), ///< End of RXD buffer and TXD buffer reached.
#endif
NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached.
NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED) ///< Transaction started.
/*lint -restore*/
} nrf_spim_event_t;
#ifdef NRF52
/**
* @brief SPIM shortcuts.
*/
typedef enum
{
NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk ///< Shortcut between END event and START task.
} nrf_spim_short_mask_t;
#endif
/**
* @brief SPIM interrupts.
*/
typedef enum
{
NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
#ifdef NRF52
NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event.
#endif
NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk ///< Interrupt on STARTED event.
} nrf_spim_int_mask_t;
/**
* @brief SPI master data rates.
*/
typedef enum
{
NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
// [conversion to 'int' needed to prevent compilers from complaining
// that the provided value (0x80000000UL) is out of range of "int"]
NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
} nrf_spim_frequency_t;
/**
* @brief SPI modes.
*/
typedef enum
{
NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock.
NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock.
} nrf_spim_mode_t;
/**
* @brief SPI bit orders.
*/
typedef enum
{
NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
} nrf_spim_bit_order_t;
/**
* @brief Function for activating a specific SPIM task.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_task Task to activate.
*/
__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_spim,
nrf_spim_task_t spim_task);
/**
* @brief Function for getting the address of a specific SPIM task register.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_task Requested task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_spim,
nrf_spim_task_t spim_task);
/**
* @brief Function for clearing a specific SPIM event.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_event Event to clear.
*/
__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_spim,
nrf_spim_event_t spim_event);
/**
* @brief Function for checking the state of a specific SPIM event.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_spim,
nrf_spim_event_t spim_event);
/**
* @brief Function for getting the address of a specific SPIM event register.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_spim,
nrf_spim_event_t spim_event);
#ifdef NRF52
/**
* @brief Function for enabling specified shortcuts.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_shorts_mask Shortcuts to enable.
*/
__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_spim,
uint32_t spim_shorts_mask);
/**
* @brief Function for disabling specified shortcuts.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_shorts_mask Shortcuts to disable.
*/
__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_spim,
uint32_t spim_shorts_mask);
/**
* @brief Function for getting shorts setting.
*
* @param[in] p_spim SPIM instance.
*/
__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_spim);
#endif
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_spim,
uint32_t spim_int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_spim,
uint32_t spim_int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_spim SPIM instance.
* @param[in] spim_int Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_spim,
nrf_spim_int_mask_t spim_int);
/**
* @brief Function for enabling the SPIM peripheral.
*
* @param[in] p_spim SPIM instance.
*/
__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_spim);
/**
* @brief Function for disabling the SPIM peripheral.
*
* @param[in] p_spim SPIM instance.
*/
__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_spim);
/**
* @brief Function for configuring SPIM pins.
*
* If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_spim SPIM instance.
* @param[in] sck_pin SCK pin number.
* @param[in] mosi_pin MOSI pin number.
* @param[in] miso_pin MISO pin number.
*/
__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_spim,
uint32_t sck_pin,
uint32_t mosi_pin,
uint32_t miso_pin);
/**
* @brief Function for setting the SPI master data rate.
*
* @param[in] p_spim SPIM instance.
* @param[in] frequency SPI frequency.
*/
__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_spim,
nrf_spim_frequency_t frequency);
/**
* @brief Function for setting the transmit buffer.
*
* @param[in] p_spim SPIM instance.
* @param[in] p_buffer Pointer to the buffer with data to send.
* @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_spim,
uint8_t const * p_buffer,
uint8_t length);
/**
* @brief Function for setting the receive buffer.
*
* @param[in] p_spim SPIM instance.
* @param[in] p_buffer Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_spim,
uint8_t * p_buffer,
uint8_t length);
/**
* @brief Function for setting the SPI configuration.
*
* @param[in] p_spim SPIM instance.
* @param[in] spi_mode SPI mode.
* @param[in] spi_bit_order SPI bit order.
*/
__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_spim,
nrf_spim_mode_t spi_mode,
nrf_spim_bit_order_t spi_bit_order);
/**
* @brief Function for setting the over-read character.
*
* @param[in] p_spim SPIM instance.
* @param[in] orc Over-read character that is clocked out in case of
* an over-read of the TXD buffer.
*/
__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_spim,
uint8_t orc);
#ifdef NRF52
/**
* @brief Function for enabling the TX list feature.
*
* @param[in] p_spim SPIM instance.
*/
__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_spim);
/**
* @brief Function for disabling the TX list feature.
*
* @param[in] p_spim SPIM instance.
*/
__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_spim);
/**
* @brief Function for enabling the RX list feature.
*
* @param[in] p_spim SPIM instance.
*/
__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_spim);
/**
* @brief Function for disabling the RX list feature.
*
* @param[in] p_spim SPIM instance.
*/
__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_spim);
#endif
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_spim,
nrf_spim_task_t spim_task)
{
*((volatile uint32_t *)((uint8_t *)p_spim + (uint32_t)spim_task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_spim,
nrf_spim_task_t spim_task)
{
return (uint32_t)((uint8_t *)p_spim + (uint32_t)spim_task);
}
__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_spim,
nrf_spim_event_t spim_event)
{
*((volatile uint32_t *)((uint8_t *)p_spim + (uint32_t)spim_event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_spim,
nrf_spim_event_t spim_event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_spim + (uint32_t)spim_event);
}
__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_spim,
nrf_spim_event_t spim_event)
{
return (uint32_t)((uint8_t *)p_spim + (uint32_t)spim_event);
}
#ifdef NRF52
__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_spim,
uint32_t spim_shorts_mask)
{
p_spim->SHORTS |= spim_shorts_mask;
}
__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_spim,
uint32_t spim_shorts_mask)
{
p_spim->SHORTS &= ~(spim_shorts_mask);
}
__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_spim)
{
return p_spim->SHORTS;
}
#endif
__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_spim,
uint32_t spim_int_mask)
{
p_spim->INTENSET = spim_int_mask;
}
__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_spim,
uint32_t spim_int_mask)
{
p_spim->INTENCLR = spim_int_mask;
}
__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_spim,
nrf_spim_int_mask_t spim_int)
{
return (bool)(p_spim->INTENSET & spim_int);
}
__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_spim)
{
p_spim->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_spim)
{
p_spim->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_spim,
uint32_t sck_pin,
uint32_t mosi_pin,
uint32_t miso_pin)
{
p_spim->PSEL.SCK = sck_pin;
p_spim->PSEL.MOSI = mosi_pin;
p_spim->PSEL.MISO = miso_pin;
}
__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_spim,
nrf_spim_frequency_t frequency)
{
p_spim->FREQUENCY = frequency;
}
__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_spim,
uint8_t const * p_buffer,
uint8_t length)
{
p_spim->TXD.PTR = (uint32_t)p_buffer;
p_spim->TXD.MAXCNT = length;
}
__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_spim,
uint8_t * p_buffer,
uint8_t length)
{
p_spim->RXD.PTR = (uint32_t)p_buffer;
p_spim->RXD.MAXCNT = length;
}
__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_spim,
nrf_spim_mode_t spi_mode,
nrf_spim_bit_order_t spi_bit_order)
{
uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
switch (spi_mode)
{
default:
case NRF_SPIM_MODE_0:
config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
break;
case NRF_SPIM_MODE_1:
config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
break;
case NRF_SPIM_MODE_2:
config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
break;
case NRF_SPIM_MODE_3:
config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
break;
}
p_spim->CONFIG = config;
}
__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_spim,
uint8_t orc)
{
p_spim->ORC = orc;
}
#ifdef NRF52
__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_spim)
{
p_spim->TXD.LIST = 1;
}
__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_spim)
{
p_spim->TXD.LIST = 0;
}
__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_spim)
{
p_spim->RXD.LIST = 1;
}
__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_spim)
{
p_spim->RXD.LIST = 0;
}
#endif
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_SPIM_H__
/** @} */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @defgroup nrf_spis_hal SPIS HAL
* @{
* @ingroup nrf_spis
*
* @brief Hardware access layer for accessing the SPIS peripheral.
*/
#ifndef NRF_SPIS_H__
#define NRF_SPIS_H__
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "nrf.h"
/**
* @brief This value can be used as a parameter for the @ref nrf_spis_pins_set
* function to specify that a given SPI signal (SCK, MOSI, or MISO)
* shall not be connected to a physical pin.
*/
#define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF
/**
* @brief SPIS tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore.
NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it.
/*lint -restore*/
} nrf_spis_task_t;
/**
* @brief SPIS events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed.
NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired.
/*lint -restore*/
} nrf_spis_event_t;
/**
* @brief SPIS shortcuts.
*/
typedef enum
{
NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task.
} nrf_spis_short_mask_t;
/**
* @brief SPIS interrupts.
*/
typedef enum
{
NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event.
NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event.
} nrf_spis_int_mask_t;
/**
* @brief SPI modes.
*/
typedef enum
{
NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock.
NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock.
NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock.
NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock.
} nrf_spis_mode_t;
/**
* @brief SPI bit orders.
*/
typedef enum
{
NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
} nrf_spis_bit_order_t;
/**
* @brief SPI semaphore status.
*/
typedef enum
{
NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free.
NRF_SPIS_SEMSTAT_CPU = 1, ///< Semaphore is assigned to the CPU.
NRF_SPIS_SEMSTAT_SPIS = 2, ///< Semaphore is assigned to the SPI slave.
NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending.
} nrf_spis_semstat_t;
/**
* @brief SPIS status.
*/
typedef enum
{
NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented.
NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented.
} nrf_spis_status_mask_t;
/**
* @brief Function for activating a specific SPIS task.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_task Task to activate.
*/
__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_spis,
nrf_spis_task_t spis_task);
/**
* @brief Function for getting the address of a specific SPIS task register.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_task Requested task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_spis,
nrf_spis_task_t spis_task);
/**
* @brief Function for clearing a specific SPIS event.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_event Event to clear.
*/
__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_spis,
nrf_spis_event_t spis_event);
/**
* @brief Function for checking the state of a specific SPIS event.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_spis,
nrf_spis_event_t spis_event);
/**
* @brief Function for getting the address of a specific SPIS event register.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_spis,
nrf_spis_event_t spis_event);
/**
* @brief Function for enabling specified shortcuts.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_shorts_mask Shortcuts to enable.
*/
__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_spis,
uint32_t spis_shorts_mask);
/**
* @brief Function for disabling specified shortcuts.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_shorts_mask Shortcuts to disable.
*/
__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_spis,
uint32_t spis_shorts_mask);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_spis,
uint32_t spis_int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_spis,
uint32_t spis_int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_spis SPIS instance.
* @param[in] spis_int Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_spis,
nrf_spis_int_mask_t spis_int);
/**
* @brief Function for enabling the SPIS peripheral.
*
* @param[in] p_spis SPIS instance.
*/
__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_spis);
/**
* @brief Function for disabling the SPIS peripheral.
*
* @param[in] p_spis SPIS instance.
*/
__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_spis);
/**
* @brief Function for retrieving the SPIS semaphore status.
*
* @param[in] p_spis SPIS instance.
*
* @returns Current semaphore status.
*/
__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_spis);
/**
* @brief Function for retrieving the SPIS status.
*
* @param[in] p_spis SPIS instance.
*
* @returns Current SPIS status.
*/
__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_spis);
/**
* @brief Function for configuring SPIS pins.
*
* If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_spis SPIS instance.
* @param[in] sck_pin SCK pin number.
* @param[in] mosi_pin MOSI pin number.
* @param[in] miso_pin MISO pin number.
* @param[in] csn_pin CSN pin number.
*/
__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_spis,
uint32_t sck_pin,
uint32_t mosi_pin,
uint32_t miso_pin,
uint32_t csn_pin);
/**
* @brief Function for setting the transmit buffer.
*
* @param[in] p_spis SPIS instance.
* @param[in] p_buffer Pointer to the buffer that contains the data to send.
* @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_spis,
uint8_t const * p_buffer,
uint8_t length);
/**
* @brief Function for setting the receive buffer.
*
* @param[in] p_spis SPIS instance.
* @param[in] p_buffer Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_spis,
uint8_t * p_buffer,
uint8_t length);
/**
* @brief Function for getting the number of bytes transmitted
* in the last granted transaction.
*
* @param[in] p_spis SPIS instance.
*
* @returns Number of bytes transmitted.
*/
__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_spis);
/**
* @brief Function for getting the number of bytes received
* in the last granted transaction.
*
* @param[in] p_spis SPIS instance.
*
* @returns Number of bytes received.
*/
__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_spis);
/**
* @brief Function for setting the SPI configuration.
*
* @param[in] p_spis SPIS instance.
* @param[in] spi_mode SPI mode.
* @param[in] spi_bit_order SPI bit order.
*/
__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_spis,
nrf_spis_mode_t spi_mode,
nrf_spis_bit_order_t spi_bit_order);
/**
* @brief Function for setting the default character.
*
* @param[in] p_spis SPIS instance.
* @param[in] def Default character that is clocked out in case of
* an overflow of the RXD buffer.
*/
__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_spis,
uint8_t def);
/**
* @brief Function for setting the over-read character.
*
* @param[in] p_spis SPIS instance.
* @param[in] orc Over-read character that is clocked out in case of
* an over-read of the TXD buffer.
*/
__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_spis,
uint8_t orc);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_spis,
nrf_spis_task_t spis_task)
{
*((volatile uint32_t *)((uint8_t *)p_spis + (uint32_t)spis_task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_spis,
nrf_spis_task_t spis_task)
{
return (uint32_t)p_spis + (uint32_t)spis_task;
}
__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_spis,
nrf_spis_event_t spis_event)
{
*((volatile uint32_t *)((uint8_t *)p_spis + (uint32_t)spis_event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_spis,
nrf_spis_event_t spis_event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_spis + (uint32_t)spis_event);
}
__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_spis,
nrf_spis_event_t spis_event)
{
return (uint32_t)p_spis + (uint32_t)spis_event;
}
__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_spis,
uint32_t spis_shorts_mask)
{
p_spis->SHORTS |= spis_shorts_mask;
}
__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_spis,
uint32_t spis_shorts_mask)
{
p_spis->SHORTS &= ~(spis_shorts_mask);
}
__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_spis,
uint32_t spis_int_mask)
{
p_spis->INTENSET = spis_int_mask;
}
__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_spis,
uint32_t spis_int_mask)
{
p_spis->INTENCLR = spis_int_mask;
}
__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_spis,
nrf_spis_int_mask_t spis_int)
{
return (bool)(p_spis->INTENSET & spis_int);
}
__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_spis)
{
p_spis->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_spis)
{
p_spis->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_spis)
{
return (nrf_spis_semstat_t) ((p_spis->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk)
>> SPIS_SEMSTAT_SEMSTAT_Pos);
}
__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_spis)
{
return (nrf_spis_status_mask_t) p_spis->STATUS;
}
__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_spis,
uint32_t sck_pin,
uint32_t mosi_pin,
uint32_t miso_pin,
uint32_t csn_pin)
{
p_spis->PSELSCK = sck_pin;
p_spis->PSELMOSI = mosi_pin;
p_spis->PSELMISO = miso_pin;
p_spis->PSELCSN = csn_pin;
}
__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_spis,
uint8_t const * p_buffer,
uint8_t length)
{
p_spis->TXDPTR = (uint32_t)p_buffer;
p_spis->MAXTX = length;
}
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_spis,
uint8_t * p_buffer,
uint8_t length)
{
p_spis->RXDPTR = (uint32_t)p_buffer;
p_spis->MAXRX = length;
}
__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_spis)
{
return (uint8_t) p_spis->AMOUNTRX;
}
__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_spis)
{
return (uint8_t) p_spis->AMOUNTTX;
}
__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_spis,
nrf_spis_mode_t spi_mode,
nrf_spis_bit_order_t spi_bit_order)
{
uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ?
SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst);
switch (spi_mode)
{
default:
case NRF_SPIS_MODE_0:
config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
(SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
break;
case NRF_SPIS_MODE_1:
config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
(SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
break;
case NRF_SPIS_MODE_2:
config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
(SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
break;
case NRF_SPIS_MODE_3:
config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
(SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
break;
}
p_spis->CONFIG = config;
}
__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_spis,
uint8_t orc)
{
p_spis->ORC = orc;
}
__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_spis,
uint8_t def)
{
p_spis->DEF = def;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_SPIS_H__
/** @} */

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/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_TEMP_H__
#define NRF_TEMP_H__
#include "nrf.h"
/**
* @defgroup nrf_temperature TEMP (temperature) abstraction
* @{
* @ingroup nrf_drivers temperature_example
* @brief Temperature module init and read functions.
*
*/
/**@cond NO_DOXYGEN */
#define MASK_SIGN (0x00000200UL)
#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
/**
* @brief Function for preparing the temp module for temperature measurement.
*
* This function initializes the TEMP module and writes to the hidden configuration register.
*/
static __INLINE void nrf_temp_init(void)
{
/**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */
*(uint32_t *) 0x4000C504 = 0;
}
/**
* @brief Function for reading temperature measurement.
*
* The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value.
*/
static __INLINE int32_t nrf_temp_read(void)
{
/**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */
return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP);
}
/**@endcond */
/** @} */
#endif

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @defgroup nrf_timer_hal Timer HAL
* @{
* @ingroup nrf_timer
*
* @brief Hardware access layer for accessing the timer peripheral.
*/
#ifndef NRF_TIMER_H__
#define NRF_TIMER_H__
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "nrf.h"
#include "nrf_assert.h"
/**
* @brief Macro for validating the correctness of the BIT_WIDTH setting.
*/
#ifdef NRF51
/**
* In the nRF51 Series, timer instance 0 supports all available bit widths.
* The other two instances support only 8 and 16 bits.
*/
#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_timer, bit_width) \
((p_timer == NRF_TIMER0) || (bit_width <= NRF_TIMER_BIT_WIDTH_16))
#else
/**
* In the nRF52 Series, all timer instances support all available bit widths.
*/
#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_timer, bit_width) true
#endif
/**
* @brief Macro for getting the number of capture/compare channels available
* in a given timer instance.
*/
#ifdef NRF51
#define NRF_TIMER_CC_CHANNEL_COUNT(id) 4
#else
#define NRF_TIMER_CC_CHANNEL_COUNT(id) ((id) <= 2 ? 4 : 6)
#endif
/**
* @brief Timer tasks.
*/
typedef enum
{
/*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_TIMER_TASK_START = offsetof(NRF_TIMER_Type, TASKS_START), ///< Task for starting the timer.
NRF_TIMER_TASK_STOP = offsetof(NRF_TIMER_Type, TASKS_STOP), ///< Task for stopping the timer.
NRF_TIMER_TASK_COUNT = offsetof(NRF_TIMER_Type, TASKS_COUNT), ///< Task for incrementing the timer (in counter mode).
NRF_TIMER_TASK_CLEAR = offsetof(NRF_TIMER_Type, TASKS_CLEAR), ///< Task for resetting the timer value.
NRF_TIMER_TASK_SHUTDOWN = offsetof(NRF_TIMER_Type, TASKS_SHUTDOWN), ///< Task for powering off the timer.
NRF_TIMER_TASK_CAPTURE0 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[0]), ///< Task for capturing the timer value on channel 0.
NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1.
NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2.
NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3.
#ifdef NRF52
NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4.
NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5.
#endif
/*lint -restore*/
} nrf_timer_task_t;
/**
* @brief Timer events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_TIMER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0.
NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1.
NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2.
NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3.
#ifdef NRF52
NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4.
NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5.
#endif
/*lint -restore*/
} nrf_timer_event_t;
/**
* @brief Types of timer shortcuts.
*/
typedef enum
{
NRF_TIMER_SHORT_COMPARE0_STOP_MASK = TIMER_SHORTS_COMPARE0_STOP_Msk, ///< Shortcut for stopping the timer based on compare 0.
NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk, ///< Shortcut for stopping the timer based on compare 1.
NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk, ///< Shortcut for stopping the timer based on compare 2.
NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk, ///< Shortcut for stopping the timer based on compare 3.
#ifdef NRF52
NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk, ///< Shortcut for stopping the timer based on compare 4.
NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk, ///< Shortcut for stopping the timer based on compare 5.
#endif
NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0.
NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1.
NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2.
NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3.
#ifdef NRF52
NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4.
NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5.
#endif
} nrf_timer_short_mask_t;
/**
* @brief Timer modes.
*/
typedef enum
{
NRF_TIMER_MODE_TIMER = TIMER_MODE_MODE_Timer, ///< Timer mode: timer.
NRF_TIMER_MODE_COUNTER = TIMER_MODE_MODE_Counter, ///< Timer mode: counter.
#ifdef NRF52
NRF_TIMER_MODE_LOW_POWER_COUNTER = TIMER_MODE_MODE_LowPowerCounter, ///< Timer mode: low-power counter.
#endif
} nrf_timer_mode_t;
/**
* @brief Timer bit width.
*/
typedef enum
{
NRF_TIMER_BIT_WIDTH_8 = TIMER_BITMODE_BITMODE_08Bit, ///< Timer bit width 8 bit.
NRF_TIMER_BIT_WIDTH_16 = TIMER_BITMODE_BITMODE_16Bit, ///< Timer bit width 16 bit.
NRF_TIMER_BIT_WIDTH_24 = TIMER_BITMODE_BITMODE_24Bit, ///< Timer bit width 24 bit.
NRF_TIMER_BIT_WIDTH_32 = TIMER_BITMODE_BITMODE_32Bit ///< Timer bit width 32 bit.
} nrf_timer_bit_width_t;
/**
* @brief Timer prescalers.
*/
typedef enum
{
NRF_TIMER_FREQ_16MHz = 0, ///< Timer frequency 16 MHz.
NRF_TIMER_FREQ_8MHz, ///< Timer frequency 8 MHz.
NRF_TIMER_FREQ_4MHz, ///< Timer frequency 4 MHz.
NRF_TIMER_FREQ_2MHz, ///< Timer frequency 2 MHz.
NRF_TIMER_FREQ_1MHz, ///< Timer frequency 1 MHz.
NRF_TIMER_FREQ_500kHz, ///< Timer frequency 500 kHz.
NRF_TIMER_FREQ_250kHz, ///< Timer frequency 250 kHz.
NRF_TIMER_FREQ_125kHz, ///< Timer frequency 125 kHz.
NRF_TIMER_FREQ_62500Hz, ///< Timer frequency 62500 Hz.
NRF_TIMER_FREQ_31250Hz ///< Timer frequency 31250 Hz.
} nrf_timer_frequency_t;
/**
* @brief Timer capture/compare channels.
*/
typedef enum
{
NRF_TIMER_CC_CHANNEL0 = 0, ///< Timer capture/compare channel 0.
NRF_TIMER_CC_CHANNEL1, ///< Timer capture/compare channel 1.
NRF_TIMER_CC_CHANNEL2, ///< Timer capture/compare channel 2.
NRF_TIMER_CC_CHANNEL3, ///< Timer capture/compare channel 3.
#ifdef NRF52
NRF_TIMER_CC_CHANNEL4, ///< Timer capture/compare channel 4.
NRF_TIMER_CC_CHANNEL5, ///< Timer capture/compare channel 5.
#endif
} nrf_timer_cc_channel_t;
/**
* @brief Timer interrupts.
*/
typedef enum
{
NRF_TIMER_INT_COMPARE0_MASK = TIMER_INTENSET_COMPARE0_Msk, ///< Timer interrupt from compare event on channel 0.
NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1.
NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2.
NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3.
#ifdef NRF52
NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4.
NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5.
#endif
} nrf_timer_int_mask_t;
/**
* @brief Function for activating a specific timer task.
*
* @param[in] p_timer Timer instance.
* @param[in] task Task to activate.
*/
__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_timer,
nrf_timer_task_t task);
/**
* @brief Function for getting the address of a specific timer task register.
*
* @param[in] p_timer Timer instance.
* @param[in] task Requested task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_timer,
nrf_timer_task_t task);
/**
* @brief Function for clearing a specific timer event.
*
* @param[in] p_timer Timer instance.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_timer,
nrf_timer_event_t event);
/**
* @brief Function for checking the state of a specific timer event.
*
* @param[in] p_timer Timer instance.
* @param[in] event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_timer,
nrf_timer_event_t event);
/**
* @brief Function for getting the address of a specific timer event register.
*
* @param[in] p_timer Timer instance.
* @param[in] event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_timer,
nrf_timer_event_t event);
/**
* @brief Function for enabling specified shortcuts.
*
* @param[in] p_timer Timer instance.
* @param[in] timer_shorts_mask Shortcuts to enable.
*/
__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_timer,
uint32_t timer_shorts_mask);
/**
* @brief Function for disabling specified shortcuts.
*
* @param[in] p_timer Timer instance.
* @param[in] timer_shorts_mask Shortcuts to disable.
*/
__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_timer,
uint32_t timer_shorts_mask);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_timer Timer instance.
* @param[in] timer_int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_timer,
uint32_t timer_int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_timer Timer instance.
* @param[in] timer_int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_timer,
uint32_t timer_int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_timer Timer instance.
* @param[in] timer_int Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_timer,
uint32_t timer_int);
/**
* @brief Function for setting the timer mode.
*
* @param[in] p_timer Timer instance.
* @param[in] mode Timer mode.
*/
__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_timer,
nrf_timer_mode_t mode);
/**
* @brief Function for retrieving the timer mode.
*
* @param[in] p_timer Timer instance.
*
* @return Timer mode.
*/
__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_timer);
/**
* @brief Function for setting the timer bit width.
*
* @param[in] p_timer Timer instance.
* @param[in] bit_width Timer bit width.
*/
__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_timer,
nrf_timer_bit_width_t bit_width);
/**
* @brief Function for retrieving the timer bit width.
*
* @param[in] p_timer Timer instance.
*
* @return Timer bit width.
*/
__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_timer);
/**
* @brief Function for setting the timer frequency.
*
* @param[in] p_timer Timer instance.
* @param[in] frequency Timer frequency.
*/
__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_timer,
nrf_timer_frequency_t frequency);
/**
* @brief Function for retrieving the timer frequency.
*
* @param[in] p_timer Timer instance.
*
* @return Timer frequency.
*/
__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_timer);
/**
* @brief Function for writing the capture/compare register for a specified channel.
*
* @param[in] p_timer Timer instance.
* @param[in] cc_channel Requested capture/compare channel.
* @param[in] cc_value Value to write to the capture/compare register.
*/
__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_timer,
nrf_timer_cc_channel_t cc_channel,
uint32_t cc_value);
/**
* @brief Function for retrieving the capture/compare value for a specified channel.
*
* @param[in] p_timer Timer instance.
* @param[in] cc_channel Requested capture/compare channel.
*
* @return Value from the requested capture/compare register.
*/
__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_timer,
nrf_timer_cc_channel_t cc_channel);
/**
* @brief Function for getting a specific timer capture task.
*
* @param[in] channel Capture channel.
*
* @return Capture task.
*/
__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel);
/**
* @brief Function for getting a specific timer compare event.
*
* @param[in] channel Compare channel.
*
* @return Compare event.
*/
__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel);
/**
* @brief Function for getting a specific timer compare interrupt.
*
* @param[in] channel Compare channel.
*
* @return Compare interrupt.
*/
__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel);
/**
* @brief Function for calculating the number of timer ticks for a given time
* (in microseconds) and timer frequency.
*
* @param[in] time_us Time in microseconds.
* @param[in] frequency Timer frequency.
*
* @return Number of timer ticks.
*/
__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
nrf_timer_frequency_t frequency);
/**
* @brief Function for calculating the number of timer ticks for a given time
* (in milliseconds) and timer frequency.
*
* @param[in] time_ms Time in milliseconds.
* @param[in] frequency Timer frequency.
*
* @return Number of timer ticks.
*/
__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
nrf_timer_frequency_t frequency);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_timer,
nrf_timer_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_timer + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_timer,
nrf_timer_task_t task)
{
return (uint32_t *)((uint8_t *)p_timer + (uint32_t)task);
}
__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_timer,
nrf_timer_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_timer + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_timer,
nrf_timer_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_timer + (uint32_t)event);
}
__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_timer,
nrf_timer_event_t event)
{
return (uint32_t *)((uint8_t *)p_timer + (uint32_t)event);
}
__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_timer,
uint32_t timer_shorts_mask)
{
p_timer->SHORTS |= timer_shorts_mask;
}
__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_timer,
uint32_t timer_shorts_mask)
{
p_timer->SHORTS &= ~(timer_shorts_mask);
}
__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_timer,
uint32_t timer_int_mask)
{
p_timer->INTENSET = timer_int_mask;
}
__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_timer,
uint32_t timer_int_mask)
{
p_timer->INTENCLR = timer_int_mask;
}
__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_timer,
uint32_t timer_int)
{
return (bool)(p_timer->INTENSET & timer_int);
}
__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_timer,
nrf_timer_mode_t mode)
{
p_timer->MODE = (p_timer->MODE & ~TIMER_MODE_MODE_Msk) |
((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk);
}
__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_timer)
{
return (nrf_timer_mode_t)(p_timer->MODE);
}
__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_timer,
nrf_timer_bit_width_t bit_width)
{
p_timer->BITMODE = (p_timer->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) |
((bit_width << TIMER_BITMODE_BITMODE_Pos) &
TIMER_BITMODE_BITMODE_Msk);
}
__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_timer)
{
return (nrf_timer_bit_width_t)(p_timer->BITMODE);
}
__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_timer,
nrf_timer_frequency_t frequency)
{
p_timer->PRESCALER = (p_timer->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) |
((frequency << TIMER_PRESCALER_PRESCALER_Pos) &
TIMER_PRESCALER_PRESCALER_Msk);
}
__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_timer)
{
return (nrf_timer_frequency_t)(p_timer->PRESCALER);
}
__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_timer,
nrf_timer_cc_channel_t cc_channel,
uint32_t cc_value)
{
p_timer->CC[cc_channel] = cc_value;
}
__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_timer,
nrf_timer_cc_channel_t cc_channel)
{
return (uint32_t)p_timer->CC[cc_channel];
}
__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel)
{
return (nrf_timer_task_t)
((uint32_t)NRF_TIMER_TASK_CAPTURE0 + (channel * sizeof(uint32_t)));
}
__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel)
{
return (nrf_timer_event_t)
((uint32_t)NRF_TIMER_EVENT_COMPARE0 + (channel * sizeof(uint32_t)));
}
__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel)
{
return (nrf_timer_int_mask_t)
((uint32_t)NRF_TIMER_INT_COMPARE0_MASK << channel);
}
__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
nrf_timer_frequency_t frequency)
{
// The "frequency" parameter here is actually the prescaler value, and the
// timer runs at the following frequency: f = 16 MHz / 2^prescaler.
uint32_t prescaler = (uint32_t)frequency;
ASSERT(time_us <= (UINT32_MAX / 16UL));
return ((time_us * 16UL) >> prescaler);
}
__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
nrf_timer_frequency_t frequency)
{
// The "frequency" parameter here is actually the prescaler value, and the
// timer runs at the following frequency: f = 16000 kHz / 2^prescaler.
uint32_t prescaler = (uint32_t)frequency;
ASSERT(time_ms <= (UINT32_MAX / 16000UL));
return ((time_ms * 16000UL) >> prescaler);
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_TIMER_H__
/** @} */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_TWI_H__
#define NRF_TWI_H__
/**
* @defgroup nrf_twi_hal TWI HAL
* @{
* @ingroup nrf_twi_master
*
* @brief Hardware access layer for managing the TWI peripheral.
*/
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include "nrf.h"
/**
* @brief TWI tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_TWI_TASK_STARTRX = offsetof(NRF_TWI_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
NRF_TWI_TASK_STARTTX = offsetof(NRF_TWI_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
NRF_TWI_TASK_STOP = offsetof(NRF_TWI_Type, TASKS_STOP), ///< Stop TWI transaction.
NRF_TWI_TASK_SUSPEND = offsetof(NRF_TWI_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
NRF_TWI_TASK_RESUME = offsetof(NRF_TWI_Type, TASKS_RESUME) ///< Resume TWI transaction.
/*lint -restore*/
} nrf_twi_task_t;
/**
* @brief TWI events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_TWI_EVENT_STOPPED = offsetof(NRF_TWI_Type, EVENTS_STOPPED), ///< TWI stopped.
NRF_TWI_EVENT_RXDREADY = offsetof(NRF_TWI_Type, EVENTS_RXDREADY), ///< TWI RXD byte received.
NRF_TWI_EVENT_TXDSENT = offsetof(NRF_TWI_Type, EVENTS_TXDSENT), ///< TWI TXD byte sent.
NRF_TWI_EVENT_ERROR = offsetof(NRF_TWI_Type, EVENTS_ERROR), ///< TWI error.
NRF_TWI_EVENT_BB = offsetof(NRF_TWI_Type, EVENTS_BB), ///< TWI byte boundary, generated before each byte that is sent or received.
NRF_TWI_EVENT_SUSPENDED = offsetof(NRF_TWI_Type, EVENTS_SUSPENDED) ///< TWI entered the suspended state.
/*lint -restore*/
} nrf_twi_event_t;
/**
* @brief TWI shortcuts.
*/
typedef enum
{
NRF_TWI_SHORT_BB_SUSPEND_MASK = TWI_SHORTS_BB_SUSPEND_Msk, ///< Shortcut between BB event and SUSPEND task.
NRF_TWI_SHORT_BB_STOP_MASK = TWI_SHORTS_BB_STOP_Msk, ///< Shortcut between BB event and STOP task.
} nrf_twi_short_mask_t;
/**
* @brief TWI interrupts.
*/
typedef enum
{
NRF_TWI_INT_STOPPED_MASK = TWI_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
NRF_TWI_INT_RXDREADY_MASK = TWI_INTENSET_RXDREADY_Msk, ///< Interrupt on RXDREADY event.
NRF_TWI_INT_TXDSENT_MASK = TWI_INTENSET_TXDSENT_Msk, ///< Interrupt on TXDSENT event.
NRF_TWI_INT_ERROR_MASK = TWI_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
NRF_TWI_INT_BB_MASK = TWI_INTENSET_BB_Msk, ///< Interrupt on BB event.
NRF_TWI_INT_SUSPENDED_MASK = TWI_INTENSET_SUSPENDED_Msk ///< Interrupt on SUSPENDED event.
} nrf_twi_int_mask_t;
/**
* @brief TWI error source.
*/
typedef enum
{
NRF_TWI_ERROR_ADDRESS_NACK = TWI_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
NRF_TWI_ERROR_DATA_NACK = TWI_ERRORSRC_DNACK_Msk, ///< NACK received after sending a data byte.
NRF_TWI_ERROR_OVERRUN = TWI_ERRORSRC_OVERRUN_Msk ///< Overrun error.
/**< A new byte was received before the previous byte was read
* from the RXD register (previous data is lost). */
} nrf_twi_error_t;
/**
* @brief TWI master clock frequency.
*/
typedef enum
{
NRF_TWI_FREQ_100K = TWI_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
NRF_TWI_FREQ_250K = TWI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
NRF_TWI_FREQ_400K = TWI_FREQUENCY_FREQUENCY_K400 ///< 400 kbps.
} nrf_twi_frequency_t;
/**
* @brief Function for activating a specific TWI task.
*
* @param[in] p_twi TWI instance.
* @param[in] task Task to activate.
*/
__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_twi,
nrf_twi_task_t task);
/**
* @brief Function for getting the address of a specific TWI task register.
*
* @param[in] p_twi TWI instance.
* @param[in] task Requested task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_twi,
nrf_twi_task_t task);
/**
* @brief Function for clearing a specific TWI event.
*
* @param[in] p_twi TWI instance.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_twi,
nrf_twi_event_t event);
/**
* @brief Function for checking the state of a specific event.
*
* @param[in] p_twi TWI instance.
* @param[in] event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_twi,
nrf_twi_event_t event);
/**
* @brief Function for getting the address of a specific TWI event register.
*
* @param[in] p_twi TWI instance.
* @param[in] event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_twi,
nrf_twi_event_t event);
/**
* @brief Function for enabling specified shortcuts.
*
* @param[in] p_twi TWI instance.
* @param[in] shorts_mask Shortcuts to enable.
*/
__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_twi,
uint32_t shorts_mask);
/**
* @brief Function for disabling specified shortcuts.
*
* @param[in] p_twi TWI instance.
* @param[in] shorts_mask Shortcuts to disable.
*/
__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_twi,
uint32_t shorts_mask);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_twi TWI instance.
* @param[in] int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_twi,
uint32_t int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_twi TWI instance.
* @param[in] int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_twi,
uint32_t int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_twi TWI instance.
* @param[in] int_mask Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_twi,
nrf_twi_int_mask_t int_mask);
/**
* @brief Function for enabling the TWI peripheral.
*
* @param[in] p_twi TWI instance.
*/
__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_twi);
/**
* @brief Function for disabling the TWI peripheral.
*
* @param[in] p_twi TWI instance.
*/
__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_twi);
/**
* @brief Function for configuring TWI pins.
*
*
* @param[in] p_twi TWI instance.
* @param[in] scl_pin SCL pin number.
* @param[in] sda_pin SDA pin number.
*/
__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_twi,
uint32_t scl_pin,
uint32_t sda_pin);
/**
* @brief Function for setting the TWI master clock frequency.
*
* @param[in] p_twi TWI instance.
* @param[in] frequency TWI frequency.
*/
__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_twi,
nrf_twi_frequency_t frequency);
/**
* @brief Function for checking the TWI error source.
*
* The error flags are cleared after reading.
*
* @param[in] p_twi TWI instance.
*
* @return Mask with error source flags.
*/
__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_twi);
/**
* @brief Function for setting the address to be used in TWI transfers.
*
* @param[in] p_twi TWI instance.
* @param[in] address Address to be used in transfers.
*/
__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_twi, uint8_t address);
/**
* @brief Function for reading data received by TWI.
*
* @param[in] p_twi TWI instance.
*
* @return Received data.
*/
__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_twi);
/**
* @brief Function for writing data to be transmitted by TWI.
*
* @param[in] p_twi TWI instance.
* @param[in] data Data to be transmitted.
*/
__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_twi, uint8_t data);
__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_twi,
uint32_t shorts_mask);
/**
* @}
*/
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_twi,
nrf_twi_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_twi + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_twi,
nrf_twi_task_t task)
{
return (uint32_t *)((uint8_t *)p_twi + (uint32_t)task);
}
__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_twi,
nrf_twi_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_twi + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_twi,
nrf_twi_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_twi + (uint32_t)event);
}
__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_twi,
nrf_twi_event_t event)
{
return (uint32_t *)((uint8_t *)p_twi + (uint32_t)event);
}
__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_twi,
uint32_t shorts_mask)
{
p_twi->SHORTS |= shorts_mask;
}
__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_twi,
uint32_t shorts_mask)
{
p_twi->SHORTS &= ~(shorts_mask);
}
__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_twi,
uint32_t int_mask)
{
p_twi->INTENSET = int_mask;
}
__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_twi,
uint32_t int_mask)
{
p_twi->INTENCLR = int_mask;
}
__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_twi,
nrf_twi_int_mask_t int_mask)
{
return (bool)(p_twi->INTENSET & int_mask);
}
__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_twi)
{
p_twi->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_twi)
{
p_twi->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_twi,
uint32_t scl_pin,
uint32_t sda_pin)
{
p_twi->PSELSCL = scl_pin;
p_twi->PSELSDA = sda_pin;
}
__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_twi,
nrf_twi_frequency_t frequency)
{
p_twi->FREQUENCY = frequency;
}
__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_twi)
{
uint32_t error_source = p_twi->ERRORSRC;
// [error flags are cleared by writing '1' on their position]
p_twi->ERRORSRC = error_source;
return error_source;
}
__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_twi, uint8_t address)
{
p_twi->ADDRESS = address;
}
__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_twi)
{
return (uint8_t)p_twi->RXD;
}
__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_twi, uint8_t data)
{
p_twi->TXD = data;
}
__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_twi,
uint32_t shorts_mask)
{
p_twi->SHORTS = shorts_mask;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_TWI_H__

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_TWIM_H__
#define NRF_TWIM_H__
/**
* @defgroup nrf_twim_hal TWIM HAL
* @{
* @ingroup nrf_twi_master
*
* @brief Hardware access layer for managing the TWIM peripheral.
*/
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include "nrf.h"
/**
* @brief TWIM tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
NRF_TWIM_TASK_STOP = offsetof(NRF_TWIM_Type, TASKS_STOP), ///< Stop TWI transaction.
NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
NRF_TWIM_TASK_RESUME = offsetof(NRF_TWIM_Type, TASKS_RESUME) ///< Resume TWI transaction.
/*lint -restore*/
} nrf_twim_task_t;
/**
* @brief TWIM events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped.
NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error.
NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended.
NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started.
NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started.
NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte.
NRF_TWIM_EVENT_LASTTX = offsetof(NRF_TWIM_Type, EVENTS_LASTTX) ///< Byte boundary, starting to transmit the last byte.
/*lint -restore*/
} nrf_twim_event_t;
/**
* @brief TWIM shortcuts.
*/
typedef enum
{
NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task.
NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK = TWIM_SHORTS_LASTTX_SUSPEND_Msk, ///< Shortcut between LASTTX event and SUSPEND task.
NRF_TWIM_SHORT_LASTTX_STOP_MASK = TWIM_SHORTS_LASTTX_STOP_Msk, ///< Shortcut between LASTTX event and STOP task.
NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_STARTTX_Msk, ///< Shortcut between LASTRX event and STARTTX task.
NRF_TWIM_SHORT_LASTRX_STOP_MASK = TWIM_SHORTS_LASTRX_STOP_Msk ///< Shortcut between LASTRX event and STOP task.
} nrf_twim_short_mask_t;
/**
* @brief TWIM interrupts.
*/
typedef enum
{
NRF_TWIM_INT_STOPPED_MASK = TWIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
NRF_TWIM_INT_ERROR_MASK = TWIM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
NRF_TWIM_INT_SUSPENDED_MASK = (1 << 18), ///< Interrupt on SUSPENDED event.
NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
NRF_TWIM_INT_LASTRX_MASK = TWIM_INTENSET_LASTRX_Msk, ///< Interrupt on LASTRX event.
NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk ///< Interrupt on LASTTX event.
} nrf_twim_int_mask_t;
/**
* @brief TWIM master clock frequency.
*/
typedef enum
{
NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400 ///< 400 kbps.
} nrf_twim_frequency_t;
/**
* @brief TWIM error source.
*/
typedef enum
{
NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk ///< NACK received after sending a data byte.
} nrf_twim_error_t;
/**
* @brief Function for activating a specific TWIM task.
*
* @param[in] p_twim TWIM instance.
* @param[in] task Task to activate.
*/
__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_twim,
nrf_twim_task_t task);
/**
* @brief Function for getting the address of a specific TWIM task register.
*
* @param[in] p_twim TWIM instance.
* @param[in] task Requested task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_twim,
nrf_twim_task_t task);
/**
* @brief Function for clearing a specific TWIM event.
*
* @param[in] p_twim TWIM instance.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_twim,
nrf_twim_event_t event);
/**
* @brief Function for checking the state of a specific TWIM event.
*
* @param[in] p_twim TWIM instance.
* @param[in] event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_twim,
nrf_twim_event_t event);
/**
* @brief Function for getting the address of a specific TWIM event register.
*
* @param[in] p_twim TWIM instance.
* @param[in] event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_twim,
nrf_twim_event_t event);
/**
* @brief Function for enabling specified shortcuts.
*
* @param[in] p_twim TWIM instance.
* @param[in] shorts_mask Shortcuts to enable.
*/
__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_twim,
uint32_t shorts_mask);
/**
* @brief Function for disabling specified shortcuts.
*
* @param[in] p_twim TWIM instance.
* @param[in] shorts_mask Shortcuts to disable.
*/
__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_twim,
uint32_t shorts_mask);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_twim TWIM instance.
* @param[in] int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_twim,
uint32_t int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_twim TWIM instance.
* @param[in] int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_twim,
uint32_t int_mask);
/**
* @brief Function for checking the state of a given interrupt.
*
* @param[in] p_twim TWIM instance.
* @param[in] int_mask Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_twim,
nrf_twim_int_mask_t int_mask);
/**
* @brief Function for enabling the TWIM peripheral.
*
* @param[in] p_twim TWIM instance.
*/
__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_twim);
/**
* @brief Function for disabling the TWIM peripheral.
*
* @param[in] p_twim TWIM instance.
*/
__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_twim);
/**
* @brief Function for configuring TWI pins.
*
*
* @param[in] p_twim TWIM instance.
* @param[in] scl_pin SCL pin number.
* @param[in] sda_pin SDA pin number.
*/
__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_twim,
uint32_t scl_pin,
uint32_t sda_pin);
/**
* @brief Function for setting the TWI master clock frequency.
*
* @param[in] p_twim TWIM instance.
* @param[in] frequency TWI frequency.
*/
__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_twim,
nrf_twim_frequency_t frequency);
/**
* @brief Function for checking the TWI error source.
*
* The error flags are cleared after reading.
*
* @param[in] p_twim TWIM instance.
*
* @return Mask with error source flags.
*/
__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_twim);
/**
* @brief Function for setting the address to be used in TWI transfers.
*
* @param[in] p_twim TWIM instance.
* @param[in] address Address to be used in transfers.
*/
__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_twim,
uint8_t address);
/**
* @brief Function for setting the transmit buffer.
*
* @param[in] p_twim TWIM instance.
* @param[in] p_buffer Pointer to the buffer with data to send.
* @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_twim,
uint8_t const * p_buffer,
uint8_t length);
/**
* @brief Function for setting the receive buffer.
*
* @param[in] p_twim TWIM instance.
* @param[in] p_buffer Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_twim,
uint8_t * p_buffer,
uint8_t length);
__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_twim,
uint32_t shorts_mask);
__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_twim);
__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_twim);
/**
* @brief Function for enabling the TX list feature.
*
* @param[in] p_twim TWIM instance.
*/
__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_twim);
/**
* @brief Function for disabling the TX list feature.
*
* @param[in] p_twim TWIM instance.
*/
__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_twim);
/**
* @brief Function for enabling the RX list feature.
*
* @param[in] p_twim TWIM instance.
*/
__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_twim);
/**
* @brief Function for disabling the RX list feature.
*
* @param[in] p_twim TWIM instance.
*/
__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_twim);
/**
* @}
*/
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_twim,
nrf_twim_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_twim + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_twim,
nrf_twim_task_t task)
{
return (uint32_t *)((uint8_t *)p_twim + (uint32_t)task);
}
__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_twim,
nrf_twim_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_twim + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_twim,
nrf_twim_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_twim + (uint32_t)event);
}
__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_twim,
nrf_twim_event_t event)
{
return (uint32_t *)((uint8_t *)p_twim + (uint32_t)event);
}
__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_twim,
uint32_t shorts_mask)
{
p_twim->SHORTS |= shorts_mask;
}
__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_twim,
uint32_t shorts_mask)
{
p_twim->SHORTS &= ~(shorts_mask);
}
__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_twim,
uint32_t int_mask)
{
p_twim->INTENSET = int_mask;
}
__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_twim,
uint32_t int_mask)
{
p_twim->INTENCLR = int_mask;
}
__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_twim,
nrf_twim_int_mask_t int_mask)
{
return (bool)(p_twim->INTENSET & int_mask);
}
__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_twim)
{
p_twim->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_twim)
{
p_twim->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_twim,
uint32_t scl_pin,
uint32_t sda_pin)
{
p_twim->PSEL.SCL = scl_pin;
p_twim->PSEL.SDA = sda_pin;
}
__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_twim,
nrf_twim_frequency_t frequency)
{
p_twim->FREQUENCY = frequency;
}
__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_twim)
{
uint32_t error_source = p_twim->ERRORSRC;
// [error flags are cleared by writing '1' on their position]
p_twim->ERRORSRC = error_source;
return error_source;
}
__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_twim,
uint8_t address)
{
p_twim->ADDRESS = address;
}
__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_twim,
uint8_t const * p_buffer,
uint8_t length)
{
p_twim->TXD.PTR = (uint32_t)p_buffer;
p_twim->TXD.MAXCNT = length;
}
__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_twim,
uint8_t * p_buffer,
uint8_t length)
{
p_twim->RXD.PTR = (uint32_t)p_buffer;
p_twim->RXD.MAXCNT = length;
}
__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_twim,
uint32_t shorts_mask)
{
p_twim->SHORTS = shorts_mask;
}
__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_twim)
{
return p_twim->TXD.AMOUNT;
}
__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_twim)
{
return p_twim->RXD.AMOUNT;
}
__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_twim)
{
p_twim->TXD.LIST = 1;
}
__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_twim)
{
p_twim->TXD.LIST = 0;
}
__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_twim)
{
p_twim->RXD.LIST = 1;
}
__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_twim)
{
p_twim->RXD.LIST = 0;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_TWIM_H__

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @ingroup nrf_twis
* @defgroup nrf_twis_hal TWIS HAL
* @{
*
* @brief @tagAPI52 Hardware access layer for Two Wire Interface Slave with EasyDMA
* (TWIS) peripheral.
*/
#ifndef NRF_TWIS_H__
#define NRF_TWIS_H__
#include "nrf.h"
#include "nrf_drv_config.h"
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
/**
* @brief TWIS tasks
*/
typedef enum
{
/*lint -save -e30*/
#ifndef NRF52_PAN_30 /* STOP task is not functional in MPW3 (PAN-30) */
/* Stop task is not working properly for first release */
NRF_TWIS_TASK_STOP = offsetof(NRF_TWIS_Type, TASKS_STOP), /**< Stop TWIS transaction */
#endif
NRF_TWIS_TASK_SUSPEND = offsetof(NRF_TWIS_Type, TASKS_SUSPEND), /**< Suspend TWIS transaction */
NRF_TWIS_TASK_RESUME = offsetof(NRF_TWIS_Type, TASKS_RESUME), /**< Resume TWIS transaction */
NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command */
NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX) /**< Prepare the TWIS slave to respond to a read command */
/*lint -restore*/
} nrf_twis_task_t;
/**
* @brief TWIS events
*/
typedef enum
{
/*lint -save -e30*/
NRF_TWIS_EVENT_STOPPED = offsetof(NRF_TWIS_Type, EVENTS_STOPPED), /**< TWIS stopped */
NRF_TWIS_EVENT_ERROR = offsetof(NRF_TWIS_Type, EVENTS_ERROR), /**< TWIS error */
NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started */
NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started */
NRF_TWIS_EVENT_WRITE = offsetof(NRF_TWIS_Type, EVENTS_WRITE), /**< Write command received */
NRF_TWIS_EVENT_READ = offsetof(NRF_TWIS_Type, EVENTS_READ) /**< Read command received */
/*lint -restore*/
} nrf_twis_event_t;
/**
* @brief TWIS shortcuts
*/
typedef enum
{
NRF_TWIS_SHORT_WRITE_SUSPEND_MASK = TWIS_SHORTS_WRITE_SUSPEND_Msk, /**< Shortcut between WRITE event and SUSPEND task */
NRF_TWIS_SHORT_READ_SUSPEND_MASK = TWIS_SHORTS_READ_SUSPEND_Msk, /**< Shortcut between READ event and SUSPEND task */
} nrf_twis_short_mask_t;
/**
* @brief TWIS interrupts
*/
typedef enum
{
NRF_TWIS_INT_STOPPED_MASK = TWIS_INTEN_STOPPED_Msk, /**< Interrupt on STOPPED event */
NRF_TWIS_INT_ERROR_MASK = TWIS_INTEN_ERROR_Msk, /**< Interrupt on ERROR event */
NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event */
NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event */
NRF_TWIS_INT_WRITE_MASK = TWIS_INTEN_WRITE_Msk, /**< Interrupt on WRITE event */
NRF_TWIS_INT_READ_MASK = TWIS_INTEN_READ_Msk, /**< Interrupt on READ event */
} nrf_twis_int_mask_t;
/**
* @brief TWIS error source
*/
typedef enum
{
NRF_TWIS_ERROR_OVERFLOW = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented */
#ifdef NRF52_PAN_29
/* Patched version of bit positions in ERRORSRC register (PAN-29) */
NRF_TWIS_ERROR_DATA_NACK = 1U << 1, /**< NACK sent after receiving a data byte */
NRF_TWIS_ERROR_OVERREAD = 1U << 2 /**< TX buffer over-read detected, and prevented */
#else
/* Code that meets current documentation */
NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk, /**< NACK sent after receiving a data byte */
NRF_TWIS_ERROR_OVERREAD = TWIS_ERRORSRC_OVERREAD_Msk /**< TX buffer over-read detected, and prevented */
#endif
} nrf_twis_error_t;
/**
* @brief TWIS address matching configuration
*/
typedef enum
{
NRF_TWIS_CONFIG_ADDRESS0_MASK = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0] */
NRF_TWIS_CONFIG_ADDRESS1_MASK = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1] */
NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching */
} nrf_twis_config_addr_mask_t;
/**
* @brief Variable type to hold amount of data for EasyDMA
*
* Variable of the minimum size that can hold the amount of data to transfer.
*
* @note
* Defined to make it simple to change if EasyDMA would be updated to support more data in
* the future devices to.
*/
typedef uint8_t nrf_twis_amount_t;
/**
* @brief Smallest variable type to hold TWI address
*
* Variable of the minimum size that can hold single TWI address.
*
* @note
* Defined to make it simple to change if new TWI would support for example
* 10 bit addressing mode.
*/
typedef uint8_t nrf_twis_address_t;
/**
* @brief Function for activating a specific TWIS task.
*
* @param[in] p_twis TWIS instance.
* @param task Task.
*/
__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * const p_twis, nrf_twis_task_t task);
/**
* @brief Function for returning the address of a specific TWIS task register.
*
* @param[in] p_twis TWIS instance.
* @param task Task.
*
* @return Task address.
*/
__STATIC_INLINE uint32_t nrf_twis_task_address_get(
NRF_TWIS_Type const * const p_twis,
nrf_twis_task_t task);
/**
* @brief Function for clearing a specific event.
*
* @param[in] p_twis TWIS instance.
* @param event Event.
*/
__STATIC_INLINE void nrf_twis_event_clear(
NRF_TWIS_Type * const p_twis,
nrf_twis_event_t event);
/**
* @brief Function for returning the state of a specific event.
*
* @param[in] p_twis TWIS instance.
* @param event Event.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_twis_event_check(
NRF_TWIS_Type const * const p_twis,
nrf_twis_event_t event);
/**
* @brief Function for getting and clearing the state of specific event
*
* This function checks the state of the event and clears it.
* @param[in,out] p_twis TWIS instance
* @param event Event.
*
* @retval true If the event was set.
* @retval false If the event was not set.
*/
__STATIC_INLINE bool nrf_twis_event_get_and_clear(
NRF_TWIS_Type * const p_twis,
nrf_twis_event_t event);
/**
* @brief Function for returning the address of a specific TWIS event register.
*
* @param[in] p_twis TWIS instance.
* @param event Event.
*
* @return Address.
*/
__STATIC_INLINE uint32_t nrf_twis_event_address_get(
NRF_TWIS_Type const * const p_twis,
nrf_twis_event_t event);
/**
* @brief Function for setting a shortcut.
*
* @param[in] p_twis TWIS instance.
* @param short_mask Shortcuts mask.
*/
__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_twis, uint32_t short_mask);
/**
* @brief Function for clearing shortcuts.
*
* @param[in] p_twis TWIS instance.
* @param short_mask Shortcuts mask.
*/
__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_twis, uint32_t short_mask);
/**
* @brief Get the shorts mask
*
* Function returns shorts register.
* @param[in] p_twis TWIS instance.
* @return Flags of currently enabled shortcuts
*/
__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_twis);
/**
* @brief Function for enabling selected interrupts.
*
* @param[in] p_twis TWIS instance.
* @param int_mask Interrupts mask.
*/
__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * const p_twis, uint32_t int_mask);
/**
* @brief Function for retrieving the state of selected interrupts.
*
* @param[in] p_twis TWIS instance.
* @param int_mask Interrupts mask.
*
* @retval true If any of selected interrupts is enabled.
* @retval false If none of selected interrupts is enabled.
*/
__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_twis, uint32_t int_mask);
/**
* @brief Function for disabling selected interrupts.
*
* @param[in] p_twis TWIS instance.
* @param int_mask Interrupts mask.
*/
__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_twis, uint32_t int_mask);
/**
* @brief Function for retrieving and clearing the TWIS error source.
*
* @attention Error sources are cleared after read.
* @param[in] p_twis TWIS instance
* @return Error source mask with values from @ref nrf_twis_error_t.
*/
__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_twis);
/**
* @brief Get information which of addresses matched
*
* Function returns index in the address table
* that points to the address that already matched.
* @param[in] p_twis TWIS instance
* @return Index of matched address
*/
__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_twis);
/**
* @brief Function for enabling TWIS.
*
* @param[in] p_twis TWIS instance.
*/
__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * const p_twis);
/**
* @brief Function for disabling TWIS.
*
* @param[in] p_twis TWIS instance.
*/
__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * const p_twis);
/**
* @brief Function for configuring TWIS pins.
*
* @param[in] p_twis TWIS instance.
* @param scl SCL pin number.
* @param sda SDA pin number.
*/
__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * const p_twis, uint32_t scl, uint32_t sda);
/**
* @brief Function for setting the receive buffer.
*
* @param[in] p_twis TWIS instance.
* @param p_buf Pointer to the buffer for received data.
* @param length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_twis_rx_buffer_set(
NRF_TWIS_Type * const p_twis,
uint8_t * p_buf,
nrf_twis_amount_t length);
/**
* @brief Function that prepares TWIS for receiving
*
* This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task.
* @param[in] p_twis TWIS instance.
* @param p_buf Pointer to the buffer for received data.
* @param length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_twis_rx_prepare(
NRF_TWIS_Type * const p_twis,
uint8_t * p_buf,
nrf_twis_amount_t length);
/**
* @brief Function for getting number of bytes received in the last transaction.
*
* @param[in] p_twis TWIS instance.
* @return Amount of bytes received.
* */
__STATIC_INLINE nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_twis);
/**
* @brief Function for setting the transmit buffer.
*
* @param[in] p_twis TWIS instance.
* @param p_buf Pointer to the buffer with data to send.
* @param length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_twis_tx_buffer_set(
NRF_TWIS_Type * const p_twis,
uint8_t const * p_buf,
nrf_twis_amount_t length);
/**
* @brief Function that prepares TWIS for transmitting
*
* This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task.
* @param[in] p_twis TWIS instance.
* @param p_buf Pointer to the buffer with data to send.
* @param length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_twis_tx_prepare(
NRF_TWIS_Type * const p_twis,
uint8_t const * p_buf,
nrf_twis_amount_t length);
/**
* @brief Function for getting number of bytes transmitted in the last transaction.
*
* @param[in] p_twis TWIS instance.
* @return Amount of bytes transmitted.
*/
__STATIC_INLINE nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_twis);
/**
* @brief Function for setting slave address
*
* Function sets the selected address for this TWI interface.
* @param[in] p_twis TWIS instance.
* @param n Index of address to set
* @param addr Addres to set
* @sa nrf_twis_config_address_set
* @sa nrf_twis_config_address_get
*/
__STATIC_INLINE void nrf_twis_address_set(
NRF_TWIS_Type * const p_twis,
uint_fast8_t n,
nrf_twis_address_t addr);
/**
* @brief Function for retrieving configured slave address
*
* Function gets the selected address for this TWI interface.
* @param[in] p_twis TWIS instance.
* @param n Index of address to get
*/
__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(
NRF_TWIS_Type const * const p_twis,
uint_fast8_t n);
/**
* @brief Function for setting the device address configuration.
*
* @param[in] p_twis TWIS instance.
* @param addr_mask Mask of address indexes of what device should answer to.
*
* @sa nrf_twis_address_set
*/
__STATIC_INLINE void nrf_twis_config_address_set(
NRF_TWIS_Type * const p_twis,
nrf_twis_config_addr_mask_t addr_mask);
/**
* @brief Function for retrieving the device address configuration.
*
* @param[in] p_twis TWIS instance.
*
* @return Mask of address indexes of what device should answer to.
*/
__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(
NRF_TWIS_Type const * const p_twis);
/**
* @brief Function for setting the over-read character.
*
* @param[in] p_twis TWIS instance.
* @param[in] orc Over-read character. Character clocked out in case of
* over-read of the TXD buffer.
*/
__STATIC_INLINE void nrf_twis_orc_set(
NRF_TWIS_Type * const p_twis,
uint8_t orc);
/**
* @brief Function for setting the over-read character.
*
* @param[in] p_twis TWIS instance.
*
* @return Over-read character configured for selected instance.
*/
__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_twis);
/** @} */ /* End of nrf_twis_hal */
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
/* ------------------------------------------------------------------------------------------------
* Internal functions
*/
/**
* @internal
* @brief Internal function for getting task/event register address
*
* @param[in] p_twis TWIS instance.
* @oaram offset Offset of the register from the instance beginning
*
* @attention offset has to be modulo 4 value. In other case we can get hardware fault.
* @return Pointer to the register
*/
__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type * const p_twis, uint32_t offset)
{
return (volatile uint32_t*)((uint8_t *)p_twis + (uint32_t)offset);
}
/**
* @internal
* @brief Internal function for getting task/event register address - constant version
*
* @param[in] p_twis TWIS instance.
* @oaram offset Offset of the register from the instance beginning
*
* @attention offset has to be modulo 4 value. In other case we can get hardware fault.
* @return Pointer to the register
*/
__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * const p_twis, uint32_t offset)
{
return (volatile const uint32_t*)((uint8_t *)p_twis + (uint32_t)offset);
}
/* ------------------------------------------------------------------------------------------------
* Interface functions definitions
*/
void nrf_twis_task_trigger(NRF_TWIS_Type * const p_twis, nrf_twis_task_t task)
{
*(nrf_twis_getRegPtr(p_twis, (uint32_t)task)) = 1UL;
}
uint32_t nrf_twis_task_address_get(
NRF_TWIS_Type const * const p_twis,
nrf_twis_task_t task)
{
return (uint32_t)nrf_twis_getRegPtr_c(p_twis, (uint32_t)task);
}
void nrf_twis_event_clear(
NRF_TWIS_Type * const p_twis,
nrf_twis_event_t event)
{
*(nrf_twis_getRegPtr(p_twis, (uint32_t)event)) = 0UL;
}
bool nrf_twis_event_check(
NRF_TWIS_Type const * const p_twis,
nrf_twis_event_t event)
{
return (bool)*nrf_twis_getRegPtr_c(p_twis, (uint32_t)event);
}
bool nrf_twis_event_get_and_clear(
NRF_TWIS_Type * const p_twis,
nrf_twis_event_t event)
{
bool ret = nrf_twis_event_check(p_twis, event);
if(ret)
{
nrf_twis_event_clear(p_twis, event);
}
return ret;
}
uint32_t nrf_twis_event_address_get(
NRF_TWIS_Type const * const p_twis,
nrf_twis_event_t event)
{
return (uint32_t)nrf_twis_getRegPtr_c(p_twis, (uint32_t)event);
}
void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_twis, uint32_t short_mask)
{
p_twis->SHORTS |= short_mask;
}
void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_twis, uint32_t short_mask)
{
if(~0U == short_mask)
{
/* Optimized version for "disable all" */
p_twis->SHORTS = 0;
}
else
{
p_twis->SHORTS &= ~short_mask;
}
}
uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_twis)
{
return p_twis->SHORTS;
}
void nrf_twis_int_enable(NRF_TWIS_Type * const p_twis, uint32_t int_mask)
{
p_twis->INTENSET = int_mask;
}
bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_twis, uint32_t int_mask)
{
return (bool)(p_twis->INTENSET & int_mask);
}
void nrf_twis_int_disable(NRF_TWIS_Type * const p_twis, uint32_t int_mask)
{
p_twis->INTENCLR = int_mask;
}
uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_twis)
{
uint32_t ret = p_twis->ERRORSRC;
p_twis->ERRORSRC = ret;
return ret;
}
uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_twis)
{
return (uint_fast8_t)p_twis->MATCH;
}
void nrf_twis_enable(NRF_TWIS_Type * const p_twis)
{
p_twis->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos);
}
void nrf_twis_disable(NRF_TWIS_Type * const p_twis)
{
p_twis->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos);
}
void nrf_twis_pins_set(NRF_TWIS_Type * const p_twis, uint32_t scl, uint32_t sda)
{
p_twis->PSEL.SCL = scl;
p_twis->PSEL.SDA = sda;
}
void nrf_twis_rx_buffer_set(
NRF_TWIS_Type * const p_twis,
uint8_t * p_buf,
nrf_twis_amount_t length)
{
p_twis->RXD.PTR = (uint32_t)p_buf;
p_twis->RXD.MAXCNT = length;
}
__STATIC_INLINE void nrf_twis_rx_prepare(
NRF_TWIS_Type * const p_twis,
uint8_t * p_buf,
nrf_twis_amount_t length)
{
nrf_twis_rx_buffer_set(p_twis, p_buf, length);
nrf_twis_task_trigger(p_twis, NRF_TWIS_TASK_PREPARERX);
}
nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_twis)
{
return (nrf_twis_amount_t)p_twis->RXD.AMOUNT;
}
void nrf_twis_tx_buffer_set(
NRF_TWIS_Type * const p_twis,
uint8_t const * p_buf,
nrf_twis_amount_t length)
{
p_twis->TXD.PTR = (uint32_t)p_buf;
p_twis->TXD.MAXCNT = length;
}
__STATIC_INLINE void nrf_twis_tx_prepare(
NRF_TWIS_Type * const p_twis,
uint8_t const * p_buf,
nrf_twis_amount_t length)
{
nrf_twis_tx_buffer_set(p_twis, p_buf, length);
nrf_twis_task_trigger(p_twis, NRF_TWIS_TASK_PREPARETX);
}
nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_twis)
{
return (nrf_twis_amount_t)p_twis->TXD.AMOUNT;
}
void nrf_twis_address_set(
NRF_TWIS_Type * const p_twis,
uint_fast8_t n,
nrf_twis_address_t addr)
{
p_twis->ADDRESS[n] = addr;
}
nrf_twis_address_t nrf_twis_address_get(
NRF_TWIS_Type const * const p_twis,
uint_fast8_t n)
{
return (nrf_twis_address_t)p_twis->ADDRESS[n];
}
void nrf_twis_config_address_set(
NRF_TWIS_Type * const p_twis,
nrf_twis_config_addr_mask_t addr_mask)
{
/* This is the only configuration in TWIS - just write it without masking */
p_twis->CONFIG = addr_mask;
}
nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * const p_twis)
{
return (nrf_twis_config_addr_mask_t)(p_twis->CONFIG & TWIS_ADDRESS_ADDRESS_Msk);
}
void nrf_twis_orc_set(
NRF_TWIS_Type * const p_twis,
uint8_t orc)
{
p_twis->ORC = orc;
}
uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_twis)
{
return (uint8_t)p_twis->ORC;
}
#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
#endif /* NRF_TWIS_H__ */

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nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uart.h Normal file
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_UART_H__
#define NRF_UART_H__
#include "nrf.h"
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
/**
* @defgroup nrf_uart_hal UART HAL
* @{
* @ingroup nrf_uart
*
* @brief Hardware access layer for accessing the UART peripheral.
*/
#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF
/**
* @enum nrf_uart_task_t
* @brief UART tasks.
*/
typedef enum
{
/*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_UART_TASK_STARTRX = offsetof(NRF_UART_Type, TASKS_STARTRX), /**< Task for starting reception. */
NRF_UART_TASK_STOPRX = offsetof(NRF_UART_Type, TASKS_STOPRX), /**< Task for stopping reception. */
NRF_UART_TASK_STARTTX = offsetof(NRF_UART_Type, TASKS_STARTTX), /**< Task for starting transmission. */
NRF_UART_TASK_STOPTX = offsetof(NRF_UART_Type, TASKS_STOPTX), /**< Task for stopping transmission. */
NRF_UART_TASK_SUSPEND = offsetof(NRF_UART_Type, TASKS_SUSPEND), /**< Task for suspending UART. */
/*lint -restore*/
} nrf_uart_task_t;
/**
* @enum nrf_uart_event_t
* @brief UART events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_UART_EVENT_CTS = offsetof(NRF_UART_Type, EVENTS_CTS), /**< Event from CTS line activation. */
NRF_UART_EVENT_NCTS = offsetof(NRF_UART_Type, EVENTS_NCTS), /**< Event from CTS line deactivation. */
NRF_UART_EVENT_RXDRDY = offsetof(NRF_UART_Type, EVENTS_RXDRDY),/**< Event from data ready in RXD. */
NRF_UART_EVENT_TXDRDY = offsetof(NRF_UART_Type, EVENTS_TXDRDY),/**< Event from data sent from TXD. */
NRF_UART_EVENT_ERROR = offsetof(NRF_UART_Type, EVENTS_ERROR), /**< Event from error detection. */
NRF_UART_EVENT_RXTO = offsetof(NRF_UART_Type, EVENTS_RXTO) /**< Event from receiver timeout. */
/*lint -restore*/
} nrf_uart_event_t;
/**
* @enum nrf_uart_int_mask_t
* @brief UART interrupts.
*/
typedef enum
{
/*lint -save -e30*/
NRF_UART_INT_MASK_CTS = UART_INTENCLR_CTS_Msk, /**< CTS line activation interrupt. */
NRF_UART_INT_MASK_NCTS = UART_INTENCLR_NCTS_Msk, /**< CTS line deactivation interrupt. */
NRF_UART_INT_MASK_RXDRDY = UART_INTENCLR_RXDRDY_Msk, /**< Data ready in RXD interrupt. */
NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk, /**< Data sent from TXD interrupt. */
NRF_UART_INT_MASK_ERROR = UART_INTENCLR_ERROR_Msk, /**< Error detection interrupt. */
NRF_UART_INT_MASK_RXTO = UART_INTENCLR_RXTO_Msk /**< Receiver timeout interrupt. */
/*lint -restore*/
} nrf_uart_int_mask_t;
/**
* @enum nrf_uart_baudrate_t
* @brief Baudrates supported by UART.
*/
typedef enum
{
#ifdef NRF52
NRF_UART_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
NRF_UART_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
NRF_UART_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
NRF_UART_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
NRF_UART_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
NRF_UART_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
NRF_UART_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
NRF_UART_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
NRF_UART_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
NRF_UART_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
NRF_UART_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
NRF_UART_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
NRF_UART_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
NRF_UART_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
NRF_UART_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
NRF_UART_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
#else
NRF_UART_BAUDRATE_1200 = UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
NRF_UART_BAUDRATE_2400 = UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
NRF_UART_BAUDRATE_4800 = UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
NRF_UART_BAUDRATE_9600 = UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
NRF_UART_BAUDRATE_14400 = UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
NRF_UART_BAUDRATE_19200 = UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
NRF_UART_BAUDRATE_28800 = UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
NRF_UART_BAUDRATE_38400 = UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
NRF_UART_BAUDRATE_57600 = UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
NRF_UART_BAUDRATE_76800 = UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
NRF_UART_BAUDRATE_115200 = UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
NRF_UART_BAUDRATE_230400 = UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
NRF_UART_BAUDRATE_250000 = UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
NRF_UART_BAUDRATE_460800 = UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
NRF_UART_BAUDRATE_921600 = UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
NRF_UART_BAUDRATE_1000000 = UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
#endif
} nrf_uart_baudrate_t;
/**
* @enum nrf_uart_error_mask_t
* @brief Types of UART error masks.
*/
typedef enum
{
NRF_UART_ERROR_OVERRUN_MASK = UART_ERRORSRC_OVERRUN_Msk, /**< Overrun error. */
NRF_UART_ERROR_PARITY_MASK = UART_ERRORSRC_PARITY_Msk, /**< Parity error. */
NRF_UART_ERROR_FRAMING_MASK = UART_ERRORSRC_FRAMING_Msk, /**< Framing error. */
NRF_UART_ERROR_BREAK_MASK = UART_ERRORSRC_BREAK_Msk, /**< Break error. */
} nrf_uart_error_mask_t;
/**
* @enum nrf_uart_parity_t
* @brief Types of UART parity modes.
*/
typedef enum
{
NRF_UART_PARITY_EXCLUDED = UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos, /**< Parity excluded. */
NRF_UART_PARITY_INCLUDED = UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos, /**< Parity included. */
} nrf_uart_parity_t;
/**
* @enum nrf_uart_hwfc_t
* @brief Types of UART flow control modes.
*/
typedef enum
{
NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< HW flow control disabled. */
NRF_UART_HWFC_ENABLED = UART_CONFIG_HWFC_Enabled, /**< HW flow control enabled. */
} nrf_uart_hwfc_t;
/**
* @brief Function for clearing a specific UART event.
*
* @param[in] p_reg UART instance.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event);
/**
* @brief Function for checking the state of a specific UART event.
*
* @param[in] p_reg UART instance.
* @param[in] event Event to check.
*
* @retval True if event is set, False otherwise.
*/
__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event);
/**
* @brief Function for returning the address of a specific UART event register.
*
* @param[in] p_reg UART instance.
* @param[in] event Desired event.
*
* @retval Address of specified event register.
*/
__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg,
nrf_uart_event_t event);
/**
* @brief Function for enabling a specific interrupt.
*
* @param p_reg Instance.
* @param int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param p_reg Instance.
* @param int_mask Mask of interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask);
/**
* @brief Function for disabling specific interrupts.
*
* @param p_reg Instance.
* @param int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask);
/**
* @brief Function for getting error source mask. Function is clearing error source flags after reading.
*
* @param p_reg Instance.
* @return Mask with error source flags.
*/
__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg);
/**
* @brief Function for enabling UART.
*
* @param p_reg Instance.
*/
__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg);
/**
* @brief Function for disabling UART.
*
* @param p_reg Instance.
*/
__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg);
/**
* @brief Function for configuring TX/RX pins.
*
* @param p_reg Instance.
* @param pseltxd TXD pin number.
* @param pselrxd RXD pin number.
*/
__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
/**
* @brief Function for disconnecting TX/RX pins.
*
* @param p_reg Instance.
*/
__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg);
/**
* @brief Function for getting TX pin.
*
* @param p_reg Instance.
*/
__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg);
/**
* @brief Function for getting RX pin.
*
* @param p_reg Instance.
*/
__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg);
/**
* @brief Function for getting RTS pin.
*
* @param p_reg Instance.
*/
__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg);
/**
* @brief Function for getting CTS pin.
*
* @param p_reg Instance.
*/
__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg);
/**
* @brief Function for configuring flow control pins.
*
* @param p_reg Instance.
* @param pselrts RTS pin number.
* @param pselcts CTS pin number.
*/
__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg,
uint32_t pselrts,
uint32_t pselcts);
/**
* @brief Function for disconnecting flow control pins.
*
* @param p_reg Instance.
*/
__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg);
/**
* @brief Function for reading RX data.
*
* @param p_reg Instance.
* @return Received byte.
*/
__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg);
/**
* @brief Function for setting Tx data.
*
* @param p_reg Instance.
* @param txd Byte.
*/
__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd);
/**
* @brief Function for starting an UART task.
*
* @param p_reg Instance.
* @param task Task.
*/
__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task);
/**
* @brief Function for returning the address of a specific task register.
*
* @param p_reg Instance.
* @param task Task.
*
* @return Task address.
*/
__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task);
/**
* @brief Function for configuring UART.
*
* @param p_reg Instance.
* @param hwfc Hardware flow control. Enabled if true.
* @param parity Parity. Included if true.
*/
__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg,
nrf_uart_parity_t parity,
nrf_uart_hwfc_t hwfc);
/**
* @brief Function for setting UART baudrate.
*
* @param p_reg Instance.
* @param baudrate Baudrate.
*/
__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg,
nrf_uart_event_t event)
{
return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask)
{
p_reg->INTENSET = int_mask;
}
__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask)
{
return (bool)(p_reg->INTENSET & int_mask);
}
__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask)
{
p_reg->INTENCLR = int_mask;
}
__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg)
{
uint32_t errsrc_mask = p_reg->ERRORSRC;
p_reg->ERRORSRC = errsrc_mask;
return errsrc_mask;
}
__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg)
{
p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled;
}
__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg)
{
p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled;
}
__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd)
{
p_reg->PSELTXD = pseltxd;
p_reg->PSELRXD = pselrxd;
}
__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg)
{
nrf_uart_txrx_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED);
}
__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg)
{
return p_reg->PSELTXD;
}
__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg)
{
return p_reg->PSELRXD;
}
__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg)
{
return p_reg->PSELRTS;
}
__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg)
{
return p_reg->PSELCTS;
}
__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, uint32_t pselrts, uint32_t pselcts)
{
p_reg->PSELRTS = pselrts;
p_reg->PSELCTS = pselcts;
}
__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg)
{
nrf_uart_hwfc_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED);
}
__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg)
{
return p_reg->RXD;
}
__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd)
{
p_reg->TXD = txd;
}
__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task)
{
return (uint32_t)p_reg + (uint32_t)task;
}
__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg,
nrf_uart_parity_t parity,
nrf_uart_hwfc_t hwfc)
{
p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
}
__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate)
{
p_reg->BAUDRATE = baudrate;
}
#endif //SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#endif //NRF_UART_H__

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_UARTE_H__
#define NRF_UARTE_H__
#include "nrf.h"
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF
/**
* @defgroup nrf_uarte_hal UARTE HAL
* @{
* @ingroup nrf_uart
*
* @brief Hardware access layer for accessing the UARTE peripheral.
*/
/**
* @enum nrf_uarte_task_t
* @brief UARTE tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX),///< Start UART receiver.
NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX),///< Start UART transmitter.
NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
/*lint -restore*/
} nrf_uarte_task_t;
/**
* @enum nrf_uarte_event_t
* @brief UARTE events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED),///< Receiver has started.
NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED),///< Transmitter has started.
NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped.
/*lint -restore*/
} nrf_uarte_event_t;
/**
* @brief Types of UARTE shortcuts.
*/
typedef enum
{
NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk,///< Shortcut between ENDRX event and STARTRX task.
NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk, ///< Shortcut between ENDRX event and STOPRX task.
} nrf_uarte_short_t;
/**
* @enum nrf_uarte_int_mask_t
* @brief UARTE interrupts.
*/
typedef enum
{
NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
NRF_UARTE_INT_NCTSRX_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk,///< Interrupt on RXSTARTED event.
NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk,///< Interrupt on TXSTARTED event.
NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event.
} nrf_uarte_int_mask_t;
/**
* @enum nrf_uarte_baudrate_t
* @brief Baudrates supported by UARTE.
*/
typedef enum
{
NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud.
} nrf_uarte_baudrate_t;
/**
* @enum nrf_uarte_error_mask_t
* @brief Types of UARTE error masks.
*/
typedef enum
{
NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error.
NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error.
NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error.
NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk, ///< Break error.
} nrf_uarte_error_mask_t;
/**
* @enum nrf_uarte_parity_t
* @brief Types of UARTE parity modes.
*/
typedef enum
{
NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos, ///< Parity included.
} nrf_uarte_parity_t;
/**
* @enum nrf_uarte_hwfc_t
* @brief Types of UARTE flow control modes.
*/
typedef enum
{
NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control disabled.
NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control enabled.
} nrf_uarte_hwfc_t;
/**
* @brief Function for clearing a specific UARTE event.
*
* @param[in] p_reg UARTE instance.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
/**
* @brief Function for checking the state of a specific UARTE event.
*
* @param[in] p_reg UARTE instance.
* @param[in] event Event to check.
*
* @retval True if event is set, False otherwise.
*/
__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
/**
* @brief Function for returning the address of a specific UARTE event register.
*
* @param[in] p_reg UARTE instance.
* @param[in] event Desired event.
*
* @retval Address of specified event register.
*/
__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
nrf_uarte_event_t event);
/**
* @brief Function for enabling UARTE shortcuts.
*
* @param p_reg UARTE instance.
* @param shorts_mask Shortcuts to enable.
*/
__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
/**
* @brief Function for disabling UARTE shortcuts.
*
* @param p_reg UARTE instance.
* @param shorts_mask Shortcuts to disable.
*/
__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
/**
* @brief Function for enabling UARTE interrupts.
*
* @param p_reg Instance.
* @param int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param p_reg Instance.
* @param int_mask Mask of interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask);
/**
* @brief Function for disabling specific interrupts.
*
* @param p_reg Instance.
* @param int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
/**
* @brief Function for getting error source mask. Function is clearing error source flags after reading.
*
* @param p_reg Instance.
* @return Mask with error source flags.
*/
__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
/**
* @brief Function for enabling UARTE.
*
* @param p_reg Instance.
*/
__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
/**
* @brief Function for disabling UARTE.
*
* @param p_reg Instance.
*/
__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
/**
* @brief Function for configuring TX/RX pins.
*
* @param p_reg Instance.
* @param pseltxd TXD pin number.
* @param pselrxd RXD pin number.
*/
__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
/**
* @brief Function for disconnecting TX/RX pins.
*
* @param p_reg Instance.
*/
__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
/**
* @brief Function for getting TX pin.
*
* @param p_reg Instance.
*/
__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg);
/**
* @brief Function for getting RX pin.
*
* @param p_reg Instance.
*/
__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg);
/**
* @brief Function for getting RTS pin.
*
* @param p_reg Instance.
*/
__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg);
/**
* @brief Function for getting CTS pin.
*
* @param p_reg Instance.
*/
__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg);
/**
* @brief Function for configuring flow control pins.
*
* @param p_reg Instance.
* @param pselrts RTS pin number.
* @param pselcts CTS pin number.
*/
__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
uint32_t pselrts,
uint32_t pselcts);
/**
* @brief Function for disconnecting flow control pins.
*
* @param p_reg Instance.
*/
__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
/**
* @brief Function for starting an UARTE task.
*
* @param p_reg Instance.
* @param task Task.
*/
__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
/**
* @brief Function for returning the address of a specific task register.
*
* @param p_reg Instance.
* @param task Task.
*
* @return Task address.
*/
__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
/**
* @brief Function for configuring UARTE.
*
* @param p_reg Instance.
* @param hwfc Hardware flow control. Enabled if true.
* @param parity Parity. Included if true.
*/
__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
nrf_uarte_parity_t parity,
nrf_uarte_hwfc_t hwfc);
/**
* @brief Function for setting UARTE baudrate.
*
* @param p_reg Instance.
* @param baudrate Baudrate.
*/
__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate);
/**
* @brief Function for setting the transmit buffer.
*
* @param[in] p_reg Instance.
* @param[in] p_buffer Pointer to the buffer with data to send.
* @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length);
/**
* @brief Function for getting number of bytes transmitted in the last transaction.
*
* @param[in] p_reg Instance.
*
* @retval Amount of bytes transmitted.
*/
__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg);
/**
* @brief Function for setting the receive buffer.
*
* @param[in] p_reg Instance.
* @param[in] p_buffer Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t * p_buffer,
uint8_t length);
/**
* @brief Function for getting number of bytes received in the last transaction.
*
* @param[in] p_reg Instance.
*
* @retval Amount of bytes received.
*/
__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
nrf_uarte_event_t event)
{
return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
{
p_reg->SHORTS |= shorts_mask;
}
__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
{
p_reg->SHORTS &= ~(shorts_mask);
}
__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
{
p_reg->INTENSET = int_mask;
}
__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask)
{
return (bool)(p_reg->INTENSET & int_mask);
}
__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
{
p_reg->INTENCLR = int_mask;
}
__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
{
uint32_t errsrc_mask = p_reg->ERRORSRC;
p_reg->ERRORSRC = errsrc_mask;
return errsrc_mask;
}
__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg)
{
p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
}
__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
{
p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
}
__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd)
{
p_reg->PSEL.TXD = pseltxd;
p_reg->PSEL.RXD = pselrxd;
}
__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
{
nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
}
__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg)
{
return p_reg->PSEL.TXD;
}
__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg)
{
return p_reg->PSEL.RXD;
}
__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg)
{
return p_reg->PSEL.RTS;
}
__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg)
{
return p_reg->PSEL.CTS;
}
__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, uint32_t pselrts, uint32_t pselcts)
{
p_reg->PSEL.RTS = pselrts;
p_reg->PSEL.CTS = pselcts;
}
__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
{
nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
}
__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
{
return (uint32_t)p_reg + (uint32_t)task;
}
__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
nrf_uarte_parity_t parity,
nrf_uarte_hwfc_t hwfc)
{
p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
}
__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
p_reg->BAUDRATE = baudrate;
}
__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length)
{
p_reg->TXD.PTR = (uint32_t)p_buffer;
p_reg->TXD.MAXCNT = length;
}
__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg)
{
return p_reg->TXD.AMOUNT;
}
__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t * p_buffer,
uint8_t length)
{
p_reg->RXD.PTR = (uint32_t)p_buffer;
p_reg->RXD.MAXCNT = length;
}
__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg)
{
return p_reg->RXD.AMOUNT;
}
#endif //SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#endif //NRF_UARTE_H__

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @defgroup nrf_wdt_hal WDT HAL
* @{
* @ingroup nrf_wdt
*
* @brief Hardware access layer for accessing the watchdog timer (WDT) peripheral.
*/
#ifndef NRF_WDT_H__
#define NRF_WDT_H__
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "nrf.h"
#define NRF_WDT_CHANNEL_NUMBER 0x8UL
#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, shouldn't be modified.*/
#define NRF_WDT_TASK_SET 1UL
#define NRF_WDT_EVENT_CLEAR 0UL
/**
* @enum nrf_wdt_task_t
* @brief WDT tasks.
*/
typedef enum
{
/*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */
/*lint -restore*/
} nrf_wdt_task_t;
/**
* @enum nrf_wdt_event_t
* @brief WDT events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */
/*lint -restore*/
} nrf_wdt_event_t;
/**
* @enum nrf_wdt_behaviour_t
* @brief WDT behavior in CPU SLEEP or HALT mode.
*/
typedef enum
{
NRF_WDT_BEHAVIOUR_RUN_SLEEP = WDT_CONFIG_SLEEP_Msk, /**< WDT will run when CPU is in SLEEP mode. */
NRF_WDT_BEHAVIOUR_RUN_HALT = WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in HALT mode. */
NRF_WDT_BEHAVIOUR_RUN_SLEEP_HALT = WDT_CONFIG_SLEEP_Msk | WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in SLEEP or HALT mode. */
NRF_WDT_BEHAVIOUR_PAUSE_SLEEP_HALT = 0, /**< WDT will be paused when CPU is in SLEEP or HALT mode. */
} nrf_wdt_behaviour_t;
/**
* @enum nrf_wdt_rr_register_t
* @brief WDT reload request registers.
*/
typedef enum
{
NRF_WDT_RR0 = 0, /**< Reload request register 0. */
NRF_WDT_RR1, /**< Reload request register 1. */
NRF_WDT_RR2, /**< Reload request register 2. */
NRF_WDT_RR3, /**< Reload request register 3. */
NRF_WDT_RR4, /**< Reload request register 4. */
NRF_WDT_RR5, /**< Reload request register 5. */
NRF_WDT_RR6, /**< Reload request register 6. */
NRF_WDT_RR7 /**< Reload request register 7. */
} nrf_wdt_rr_register_t;
/**
* @enum nrf_wdt_int_mask_t
* @brief WDT interrupts.
*/
typedef enum
{
NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */
} nrf_wdt_int_mask_t;
/**
* @brief Function for configuring the watchdog behavior when the CPU is sleeping or halted.
*
* @param behaviour Watchdog behavior when CPU is in SLEEP or HALT mode.
*/
__STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour)
{
NRF_WDT->CONFIG = behaviour;
}
/**
* @brief Function for starting the watchdog.
*
* @param[in] task Task.
*/
__STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task)
{
*((volatile uint32_t *)((uint8_t *)NRF_WDT + task)) = NRF_WDT_TASK_SET;
}
/**
* @brief Function for clearing the WDT event.
*
* @param[in] event Event.
*/
__STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event)
{
*((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = NRF_WDT_EVENT_CLEAR;
}
/**
* @brief Function for retrieving the state of the WDT event.
*
* @param[in] event Event.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event)
{
return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + event));
}
/**
* @brief Function for enabling a specific interrupt.
*
* @param[in] int_mask Interrupt.
*/
__STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask)
{
NRF_WDT->INTENSET = int_mask;
}
/**
* @brief Function for retrieving the state of given interrupt.
*
* @param[in] int_mask Interrupt.
*
* @retval true Interrupt is enabled.
* @retval false Interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask)
{
return (bool)(NRF_WDT->INTENSET & int_mask);
}
/**
* @brief Function for disabling a specific interrupt.
*
* @param[in] int_mask Interrupt.
*/
__STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask)
{
NRF_WDT->INTENCLR = int_mask;
}
/**
* @brief Function for returning the address of a specific WDT task register.
*
* @param[in] task Task.
*/
__STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task)
{
return ((uint32_t)NRF_WDT + task);
}
/**
* @brief Function for returning the address of a specific WDT event register.
*
* @param[in] event Event.
*
* @retval address of requested event register
*/
__STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event)
{
return ((uint32_t)NRF_WDT + event);
}
/**
* @brief Function for retrieving the watchdog status.
*
* @retval true If the watchdog is started.
* @retval false If the watchdog is not started.
*/
__STATIC_INLINE bool nrf_wdt_started(void)
{
return (bool)(NRF_WDT->RUNSTATUS);
}
/**
* @brief Function for retrieving the watchdog reload request status.
*
* @param[in] rr_register Reload request register to check.
*
* @retval true If a reload request is running.
* @retval false If no reload request is running.
*/
__STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register)
{
return (bool)(((NRF_WDT->REQSTATUS) >> rr_register) & 0x1UL);
}
/**
* @brief Function for setting the watchdog reload value.
*
* @param[in] reload_value Watchdog counter initial value.
*/
__STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value)
{
NRF_WDT->CRV = reload_value;
}
/**
* @brief Function for retrieving the watchdog reload value.
*
* @retval Reload value.
*/
__STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void)
{
return (uint32_t)NRF_WDT->CRV;
}
/**
* @brief Function for enabling a specific reload request register.
*
* @param[in] rr_register Reload request register to enable.
*/
__STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register)
{
NRF_WDT->RREN |= 0x1UL << rr_register;
}
/**
* @brief Function for disabling a specific reload request register.
*
* @param[in] rr_register Reload request register to disable.
*/
__STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register)
{
NRF_WDT->RREN &= ~(0x1UL << rr_register);
}
/**
* @brief Function for retrieving the status of a specific reload request register.
*
* @param[in] rr_register Reload request register to check.
*
* @retval true If the reload request register is enabled.
* @retval false If the reload request register is not enabled.
*/
__STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register)
{
return (bool)(NRF_WDT->RREN & (0x1UL << rr_register));
}
/**
* @brief Function for setting a specific reload request register.
*
* @param[in] rr_register Reload request register to set.
*/
__STATIC_INLINE void nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register)
{
NRF_WDT->RR[rr_register] = NRF_WDT_RR_VALUE;
}
#endif
/** @} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup persistent_storage Persistent Storage Interface
* @{
* @ingroup app_common
* @brief Abstracted flash interface.
*
* @details An abstracted interface is provided by the module to easily port the application and
* SDK modules to an alternate option. This ensures that the SDK and application are moved
* to alternate persistent storage instead of the one provided by default.
*/
#ifndef PSTORAGE_H__
#define PSTORAGE_H__
#include "pstorage_platform.h"
/**@defgroup ps_opcode Persistent Storage Access Operation Codes
* @{
* @brief Persistent Storage Access Operation Codes.
*
* @details Persistent Storage Access Operation Codes are used by Persistent storage operation
* completion callback @ref pstorage_ntf_cb_t to identify the operation type requested by
* the application.
*/
#define PSTORAGE_STORE_OP_CODE 0x01 /**< Store Operation type. */
#define PSTORAGE_LOAD_OP_CODE 0x02 /**< Load Operation type. */
#define PSTORAGE_CLEAR_OP_CODE 0x03 /**< Clear Operation type. */
#define PSTORAGE_UPDATE_OP_CODE 0x04 /**< Update Operation type. */
/**@} */
/**@defgroup pstorage_data_types Persistent Memory Interface Data Types
* @{
* @brief Data Types needed for interfacing with persistent memory.
*
* @details Data Types needed for interfacing with persistent memory.
*/
/**@brief Persistent storage operation completion callback function type.
*
* @details The persistent storage operation completion callback is used by the interface to report
* success or failure of a flash operation. Since data is not copied for a store operation,
* a callback is an indication that the resident memory can now be reused or freed.
*
* @param[in] handle Identifies the module and block for the callback that is received.
* @param[in] op_code Identifies the operation for the event that is notified.
* @param[in] result Identifies the result of a flash access operation. NRF_SUCCESS implies
* operation succeeded.
*
* @note Unmanaged (abnormal behaviour) error codes from the SoftDevice flash
* access API are forwarded as is and are expected to be handled by the
* application. For details refer to the implementation file and corresponding
* SoftDevice flash API documentation.
*
* @param[in] p_data Identifies the application data pointer. For a store operation, this points
* to the resident source of application memory that the application can now
* free or reuse. When there is a clear operation, this is NULL since no
* application pointer is needed for this operation.
* @param[in] data_len Length data the application provided for the operation.
*/
typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle,
uint8_t op_code,
uint32_t result,
uint8_t * p_data,
uint32_t data_len);
/**@brief Struct containing module registration context. */
typedef struct
{
pstorage_ntf_cb_t cb; /**< Persistent storage operation completion callback function @ref pstorage_ntf_cb_t. */
pstorage_size_t block_size; /**< Desired block size for persistent memory storage. For example, if a module has a table with 10 entries, and each entry is 64 bytes in size,
* it can request 10 blocks with a block size of 64 bytes. The module can also request one block that is 640 bytes depending
* on how it would like to access or alter the memory in persistent memory.
* The first option is preferred when it is a single entry that needs to be updated often and doesn't impact the other entries.
* The second option is preferred when table entries are not changed individually but have a common point of loading and storing
* data. */
pstorage_size_t block_count; /** Number of blocks requested by the module; minimum values is 1. */
} pstorage_module_param_t;
/**@} */
/**@defgroup pstorage_routines Persistent Storage Access Routines
* @{
* @brief Functions/Interface SDK modules used to persistently store data.
*
* @details Interface for the Application and SDK modules to load/store information persistently.
* Note: While implementation of each of the persistent storage access functions
* depends on the system and is specific to system/solution, the signature of the
* interface routines should not be altered.
*/
/**@brief Function for initializing the module.
*
* @details Function for initializing the module. This function is called once before any other APIs
* of the module are used.
*
* @retval NRF_SUCCESS Operation success.
*/
uint32_t pstorage_init(void);
/**@brief Function for registering with persistent storage interface.
*
* @param[in] p_module_param Module registration parameter.
* @param[out] p_block_id Block identifier to identify persistent memory blocks when
* registration succeeds. Application is expected to use the block IDs
* for subsequent operations on requested persistent memory. Maximum
* registrations permitted is determined by the configuration of the
* parameter PSTORAGE_NUM_OF_PAGES. If more than one memory block is
* requested, the identifier provided here is the base identifier for the
* first block and used to identify the subsequent block. The application
* uses \@ref pstorage_block_identifier_get with this base identifier and
* block number. Therefore if 10 blocks of size 64 are requested and the
* application wishes to store memory in the 6th block, it shall use
* \@ref pstorage_block_identifier_get with the base ID and provide a
* block number of 5. This way the application is only expected to
* remember the base block identifier.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
* @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
* @retval NRF_ERROR_NO_MEM Operation failure. Additional registrations can't be
* supported.
*/
uint32_t pstorage_register(pstorage_module_param_t * p_module_param,
pstorage_handle_t * p_block_id);
/**@brief Function for getting block ID with reference to base block identifier provided at the time
* of registration.
*
* @details Function to get the block ID with reference to base block identifier provided at the
* time of registration.
* If more than one memory block was requested when registering, the identifier provided
* here is the base identifier for the first block which is used to identify subsequent
* blocks. The application shall use this routine to get the block identifier, providing
* input as base identifier and block number. Therefore, if 10 blocks of size 64 are
* requested and the application wishes to store memory in the 6th block, it shall use
* \@ref pstorage_block_identifier_get with the base ID and provide a block number of 5.
* This way the application is only expected to remember the base block identifier.
*
* @param[in] p_base_id Base block ID received at the time of registration.
* @param[in] block_num Block Number, with first block numbered zero.
* @param[out] p_block_id Block identifier for the block number requested when the API succeeds.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
* @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
*/
uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id,
pstorage_size_t block_num,
pstorage_handle_t * p_block_id);
/**@brief Function for persistently storing data of length 'size' contained in the 'p_src' address
* in the storage module at 'p_dest' address. Equivalent to Storage Write.
*
* @param[in] p_dest Destination address where data is to be stored persistently.
* @param[in] p_src Source address containing data to be stored. API assumes this to be resident
* memory and no intermediate copy of data is made by the API. Must be word
* aligned.
* @param[in] size Size of data to be stored expressed in bytes. Must be word aligned and size +
* offset must be <= block size.
* @param[in] offset Offset in bytes to be applied when writing to the block.
* For example, if within a block of 100 bytes, the application wishes to
* write 20 bytes at an offset of 12, then this field should be set to 12.
* Must be word aligned.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
* @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
* @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned.
* @retval NRF_ERROR_NO_MEM Operation failure. No storage space available.
*
* @warning No copy of the data is made, meaning memory provided for the data source that is to
* be written to flash cannot be freed or reused by the application until this procedure
* is complete. The application is notified when the procedure is finished using the
* notification callback registered by the application.
*/
uint32_t pstorage_store(pstorage_handle_t * p_dest,
uint8_t * p_src,
pstorage_size_t size,
pstorage_size_t offset);
/**@brief Function for updating persistently stored data of length 'size' contained in the 'p_src'
* address in the storage module at 'p_dest' address.
*
* @param[in] p_dest Destination address where data is to be updated.
* @param[in] p_src Source address containing data to be stored. API assumes this to be resident
* memory and no intermediate copy of data is made by the API.
* @param[in] size Size of data to be stored expressed in bytes. Must be word aligned and size +
* offset must be <= block size.
* @param[in] offset Offset in bytes to be applied when writing to the block.
* For example, if within a block of 100 bytes, the application wishes to
* write 20 bytes at an offset of 12 bytes, then this field should be set to 12.
* Must be word aligned.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
* @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
* @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned.
* @retval NRF_ERROR_NO_MEM Operation failure. No storage space available.
*
* @warning No copy of the data is made, meaning memory provided for the data source that is to
* be written to flash cannot be freed or reused by the application until this procedure
* is complete. The application is notified when the procedure is finished using the
* notification callback registered by the application.
*/
uint32_t pstorage_update(pstorage_handle_t * p_dest,
uint8_t * p_src,
pstorage_size_t size,
pstorage_size_t offset);
/**@brief Function for loading persistently stored data of length 'size' from 'p_src' address
* to 'p_dest' address. Equivalent to Storage Read.
*
* @param[in] p_dest Destination address where persistently stored data is to be loaded.
* @param[in] p_src Source where data is loaded from persistent memory.
* @param[in] size Size of data to be loaded from persistent memory expressed in bytes.
* Should be word aligned.
* @param[in] offset Offset in bytes, to be applied when loading from the block.
* For example, if within a block of 100 bytes, the application wishes to
* load 20 bytes from offset of 12 bytes, then this field should be set to 12.
* Should be word aligned.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
* @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
* @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned.
* @retval NRF_ERROR_NO_MEM Operation failure. No storage space available.
*/
uint32_t pstorage_load(uint8_t * p_dest,
pstorage_handle_t * p_src,
pstorage_size_t size,
pstorage_size_t offset);
/**@brief Function for clearing data in persistent memory.
*
* @param[in] p_base_id Base block identifier in persistent memory that needs to be cleared;
* equivalent to an Erase Operation.
* @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
* This parameter is to provision for clearing of certain blocks
* of memory, or all memory blocks in a registered module. If the total size
* of the application module is used (blocks * block size) in combination with
* the identifier for the first block in the module, all blocks in the
* module will be erased. Must be multiple of block size.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
* @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
* @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned.
* @retval NRF_ERROR_NO_MEM Operation failure. No storage space available.
*
* @note Clear operations may take time. This API however, does not block until the clear
* procedure is complete. The application is notified of procedure completion using
* a notification callback registered by the application. The 'result' parameter of the
* callback indicates if the procedure was successful or not.
*/
uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size);
/**@brief Function for getting the number of pending operations with the module.
*
* @param[out] p_count Number of storage operations pending with the module. If 0, there are no
* outstanding requests.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
*/
uint32_t pstorage_access_status_get(uint32_t * p_count);
#ifdef PSTORAGE_RAW_MODE_ENABLE
/**@brief Function for registering with the persistent storage interface.
*
* @param[in] p_module_param Module registration parameter.
* @param[out] p_block_id Block identifier used to identify persistent memory blocks upon
* successful registration. The application is expected to use the block
* IDs for subsequent operations on requested persistent memory. When
* more than one memory block is requested, this identifier is the base
* identifier for the first block and used to identify subsequent blocks.
* The application shall use \@ref pstorage_block_identifier_get with
* this base identifier and block number. Therefore if 10 blocks of size
* 64 are requested and the application wishes to store memory in the 6th
* block, it shall use \@ref pstorage_block_identifier_get with the base
* ID and provide a block number of 5. Therefore, the application is only
* expected to remember the base block identifier.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
* @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
* @retval NRF_ERROR_NO_MEM Operation failure. No storage space available.
*/
uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param,
pstorage_handle_t * p_block_id);
/**@brief Function for persistently storing data of length 'size' contained in 'p_src' address in
* storage module at 'p_dest' address. Equivalent to Storage Write.
*
* @param[in] p_dest Destination address where data is to be stored persistently.
* @param[in] p_src Source address containing data to be stored. The API assumes this is resident
* memory and no intermediate copy of data is made by the API. Must be word
* aligned.
* @param[in] size Size of data to be stored expressed in bytes. Must be word aligned.
* @param[in] offset Offset in bytes to be applied when writing to the block.
* For example, if within a block of 100 bytes, the application wishes to
* write 20 bytes at an offset of 12 bytes, this field should be set to 12.
* Must be word aligned.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
* @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
* @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned.
* @retval NRF_ERROR_NO_MEM Operation failure. No storage space available.
*
* @warning No copy of the data is made, meaning memory provided for data source that is to be
* written to flash cannot be freed or reused by the application until this procedure
* is complete. The application is notified when the procedure is finished using the
* notification callback registered by the application.
*/
uint32_t pstorage_raw_store(pstorage_handle_t * p_dest,
uint8_t * p_src,
pstorage_size_t size,
pstorage_size_t offset);
/**@brief Function for clearing data in persistent memory in raw mode.
*
* @param[in] p_dest Base block identifier in persistent memory that needs to be cleared.
* Equivalent to an Erase Operation.
* @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
* Not used.
*
* @retval NRF_SUCCESS Operation success.
* @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module
* initialization.
* @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed.
* @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
* @retval NRF_ERROR_NO_MEM Operation failure. No storage space available.
*
* @note Clear operations may take time. This API, however, does not block until the clear
* procedure is complete. The application is notified of procedure completion using
* a notification callback registered by the application. The 'result' parameter of the
* callback indicates if the procedure was successful or not.
*/
uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size);
#endif // PSTORAGE_RAW_MODE_ENABLE
/**@} */
/**@} */
#endif // PSTORAGE_H__

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "pstorage.h"
#include <stdlib.h>
#include <stdint.h>
#include "nordic_common.h"
#include "nrf_error.h"
#include "nrf_assert.h"
#include "nrf.h"
#include "nrf_soc.h"
#include "app_util.h"
/** @file
*
* @defgroup persistent_storage_raw Persistent Storage Interface - Raw Mode Implementation
* @{
* @ingroup persistent_storage
* @brief Persistent Storage Interface - Raw Mode Implementation.
*
* @details This file contains the source code for raw mode implementation of pstorage.
* It is intended for special use cases where flash size is critical or the application must have
* full control of the flash, such as DFU. The registration function in this implementation only
* allocates a module id for the queue but does not locate any flash pages for the registrant.
* This implementation provides no safety checking of addresses when clearing or storing data into
* flash. The application is responsible for handling flash addresses and care must therefore be
* taken in application not to erase application area.
* This implementation does not support the @ref pstorage_update function.
*/
#define INVALID_OPCODE 0x00 /**< Invalid op code identifier. */
#ifdef NRF51
#define SOC_MAX_WRITE_SIZE 1024 /**< Maximum write size allowed for a single call to \ref sd_flash_write as specified in the SoC API on the nRF51. */
#elif NRF52
#define SOC_MAX_WRITE_SIZE 4096 /**< Maximum write size allowed for a single call to \ref sd_flash_write as specified in the SoC API on the nRF52. */
#else
#error No target defined
#endif
/**
* @brief Application registration information.
*
* @details Define application specific information that application needs to maintain to be able
* to process requests from each one of them.
*/
typedef struct
{
pstorage_ntf_cb_t cb; /**< Callback registered with the module to be notified of result of flash access. */
} pstorage_module_table_t;
/**
* @brief Defines command queue element.
*
* @details Defines command queue element. Each element encapsulates needed information to process
* a flash access command.
*/
typedef struct
{
uint8_t op_code; /**< Identifies flash access operation being queued. Element is free is op-code is INVALID_OPCODE */
pstorage_size_t size; /**< Identifies size in bytes requested for the operation. */
pstorage_size_t offset; /**< Offset requested by the application for access operation. */
pstorage_handle_t storage_addr; /**< Address/Identifier for persistent memory. */
uint8_t * p_data_addr; /**< Address/Identifier for data memory. This is assumed to be resident memory. */
} cmd_queue_element_t;
/**
* @brief Defines command queue, an element is free is op_code field is not invalid.
*
* @details Defines commands enqueued for flash access. At any point of time, this queue has one or
* more flash access operation pending if the count field is not zero. When the queue is
* not empty, the rp (read pointer) field points to the flash access command in progress
* or to requested next. The queue implements a simple first in first out algorithm.
* Data addresses are assumed to be resident.
*/
typedef struct
{
uint8_t rp; /**< Read pointer, pointing to flash access that is ongoing or to be requested next. */
uint8_t count; /**< Number of elements in the queue. */
bool flash_access; /**< Flag to ensure an flash event received is for an request issued by the module. */
cmd_queue_element_t cmd[PSTORAGE_CMD_QUEUE_SIZE]; /**< Array to maintain flash access operation details */
}cmd_queue_t;
static cmd_queue_t m_cmd_queue; /**< Flash operation request queue. */
static pstorage_module_table_t m_app_table[PSTORAGE_NUM_OF_PAGES]; /**< Registered application information table. */
static pstorage_size_t m_next_app_instance; /**< Points to the application module instance that can be allocated next */
static pstorage_size_t m_round_val; /**< Round value for multiple round operations. For erase operations, the round value will contain current round counter which is identical to number of pages erased. For store operations, the round value contains current round of operation * SOC_MAX_WRITE_SIZE to ensure each store to the SoC Flash API is within the SoC limit. */
/**
* @brief Function for processing of commands and issuing flash access request to the SoftDevice.
*
* @return The return value received from SoftDevice.
*/
static uint32_t cmd_process(void);
/**
* @brief Function for notifying application of any errors.
*
* @param[in] result Result of event being notified.
* @param[in] p_elem Pointer to the element for which a notification should be given.
*/
static void app_notify(uint32_t result, cmd_queue_element_t * p_elem);
/**
* @defgroup utility_functions Utility internal functions.
* @{
* @details Utility functions needed for interfacing with flash through SoC APIs.
* SoC APIs are non blocking and provide the result of flash access through an event.
*
* @note Only one flash access operation is permitted at a time by SoC. Hence a queue is
* maintained by this module.
*/
/**
* @brief Function for initializing a command queue element.
*
* @param[in] index Index identifying element to be initialized.
*/
static void cmd_queue_element_init(uint32_t index)
{
// Internal function and checks on range of index can be avoided
m_cmd_queue.cmd[index].op_code = INVALID_OPCODE;
m_cmd_queue.cmd[index].size = 0;
m_cmd_queue.cmd[index].storage_addr.module_id = PSTORAGE_NUM_OF_PAGES;
m_cmd_queue.cmd[index].storage_addr.block_id = 0;
m_cmd_queue.cmd[index].p_data_addr = NULL;
m_cmd_queue.cmd[index].offset = 0;
}
/**
* @brief Function for initializing the command queue.
*/
static void cmd_queue_init(void)
{
uint32_t cmd_index;
m_round_val = 0;
m_cmd_queue.rp = 0;
m_cmd_queue.count = 0;
m_cmd_queue.flash_access = false;
for(cmd_index = 0; cmd_index < PSTORAGE_CMD_QUEUE_SIZE; cmd_index++)
{
cmd_queue_element_init(cmd_index);
}
}
/**
* @brief Function for enqueueing a flash access operation.
*
* @param[in] opcode Operation code for the command to queue.
* @param[in] p_storage_addr Pointer to the destination address.
* @param[in] p_data_addr Pointer to the source address containing the data.
* @param[in] size Size of data clear or write.
* @param[in] offset Offset to the address identified by the source data address.
*
* @retval NRF_SUCCESS If the enqueueing succeeded.
* @retval NRF_ERROR_NO_MEM In case the queue is full.
* @return Any error returned by the SoftDevice flash API.
*/
static uint32_t cmd_queue_enqueue(uint8_t opcode,
pstorage_handle_t * p_storage_addr,
uint8_t * p_data_addr,
pstorage_size_t size,
pstorage_size_t offset)
{
uint32_t retval;
if (m_cmd_queue.count != PSTORAGE_CMD_QUEUE_SIZE)
{
uint8_t write_index = m_cmd_queue.rp + m_cmd_queue.count;
if (write_index >= PSTORAGE_CMD_QUEUE_SIZE)
{
write_index -= PSTORAGE_CMD_QUEUE_SIZE;
}
m_cmd_queue.cmd[write_index].op_code = opcode;
m_cmd_queue.cmd[write_index].p_data_addr = p_data_addr;
m_cmd_queue.cmd[write_index].storage_addr = (*p_storage_addr);
m_cmd_queue.cmd[write_index].size = size;
m_cmd_queue.cmd[write_index].offset = offset;
retval = NRF_SUCCESS;
if (m_cmd_queue.flash_access == false)
{
retval = cmd_process();
if (retval == NRF_ERROR_BUSY)
{
// In case of busy error code, it is possible to attempt to access flash.
retval = NRF_SUCCESS;
}
}
m_cmd_queue.count++;
}
else
{
retval = NRF_ERROR_NO_MEM;
}
return retval;
}
/**
* @brief Function for dequeueing a command element.
*
* @retval NRF_SUCCESS If the dequeueing succeeded and next command was processed.
* @return Any error returned by the SoftDevice flash API.
*/
static uint32_t cmd_queue_dequeue(void)
{
uint32_t retval = NRF_SUCCESS;
// If any flash operation is enqueued, schedule
if ((m_cmd_queue.count > 0) && (m_cmd_queue.flash_access == false))
{
retval = cmd_process();
if (retval != NRF_SUCCESS)
{
// Flash could be accessed by other modules, hence a busy error is
// acceptable, but any other error needs to be indicated.
if (retval == NRF_ERROR_BUSY)
{
// In case of busy error code, it is possible to attempt to access flash.
retval = NRF_SUCCESS;
}
}
}
else
{
// No flash access request pending.
}
return retval;
}
/**
* @brief Function for notifying application of any errors.
*
* @param[in] result Result of event being notified.
* @param[in] p_elem Pointer to the element for which a notification should be given.
*/
static void app_notify(uint32_t result, cmd_queue_element_t * p_elem)
{
pstorage_ntf_cb_t ntf_cb;
uint8_t op_code = p_elem->op_code;
ntf_cb = m_app_table[p_elem->storage_addr.module_id].cb;
// Indicate result to client.
ntf_cb(&p_elem->storage_addr,
op_code,
result,
p_elem->p_data_addr,
p_elem->size);
}
/**
* @brief Function for handling of system events from SoftDevice.
*
* @param[in] sys_evt System event received.
*/
void pstorage_sys_event_handler(uint32_t sys_evt)
{
uint32_t retval = NRF_SUCCESS;
// The event shall only be processed if requested by this module.
if (m_cmd_queue.flash_access == true)
{
cmd_queue_element_t * p_cmd;
m_cmd_queue.flash_access = false;
switch (sys_evt)
{
case NRF_EVT_FLASH_OPERATION_SUCCESS:
{
p_cmd = &m_cmd_queue.cmd[m_cmd_queue.rp];
m_round_val++;
bool command_finished = ((m_round_val * SOC_MAX_WRITE_SIZE) >= p_cmd->size);
if (command_finished)
{
uint8_t queue_rp = m_cmd_queue.rp;
m_round_val = 0;
m_cmd_queue.count--;
m_cmd_queue.rp++;
if (m_cmd_queue.rp >= PSTORAGE_CMD_QUEUE_SIZE)
{
m_cmd_queue.rp -= PSTORAGE_CMD_QUEUE_SIZE;
}
app_notify(retval, &m_cmd_queue.cmd[queue_rp]);
// Initialize/free the element as it is now processed.
cmd_queue_element_init(queue_rp);
}
// Schedule any queued flash access operations.
retval = cmd_queue_dequeue();
if (retval != NRF_SUCCESS)
{
app_notify(retval, &m_cmd_queue.cmd[m_cmd_queue.rp]);
}
}
break;
case NRF_EVT_FLASH_OPERATION_ERROR:
app_notify(NRF_ERROR_TIMEOUT, &m_cmd_queue.cmd[m_cmd_queue.rp]);
break;
default:
// No implementation needed.
break;
}
}
}
/**
* @brief Function for processing of commands and issuing flash access request to the SoftDevice.
*
* @return The return value received from SoftDevice.
*/
static uint32_t cmd_process(void)
{
uint32_t retval;
uint32_t storage_addr;
cmd_queue_element_t * p_cmd;
retval = NRF_ERROR_FORBIDDEN;
p_cmd = &m_cmd_queue.cmd[m_cmd_queue.rp];
storage_addr = p_cmd->storage_addr.block_id;
switch (p_cmd->op_code)
{
case PSTORAGE_STORE_OP_CODE:
{
uint32_t size;
uint32_t offset;
uint8_t * p_data_addr = p_cmd->p_data_addr;
offset = (m_round_val * SOC_MAX_WRITE_SIZE);
size = p_cmd->size - offset;
p_data_addr += offset;
storage_addr += (p_cmd->offset + offset);
if (size < SOC_MAX_WRITE_SIZE)
{
retval = sd_flash_write(((uint32_t *)storage_addr),
(uint32_t *)p_data_addr,
size / sizeof(uint32_t));
}
else
{
retval = sd_flash_write(((uint32_t *)storage_addr),
(uint32_t *)p_data_addr,
SOC_MAX_WRITE_SIZE / sizeof(uint32_t));
}
}
break;
case PSTORAGE_CLEAR_OP_CODE:
{
uint32_t page_number;
page_number = ((storage_addr / PSTORAGE_FLASH_PAGE_SIZE) +
m_round_val);
retval = sd_flash_page_erase(page_number);
}
break;
default:
// Should never reach here.
break;
}
if (retval == NRF_SUCCESS)
{
m_cmd_queue.flash_access = true;
}
return retval;
}
/** @} */
uint32_t pstorage_init(void)
{
cmd_queue_init();
m_next_app_instance = 0;
m_round_val = 0;
for(unsigned int index = 0; index < PSTORAGE_NUM_OF_PAGES; index++)
{
m_app_table[index].cb = NULL;
}
return NRF_SUCCESS;
}
uint32_t pstorage_register(pstorage_module_param_t * p_module_param,
pstorage_handle_t * p_block_id)
{
if (m_next_app_instance == PSTORAGE_NUM_OF_PAGES)
{
return NRF_ERROR_NO_MEM;
}
p_block_id->module_id = m_next_app_instance;
m_app_table[m_next_app_instance++].cb = p_module_param->cb;
return NRF_SUCCESS;
}
uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id,
pstorage_size_t block_num,
pstorage_handle_t * p_block_id)
{
return NRF_ERROR_NOT_SUPPORTED;
}
uint32_t pstorage_store(pstorage_handle_t * p_dest,
uint8_t * p_src,
pstorage_size_t size,
pstorage_size_t offset)
{
// Verify word alignment.
if ((!is_word_aligned(p_src)) || (!is_word_aligned(p_src+offset)))
{
return NRF_ERROR_INVALID_ADDR;
}
return cmd_queue_enqueue(PSTORAGE_STORE_OP_CODE, p_dest, p_src, size, offset);
}
uint32_t pstorage_clear(pstorage_handle_t * p_dest, pstorage_size_t size)
{
return cmd_queue_enqueue(PSTORAGE_CLEAR_OP_CODE, p_dest, NULL , size, 0);
}
/**
* @}
*/

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "nrf_drv_timer.h"
#include "nrf_drv_common.h"
#include "app_util_platform.h"
#if (TIMER_COUNT == 0)
#error "No TIMER instances enabled in the driver configuration file."
#endif
/**@brief Timer control block. */
typedef struct
{
nrf_timer_event_handler_t handler;
void * context;
nrf_drv_state_t state;
} timer_control_block_t;
static timer_control_block_t m_cb[TIMER_COUNT];
static const nrf_drv_timer_config_t m_default_config[TIMER_COUNT] = {
#if TIMER0_ENABLED
NRF_DRV_TIMER_DEFAULT_CONFIG(0),
#endif
#if TIMER1_ENABLED
NRF_DRV_TIMER_DEFAULT_CONFIG(1),
#endif
#if TIMER2_ENABLED
NRF_DRV_TIMER_DEFAULT_CONFIG(2),
#endif
#if TIMER3_ENABLED
NRF_DRV_TIMER_DEFAULT_CONFIG(3),
#endif
#if TIMER4_ENABLED
NRF_DRV_TIMER_DEFAULT_CONFIG(4),
#endif
};
ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance,
nrf_drv_timer_config_t const * p_config,
nrf_timer_event_handler_t timer_event_handler)
{
timer_control_block_t * p_cb = &m_cb[p_instance->instance_id];
#ifdef SOFTDEVICE_PRESENT
ASSERT(p_instance->p_reg != NRF_TIMER0);
#endif
ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width));
if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
{
return NRF_ERROR_INVALID_STATE;
}
if (timer_event_handler == NULL)
{
return NRF_ERROR_INVALID_PARAM;
}
if (p_config == NULL)
{
p_config = &m_default_config[p_instance->instance_id];
}
p_cb->handler = timer_event_handler;
p_cb->context = p_config->p_context;
uint8_t i;
for (i = 0; i < p_instance->cc_channel_count; ++i)
{
nrf_timer_event_clear(p_instance->p_reg,
nrf_timer_compare_event_get(i));
}
nrf_drv_common_irq_enable(nrf_drv_get_IRQn(p_instance->p_reg),
p_config->interrupt_priority);
nrf_timer_mode_set(p_instance->p_reg, p_config->mode);
nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width);
nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency);
p_cb->state = NRF_DRV_STATE_INITIALIZED;
return NRF_SUCCESS;
}
void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance)
{
nrf_drv_common_irq_disable(nrf_drv_get_IRQn(p_instance->p_reg));
#define DISABLE_ALL UINT32_MAX
nrf_timer_shorts_disable(p_instance->p_reg, DISABLE_ALL);
nrf_timer_int_disable(p_instance->p_reg, DISABLE_ALL);
#undef DISABLE_ALL
nrf_drv_timer_disable(p_instance);
m_cb[p_instance->instance_id].state = NRF_DRV_STATE_UNINITIALIZED;
}
void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance)
{
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_INITIALIZED);
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
m_cb[p_instance->instance_id].state = NRF_DRV_STATE_POWERED_ON;
}
void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance)
{
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_SHUTDOWN);
m_cb[p_instance->instance_id].state = NRF_DRV_STATE_INITIALIZED;
}
void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance)
{
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
}
void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance)
{
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_STOP);
}
void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance)
{
ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_CLEAR);
}
void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance)
{
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
ASSERT(nrf_timer_mode_get(p_instance->p_reg) != NRF_TIMER_MODE_TIMER);
nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_COUNT);
}
uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel)
{
ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
ASSERT(cc_channel < p_instance->cc_channel_count);
nrf_timer_task_trigger(p_instance->p_reg,
nrf_timer_capture_task_get(cc_channel));
return nrf_timer_cc_read(p_instance->p_reg, cc_channel);
}
void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel,
uint32_t cc_value,
bool enable_int)
{
nrf_timer_int_mask_t timer_int = nrf_timer_compare_int_get(cc_channel);
if (enable_int)
{
nrf_timer_int_enable(p_instance->p_reg, timer_int);
}
else
{
nrf_timer_int_disable(p_instance->p_reg, timer_int);
}
nrf_timer_cc_write(p_instance->p_reg, cc_channel, cc_value);
}
void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel,
uint32_t cc_value,
nrf_timer_short_mask_t timer_short_mask,
bool enable_int)
{
nrf_timer_shorts_disable(p_instance->p_reg,
(TIMER_SHORTS_COMPARE0_STOP_Msk << cc_channel) |
(TIMER_SHORTS_COMPARE0_CLEAR_Msk << cc_channel));
nrf_timer_shorts_enable(p_instance->p_reg, timer_short_mask);
(void)nrf_drv_timer_compare(p_instance,
cc_channel,
cc_value,
enable_int);
}
void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance,
uint32_t channel)
{
ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
ASSERT(channel < p_instance->cc_channel_count);
nrf_timer_event_clear(p_instance->p_reg,
nrf_timer_compare_event_get(channel));
nrf_timer_int_enable(p_instance->p_reg,
nrf_timer_compare_int_get(channel));
}
void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance,
uint32_t channel)
{
ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
ASSERT(channel < p_instance->cc_channel_count);
nrf_timer_int_disable(p_instance->p_reg,
nrf_timer_compare_int_get(channel));
}
static void irq_handler(NRF_TIMER_Type * p_reg,
timer_control_block_t * p_cb,
uint8_t channel_count)
{
uint8_t i;
for (i = 0; i < channel_count; ++i)
{
nrf_timer_event_t event = nrf_timer_compare_event_get(i);
nrf_timer_int_mask_t int_mask = nrf_timer_compare_int_get(i);
if (nrf_timer_event_check(p_reg, event) &&
nrf_timer_int_enable_check(p_reg, int_mask))
{
nrf_timer_event_clear(p_reg, event);
p_cb->handler(event, p_cb->context);
}
}
}
#if TIMER0_ENABLED
void TIMER0_IRQHandler(void)
{
irq_handler(NRF_TIMER0, &m_cb[TIMER0_INSTANCE_INDEX],
NRF_TIMER_CC_CHANNEL_COUNT(0));
}
#endif
#if TIMER1_ENABLED
void TIMER1_IRQHandler(void)
{
irq_handler(NRF_TIMER1, &m_cb[TIMER1_INSTANCE_INDEX],
NRF_TIMER_CC_CHANNEL_COUNT(1));
}
#endif
#if TIMER2_ENABLED
void TIMER2_IRQHandler(void)
{
irq_handler(NRF_TIMER2, &m_cb[TIMER2_INSTANCE_INDEX],
NRF_TIMER_CC_CHANNEL_COUNT(2));
}
#endif
#if TIMER3_ENABLED
void TIMER3_IRQHandler(void)
{
irq_handler(NRF_TIMER3, &m_cb[TIMER3_INSTANCE_INDEX],
NRF_TIMER_CC_CHANNEL_COUNT(3));
}
#endif
#if TIMER4_ENABLED
void TIMER4_IRQHandler(void)
{
irq_handler(NRF_TIMER4, &m_cb[TIMER4_INSTANCE_INDEX],
NRF_TIMER_CC_CHANNEL_COUNT(4));
}
#endif

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
* @addtogroup nrf_timer Timer HAL and driver
* @ingroup nrf_drivers
* @brief Timer APIs.
* @details The timer HAL provides basic APIs for accessing the registers
* of the timer. The timer driver provides APIs on a higher level.
*
* @defgroup lib_driver_timer Timer driver
* @{
* @ingroup nrf_timer
* @brief Multi-instance timer driver.
*/
#ifndef NRF_DRV_TIMER_H__
#define NRF_DRV_TIMER_H__
#include "nordic_common.h"
#include "nrf_drv_config.h"
#include "nrf_timer.h"
#include "sdk_errors.h"
#include "nrf_assert.h"
/**
* @brief Timer driver instance data structure.
*/
typedef struct
{
NRF_TIMER_Type * p_reg; ///< Pointer to the structure with TIMER peripheral instance registers.
uint8_t instance_id; ///< Driver instance index.
uint8_t cc_channel_count; ///< Number of capture/compare channels.
} nrf_drv_timer_t;
/**
* @brief Macro for creating a timer driver instance.
*/
#define NRF_DRV_TIMER_INSTANCE(id) \
{ \
.p_reg = CONCAT_2(NRF_TIMER, id), \
.instance_id = CONCAT_3(TIMER, id, _INSTANCE_INDEX), \
.cc_channel_count = NRF_TIMER_CC_CHANNEL_COUNT(id), \
}
/**
* @brief Timer driver instance configuration structure.
*/
typedef struct
{
nrf_timer_frequency_t frequency; ///< Frequency.
nrf_timer_mode_t mode; ///< Mode of operation.
nrf_timer_bit_width_t bit_width; ///< Bit width.
uint8_t interrupt_priority; ///< Interrupt priority.
void * p_context; ///< Context passed to interrupt handler.
} nrf_drv_timer_config_t;
#define TIMER_CONFIG_FREQUENCY(id) CONCAT_3(TIMER, id, _CONFIG_FREQUENCY)
#define TIMER_CONFIG_MODE(id) CONCAT_3(TIMER, id, _CONFIG_MODE)
#define TIMER_CONFIG_BIT_WIDTH(id) CONCAT_3(TIMER, id, _CONFIG_BIT_WIDTH)
#define TIMER_CONFIG_IRQ_PRIORITY(id) CONCAT_3(TIMER, id, _CONFIG_IRQ_PRIORITY)
/**
* @brief Timer driver instance default configuration.
*/
#define NRF_DRV_TIMER_DEFAULT_CONFIG(id) \
{ \
.frequency = TIMER_CONFIG_FREQUENCY(id), \
.mode = (nrf_timer_mode_t)TIMER_CONFIG_MODE(id), \
.bit_width = (nrf_timer_bit_width_t)TIMER_CONFIG_BIT_WIDTH(id), \
.interrupt_priority = TIMER_CONFIG_IRQ_PRIORITY(id), \
.p_context = NULL \
}
/**
* @brief Timer driver event handler type.
*
* @param[in] event_type Timer event.
* @param[in] p_context General purpose parameter set during initialization of
* the timer. This parameter can be used to pass
* additional information to the handler function, for
* example, the timer ID.
*/
typedef void (* nrf_timer_event_handler_t)(nrf_timer_event_t event_type,
void * p_context);
/**
* @brief Function for initializing the timer.
*
* @param[in] p_instance Timer instance.
* @param[in] p_config Initial configuration.
* If NULL, the default configuration is used.
* @param[in] timer_event_handler Event handler provided by the user.
* Must not be NULL.
*
* @retval NRF_SUCCESS If initialization was successful.
* @retval NRF_ERROR_INVALID_STATE If the instance is already initialized.
* @retval NRF_ERROR_INVALID_PARAM If no handler was provided.
*/
ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance,
nrf_drv_timer_config_t const * p_config,
nrf_timer_event_handler_t timer_event_handler);
/**
* @brief Function for uninitializing the timer.
*
* @param[in] p_instance Timer instance.
*/
void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance);
/**
* @brief Function for turning on the timer.
*
* @param[in] p_instance Timer instance.
*/
void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance);
/**
* @brief Function for turning off the timer.
*
* Note that the timer will allow to enter the lowest possible SYSTEM_ON state
* only after this function is called.
*
* @param[in] p_instance Timer instance.
*/
void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance);
/**
* @brief Function for pausing the timer.
*
* @param[in] p_instance Timer instance.
*/
void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance);
/**
* @brief Function for resuming the timer.
*
* @param[in] p_instance Timer instance.
*/
void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance);
/**
* @brief Function for clearing the timer.
*
* @param[in] p_instance Timer instance.
*/
void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance);
/**
* @brief Function for incrementing the timer.
*
* @param[in] p_instance Timer instance.
*/
void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance);
/**
* @brief Function for returning the address of a specific timer task.
*
* @param[in] p_instance Timer instance.
* @param[in] timer_task Timer task.
*
* @return Task address.
*/
__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get(
nrf_drv_timer_t const * const p_instance,
nrf_timer_task_t timer_task);
/**
* @brief Function for returning the address of a specific timer capture task.
*
* @param[in] p_instance Timer instance.
* @param[in] channel Capture channel number.
*
* @return Task address.
*/
__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get(
nrf_drv_timer_t const * const p_instance,
uint32_t channel);
/**
* @brief Function for returning the address of a specific timer event.
*
* @param[in] p_instance Timer instance.
* @param[in] timer_event Timer event.
*
* @return Event address.
*/
__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get(
nrf_drv_timer_t const * const p_instance,
nrf_timer_event_t timer_event);
/**
* @brief Function for returning the address of a specific timer compare event.
*
* @param[in] p_instance Timer instance.
* @param[in] channel Compare channel number.
*
* @return Event address.
*/
__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get(
nrf_drv_timer_t const * const p_instance,
uint32_t channel);
/**
* @brief Function for capturing the timer value.
*
* @param[in] p_instance Timer instance.
* @param[in] cc_channel Capture channel number.
*
* @return Captured value.
*/
uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel);
/**
* @brief Function for returning the capture value from a specific channel.
*
* Use this function to read channel values when PPI is used for capturing.
*
* @param[in] p_instance Timer instance.
* @param[in] cc_channel Capture channel number.
*
* @return Captured value.
*/
__STATIC_INLINE uint32_t nrf_drv_timer_capture_get(
nrf_drv_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel);
/**
* @brief Function for setting the timer channel in compare mode.
*
* @param[in] p_instance Timer instance.
* @param[in] cc_channel Compare channel number.
* @param[in] cc_value Compare value.
* @param[in] enable_int Enable or disable the interrupt for the compare channel.
*/
void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel,
uint32_t cc_value,
bool enable_int);
/**
* @brief Function for setting the timer channel in extended compare mode.
*
* @param[in] p_instance Timer instance.
* @param[in] cc_channel Compare channel number.
* @param[in] cc_value Compare value.
* @param[in] timer_short_mask Shortcut between the compare event on the channel
* and the timer task (STOP or CLEAR).
* @param[in] enable_int Enable or disable the interrupt for the compare
* channel.
*/
void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel,
uint32_t cc_value,
nrf_timer_short_mask_t timer_short_mask,
bool enable_int);
/**
* @brief Function for converting time in microseconds to timer ticks.
*
* @param[in] p_instance Timer instance.
* @param[in] time_us Time in microseconds.
*
* @return Number of ticks.
*/
__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks(
nrf_drv_timer_t const * const p_instance,
uint32_t time_us);
/**
* @brief Function for converting time in milliseconds to timer ticks.
*
* @param[in] p_instance Timer instance.
* @param[in] time_ms Time in milliseconds.
*
* @return Number of ticks.
*/
__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks(
nrf_drv_timer_t const * const p_instance,
uint32_t time_ms);
/**
* @brief Function for enabling timer compare interrupt.
*
* @param[in] p_instance Timer instance.
* @param[in] channel Compare channel.
*/
void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance,
uint32_t channel);
/**
* @brief Function for disabling timer compare interrupt.
*
* @param[in] p_instance Timer instance.
* @param[in] channel Compare channel.
*/
void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance,
uint32_t channel);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get(
nrf_drv_timer_t const * const p_instance,
nrf_timer_task_t timer_task)
{
return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, timer_task);
}
__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get(
nrf_drv_timer_t const * const p_instance,
uint32_t channel)
{
ASSERT(channel < p_instance->cc_channel_count);
return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg,
nrf_timer_capture_task_get(channel));
}
__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get(
nrf_drv_timer_t const * const p_instance,
nrf_timer_event_t timer_event)
{
return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, timer_event);
}
__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get(
nrf_drv_timer_t const * const p_instance,
uint32_t channel)
{
ASSERT(channel < p_instance->cc_channel_count);
return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg,
nrf_timer_compare_event_get(channel));
}
__STATIC_INLINE uint32_t nrf_drv_timer_capture_get(
nrf_drv_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel)
{
return nrf_timer_cc_read(p_instance->p_reg, cc_channel);
}
__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks(
nrf_drv_timer_t const * const p_instance,
uint32_t timer_us)
{
return nrf_timer_us_to_ticks(timer_us,
nrf_timer_frequency_get(p_instance->p_reg));
}
__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks(
nrf_drv_timer_t const * const p_instance,
uint32_t timer_ms)
{
return nrf_timer_ms_to_ticks(timer_ms,
nrf_timer_frequency_get(p_instance->p_reg));
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRF_DRV_TIMER_H__
/** @} */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "nrf_drv_uart.h"
#include "nrf_assert.h"
#include "nordic_common.h"
#include "nrf_drv_common.h"
#include "nrf_gpio.h"
#include "app_util_platform.h"
// This set of macros makes it possible to exclude parts of code, when one type
// of supported peripherals is not used.
#ifdef NRF51
#define UART_IN_USE
#elif defined(NRF52)
#if (UART_EASY_DMA_SUPPORT == 1)
#define UARTE_IN_USE
#endif
#if (UART_LEGACY_SUPPORT == 1)
#define UART_IN_USE
#endif
#endif
#if (defined(UARTE_IN_USE) && defined(UART_IN_USE))
// UARTE and UART combined
#define CODE_FOR_UARTE(code) if (m_cb.use_easy_dma) { code }
#define CODE_FOR_UART(code) else { code }
#elif (defined(UARTE_IN_USE) && !defined(UART_IN_USE))
// UARTE only
#define CODE_FOR_UARTE(code) { code }
#define CODE_FOR_UART(code)
#elif (!defined(UARTE_IN_USE) && defined(UART_IN_USE))
// UART only
#define CODE_FOR_UARTE(code)
#define CODE_FOR_UART(code) { code }
#else
#error "Wrong configuration."
#endif
#ifndef IS_EASY_DMA_RAM_ADDRESS
#define IS_EASY_DMA_RAM_ADDRESS(addr) (((uint32_t)addr & 0xFFFF0000) == 0x20000000)
#endif
#define TX_COUNTER_ABORT_REQ_VALUE 256
typedef struct
{
void * p_context;
nrf_uart_event_handler_t handler;
uint8_t const * p_tx_buffer;
uint8_t * p_rx_buffer;
uint8_t * p_rx_secondary_buffer;
volatile uint16_t tx_counter;
uint8_t tx_buffer_length;
uint8_t rx_buffer_length;
uint8_t rx_secondary_buffer_length;
volatile uint8_t rx_counter;
bool rx_enabled;
nrf_drv_state_t state;
#if (defined(UARTE_IN_USE) && defined(UART_IN_USE))
bool use_easy_dma;
#endif
} uart_control_block_t;
static uart_control_block_t m_cb;
static const nrf_drv_uart_config_t m_default_config = NRF_DRV_UART_DEFAULT_CONFIG;
__STATIC_INLINE void apply_config(nrf_drv_uart_config_t const * p_config)
{
nrf_gpio_pin_set(p_config->pseltxd);
nrf_gpio_cfg_output(p_config->pseltxd);
nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL);
CODE_FOR_UARTE
(
nrf_uarte_baudrate_set(NRF_UARTE0, (nrf_uarte_baudrate_t)p_config->baudrate);
nrf_uarte_configure(NRF_UARTE0, (nrf_uarte_parity_t)p_config->parity,
(nrf_uarte_hwfc_t)p_config->hwfc);
nrf_uarte_txrx_pins_set(NRF_UARTE0, p_config->pseltxd, p_config->pselrxd);
if (p_config->hwfc == NRF_UART_HWFC_ENABLED)
{
nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL);
nrf_gpio_pin_set(p_config->pselrts);
nrf_gpio_cfg_output(p_config->pselrts);
nrf_uarte_hwfc_pins_set(NRF_UARTE0, p_config->pselrts, p_config->pselcts);
}
)
CODE_FOR_UART
(
nrf_uart_baudrate_set(NRF_UART0, p_config->baudrate);
nrf_uart_configure(NRF_UART0, p_config->parity, p_config->hwfc);
nrf_uart_txrx_pins_set(NRF_UART0, p_config->pseltxd, p_config->pselrxd);
if (p_config->hwfc == NRF_UART_HWFC_ENABLED)
{
nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL);
nrf_gpio_pin_set(p_config->pselrts);
nrf_gpio_cfg_output(p_config->pselrts);
nrf_uart_hwfc_pins_set(NRF_UART0, p_config->pselrts, p_config->pselcts);
}
)
}
__STATIC_INLINE void interrupts_enable(uint8_t interrupt_priority)
{
CODE_FOR_UARTE
(
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX);
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX);
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ERROR);
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_RXTO);
nrf_uarte_int_enable(NRF_UARTE0, NRF_UARTE_INT_ENDRX_MASK |
NRF_UARTE_INT_ENDTX_MASK |
NRF_UARTE_INT_ERROR_MASK |
NRF_UARTE_INT_RXTO_MASK);
)
CODE_FOR_UART
(
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY);
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXTO);
nrf_uart_int_enable(NRF_UART0, NRF_UART_INT_MASK_TXDRDY |
NRF_UART_INT_MASK_RXTO);
)
nrf_drv_common_irq_enable(UART0_IRQn, interrupt_priority);
}
__STATIC_INLINE void interrupts_disable(void)
{
CODE_FOR_UARTE
(
nrf_uarte_int_disable(NRF_UARTE0, NRF_UARTE_INT_ENDRX_MASK |
NRF_UARTE_INT_ENDTX_MASK |
NRF_UARTE_INT_ERROR_MASK |
NRF_UARTE_INT_RXTO_MASK);
)
CODE_FOR_UART
(
nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY |
NRF_UART_INT_MASK_TXDRDY |
NRF_UART_INT_MASK_ERROR |
NRF_UART_INT_MASK_RXTO);
)
nrf_drv_common_irq_disable(UART0_IRQn);
}
__STATIC_INLINE void pins_to_default(void)
{
/* Reset pins to default states */
uint32_t txd;
uint32_t rxd;
uint32_t rts;
uint32_t cts;
CODE_FOR_UARTE
(
txd = nrf_uarte_tx_pin_get(NRF_UARTE0);
rxd = nrf_uarte_rx_pin_get(NRF_UARTE0);
rts = nrf_uarte_rts_pin_get(NRF_UARTE0);
cts = nrf_uarte_cts_pin_get(NRF_UARTE0);
nrf_uarte_txrx_pins_disconnect(NRF_UARTE0);
nrf_uarte_hwfc_pins_disconnect(NRF_UARTE0);
)
CODE_FOR_UART
(
txd = nrf_uart_tx_pin_get(NRF_UART0);
rxd = nrf_uart_rx_pin_get(NRF_UART0);
rts = nrf_uart_rts_pin_get(NRF_UART0);
cts = nrf_uart_cts_pin_get(NRF_UART0);
nrf_uart_txrx_pins_disconnect(NRF_UART0);
nrf_uart_hwfc_pins_disconnect(NRF_UART0);
)
nrf_gpio_cfg_default(txd);
nrf_gpio_cfg_default(rxd);
if (cts != NRF_UART_PSEL_DISCONNECTED)
{
nrf_gpio_cfg_default(cts);
}
if (rts != NRF_UART_PSEL_DISCONNECTED)
{
nrf_gpio_cfg_default(rts);
}
}
__STATIC_INLINE void uart_enable(void)
{
CODE_FOR_UARTE(nrf_uarte_enable(NRF_UARTE0);)
CODE_FOR_UART(nrf_uart_enable(NRF_UART0););
}
__STATIC_INLINE void uart_disable(void)
{
CODE_FOR_UARTE(nrf_uarte_disable(NRF_UARTE0);)
CODE_FOR_UART(nrf_uart_disable(NRF_UART0););
}
ret_code_t nrf_drv_uart_init(nrf_drv_uart_config_t const * p_config,
nrf_uart_event_handler_t event_handler)
{
if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED)
{
return NRF_ERROR_INVALID_STATE;
}
if (p_config == NULL)
{
p_config = &m_default_config;
}
#if (defined(UARTE_IN_USE) && defined(UART_IN_USE))
m_cb.use_easy_dma = p_config->use_easy_dma;
#endif
apply_config(p_config);
m_cb.handler = event_handler;
m_cb.p_context = p_config->p_context;
if (m_cb.handler)
{
interrupts_enable(p_config->interrupt_priority);
}
uart_enable();
m_cb.rx_buffer_length = 0;
m_cb.rx_secondary_buffer_length = 0;
m_cb.tx_buffer_length = 0;
m_cb.state = NRF_DRV_STATE_INITIALIZED;
m_cb.rx_enabled = false;
return NRF_SUCCESS;
}
void nrf_drv_uart_uninit(void)
{
uart_disable();
if (m_cb.handler)
{
interrupts_disable();
}
pins_to_default();
m_cb.state = NRF_DRV_STATE_UNINITIALIZED;
m_cb.handler = NULL;
}
#if defined(UART_IN_USE)
__STATIC_INLINE void tx_byte(void)
{
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY);
uint8_t txd = m_cb.p_tx_buffer[m_cb.tx_counter];
m_cb.tx_counter++;
nrf_uart_txd_set(NRF_UART0, txd);
}
__STATIC_INLINE ret_code_t nrf_drv_uart_tx_for_uart()
{
ret_code_t err_code = NRF_SUCCESS;
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY);
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTTX);
tx_byte();
if (m_cb.handler == NULL)
{
while (m_cb.tx_counter < (uint16_t) m_cb.tx_buffer_length)
{
while (!nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_TXDRDY) &&
m_cb.tx_counter != TX_COUNTER_ABORT_REQ_VALUE)
{
}
if (m_cb.tx_counter != TX_COUNTER_ABORT_REQ_VALUE)
{
tx_byte();
}
}
if (m_cb.tx_counter == TX_COUNTER_ABORT_REQ_VALUE)
{
err_code = NRF_ERROR_FORBIDDEN;
}
else
{
while (!nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_TXDRDY))
{
}
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPTX);
}
m_cb.tx_buffer_length = 0;
}
return err_code;
}
#endif
#if defined(UARTE_IN_USE)
__STATIC_INLINE ret_code_t nrf_drv_uart_tx_for_uarte()
{
ret_code_t err_code = NRF_SUCCESS;
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX);
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_TXSTOPPED);
nrf_uarte_tx_buffer_set(NRF_UARTE0, m_cb.p_tx_buffer, m_cb.tx_buffer_length);
nrf_uarte_task_trigger(NRF_UARTE0, NRF_UARTE_TASK_STARTTX);
if (m_cb.handler == NULL)
{
bool endtx;
bool txstopped;
do
{
endtx = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX);
txstopped = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_TXSTOPPED);
}
while ((!endtx) && (!txstopped));
if (txstopped)
{
err_code = NRF_ERROR_FORBIDDEN;
}
m_cb.tx_buffer_length = 0;
}
return err_code;
}
#endif
ret_code_t nrf_drv_uart_tx(uint8_t const * const p_data, uint8_t length)
{
ASSERT(m_cb.state == NRF_DRV_STATE_INITIALIZED);
ASSERT(length>0);
ASSERT(p_data);
CODE_FOR_UARTE
(
// EasyDMA requires that transfer buffers are placed in DataRAM,
// signal error if the are not.
if (!IS_EASY_DMA_RAM_ADDRESS(p_data))
{
return NRF_ERROR_INVALID_ADDR;
}
)
if (nrf_drv_uart_tx_in_progress())
{
return NRF_ERROR_BUSY;
}
m_cb.tx_buffer_length = length;
m_cb.p_tx_buffer = p_data;
m_cb.tx_counter = 0;
CODE_FOR_UARTE
(
return nrf_drv_uart_tx_for_uarte();
)
CODE_FOR_UART
(
return nrf_drv_uart_tx_for_uart();
)
}
bool nrf_drv_uart_tx_in_progress(void)
{
return (m_cb.tx_buffer_length != 0);
}
#if defined(UART_IN_USE)
__STATIC_INLINE void rx_enable(void)
{
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_ERROR);
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXDRDY);
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTRX);
}
__STATIC_INLINE void rx_byte(void)
{
if (!m_cb.rx_buffer_length)
{
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXDRDY);
// Byte received when buffer is not set - data lost.
(void) nrf_uart_rxd_get(NRF_UART0);
return;
}
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXDRDY);
m_cb.p_rx_buffer[m_cb.rx_counter] = nrf_uart_rxd_get(NRF_UART0);
m_cb.rx_counter++;
}
__STATIC_INLINE ret_code_t nrf_drv_uart_rx_for_uart(uint8_t * p_data, uint8_t length, bool second_buffer)
{
if ((!m_cb.rx_enabled) && (!second_buffer))
{
rx_enable();
}
if (m_cb.handler == NULL)
{
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXTO);
bool rxrdy;
bool rxto;
bool error;
do
{
do
{
error = nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_ERROR);
rxrdy = nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_RXDRDY);
rxto = nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_RXTO);
} while ((!rxrdy) && (!rxto) && (!error));
if (error || rxto)
{
break;
}
rx_byte();
} while (m_cb.rx_buffer_length > m_cb.rx_counter);
m_cb.rx_buffer_length = 0;
if (error)
{
return NRF_ERROR_INTERNAL;
}
if (rxto)
{
return NRF_ERROR_FORBIDDEN;
}
if (m_cb.rx_enabled)
{
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTRX);
}
else
{
// Skip stopping RX if driver is forced to be enabled.
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX);
}
}
else
{
nrf_uart_int_enable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
}
return NRF_SUCCESS;
}
#endif
#if defined(UARTE_IN_USE)
__STATIC_INLINE ret_code_t nrf_drv_uart_rx_for_uarte(uint8_t * p_data, uint8_t length, bool second_buffer)
{
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX);
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_RXTO);
nrf_uarte_rx_buffer_set(NRF_UARTE0, p_data, length);
if (!second_buffer)
{
nrf_uarte_task_trigger(NRF_UARTE0, NRF_UARTE_TASK_STARTRX);
}
else
{
nrf_uarte_shorts_enable(NRF_UARTE0, NRF_UARTE_SHORT_ENDRX_STARTRX);
}
if (m_cb.handler == NULL)
{
bool endrx;
bool rxto;
bool error;
do {
endrx = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX);
rxto = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_RXTO);
error = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ERROR);
}while ((!endrx) && (!rxto) && (!error));
m_cb.rx_buffer_length = 0;
if (error)
{
return NRF_ERROR_INTERNAL;
}
if (rxto)
{
return NRF_ERROR_FORBIDDEN;
}
}
else
{
nrf_uarte_int_enable(NRF_UARTE0, NRF_UARTE_INT_ERROR_MASK | NRF_UARTE_INT_ENDRX_MASK);
}
return NRF_SUCCESS;
}
#endif
ret_code_t nrf_drv_uart_rx(uint8_t * p_data, uint8_t length)
{
ASSERT(m_cb.state == NRF_DRV_STATE_INITIALIZED);
ASSERT(length>0);
CODE_FOR_UARTE
(
// EasyDMA requires that transfer buffers are placed in DataRAM,
// signal error if the are not.
if (!IS_EASY_DMA_RAM_ADDRESS(p_data))
{
return NRF_ERROR_INVALID_ADDR;
}
)
bool second_buffer = false;
if (m_cb.handler)
{
CODE_FOR_UARTE
(
nrf_uarte_int_disable(NRF_UARTE0, NRF_UARTE_INT_ERROR_MASK | NRF_UARTE_INT_ENDRX_MASK);
)
CODE_FOR_UART
(
nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
)
}
if (m_cb.rx_buffer_length != 0)
{
if (m_cb.rx_secondary_buffer_length != 0)
{
if (m_cb.handler)
{
CODE_FOR_UARTE
(
nrf_uarte_int_enable(NRF_UARTE0, NRF_UARTE_INT_ERROR_MASK | NRF_UARTE_INT_ENDRX_MASK);
)
CODE_FOR_UART
(
nrf_uart_int_enable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
)
}
return NRF_ERROR_BUSY;
}
second_buffer = true;
}
if (!second_buffer)
{
m_cb.rx_buffer_length = length;
m_cb.p_rx_buffer = p_data;
m_cb.rx_counter = 0;
m_cb.rx_secondary_buffer_length = 0;
}
else
{
m_cb.p_rx_secondary_buffer = p_data;
m_cb.rx_secondary_buffer_length = length;
}
CODE_FOR_UARTE
(
return nrf_drv_uart_rx_for_uarte(p_data, length, second_buffer);
)
CODE_FOR_UART
(
return nrf_drv_uart_rx_for_uart(p_data, length, second_buffer);
)
}
void nrf_drv_uart_rx_enable(void)
{
//Easy dma mode does not support enabling receiver without setting up buffer.
CODE_FOR_UARTE
(
ASSERT(false);
)
CODE_FOR_UART
(
if (!m_cb.rx_enabled)
{
rx_enable();
m_cb.rx_enabled = true;
}
)
}
void nrf_drv_uart_rx_disable(void)
{
//Easy dma mode does not support enabling receiver without setting up buffer.
CODE_FOR_UARTE
(
ASSERT(false);
)
CODE_FOR_UART
(
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX);
m_cb.rx_enabled = false;
)
}
uint32_t nrf_drv_uart_errorsrc_get(void)
{
uint32_t errsrc;
CODE_FOR_UARTE
(
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ERROR);
errsrc = nrf_uarte_errorsrc_get_and_clear(NRF_UARTE0);
)
CODE_FOR_UART
(
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_ERROR);
errsrc = nrf_uart_errorsrc_get_and_clear(NRF_UART0);
)
return errsrc;
}
__STATIC_INLINE void rx_done_event(uint8_t bytes, uint8_t * p_data)
{
nrf_drv_uart_event_t event;
event.type = NRF_DRV_UART_EVT_RX_DONE;
event.data.rxtx.bytes = bytes;
event.data.rxtx.p_data = p_data;
m_cb.handler(&event,m_cb.p_context);
}
__STATIC_INLINE void tx_done_event(uint8_t bytes)
{
nrf_drv_uart_event_t event;
event.type = NRF_DRV_UART_EVT_TX_DONE;
event.data.rxtx.bytes = bytes;
event.data.rxtx.p_data = (uint8_t *)m_cb.p_tx_buffer;
m_cb.tx_buffer_length = 0;
m_cb.handler(&event,m_cb.p_context);
}
void nrf_drv_uart_tx_abort(void)
{
CODE_FOR_UARTE
(
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_TXSTOPPED);
nrf_uarte_task_trigger(NRF_UARTE0, NRF_UARTE_TASK_STOPTX);
if (m_cb.handler == NULL)
{
while(!nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_TXSTOPPED));
}
)
CODE_FOR_UART
(
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPTX);
if (m_cb.handler)
{
tx_done_event(m_cb.tx_counter);
}
else
{
m_cb.tx_counter = TX_COUNTER_ABORT_REQ_VALUE;
}
)
}
void nrf_drv_uart_rx_abort(void)
{
CODE_FOR_UARTE
(
nrf_uarte_task_trigger(NRF_UARTE0, NRF_UARTE_TASK_STOPRX);
)
CODE_FOR_UART
(
nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX);
)
}
#if defined(UART_IN_USE)
__STATIC_INLINE void uart_irq_handler()
{
if (nrf_uart_int_enable_check(NRF_UART0, NRF_UART_INT_MASK_ERROR) &&
nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_ERROR))
{
nrf_drv_uart_event_t event;
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_ERROR);
nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
if (!m_cb.rx_enabled)
{
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX);
}
event.type = NRF_DRV_UART_EVT_ERROR;
event.data.error.error_mask = nrf_uart_errorsrc_get_and_clear(NRF_UART0);
event.data.error.rxtx.bytes = m_cb.rx_buffer_length;
event.data.error.rxtx.p_data = m_cb.p_rx_buffer;
//abort transfer
m_cb.rx_buffer_length = 0;
m_cb.rx_secondary_buffer_length = 0;
m_cb.handler(&event,m_cb.p_context);
}
else if (nrf_uart_int_enable_check(NRF_UART0, NRF_UART_INT_MASK_RXDRDY) &&
nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_RXDRDY))
{
rx_byte();
if (m_cb.rx_buffer_length == m_cb.rx_counter)
{
if (m_cb.rx_secondary_buffer_length)
{
uint8_t * p_data = m_cb.p_rx_buffer;
uint8_t rx_counter = m_cb.rx_counter;
//Switch to secondary buffer.
m_cb.rx_buffer_length = m_cb.rx_secondary_buffer_length;
m_cb.p_rx_buffer = m_cb.p_rx_secondary_buffer;
m_cb.rx_secondary_buffer_length = 0;
m_cb.rx_counter = 0;
rx_done_event(rx_counter, p_data);
}
else
{
if (!m_cb.rx_enabled)
{
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX);
}
nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
m_cb.rx_buffer_length = 0;
rx_done_event(m_cb.rx_counter, m_cb.p_rx_buffer);
}
}
}
if (nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_TXDRDY))
{
if (m_cb.tx_counter < (uint16_t) m_cb.tx_buffer_length)
{
tx_byte();
}
else
{
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY);
if (m_cb.tx_buffer_length)
{
tx_done_event(m_cb.tx_buffer_length);
}
}
}
if (nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_RXTO))
{
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXTO);
// RXTO event may be triggered as a result of abort call. In th
if (m_cb.rx_enabled)
{
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTRX);
}
if (m_cb.rx_buffer_length)
{
m_cb.rx_buffer_length = 0;
rx_done_event(m_cb.rx_counter, m_cb.p_rx_buffer);
}
}
}
#endif
#if defined(UARTE_IN_USE)
__STATIC_INLINE void uarte_irq_handler()
{
if (nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ERROR))
{
nrf_drv_uart_event_t event;
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ERROR);
event.type = NRF_DRV_UART_EVT_ERROR;
event.data.error.error_mask = nrf_uarte_errorsrc_get_and_clear(NRF_UARTE0);
event.data.error.rxtx.bytes = nrf_uarte_rx_amount_get(NRF_UARTE0);
event.data.error.rxtx.p_data = m_cb.p_rx_buffer;
//abort transfer
m_cb.rx_buffer_length = 0;
m_cb.rx_secondary_buffer_length = 0;
m_cb.handler(&event,m_cb.p_context);
}
else if (nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX))
{
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX);
uint8_t amount = nrf_uarte_rx_amount_get(NRF_UARTE0);
// If the transfer was stopped before completion, amount of transfered bytes
// will not be equal to the buffer length. Interrupted trunsfer is ignored.
if (amount == m_cb.rx_buffer_length)
{
if (m_cb.rx_secondary_buffer_length)
{
uint8_t * p_data = m_cb.p_rx_buffer;
nrf_uarte_shorts_disable(NRF_UARTE0, NRF_UARTE_SHORT_ENDRX_STARTRX);
m_cb.rx_buffer_length = m_cb.rx_secondary_buffer_length;
m_cb.p_rx_buffer = m_cb.p_rx_secondary_buffer;
m_cb.rx_secondary_buffer_length = 0;
rx_done_event(amount, p_data);
}
else
{
m_cb.rx_buffer_length = 0;
rx_done_event(amount, m_cb.p_rx_buffer);
}
}
}
if (nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_RXTO))
{
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_RXTO);
if (m_cb.rx_buffer_length)
{
m_cb.rx_buffer_length = 0;
rx_done_event(nrf_uarte_rx_amount_get(NRF_UARTE0), m_cb.p_rx_buffer);
}
}
if (nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX))
{
nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX);
if (m_cb.tx_buffer_length)
{
tx_done_event(nrf_uarte_tx_amount_get(NRF_UARTE0));
}
}
}
#endif
void UART0_IRQHandler(void)
{
CODE_FOR_UARTE
(
uarte_irq_handler();
)
CODE_FOR_UART
(
uart_irq_handler();
)
}

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
* @addtogroup nrf_uart UART driver and HAL
* @ingroup nrf_drivers
* @brief UART API.
* @details The UART driver provides APIs for utilizing the UART peripheral.
*
* @defgroup nrf_drv_uart UART driver
* @{
* @ingroup nrf_uart
*
* @brief UART driver.
*/
#ifndef NRF_DRV_UART_H
#define NRF_DRV_UART_H
#include "nrf_uart.h"
#ifdef NRF52
#include "nrf_uarte.h"
#endif
#include "sdk_errors.h"
#include "nrf_drv_config.h"
/**
* @brief Types of UART driver events.
*/
typedef enum
{
NRF_DRV_UART_EVT_TX_DONE, ///< Requested TX transfer completed.
NRF_DRV_UART_EVT_RX_DONE, ///< Requested RX transfer completed.
NRF_DRV_UART_EVT_ERROR, ///< Error reported by UART peripheral.
} nrf_drv_uart_evt_type_t;
/**@brief Structure for UART configuration. */
typedef struct
{
uint32_t pseltxd; ///< TXD pin number.
uint32_t pselrxd; ///< RXD pin number.
uint32_t pselcts; ///< CTS pin number.
uint32_t pselrts; ///< RTS pin number.
void * p_context; ///< Context passed to interrupt handler.
nrf_uart_hwfc_t hwfc; ///< Flow control configuration.
nrf_uart_parity_t parity; ///< Parity configuration.
nrf_uart_baudrate_t baudrate; ///< Baudrate.
uint8_t interrupt_priority; ///< Interrupt priority.
#ifdef NRF52
bool use_easy_dma;
#endif
} nrf_drv_uart_config_t;
/**@brief UART default configuration. */
#ifdef NRF52
#if !UART_LEGACY_SUPPORT
#define DEFAULT_CONFIG_USE_EASY_DMA true
#elif !UART_EASY_DMA_SUPPORT
#define DEFAULT_CONFIG_USE_EASY_DMA false
#else
#define DEFAULT_CONFIG_USE_EASY_DMA UART0_CONFIG_USE_EASY_DMA
#endif
#define NRF_DRV_UART_DEFAULT_CONFIG \
{ \
.pseltxd = UART0_CONFIG_PSEL_TXD, \
.pselrxd = UART0_CONFIG_PSEL_RXD, \
.pselcts = UART0_CONFIG_PSEL_CTS, \
.pselrts = UART0_CONFIG_PSEL_RTS, \
.p_context = NULL, \
.hwfc = UART0_CONFIG_HWFC, \
.parity = UART0_CONFIG_PARITY, \
.baudrate = UART0_CONFIG_BAUDRATE, \
.interrupt_priority = UART0_CONFIG_IRQ_PRIORITY, \
.use_easy_dma = DEFAULT_CONFIG_USE_EASY_DMA \
}
#else
#define NRF_DRV_UART_DEFAULT_CONFIG \
{ \
.pseltxd = UART0_CONFIG_PSEL_TXD, \
.pselrxd = UART0_CONFIG_PSEL_RXD, \
.pselcts = UART0_CONFIG_PSEL_CTS, \
.pselrts = UART0_CONFIG_PSEL_RTS, \
.p_context = NULL, \
.hwfc = UART0_CONFIG_HWFC, \
.parity = UART0_CONFIG_PARITY, \
.baudrate = UART0_CONFIG_BAUDRATE, \
.interrupt_priority = UART0_CONFIG_IRQ_PRIORITY \
}
#endif
/**@brief Structure for UART transfer completion event. */
typedef struct
{
uint8_t * p_data; ///< Pointer to memory used for transfer.
uint8_t bytes; ///< Number of bytes transfered.
} nrf_drv_uart_xfer_evt_t;
/**@brief Structure for UART error event. */
typedef struct
{
nrf_drv_uart_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transfered.
uint32_t error_mask;///< Mask of error flags that generated the event.
} nrf_drv_uart_error_evt_t;
/**@brief Structure for UART event. */
typedef struct
{
nrf_drv_uart_evt_type_t type; ///< Event type.
union
{
nrf_drv_uart_xfer_evt_t rxtx; ///< Data provided for transfer completion events.
nrf_drv_uart_error_evt_t error;///< Data provided for error event.
} data;
} nrf_drv_uart_event_t;
/**
* @brief UART interrupt event handler.
*
* @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available
* only within the context of the event handler.
* @param[in] p_context Context passed to interrupt handler, set on initialization.
*/
typedef void (*nrf_uart_event_handler_t)(nrf_drv_uart_event_t * p_event, void * p_context);
/**
* @brief Function for initializing the UART driver.
*
* This function configures and enables UART. After this function GPIO pins are controlled by UART.
*
* @param[in] p_config Initial configuration. Default configuration used if NULL.
* @param[in] event_handler Event handler provided by the user. If not provided driver works in
* blocking mode.
*
* @retval NRF_SUCCESS If initialization was successful.
* @retval NRF_ERROR_INVALID_STATE If driver is already initialized.
*/
ret_code_t nrf_drv_uart_init(nrf_drv_uart_config_t const * p_config,
nrf_uart_event_handler_t event_handler);
/**
* @brief Function for uninitializing the UART driver.
*/
void nrf_drv_uart_uninit(void);
/**
* @brief Function for getting the address of a specific UART task.
*
* @param[in] task Task.
*
* @return Task address.
*/
__STATIC_INLINE uint32_t nrf_drv_uart_task_address_get(nrf_uart_task_t task);
/**
* @brief Function for getting the address of a specific UART event.
*
* @param[in] event Event.
*
* @return Event address.
*/
__STATIC_INLINE uint32_t nrf_drv_uart_event_address_get(nrf_uart_event_t event);
/**
* @brief Function for sending data over UART.
*
* If an event handler was provided in nrf_drv_uart_init() call, this function
* returns immediately and the handler is called when the transfer is done.
* Otherwise, the transfer is performed in blocking mode, i.e. this function
* returns when the transfer is finished. Blocking mode is not using interrupt so
* there is no context switching inside the function.
*
* @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers
* are placed in the Data RAM region. If they are not and UARTE instance is
* used, this function will fail with error code NRF_ERROR_INVALID_ADDR.
*
* @param[in] p_data Pointer to data.
* @param[in] length Number of bytes to send.
*
* @retval NRF_SUCCESS If initialization was successful.
* @retval NRF_ERROR_BUSY If driver is already transferring.
* @retval NRF_ERROR_FORBIDDEN If the transfer was aborted from a different context
* (blocking mode only, also see @ref nrf_drv_uart_rx_disable).
* @retval NRF_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only).
*/
ret_code_t nrf_drv_uart_tx(uint8_t const * const p_data, uint8_t length);
/**
* @brief Function for checking if UART is currently transmitting.
*
* @retval true If UART is transmitting.
* @retval false If UART is not transmitting.
*/
bool nrf_drv_uart_tx_in_progress(void);
/**
* @brief Function for aborting any ongoing transmission.
* @note @ref NRF_DRV_UART_EVT_TX_DONE event will be generated in non-blocking mode. Event will
* contain number of bytes sent until abort was called. If Easy DMA is not used event will be
* called from the function context. If Easy DMA is used it will be called from UART interrupt
* context.
*/
void nrf_drv_uart_tx_abort(void);
/**
* @brief Function for receiving data over UART.
*
* If an event handler was provided in the nrf_drv_uart_init() call, this function
* returns immediately and the handler is called when the transfer is done.
* Otherwise, the transfer is performed in blocking mode, i.e. this function
* returns when the transfer is finished. Blocking mode is not using interrupt so
* there is no context switching inside the function.
* The receive buffer pointer is double buffered in non-blocking mode. The secondary
* buffer can be set immediately after starting the transfer and will be filled
* when the primary buffer is full. The double buffering feature allows
* receiving data continuously.
*
* @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers
* are placed in the Data RAM region. If they are not and UARTE instance is
* used, this function will fail with error code NRF_ERROR_INVALID_ADDR.
* @param[in] p_data Pointer to data.
* @param[in] length Number of bytes to receive.
*
* @retval NRF_SUCCESS If initialization was successful.
* @retval NRF_ERROR_BUSY If the driver is already receiving
* (and the secondary buffer has already been set
* in non-blocking mode).
* @retval NRF_ERROR_FORBIDDEN If the transfer was aborted from a different context
* (blocking mode only, also see @ref nrf_drv_uart_rx_disable).
* @retval NRF_ERROR_INTERNAL If UART peripheral reported an error.
* @retval NRF_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only).
*/
ret_code_t nrf_drv_uart_rx(uint8_t * p_data, uint8_t length);
/**
* @brief Function for enabling receiver.
*
* UART has 6 byte long RX FIFO and it will be used to store incoming data. If user will not call
* UART receive function before FIFO is filled, overrun error will encounter. Enabling receiver
* without specifying RX buffer is supported only in UART mode (without Easy DMA). Receiver must be
* explicitly closed by the user @sa nrf_drv_uart_rx_disable. Function asserts if mode is wrong.
*/
void nrf_drv_uart_rx_enable(void);
/**
* @brief Function for disabling receiver.
*
* Function must be called to close the receiver after it has been explicitly enabled by
* @sa nrf_drv_uart_rx_enable. Feature is supported only in UART mode (without Easy DMA). Function
* asserts if mode is wrong.
*/
void nrf_drv_uart_rx_disable(void);
/**
* @brief Function for aborting any ongoing reception.
* @note @ref NRF_DRV_UART_EVT_RX_DONE event will be generated in non-blocking mode. Event will
* contain number of bytes received until abort was called. If Easy DMA is not used event will be
* called from the function context. If Easy DMA is used it will be called from UART interrupt
* context.
*/
void nrf_drv_uart_rx_abort(void);
/**
* @brief Function for reading error source mask. Mask contains values from @ref nrf_uart_error_mask_t.
* @note Function should be used in blocking mode only. In case of non-blocking mode error event is
* generated. Function clears error sources after reading.
*
* @retval Mask of reported errors.
*/
uint32_t nrf_drv_uart_errorsrc_get(void);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE uint32_t nrf_drv_uart_task_address_get(nrf_uart_task_t task)
{
return nrf_uart_task_address_get(NRF_UART0, task);
}
__STATIC_INLINE uint32_t nrf_drv_uart_event_address_get(nrf_uart_event_t event)
{
return nrf_uart_event_address_get(NRF_UART0, event);
}
#endif //SUPPRESS_INLINE_IMPLEMENTATION
#endif //NRF_DRV_UART_H
/** @} */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "nrf_drv_wdt.h"
#include "nrf_drv_common.h"
#include "nrf_error.h"
#include "nrf_assert.h"
#include "nrf_wdt.h"
#include "app_util_platform.h"
#include <stdbool.h>
#include <stdint.h>
/**@brief WDT event handler. */
static nrf_wdt_event_handler_t m_wdt_event_handler;
/**@brief WDT state. */
static nrf_drv_state_t m_state;
/**@brief WDT alloc table. */
static uint32_t m_alloc_index;
static const nrf_drv_wdt_config_t m_default_config = NRF_DRV_WDT_DEAFULT_CONFIG;
/**@brief WDT interrupt handler. */
void WDT_IRQHandler(void)
{
if (nrf_wdt_int_enable_check(NRF_WDT_INT_TIMEOUT_MASK) == true)
{
nrf_wdt_event_clear(NRF_WDT_EVENT_TIMEOUT);
m_wdt_event_handler();
}
}
ret_code_t nrf_drv_wdt_init(nrf_drv_wdt_config_t const * p_config,
nrf_wdt_event_handler_t wdt_event_handler)
{
ASSERT(wdt_event_handler != NULL);
m_wdt_event_handler = wdt_event_handler;
if (m_state == NRF_DRV_STATE_UNINITIALIZED)
{
m_state = NRF_DRV_STATE_INITIALIZED;
}
else
{
return NRF_ERROR_INVALID_STATE; // WDT already initialized
}
if (p_config == NULL)
{
p_config = &m_default_config;
}
nrf_wdt_behaviour_set(p_config->behaviour);
nrf_wdt_reload_value_set((p_config->reload_value * 32768) / 1000);
nrf_drv_common_irq_enable(WDT_IRQn, p_config->interrupt_priority);
return NRF_SUCCESS;
}
void nrf_drv_wdt_enable(void)
{
ASSERT(m_alloc_index != 0);
ASSERT(m_state == NRF_DRV_STATE_INITIALIZED);
nrf_wdt_int_enable(NRF_WDT_INT_TIMEOUT_MASK);
nrf_wdt_task_trigger(NRF_WDT_TASK_START);
m_state = NRF_DRV_STATE_POWERED_ON;
}
void nrf_drv_wdt_feed(void)
{
ASSERT(m_state == NRF_DRV_STATE_POWERED_ON);
for(uint32_t i = 0; i < m_alloc_index; i++)
{
nrf_wdt_reload_request_set((nrf_wdt_rr_register_t)(NRF_WDT_RR0 + i));
}
}
ret_code_t nrf_drv_wdt_channel_alloc(nrf_drv_wdt_channel_id * p_channel_id)
{
ret_code_t result;
ASSERT(p_channel_id);
ASSERT(m_state == NRF_DRV_STATE_INITIALIZED);
CRITICAL_REGION_ENTER();
if (m_alloc_index < NRF_WDT_CHANNEL_NUMBER)
{
*p_channel_id = (nrf_drv_wdt_channel_id)(NRF_WDT_RR0 + m_alloc_index);
m_alloc_index++;
nrf_wdt_reload_request_enable(*p_channel_id);
result = NRF_SUCCESS;
}
else
{
result = NRF_ERROR_NO_MEM;
}
CRITICAL_REGION_EXIT();
return result;
}
void nrf_drv_wdt_channel_feed(nrf_drv_wdt_channel_id channel_id)
{
ASSERT(m_state == NRF_DRV_STATE_POWERED_ON);
nrf_wdt_reload_request_set(channel_id);
}

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
* @addtogroup nrf_wdt WDT HAL and driver
* @ingroup nrf_drivers
* @brief Watchdog timer (WDT) APIs.
* @details The WDT HAL provides basic APIs for accessing the registers of the watchdog timer.
* The WDT driver provides APIs on a higher level.
* @defgroup lib_driver_wdt WDT driver
* @{
* @ingroup nrf_wdt
*
* @brief Driver for managing the watchdog timer (WDT).
*/
#ifndef NRF_DRV_WDT_H__
#define NRF_DRV_WDT_H__
#include <stdbool.h>
#include <stdint.h>
#include "sdk_errors.h"
#include "nrf_wdt.h"
#include "nrf_drv_config.h"
/**@brief Struct for WDT initialization. */
typedef struct
{
nrf_wdt_behaviour_t behaviour; /**< WDT behaviour when CPU in sleep/halt mode. */
uint32_t reload_value; /**< WDT reload value in ms. */
uint8_t interrupt_priority; /**< WDT interrupt priority */
} nrf_drv_wdt_config_t;
/**@brief WDT event handler function type. */
typedef void (*nrf_wdt_event_handler_t)(void);
/**@brief WDT channel id type. */
typedef nrf_wdt_rr_register_t nrf_drv_wdt_channel_id;
#define NRF_DRV_WDT_DEAFULT_CONFIG \
{ \
.behaviour = WDT_CONFIG_BEHAVIOUR, \
.reload_value = WDT_CONFIG_RELOAD_VALUE, \
.interrupt_priority = WDT_CONFIG_IRQ_PRIORITY, \
}
/**
* @brief This function initializes watchdog.
*
* @param[in] p_config Initial configuration. Default configuration used if NULL.
* @param[in] wdt_event_handler specifies event handler provided by user.
*
* @note Function asserts if wdt_event_handler is NULL.
*
* @return NRF_SUCCESS on success, NRF_ERROR_INVALID_STATE if module ws already initialized.
*/
ret_code_t nrf_drv_wdt_init(nrf_drv_wdt_config_t const * p_config,
nrf_wdt_event_handler_t wdt_event_handler);
/**
* @brief This function allocate watchdog channel.
*
* @note This function can not be called after nrf_drv_wdt_start(void).
*
* @param[out] p_channel_id ID of granted channel.
*
* @return NRF_SUCCESS on success, otherwise an error code.
*/
ret_code_t nrf_drv_wdt_channel_alloc(nrf_drv_wdt_channel_id * p_channel_id);
/**
* @brief This function starts watchdog.
*
* @note After calling this function the watchdog is started, so the user needs to feed all allocated
* watchdog channels to avoid reset. At least one watchdog channel has to be allocated.
*/
void nrf_drv_wdt_enable(void);
/**
* @brief This function feeds the watchdog.
*
* @details Function feeds all allocated watchdog channels.
*/
void nrf_drv_wdt_feed(void);
/**
* @brief This function feeds the invidual watchdog channel.
*
* @param[in] channel_id ID of watchdog channel.
*/
void nrf_drv_wdt_channel_feed(nrf_drv_wdt_channel_id channel_id);
/**@brief Function for returning a requested task address for the wdt driver module.
*
* @param[in] task One of the peripheral tasks.
*
* @retval Task address.
*/
__STATIC_INLINE uint32_t nrf_drv_wdt_ppi_task_addr(nrf_wdt_task_t task)
{
return nrf_wdt_task_address_get(task);
}
/**@brief Function for returning a requested event address for the wdt driver module.
*
* @param[in] event One of the peripheral events.
*
* @retval Event address
*/
__STATIC_INLINE uint32_t nrf_drv_wdt_ppi_event_addr(nrf_wdt_event_t event)
{
return nrf_wdt_event_address_get(event);
}
#endif
/** @} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup memory_pool_internal Memory Pool Internal
* @{
* @ingroup memory_pool
*
* @brief Memory pool internal definitions
*/
#ifndef MEM_POOL_INTERNAL_H__
#define MEM_POOL_INTERNAL_H__
#define TX_BUF_SIZE 4u /**< TX buffer size in bytes. */
#define RX_BUF_SIZE 32u /**< RX buffer size in bytes. */
#define RX_BUF_QUEUE_SIZE 8u /**< RX buffer element size. */
#endif // MEM_POOL_INTERNAL_H__
/** @} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "bootloader.h"
#include "bootloader_types.h"
#include "bootloader_util.h"
#include "bootloader_settings.h"
#include "dfu.h"
#include "dfu_transport.h"
#include "nrf.h"
#include "app_error.h"
#include "nrf_sdm.h"
#include "nrf_mbr.h"
#include "nordic_common.h"
#include "crc16.h"
#include "pstorage.h"
#include "app_scheduler.h"
#include "nrf_delay.h"
#include "sdk_common.h"
#include "app_timer_appsh.h"
#define APP_TIMER_PRESCALER 0
#define IRQ_ENABLED 0x01 /**< Field identifying if an interrupt is enabled. */
#ifdef NRF52
#define MAX_NUMBER_INTERRUPTS 39
#else
#define MAX_NUMBER_INTERRUPTS 32 /**< Maximum number of interrupts available. */
#endif
/**@brief Enumeration for specifying current bootloader status.
*/
typedef enum
{
BOOTLOADER_UPDATING, /**< Bootloader status for indicating that an update is in progress. */
BOOTLOADER_SETTINGS_SAVING, /**< Bootloader status for indicating that saving of bootloader settings is in progress. */
BOOTLOADER_COMPLETE, /**< Bootloader status for indicating that all operations for the update procedure has completed and it is safe to reset the system. */
BOOTLOADER_TIMEOUT, /**< Bootloader status field for indicating that a timeout has occured and current update process should be aborted. */
BOOTLOADER_RESET, /**< Bootloader status field for indicating that a reset has been requested and current update process should be aborted. */
} bootloader_status_t;
static pstorage_handle_t m_bootsettings_handle; /**< Pstorage handle to use for registration and identifying the bootloader module on subsequent calls to the pstorage module for load and store of bootloader setting in flash. */
static bootloader_status_t m_update_status; /**< Current update status for the bootloader module to ensure correct behaviour when updating settings and when update completes. */
// Adafruit modification for dual transports and forced startup DFU
extern bool is_ota(void);
APP_TIMER_DEF( _forced_startup_dfu_timer );
volatile bool forced_startup_dfu_packet_received = false;
volatile static bool _terminate_startup_dfu = false;
/**@brief Function for handling callbacks from pstorage module.
*
* @details Handles pstorage results for clear and storage operation. For detailed description of
* the parameters provided with the callback, please refer to \ref pstorage_ntf_cb_t.
*/
static void pstorage_callback_handler(pstorage_handle_t * p_handle,
uint8_t op_code,
uint32_t result,
uint8_t * p_data,
uint32_t data_len)
{
// If we are in BOOTLOADER_SETTINGS_SAVING state and we receive an PSTORAGE_STORE_OP_CODE
// response then settings has been saved and update has completed.
if ((m_update_status == BOOTLOADER_SETTINGS_SAVING) && (op_code == PSTORAGE_STORE_OP_CODE))
{
m_update_status = BOOTLOADER_COMPLETE;
}
APP_ERROR_CHECK(result);
}
// Adafruit modifcation
static void terminate_startup_dfu(void * p_event_data, uint16_t event_size)
{
(void) p_event_data;
(void) event_size;
_terminate_startup_dfu = true;
}
/* Terminate the forced DFU mode on startup if no packets is received
* by put an terminal handler to scheduler
*/
static void forced_startup_dfu_timer_handler(void * p_context)
{
// No packets are received within timeout, terminal and DFU mode
// forced_startup_dfu_packet_received is set by process_dfu_packet() in dfu_transport_serial.c
if (!forced_startup_dfu_packet_received)
{
app_sched_event_put(NULL, 0, terminate_startup_dfu);
}
}
/**@brief Function for waiting for events.
*
* @details This function will place the chip in low power mode while waiting for events from
* the SoftDevice or other peripherals. When interrupted by an event, it will call the
* @ref app_sched_execute function to process the received event. This function will return
* when the final state of the firmware update is reached OR when a tear down is in
* progress.
*/
static void wait_for_events(void)
{
for (;;)
{
// Wait in low power state for any events.
uint32_t err_code = sd_app_evt_wait();
APP_ERROR_CHECK(err_code);
// Event received. Process it from the scheduler.
app_sched_execute();
if ((m_update_status == BOOTLOADER_COMPLETE) ||
(m_update_status == BOOTLOADER_TIMEOUT) ||
(m_update_status == BOOTLOADER_RESET))
{
// When update has completed or a timeout/reset occured we will return.
return;
}
// Forced startup dfu mode timeout without any received packet
if (_terminate_startup_dfu)
{
return;
}
}
}
bool bootloader_app_is_valid(uint32_t app_addr)
{
const bootloader_settings_t * p_bootloader_settings;
// There exists an application in CODE region 1.
if (*((uint32_t *)app_addr) == EMPTY_FLASH_MASK)
{
return false;
}
bool success = false;
bootloader_util_settings_get(&p_bootloader_settings);
// The application in CODE region 1 is flagged as valid during update.
if (p_bootloader_settings->bank_0 == BANK_VALID_APP)
{
uint16_t image_crc = 0;
// A stored crc value of 0 indicates that CRC checking is not used.
if (p_bootloader_settings->bank_0_crc != 0)
{
image_crc = crc16_compute((uint8_t *)DFU_BANK_0_REGION_START,
p_bootloader_settings->bank_0_size,
NULL);
}
success = (image_crc == p_bootloader_settings->bank_0_crc);
}
return success;
}
static void bootloader_settings_save(bootloader_settings_t * p_settings)
{
uint32_t err_code = pstorage_clear(&m_bootsettings_handle, sizeof(bootloader_settings_t));
APP_ERROR_CHECK(err_code);
err_code = pstorage_store(&m_bootsettings_handle,
(uint8_t *)p_settings,
sizeof(bootloader_settings_t),
0);
APP_ERROR_CHECK(err_code);
}
void bootloader_dfu_update_process(dfu_update_status_t update_status)
{
static bootloader_settings_t settings;
const bootloader_settings_t * p_bootloader_settings;
bootloader_util_settings_get(&p_bootloader_settings);
if (update_status.status_code == DFU_UPDATE_APP_COMPLETE)
{
settings.bank_0_crc = update_status.app_crc;
settings.bank_0_size = update_status.app_size;
settings.bank_0 = BANK_VALID_APP;
settings.bank_1 = BANK_INVALID_APP;
m_update_status = BOOTLOADER_SETTINGS_SAVING;
bootloader_settings_save(&settings);
}
else if (update_status.status_code == DFU_UPDATE_SD_COMPLETE)
{
settings.bank_0_crc = update_status.app_crc;
settings.bank_0_size = update_status.sd_size +
update_status.bl_size +
update_status.app_size;
settings.bank_0 = BANK_VALID_SD;
settings.bank_1 = BANK_INVALID_APP;
settings.sd_image_size = update_status.sd_size;
settings.bl_image_size = update_status.bl_size;
settings.app_image_size = update_status.app_size;
settings.sd_image_start = update_status.sd_image_start;
m_update_status = BOOTLOADER_SETTINGS_SAVING;
bootloader_settings_save(&settings);
}
else if (update_status.status_code == DFU_UPDATE_BOOT_COMPLETE)
{
settings.bank_0 = p_bootloader_settings->bank_0;
settings.bank_0_crc = p_bootloader_settings->bank_0_crc;
settings.bank_0_size = p_bootloader_settings->bank_0_size;
settings.bank_1 = BANK_VALID_BOOT;
settings.sd_image_size = update_status.sd_size;
settings.bl_image_size = update_status.bl_size;
settings.app_image_size = update_status.app_size;
m_update_status = BOOTLOADER_SETTINGS_SAVING;
bootloader_settings_save(&settings);
}
else if (update_status.status_code == DFU_UPDATE_SD_SWAPPED)
{
if (p_bootloader_settings->bank_0 == BANK_VALID_SD)
{
settings.bank_0_crc = 0;
settings.bank_0_size = 0;
settings.bank_0 = BANK_INVALID_APP;
}
// This handles cases where SoftDevice was not updated, hence bank0 keeps its settings.
else
{
settings.bank_0 = p_bootloader_settings->bank_0;
settings.bank_0_crc = p_bootloader_settings->bank_0_crc;
settings.bank_0_size = p_bootloader_settings->bank_0_size;
}
settings.bank_1 = BANK_INVALID_APP;
settings.sd_image_size = 0;
settings.bl_image_size = 0;
settings.app_image_size = 0;
m_update_status = BOOTLOADER_SETTINGS_SAVING;
bootloader_settings_save(&settings);
}
else if (update_status.status_code == DFU_TIMEOUT)
{
// Timeout has occurred. Close the connection with the DFU Controller.
uint32_t err_code;
if ( is_ota() )
{
err_code = dfu_transport_ble_close();
}else
{
err_code = dfu_transport_serial_close();
}
APP_ERROR_CHECK(err_code);
m_update_status = BOOTLOADER_TIMEOUT;
}
else if (update_status.status_code == DFU_BANK_0_ERASED)
{
settings.bank_0_crc = 0;
settings.bank_0_size = 0;
settings.bank_0 = BANK_INVALID_APP;
settings.bank_1 = p_bootloader_settings->bank_1;
bootloader_settings_save(&settings);
}
else if (update_status.status_code == DFU_RESET)
{
m_update_status = BOOTLOADER_RESET;
}
else
{
// No implementation needed.
}
}
uint32_t bootloader_init(void)
{
uint32_t err_code;
pstorage_module_param_t storage_params = {.cb = pstorage_callback_handler};
err_code = pstorage_init();
VERIFY_SUCCESS(err_code);
m_bootsettings_handle.block_id = BOOTLOADER_SETTINGS_ADDRESS;
err_code = pstorage_register(&storage_params, &m_bootsettings_handle);
return err_code;
}
uint32_t bootloader_dfu_start(bool ota, uint32_t timeout_ms)
{
uint32_t err_code;
// Clear swap if banked update is used.
err_code = dfu_init();
VERIFY_SUCCESS(err_code);
if ( ota )
{
err_code = dfu_transport_ble_update_start();
}else
{
// timeout_ms > 0 is forced startup DFU
if ( timeout_ms )
{
forced_startup_dfu_packet_received = false;
_terminate_startup_dfu = false;
(void) app_timer_create(&_forced_startup_dfu_timer, APP_TIMER_MODE_SINGLE_SHOT, forced_startup_dfu_timer_handler);
app_timer_start(_forced_startup_dfu_timer, APP_TIMER_TICKS(timeout_ms, APP_TIMER_PRESCALER), NULL);
}
err_code = dfu_transport_serial_update_start();
}
wait_for_events();
// Close Serial transport after done
if ( !ota ) dfu_transport_serial_close();
return err_code;
}
/**@brief Function for disabling all interrupts before jumping from bootloader to application.
*/
static void interrupts_disable(void)
{
uint32_t interrupt_setting_mask;
uint32_t irq = 0; // We start from first interrupt, i.e. interrupt 0.
// Fetch the current interrupt settings.
interrupt_setting_mask = NVIC->ISER[0];
for (; irq < MAX_NUMBER_INTERRUPTS; irq++)
{
if (interrupt_setting_mask & (IRQ_ENABLED << irq))
{
// The interrupt was enabled, and hence disable it.
NVIC_DisableIRQ((IRQn_Type)irq);
}
}
}
void bootloader_app_start(uint32_t app_addr)
{
// If the applications CRC has been checked and passed, the magic number will be written and we
// can start the application safely.
uint32_t err_code = sd_softdevice_disable();
APP_ERROR_CHECK(err_code);
interrupts_disable();
// Disable RTC1
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk;
NRF_RTC1->TASKS_STOP = 1;
NRF_RTC1->TASKS_CLEAR = 1;
err_code = sd_softdevice_vector_table_base_set(CODE_REGION_1_START);
APP_ERROR_CHECK(err_code);
bootloader_util_app_start(CODE_REGION_1_START);
}
bool bootloader_dfu_sd_in_progress(void)
{
const bootloader_settings_t * p_bootloader_settings;
bootloader_util_settings_get(&p_bootloader_settings);
if (p_bootloader_settings->bank_0 == BANK_VALID_SD ||
p_bootloader_settings->bank_1 == BANK_VALID_BOOT)
{
return true;
}
return false;
}
uint32_t bootloader_dfu_sd_update_continue(void)
{
uint32_t err_code;
if ((dfu_sd_image_validate() == NRF_SUCCESS) &&
(dfu_bl_image_validate() == NRF_SUCCESS))
{
return NRF_SUCCESS;
}
// Ensure that flash operations are not executed within the first 100 ms seconds to allow
// a debugger to be attached.
nrf_delay_ms(100);
err_code = dfu_sd_image_swap();
APP_ERROR_CHECK(err_code);
err_code = dfu_sd_image_validate();
APP_ERROR_CHECK(err_code);
err_code = dfu_bl_image_swap();
APP_ERROR_CHECK(err_code);
return err_code;
}
uint32_t bootloader_dfu_sd_update_finalize(void)
{
dfu_update_status_t update_status = {DFU_UPDATE_SD_SWAPPED, };
bootloader_dfu_update_process(update_status);
wait_for_events();
return NRF_SUCCESS;
}
void bootloader_settings_get(bootloader_settings_t * const p_settings)
{
const bootloader_settings_t * p_bootloader_settings;
bootloader_util_settings_get(&p_bootloader_settings);
p_settings->bank_0 = p_bootloader_settings->bank_0;
p_settings->bank_0_crc = p_bootloader_settings->bank_0_crc;
p_settings->bank_0_size = p_bootloader_settings->bank_0_size;
p_settings->bank_1 = p_bootloader_settings->bank_1;
p_settings->sd_image_size = p_bootloader_settings->sd_image_size;
p_settings->bl_image_size = p_bootloader_settings->bl_image_size;
p_settings->app_image_size = p_bootloader_settings->app_image_size;
p_settings->sd_image_start = p_bootloader_settings->sd_image_start;
}

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup nrf_bootloader Bootloader API.
* @{
*
* @brief Bootloader module interface.
*/
#ifndef BOOTLOADER_H__
#define BOOTLOADER_H__
#include <stdbool.h>
#include <stdint.h>
#include "bootloader_types.h"
#include <dfu_types.h>
/**@brief Function for initializing the Bootloader.
*
* @retval NRF_SUCCESS If bootloader was succesfully initialized.
*/
uint32_t bootloader_init(void);
/**@brief Function for validating application region in flash.
*
* @param[in] app_addr Address to the region in flash where the application is stored.
*
* @retval true If Application region is valid.
* @retval false If Application region is not valid.
*/
bool bootloader_app_is_valid(uint32_t app_addr);
/**@brief Function for starting the Device Firmware Update.
*
* @retval NRF_SUCCESS If new application image was successfully transferred.
*/
uint32_t bootloader_dfu_start(bool ota, uint32_t timeout_ms);
/**@brief Function for exiting bootloader and booting into application.
*
* @details This function will disable SoftDevice and all interrupts before jumping to application.
* The SoftDevice vector table base for interrupt forwarding will be set the application
* address.
*
* @param[in] app_addr Address to the region where the application is stored.
*/
void bootloader_app_start(uint32_t app_addr);
/**@brief Function for retrieving the bootloader settings.
*
* @param[out] p_settings A copy of the current bootloader settings is returned in the structure
* provided.
*/
void bootloader_settings_get(bootloader_settings_t * const p_settings);
/**@brief Function for processing DFU status update.
*
* @param[in] update_status DFU update status.
*/
void bootloader_dfu_update_process(dfu_update_status_t update_status);
/**@brief Function getting state of SoftDevice update in progress.
* After a successfull SoftDevice transfer the system restarts in orderto disable SoftDevice
* and complete the update.
*
* @retval true A SoftDevice update is in progress. This indicates that second stage
* of a SoftDevice update procedure can be initiated.
* @retval false No SoftDevice update is in progress.
*/
bool bootloader_dfu_sd_in_progress(void);
/**@brief Function for continuing the Device Firmware Update of a SoftDevice.
*
* @retval NRF_SUCCESS If the final stage of SoftDevice update was successful.
*/
uint32_t bootloader_dfu_sd_update_continue(void);
/**@brief Function for finalizing the Device Firmware Update of a SoftDevice.
*
* @retval NRF_SUCCESS If the final stage of SoftDevice update was successful.
*/
uint32_t bootloader_dfu_sd_update_finalize(void);
#endif // BOOTLOADER_H__
/**@} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "bootloader_settings.h"
#include <stdint.h>
#include <dfu_types.h>
#if defined ( __CC_ARM )
uint8_t m_boot_settings[CODE_PAGE_SIZE] __attribute__((at(BOOTLOADER_SETTINGS_ADDRESS))) __attribute__((used)); /**< This variable reserves a codepage for bootloader specific settings, to ensure the compiler doesn't locate any code or variables at his location. */
uint32_t m_uicr_bootloader_start_address __attribute__((at(NRF_UICR_BOOT_START_ADDRESS))) = BOOTLOADER_REGION_START; /**< This variable makes the linker script write the bootloader start address to the UICR register. This value will be written in the HEX file and thus written to UICR when the bootloader is flashed into the chip. */
#elif defined ( __GNUC__ )
uint8_t m_boot_settings[CODE_PAGE_SIZE] __attribute__ ((section(".bootloaderSettings"))); /**< This variable reserves a codepage for bootloader specific settings, to ensure the compiler doesn't locate any code or variables at his location. */
volatile uint32_t m_uicr_bootloader_start_address __attribute__ ((section(".uicrBootStartAddress"))) = BOOTLOADER_REGION_START; /**< This variable ensures that the linker script will write the bootloader start address to the UICR register. This value will be written in the HEX file and thus written to UICR when the bootloader is flashed into the chip. */
#elif defined ( __ICCARM__ )
__no_init uint8_t m_boot_settings[CODE_PAGE_SIZE] @ BOOTLOADER_SETTINGS_ADDRESS; /**< This variable reserves a codepage for bootloader specific settings, to ensure the compiler doesn't locate any code or variables at his location. */
__root const uint32_t m_uicr_bootloader_start_address @ NRF_UICR_BOOT_START_ADDRESS = BOOTLOADER_REGION_START; /**< This variable ensures that the linker script will write the bootloader start address to the UICR register. This value will be written in the HEX file and thus written to UICR when the bootloader is flashed into the chip. */
#endif
#if defined ( NRF52 )
#if defined ( __CC_ARM )
uint8_t m_mbr_params_page[CODE_PAGE_SIZE] __attribute__((at(BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS))) __attribute__((used)); /**< This variable reserves a codepage for mbr parameters, to ensure the compiler doesn't locate any code or variables at his location. */
uint32_t m_uicr_mbr_params_page_address __attribute__((at(NRF_UICR_MBR_PARAMS_PAGE_ADDRESS)))
= BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS; /**< This variable makes the linker script write the mbr parameters page address to the UICR register. This value will be written in the HEX file and thus written to the UICR when the bootloader is flashed into the chip */
#elif defined (__GNUC__ )
uint8_t m_mbr_params_page[CODE_PAGE_SIZE] __attribute__ ((section(".mbrParamsPage"))); /**< This variable reserves a codepage for mbr parameters, to ensure the compiler doesn't locate any code or variables at his location. */
volatile uint32_t m_uicr_mbr_params_page_address __attribute__ ((section(".uicrMbrParamsPageAddress")))
= BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS; /**< This variable makes the linker script write the mbr parameters page address to the UICR register. This value will be written in the HEX file and thus written to the UICR when the bootloader is flashed into the chip */
#elif defined (__ICCARM__ )
__no_init uint8_t m_mbr_params_page[CODE_PAGE_SIZE] @ BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS; /**< This variable reserves a codepage for bootloader specific settings, to ensure the compiler doesn't locate any code or variables at his location. */
__root const uint32_t m_uicr_mbr_params_page_address @ NRF_UICR_MBR_PARAMS_PAGE_ADDRESS = BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS; /**< This variable ensures that the linker script will write the bootloader start address to the UICR register. This value will be written in the HEX file and thus written to UICR when the bootloader is flashed into the chip. */
#endif
#endif //defined ( NRF52 )
void bootloader_util_settings_get(const bootloader_settings_t ** pp_bootloader_settings)
{
// Read only pointer to bootloader settings in flash.
bootloader_settings_t const * const p_bootloader_settings =
(bootloader_settings_t *)&m_boot_settings[0];
*pp_bootloader_settings = p_bootloader_settings;
}

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup nrf_bootloader_settings Bootloader settings API.
* @{
*
* @brief Bootloader settings module interface.
*/
#ifndef BOOTLOADER_SETTINGS_H__
#define BOOTLOADER_SETTINGS_H__
#include <stdint.h>
#include "bootloader_types.h"
/**@brief Function for getting the bootloader settings.
*
* @param[out] pp_bootloader_settings Bootloader settings.
*/
void bootloader_util_settings_get(const bootloader_settings_t ** pp_bootloader_settings);
#endif // BOOTLOADER_SETTINGS_H__
/**@} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup nrf_bootloader_types Types and definitions.
* @{
*
* @ingroup nrf_bootloader
*
* @brief Bootloader module type and definitions.
*/
#ifndef BOOTLOADER_TYPES_H__
#define BOOTLOADER_TYPES_H__
#include <stdint.h>
#define BOOTLOADER_DFU_START 0xB1
#define BOOTLOADER_SVC_APP_DATA_PTR_GET 0x02
/**@brief DFU Bank state code, which indicates wether the bank contains: A valid image, invalid image, or an erased flash.
*/
typedef enum
{
BANK_VALID_APP = 0x01,
BANK_VALID_SD = 0xA5,
BANK_VALID_BOOT = 0xAA,
BANK_ERASED = 0xFE,
BANK_INVALID_APP = 0xFF,
} bootloader_bank_code_t;
/**@brief Structure holding bootloader settings for application and bank data.
*/
typedef struct
{
bootloader_bank_code_t bank_0; /**< Variable to store if bank 0 contains a valid application. */
uint16_t bank_0_crc; /**< If bank is valid, this field will contain a valid CRC of the total image. */
bootloader_bank_code_t bank_1; /**< Variable to store if bank 1 has been erased/prepared for new image. Bank 1 is only used in Banked Update scenario. */
uint32_t bank_0_size; /**< Size of active image in bank0 if present, otherwise 0. */
uint32_t sd_image_size; /**< Size of SoftDevice image in bank0 if bank_0 code is BANK_VALID_SD. */
uint32_t bl_image_size; /**< Size of Bootloader image in bank0 if bank_0 code is BANK_VALID_SD. */
uint32_t app_image_size; /**< Size of Application image in bank0 if bank_0 code is BANK_VALID_SD. */
uint32_t sd_image_start; /**< Location in flash where SoftDevice image is stored for SoftDevice update. */
} bootloader_settings_t;
#endif // BOOTLOADER_TYPES_H__
/**@} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "bootloader_util.h"
#include <stdint.h>
#include <string.h>
/**
* @brief Function for aborting current application/bootloader jump to to other app/bootloader.
*
* @details This functions will use the address provide to swap the stack pointer and then load
* the address of the reset handler to be executed. It will check current system mode
* (thread/handler) and if in thread mode it will reset into other application.
* If in handler mode \ref isr_abort will be executed to ensure correct exit of handler
* mode and jump into reset handler of other application.
*
* @param[in] start_addr Start address of other application. This address must point to the
initial stack pointer of the application.
*
* @note This function will never return but issue a reset into provided application.
*/
#if defined ( __CC_ARM )
__asm static void bootloader_util_reset(uint32_t start_addr)
{
LDR R5, [R0] ; Get App initial MSP for bootloader.
MSR MSP, R5 ; Set the main stack pointer to the applications MSP.
LDR R0, [R0, #0x04] ; Load Reset handler into R0. This will be first argument to branch instruction (BX).
MOVS R4, #0xFF ; Load ones to R4.
SXTB R4, R4 ; Sign extend R4 to obtain 0xFFFFFFFF instead of 0xFF.
MRS R5, IPSR ; Load IPSR to R5 to check for handler or thread mode.
CMP R5, #0x00 ; Compare, if 0 then we are in thread mode and can continue to reset handler of bootloader.
BNE isr_abort ; If not zero we need to exit current ISR and jump to reset handler of bootloader.
MOV LR, R4 ; Clear the link register and set to ones to ensure no return, R4 = 0xFFFFFFFF.
BX R0 ; Branch to reset handler of bootloader.
isr_abort
; R4 contains ones from line above. Will be popped as R12 when exiting ISR (Cleaning up the registers).
MOV R5, R4 ; Fill with ones before jumping to reset handling. We be popped as LR when exiting ISR. Ensures no return to application.
MOV R6, R0 ; Move address of reset handler to R6. Will be popped as PC when exiting ISR. Ensures the reset handler will be executed when exist ISR.
MOVS r7, #0x21 ; Move MSB reset value of xPSR to R7. Will be popped as xPSR when exiting ISR. xPSR is 0x21000000 thus MSB is 0x21.
REV r7, r7 ; Reverse byte order to put 0x21 as MSB.
PUSH {r4-r7} ; Push everything to new stack to allow interrupt handler to fetch it on exiting the ISR.
MOVS R4, #0x00 ; Fill with zeros before jumping to reset handling. We be popped as R0 when exiting ISR (Cleaning up of the registers).
MOVS R5, #0x00 ; Fill with zeros before jumping to reset handling. We be popped as R1 when exiting ISR (Cleaning up of the registers).
MOVS R6, #0x00 ; Fill with zeros before jumping to reset handling. We be popped as R2 when exiting ISR (Cleaning up of the registers).
MOVS R7, #0x00 ; Fill with zeros before jumping to reset handling. We be popped as R3 when exiting ISR (Cleaning up of the registers).
PUSH {r4-r7} ; Push zeros (R4-R7) to stack to prepare for exiting the interrupt routine.
MOVS R0, #0xF9 ; Move the execution return command into register, 0xFFFFFFF9.
SXTB R0, R0 ; Sign extend R0 to obtain 0xFFFFFFF9 instead of 0xF9.
BX R0 ; No return - Handler mode will be exited. Stack will be popped and execution will continue in reset handler initializing other application.
ALIGN
}
#elif defined ( __GNUC__ )
static inline void bootloader_util_reset(uint32_t start_addr)
{
__asm volatile(
"ldr r0, [%0]\t\n" // Get App initial MSP for bootloader.
"msr msp, r0\t\n" // Set the main stack pointer to the applications MSP.
"ldr r0, [%0, #0x04]\t\n" // Load Reset handler into R0.
"movs r4, #0xFF\t\n" // Move ones to R4.
"sxtb r4, r4\t\n" // Sign extend R4 to obtain 0xFFFFFFFF instead of 0xFF.
"mrs r5, IPSR\t\n" // Load IPSR to R5 to check for handler or thread mode.
"cmp r5, #0x00\t\n" // Compare, if 0 then we are in thread mode and can continue to reset handler of bootloader.
"bne isr_abort\t\n" // If not zero we need to exit current ISR and jump to reset handler of bootloader.
"mov lr, r4\t\n" // Clear the link register and set to ones to ensure no return.
"bx r0\t\n" // Branch to reset handler of bootloader.
"isr_abort: \t\n"
"mov r5, r4\t\n" // Fill with ones before jumping to reset handling. Will be popped as LR when exiting ISR. Ensures no return to application.
"mov r6, r0\t\n" // Move address of reset handler to R6. Will be popped as PC when exiting ISR. Ensures the reset handler will be executed when exist ISR.
"movs r7, #0x21\t\n" // Move MSB reset value of xPSR to R7. Will be popped as xPSR when exiting ISR. xPSR is 0x21000000 thus MSB is 0x21.
"rev r7, r7\t\n" // Reverse byte order to put 0x21 as MSB.
"push {r4-r7}\t\n" // Push everything to new stack to allow interrupt handler to fetch it on exiting the ISR.
"movs r4, #0x00\t\n" // Fill with zeros before jumping to reset handling. We be popped as R0 when exiting ISR (Cleaning up of the registers).
"movs r5, #0x00\t\n" // Fill with zeros before jumping to reset handling. We be popped as R1 when exiting ISR (Cleaning up of the registers).
"movs r6, #0x00\t\n" // Fill with zeros before jumping to reset handling. We be popped as R2 when exiting ISR (Cleaning up of the registers).
"movs r7, #0x00\t\n" // Fill with zeros before jumping to reset handling. We be popped as R3 when exiting ISR (Cleaning up of the registers).
"push {r4-r7}\t\n" // Push zeros (R4-R7) to stack to prepare for exiting the interrupt routine.
"movs r0, #0xF9\t\n" // Move the execution return command into register, 0xFFFFFFF9.
"sxtb r0, r0\t\n" // Sign extend R0 to obtain 0xFFFFFFF9 instead of 0xF9.
"bx r0\t\n" // No return - Handler mode will be exited. Stack will be popped and execution will continue in reset handler initializing other application.
".align\t\n"
:: "r" (start_addr) // Argument list for the gcc assembly. start_addr is %0.
: "r0", "r4", "r5", "r6", "r7" // List of register maintained manually.
);
}
#elif defined ( __ICCARM__ )
static inline void bootloader_util_reset(uint32_t start_addr)
{
asm("ldr r5, [%0]\n" // Get App initial MSP for bootloader.
"msr msp, r5\n" // Set the main stack pointer to the applications MSP.
"ldr r0, [%0, #0x04]\n" // Load Reset handler into R0.
"movs r4, #0x00\n" // Load zero into R4.
"mvns r4, r4\n" // Invert R4 to ensure it contain ones.
"mrs r5, IPSR\n" // Load IPSR to R5 to check for handler or thread mode
"cmp r5, #0x00\n" // Compare, if 0 then we are in thread mode and can continue to reset handler of bootloader.
"bne.n isr_abort\n" // If not zero we need to exit current ISR and jump to reset handler of bootloader.
"mov lr, r4\n" // Clear the link register and set to ones to ensure no return.
"bx r0\n" // Branch to reset handler of bootloader.
"isr_abort: \n"
// R4 contains ones from line above. We be popped as R12 when exiting ISR (Cleaning up the registers).
"mov r5, r4\n" // Fill with ones before jumping to reset handling. Will be popped as LR when exiting ISR. Ensures no return to application.
"mov r6, r0\n" // Move address of reset handler to R6. Will be popped as PC when exiting ISR. Ensures the reset handler will be executed when exist ISR.
"movs r7, #0x21\n" // Move MSB reset value of xPSR to R7. Will be popped as xPSR when exiting ISR. xPSR is 0x21000000 thus MSB is 0x21.
"rev r7, r7\n" // Reverse byte order to put 0x21 as MSB.
"push {r4-r7}\n" // Push everything to new stack to allow interrupt handler to fetch it on exiting the ISR.
"movs r4, #0x00\n" // Fill with zeros before jumping to reset handling. We be popped as R0 when exiting ISR (Cleaning up of the registers).
"movs r5, #0x00\n" // Fill with zeros before jumping to reset handling. We be popped as R1 when exiting ISR (Cleaning up of the registers).
"movs r6, #0x00\n" // Fill with zeros before jumping to reset handling. We be popped as R2 when exiting ISR (Cleaning up of the registers).
"movs r7, #0x00\n" // Fill with zeros before jumping to reset handling. We be popped as R3 when exiting ISR (Cleaning up of the registers).
"push {r4-r7}\n" // Push zeros (R4-R7) to stack to prepare for exiting the interrupt routine.
"movs r0, #0x06\n" // Load 0x06 into R6 to prepare for exec return command.
"mvns r0, r0\n" // Invert 0x06 to obtain EXEC_RETURN, 0xFFFFFFF9.
"bx r0\n" // No return - Handler mode will be exited. Stack will be popped and execution will continue in reset handler initializing other application.
:: "r" (start_addr) // Argument list for the IAR assembly. start_addr is %0.
: "r0", "r4", "r5", "r6", "r7"); // List of register maintained manually.
}
#else
#error Compiler not supported.
#endif
void bootloader_util_app_start(uint32_t start_addr)
{
bootloader_util_reset(start_addr);
}

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup nrf_bootloader_util Bootloader util API.
* @{
*
* @brief Bootloader util module interface.
*/
#ifndef BOOTLOADER_UTIL_H__
#define BOOTLOADER_UTIL_H__
#include <stdint.h>
#include "bootloader_types.h"
/**@brief Function for starting the application (or bootloader) at the provided address.
*
* @param[in] start_addr Start address.
*
* @note This function will never retrun. Instead it will reset into the application of the
* provided address.
*/
void bootloader_util_app_start(uint32_t start_addr);
#endif // BOOTLOADER_UTIL_H__
/**@} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup nrf_dfu Device Firmware Update API.
* @{
*
* @brief Device Firmware Update module interface.
*/
#ifndef DFU_H__
#define DFU_H__
#include <dfu_types.h>
#include <stdbool.h>
#include <stdint.h>
/**@brief DFU event callback for asynchronous calls.
*
* @param[in] packet Packet type for which this callback is related. START_PACKET, DATA_PACKET.
* @param[in] result Operation result code. NRF_SUCCESS when a queued operation was successful.
* @param[in] p_data Pointer to the data to which the operation is related.
*/
typedef void (*dfu_callback_t)(uint32_t packet, uint32_t result, uint8_t * p_data);
/**@brief Function for initializing the Device Firmware Update module.
*
* @return NRF_SUCCESS on success, an error_code otherwise.
*/
uint32_t dfu_init(void);
/**@brief Function for registering a callback listener for \ref dfu_data_pkt_handle callbacks.
*
* @param[in] callback_handler Callback handler for receiving DFU events on completed operations
* of DFU packets.
*/
void dfu_register_callback(dfu_callback_t callback_handler);
/**@brief Function for setting the DFU image size.
*
* @details Function sets the DFU image size. This function must be called when an update is started
* in order to notify the DFU of the new image size. If multiple images are to be
* transferred within the same update context then this function must be called with size
* information for each image being transfered.
* If an image type is not being transfered, e.g. SoftDevice but no Application , then the
* image size for application must be zero.
*
* @param[in] p_packet Pointer to the DFU packet containing information on DFU update process to
* be started.
*
* @return NRF_SUCCESS on success, an error_code otherwise.
*/
uint32_t dfu_start_pkt_handle(dfu_update_packet_t * p_packet);
/**@brief Function for handling DFU data packets.
*
* @param[in] p_packet Pointer to the DFU packet.
*
* @return NRF_SUCCESS on success, an error_code otherwise.
*/
uint32_t dfu_data_pkt_handle(dfu_update_packet_t * p_packet);
/**@brief Function for handling DFU init packets.
*
* @return NRF_SUCCESS on success, an error_code otherwise.
*/
uint32_t dfu_init_pkt_handle(dfu_update_packet_t * p_packet);
/**@brief Function for validating a transferred image after the transfer has completed.
*
* @return NRF_SUCCESS on success, an error_code otherwise.
*/
uint32_t dfu_image_validate(void);
/**@brief Function for activating the transfered image after validation has successfully completed.
*
* @return NRF_SUCCESS on success, an error_code otherwise.
*/
uint32_t dfu_image_activate(void);
/**@brief Function for reseting the current update procedure and return to initial state.
*
* @details This function call will result in a system reset to ensure correct system behavior.
* The reset will might be scheduled to execute at a later point in time to ensure pending
* flash operations has completed.
*/
void dfu_reset(void);
/**@brief Function for validating that new bootloader has been correctly installed.
*
* @return NRF_SUCCESS if install was successful. NRF_ERROR_NULL if the images differs.
*/
uint32_t dfu_bl_image_validate(void);
/**@brief Function for validating that new SoftDevicehas been correctly installed.
*
* @return NRF_SUCCESS if install was successful. NRF_ERROR_NULL if the images differs.
*/
uint32_t dfu_sd_image_validate(void);
/**@brief Function for swapping existing bootloader with newly received.
*
* @return NRF_SUCCESS on succesfull swapping. For error code please refer to
* \ref sd_mbr_command_copy_bl_t.
*/
uint32_t dfu_bl_image_swap(void);
/**@brief Function for swapping existing SoftDevice with newly received.
*
* @return NRF_SUCCESS on succesfull swapping. For error code please refer to
* \ref sd_mbr_command_copy_sd_t.
*/
uint32_t dfu_sd_image_swap(void);
/**@brief Function for handling DFU init packet complete.
*
* @return NRF_SUCCESS on success, an error_code otherwise.
*/
uint32_t dfu_init_pkt_complete(void);
#endif // DFU_H__
/** @} */

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "dfu_app_handler.h"
#include <string.h>
#include "bootloader_util.h"
#include "nrf.h"
#include "nrf_sdm.h"
#include "ble_gatt.h"
#include "ble_gatts.h"
#include "app_error.h"
#include "dfu_ble_svc.h"
#include "device_manager.h"
#include "nrf_delay.h"
#define IRQ_ENABLED 0x01 /**< Field that identifies if an interrupt is enabled. */
#define MAX_NUMBER_INTERRUPTS 32 /**< Maximum number of interrupts available. */
static void dfu_app_reset_prepare(void); /**< Forward declaration of default reset handler. */
static dfu_app_reset_prepare_t m_reset_prepare = dfu_app_reset_prepare; /**< Callback function to application to prepare for system reset. Allows application to clean up service and memory before reset. */
static dfu_ble_peer_data_t m_peer_data; /**< Peer data to be used for data exchange when resetting into DFU mode. */
static dm_handle_t m_dm_handle; /**< Device Manager handle with instance IDs of current BLE connection. */
/**@brief Function for reset_prepare handler if the application has not registered a handler.
*/
static void dfu_app_reset_prepare(void)
{
// Reset prepare should be handled by application.
// This function can be extended to include default handling if application does not implement
// own handler.
}
/**@brief Function for disabling all interrupts before jumping from bootloader to application.
*/
static void interrupts_disable(void)
{
uint32_t interrupt_setting_mask;
uint32_t irq;
// Fetch the current interrupt settings.
interrupt_setting_mask = NVIC->ISER[0];
// Loop from interrupt 0 for disabling of all interrupts.
for (irq = 0; irq < MAX_NUMBER_INTERRUPTS; irq++)
{
if (interrupt_setting_mask & (IRQ_ENABLED << irq))
{
// The interrupt was enabled, hence disable it.
NVIC_DisableIRQ((IRQn_Type)irq);
}
}
}
/**@brief Function for providing peer information to DFU for re-establishing a bonded connection in
* DFU mode.
*
* @param[in] conn_handle Connection handle for the connection requesting DFU mode.
*/
static void dfu_app_peer_data_set(uint16_t conn_handle)
{
uint32_t err_code;
dm_sec_keyset_t key_set;
uint32_t app_context_data = 0;
dm_application_context_t app_context;
/** [DFU bond sharing] */
err_code = dm_handle_get(conn_handle, &m_dm_handle);
if (err_code == NRF_SUCCESS)
{
err_code = dm_distributed_keys_get(&m_dm_handle, &key_set);
if (err_code == NRF_SUCCESS)
{
APP_ERROR_CHECK(err_code);
m_peer_data.addr = key_set.keys_central.p_id_key->id_addr_info;
m_peer_data.irk = key_set.keys_central.p_id_key->id_info;
m_peer_data.enc_key.enc_info = key_set.keys_periph.enc_key.p_enc_key->enc_info;
m_peer_data.enc_key.master_id = key_set.keys_periph.enc_key.p_enc_key->master_id;
err_code = dfu_ble_svc_peer_data_set(&m_peer_data);
APP_ERROR_CHECK(err_code);
app_context_data = (DFU_APP_ATT_TABLE_CHANGED << DFU_APP_ATT_TABLE_POS);
app_context.len = sizeof(app_context_data);
app_context.p_data = (uint8_t *)&app_context_data;
app_context.flags = 0;
err_code = dm_application_context_set(&m_dm_handle, &app_context);
APP_ERROR_CHECK(err_code);
}
else
{
// Keys were not available, thus we have a non-encrypted connection.
err_code = dm_peer_addr_get(&m_dm_handle, &m_peer_data.addr);
APP_ERROR_CHECK(err_code);
err_code = dfu_ble_svc_peer_data_set(&m_peer_data);
APP_ERROR_CHECK(err_code);
}
}
/** [DFU bond sharing] */
}
/**@brief Function for preparing the reset, disabling SoftDevice, and jumping to the bootloader.
*
* @param[in] conn_handle Connection handle for peer requesting to enter DFU mode.
*/
static void bootloader_start(uint16_t conn_handle)
{
uint32_t err_code;
uint16_t sys_serv_attr_len = sizeof(m_peer_data.sys_serv_attr);
err_code = sd_ble_gatts_sys_attr_get(conn_handle,
m_peer_data.sys_serv_attr,
&sys_serv_attr_len,
BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS);
if (err_code != NRF_SUCCESS)
{
// Any error at this stage means the system service attributes could not be fetched.
// This means the service changed indication cannot be sent in DFU mode, but connection
// is still possible to establish.
}
m_reset_prepare();
err_code = sd_power_gpregret_set(BOOTLOADER_DFU_START);
APP_ERROR_CHECK(err_code);
err_code = sd_softdevice_disable();
APP_ERROR_CHECK(err_code);
err_code = sd_softdevice_vector_table_base_set(NRF_UICR->NRFFW[0]);
APP_ERROR_CHECK(err_code);
dfu_app_peer_data_set(conn_handle);
NVIC_ClearPendingIRQ(SWI2_IRQn);
interrupts_disable();
bootloader_util_app_start(NRF_UICR->NRFFW[0]);
}
void dfu_app_on_dfu_evt(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt)
{
switch (p_evt->ble_dfu_evt_type)
{
case BLE_DFU_START:
// Starting the bootloader - will cause reset.
bootloader_start(p_dfu->conn_handle);
break;
default:
{
// Unsupported event received from DFU Service.
// Send back BLE_DFU_RESP_VAL_NOT_SUPPORTED message to peer.
uint32_t err_code = ble_dfu_response_send(p_dfu,
BLE_DFU_START_PROCEDURE,
BLE_DFU_RESP_VAL_NOT_SUPPORTED);
APP_ERROR_CHECK(err_code);
}
break;
}
}
void dfu_app_reset_prepare_set(dfu_app_reset_prepare_t reset_prepare_func)
{
m_reset_prepare = reset_prepare_func;
}
void dfu_app_dm_appl_instance_set(dm_application_instance_t app_instance)
{
uint32_t err_code;
err_code = dm_application_instance_set(&app_instance, &m_dm_handle);
APP_ERROR_CHECK(err_code);
}

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup nrf_dfu_app_handler DFU BLE packet handling in application
* @{
*
* @brief Handling of DFU BLE packets in the application.
*
* @details This module implements the handling of DFU packets for switching
* from an application to the bootloader and start DFU mode. The DFU
* packets are transmitted over BLE.
* This module handles only the StartDFU packet, which allows a BLE
* application to expose support for the DFU Service.
* The actual DFU Service runs in a dedicated environment after a BLE
* disconnect and reset of the \nRFXX device.
* The host must reconnect and continue the update procedure with
* access to the full DFU Service.
*
* @note The application must propagate DFU events to this module by calling
* @ref dfu_app_on_dfu_evt from the @ref ble_dfu_evt_handler_t callback.
*/
#ifndef DFU_APP_HANDLER_H__
#define DFU_APP_HANDLER_H__
#include "ble_dfu.h"
#include "nrf_svc.h"
#include "bootloader_types.h"
#include "device_manager.h"
#define DFU_APP_ATT_TABLE_POS 0 /**< Position for the ATT table changed setting. */
#define DFU_APP_ATT_TABLE_CHANGED 1 /**< Value indicating that the ATT table might have changed. This value will be set in the application-specific context in Device Manager when entering DFU mode. */
/**@brief DFU application reset_prepare function. This function is a callback that allows the
* application to prepare for an upcoming application reset.
*/
typedef void (*dfu_app_reset_prepare_t)(void);
/**@brief Function for handling events from the DFU Service.
*
* @details The application must inject this function into the DFU Service or propagate DFU events
* to the dfu_app_handler module by calling this function in the application-specific DFU event
* handler.
*
* @param[in] p_dfu Pointer to the DFU Service structure to which the include event relates.
* @param[in] p_evt Pointer to the DFU event.
*/
void dfu_app_on_dfu_evt(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt);
/**@brief Function for registering a function to prepare a reset.
*
* @details The provided function is executed before resetting the system into bootloader/DFU
* mode. By registering this function, the caller is notified before the reset and can
* thus prepare the application for reset. For example, the application can gracefully
* disconnect any peers on BLE, turn of LEDS, ensure that all pending flash operations
* have completed, and so on.
*
* @param[in] reset_prepare_func Function to be executed before a reset.
*/
void dfu_app_reset_prepare_set(dfu_app_reset_prepare_t reset_prepare_func);
/**@brief Function for setting the Device Manager application instance.
*
* @details This function allows to set the @ref dm_application_instance_t value that is returned by the
* Device Manager when the application registers using @ref dm_register.
* If this function is not called, it is not be possible to share bonding information
* from the application to the bootloader/DFU when entering DFU mode.
*
* @param[in] app_instance Value for the application instance in use.
*/
void dfu_app_dm_appl_instance_set(dm_application_instance_t app_instance);
#endif // DFU_APP_HANDLER_H__
/** @} */

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup dfu_bank_internal Device Firmware Update internal header for bank handling in DFU.
* @{
*
* @brief Device Firmware Update Bank handling module interface.
*
* @details This header is intended for shared definition and functions between single and dual bank
* implementations used for DFU support. It is not supposed to be used for external access
* to the DFU module.
*
*/
#ifndef DFU_BANK_INTERNAL_H__
#define DFU_BANK_INTERNAL_H__
#include <dfu_types.h>
/**@brief States of the DFU state machine. */
typedef enum
{
DFU_STATE_INIT_ERROR, /**< State for: dfu_init(...) error. */
DFU_STATE_IDLE, /**< State for: idle. */
DFU_STATE_PREPARING, /**< State for: preparing, indicates that the flash is being erased and no data packets can be processed. */
DFU_STATE_RDY, /**< State for: ready. */
DFU_STATE_RX_INIT_PKT, /**< State for: receiving initialization packet. */
DFU_STATE_RX_DATA_PKT, /**< State for: receiving data packet. */
DFU_STATE_VALIDATE, /**< State for: validate. */
DFU_STATE_WAIT_4_ACTIVATE /**< State for: waiting for dfu_image_activate(). */
} dfu_state_t;
#define APP_TIMER_PRESCALER 0 /**< Value of the RTC1 PRESCALER register. */
#define DFU_TIMEOUT_INTERVAL APP_TIMER_TICKS(300000, APP_TIMER_PRESCALER) /**< DFU timeout interval in units of timer ticks. */
#define IS_UPDATING_SD(START_PKT) ((START_PKT).dfu_update_mode & DFU_UPDATE_SD) /**< Macro for determining if a SoftDevice update is ongoing. */
#define IS_UPDATING_BL(START_PKT) ((START_PKT).dfu_update_mode & DFU_UPDATE_BL) /**< Macro for determining if a Bootloader update is ongoing. */
#define IS_UPDATING_APP(START_PKT) ((START_PKT).dfu_update_mode & DFU_UPDATE_APP) /**< Macro for determining if a Application update is ongoing. */
#define IMAGE_WRITE_IN_PROGRESS() (m_data_received > 0) /**< Macro for determining if an image write is in progress. */
#define IS_WORD_SIZED(SIZE) ((SIZE & (sizeof(uint32_t) - 1)) == 0) /**< Macro for checking that the provided is word sized. */
/**@cond NO_DOXYGEN */
static uint32_t m_data_received; /**< Amount of received data. */
/**@endcond */
/**@brief Type definition of function used for preparing of the bank before receiving of a
* software image.
*
* @param[in] image_size Size of software image being received.
*/
typedef void (*dfu_bank_prepare_t)(uint32_t image_size);
/**@brief Type definition of function used for handling clear complete of the bank before
* receiving of a software image.
*/
typedef void (*dfu_bank_cleared_t)(void);
/**@brief Type definition of function used for activating of the software image received.
*
* @return NRF_SUCCESS If the image has been successfully activated any other NRF_ERROR code in
* case of a failure.
*/
typedef uint32_t (*dfu_bank_activate_t)(void);
/**@brief Structure for holding of function pointers for needed prepare and activate procedure for
* the requested update procedure.
*/
typedef struct
{
dfu_bank_prepare_t prepare; /**< Function pointer to the prepare function called on start of update procedure. */
dfu_bank_cleared_t cleared; /**< Function pointer to the cleared function called after prepare function completes. */
dfu_bank_activate_t activate; /**< Function pointer to the activate function called on finalizing the update procedure. */
} dfu_bank_func_t;
#endif // DFU_BANK_INTERNAL_H__
/** @} */

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup nrf_dfu_ble_svc DFU BLE SVC
* @{
*
* @brief DFU BLE SVC in bootloader. The DFU BLE SuperVisor Calls allow an application to execute
* functions in the installed bootloader.
*
* @details This module implements handling of SuperVisor Calls in the bootloader.
* SuperVisor Calls allow for an application to execute calls into the bootloader.
* Currently, it is possible to exchange bonding information (like keys) from the
* application to a bootloader supporting DFU OTA using BLE, so the update process can be
* done through an already existing bond.
*
* @note The application must make sure that all SuperVisor Calls (SVC) are forwarded to the
* bootloader to ensure correct behavior. Forwarding of SVCs to the bootloader is
* done using the SoftDevice SVC @ref sd_softdevice_vector_table_base_set with the value
* present in @c NRF_UICR->NRFFW[0].
*/
#ifndef DFU_BLE_SVC_H__
#define DFU_BLE_SVC_H__
#include "nrf_svc.h"
#include <stdint.h>
#include "ble_gap.h"
#include "nrf.h"
#include "nrf_soc.h"
#include "nrf_error_sdm.h"
#define BOOTLOADER_SVC_BASE 0x0 /**< The number of the lowest SVC number reserved for the bootloader. */
#define SYSTEM_SERVICE_ATT_SIZE 8 /**< Size of the system service attribute length including CRC-16 at the end. */
/**@brief The SVC numbers used by the SVC functions in the SoC library. */
enum BOOTLOADER_SVCS
{
DFU_BLE_SVC_PEER_DATA_SET = BOOTLOADER_SVC_BASE, /**< SVC number for the setting of peer data call. */
BOOTLOADER_SVC_LAST
};
/**@brief DFU Peer data structure.
*
* @details This structure contains peer data needed for connection to a bonded device during DFU.
* The peer data must be provided by the application to the bootloader during buttonless
* update. See @ref dfu_ble_svc_peer_data_set. It contains bond information about the
* desired DFU peer.
*/
typedef struct
{
ble_gap_addr_t addr; /**< BLE GAP address of the device that initiated the DFU process. */
ble_gap_irk_t irk; /**< IRK of the device that initiated the DFU process if this device uses Private Resolvable Addresses. */
ble_gap_enc_key_t enc_key; /**< Encryption key structure containing encrypted diversifier and LTK for re-establishing the bond. */
uint8_t sys_serv_attr[SYSTEM_SERVICE_ATT_SIZE]; /**< System service attributes for restoring of Service Changed Indication setting in DFU mode. */
} dfu_ble_peer_data_t;
/**@brief SVC Function for setting peer data containing address, IRK, and LTK to establish bonded
* connection in DFU mode.
*
* @param[in] p_peer_data Pointer to the peer data containing keys for the connection.
*
* @retval NRF_ERROR_NULL If a NULL pointer was provided as argument.
* @retval NRF_SUCCESS If the function completed successfully.
*/
SVCALL(DFU_BLE_SVC_PEER_DATA_SET, uint32_t, dfu_ble_svc_peer_data_set(dfu_ble_peer_data_t * p_peer_data));
#endif // DFU_BLE_SVC_H__
/** @} */

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup nrf_dfu_ble_svc_internal DFU BLE SVC internal
* @{
*
* @brief DFU BLE SVC internal functions in bootloader. The DFU BLE SuperVisor Calls allow an
* application to execute functions in the installed bootloader. This interface provides
* internal Bootloader DFU functions for retrieving data exchanged through SuperVisor Calls.
*
*/
#ifndef DFU_BLE_SVC_INTERNAL_H__
#define DFU_BLE_SVC_INTERNAL_H__
#include <stdint.h>
#include "dfu_ble_svc.h"
#include "ble_gap.h"
/**@brief Internal bootloader/DFU function for retrieving peer data provided from application.
*
* @param[out] p_peer_data Peer data set by application to be used for DFU connection.
*
* @retval NRF_SUCCESS If peer data is valid and can be used for connection.
* @retval NRF_ERROR_NULL If p_peer_data is a NULL pointer.
* @retval NRF_ERROR_INVALID_DATA If peer data is not available or invalid.
*/
uint32_t dfu_ble_peer_data_get(dfu_ble_peer_data_t * p_peer_data);
#endif // DFU_BLE_SVC_INTERNAL_H__
/** @} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stddef.h>
#include "dfu.h"
#include <dfu_types.h>
#include "dfu_bank_internal.h"
#include "nrf.h"
#include "nrf_sdm.h"
#include "app_error.h"
#include "app_timer.h"
#include "bootloader.h"
#include "bootloader_types.h"
#include "pstorage.h"
#include "nrf_mbr.h"
#include "dfu_init.h"
#include "sdk_common.h"
static dfu_state_t m_dfu_state; /**< Current DFU state. */
static uint32_t m_image_size; /**< Size of the image that will be transmitted. */
static dfu_start_packet_t m_start_packet; /**< Start packet received for this update procedure. Contains update mode and image sizes information to be used for image transfer. */
static uint8_t m_init_packet[128]; /**< Init packet, can hold CRC, Hash, Signed Hash and similar, for image validation, integrety check and authorization checking. */
static uint8_t m_init_packet_length; /**< Length of init packet received. */
static uint16_t m_image_crc; /**< Calculated CRC of the image received. */
APP_TIMER_DEF(m_dfu_timer_id); /**< Application timer id. */
static bool m_dfu_timed_out = false; /**< Boolean flag value for tracking DFU timer timeout state. */
static pstorage_handle_t m_storage_handle_swap; /**< Pstorage handle for the swap area (bank 1). Bank used when updating an application or bootloader without SoftDevice. */
static pstorage_handle_t m_storage_handle_app; /**< Pstorage handle for the application area (bank 0). Bank used when updating a SoftDevice w/wo bootloader. Handle also used when swapping received application from bank 1 to bank 0. */
static pstorage_handle_t * mp_storage_handle_active; /**< Pointer to the pstorage handle for the active bank for receiving of data packets. */
static dfu_callback_t m_data_pkt_cb; /**< Callback from DFU Bank module for notification of asynchronous operation such as flash prepare. */
static dfu_bank_func_t m_functions; /**< Structure holding operations for the selected update process. */
/**@brief Function for handling callbacks from pstorage module.
*
* @details Handles pstorage results for clear and storage operation. For detailed description of
* the parameters provided with the callback, please refer to \ref pstorage_ntf_cb_t.
*/
static void pstorage_callback_handler(pstorage_handle_t * p_handle,
uint8_t op_code,
uint32_t result,
uint8_t * p_data,
uint32_t data_len)
{
switch (op_code)
{
case PSTORAGE_STORE_OP_CODE:
if ((m_dfu_state == DFU_STATE_RX_DATA_PKT) && (m_data_pkt_cb != NULL))
{
m_data_pkt_cb(DATA_PACKET, result, p_data);
}
break;
case PSTORAGE_CLEAR_OP_CODE:
if (m_dfu_state == DFU_STATE_PREPARING)
{
m_functions.cleared();
m_dfu_state = DFU_STATE_RDY;
if (m_data_pkt_cb != NULL)
{
m_data_pkt_cb(START_PACKET, result, p_data);
}
}
break;
default:
break;
}
APP_ERROR_CHECK(result);
}
/**@brief Function for handling the DFU timeout.
*
* @param[in] p_context The timeout context.
*/
static void dfu_timeout_handler(void * p_context)
{
UNUSED_PARAMETER(p_context);
dfu_update_status_t update_status;
m_dfu_timed_out = true;
update_status.status_code = DFU_TIMEOUT;
bootloader_dfu_update_process(update_status);
}
/**@brief Function for restarting the DFU Timer.
*
* @details This function will stop and restart the DFU timer. This function will be called by the
* functions handling any DFU packet received from the peer that is transferring a firmware
* image.
*/
static uint32_t dfu_timer_restart(void)
{
if (m_dfu_timed_out)
{
// The DFU timer had already timed out.
return NRF_ERROR_INVALID_STATE;
}
uint32_t err_code = app_timer_stop(m_dfu_timer_id);
APP_ERROR_CHECK(err_code);
err_code = app_timer_start(m_dfu_timer_id, DFU_TIMEOUT_INTERVAL, NULL);
APP_ERROR_CHECK(err_code);
return err_code;
}
/**@brief Function for preparing of flash before receiving SoftDevice image.
*
* @details This function will erase current application area to ensure sufficient amount of
* storage for the SoftDevice image. Upon erase complete a callback will be done.
* See \ref dfu_bank_prepare_t for further details.
*/
static void dfu_prepare_func_app_erase(uint32_t image_size)
{
uint32_t err_code;
mp_storage_handle_active = &m_storage_handle_app;
// Doing a SoftDevice update thus current application must be cleared to ensure enough space
// for new SoftDevice.
m_dfu_state = DFU_STATE_PREPARING;
err_code = pstorage_clear(&m_storage_handle_app, m_image_size);
APP_ERROR_CHECK(err_code);
}
/**@brief Function for preparing swap before receiving application or bootloader image.
*
* @details This function will erase current swap area to ensure flash is ready for storage of the
* Application or Bootloader image. Upon erase complete a callback will be done.
* See \ref dfu_bank_prepare_t for further details.
*/
static void dfu_prepare_func_swap_erase(uint32_t image_size)
{
uint32_t err_code;
mp_storage_handle_active = &m_storage_handle_swap;
m_dfu_state = DFU_STATE_PREPARING;
// err_code = pstorage_clear(&m_storage_handle_swap, DFU_IMAGE_MAX_SIZE_BANKED);
err_code = pstorage_clear(&m_storage_handle_swap, image_size);
APP_ERROR_CHECK(err_code);
}
/**@brief Function for handling behaviour when clear operation has completed.
*/
static void dfu_cleared_func_swap(void)
{
// Do nothing.
}
/**@brief Function for handling behaviour when clear operation has completed.
*/
static void dfu_cleared_func_app(void)
{
dfu_update_status_t update_status = {DFU_BANK_0_ERASED, };
bootloader_dfu_update_process(update_status);
}
/**@brief Function for calculating storage offset for receiving SoftDevice image.
*
* @details When a new SoftDevice is received it will be temporary stored in flash before moved to
* address 0x0. In order to succesfully validate transfer and relocation it is important
* that temporary image and final installed image does not ovwerlap hence an offset must
* be calculated in case new image is larger than currently installed SoftDevice.
*/
uint32_t offset_calculate(uint32_t sd_image_size)
{
uint32_t offset = 0;
if (m_start_packet.sd_image_size > DFU_BANK_0_REGION_START)
{
uint32_t page_mask = (CODE_PAGE_SIZE - 1);
uint32_t diff = m_start_packet.sd_image_size - DFU_BANK_0_REGION_START;
offset = diff & ~page_mask;
// Align offset to next page if image size is not page sized.
if ((diff & page_mask) > 0)
{
offset += CODE_PAGE_SIZE;
}
}
return offset;
}
/**@brief Function for activating received SoftDevice image.
*
* @note This function will not move the SoftDevice image.
* The bootloader settings will be marked as SoftDevice update complete and the swapping of
* current SoftDevice will occur after system reset.
*
* @return NRF_SUCCESS on success.
*/
static uint32_t dfu_activate_sd(void)
{
dfu_update_status_t update_status;
update_status.status_code = DFU_UPDATE_SD_COMPLETE;
update_status.app_crc = m_image_crc;
update_status.sd_image_start = DFU_BANK_0_REGION_START;
update_status.sd_size = m_start_packet.sd_image_size;
update_status.bl_size = m_start_packet.bl_image_size;
update_status.app_size = m_start_packet.app_image_size;
bootloader_dfu_update_process(update_status);
return NRF_SUCCESS;
}
/**@brief Function for activating received Application image.
*
* @details This function will move the received application image fram swap (bank 1) to
* application area (bank 0).
*
* @return NRF_SUCCESS on success. Error code otherwise.
*/
static uint32_t dfu_activate_app(void)
{
uint32_t err_code;
// Erase BANK 0.
err_code = pstorage_clear(&m_storage_handle_app, m_start_packet.app_image_size);
APP_ERROR_CHECK(err_code);
err_code = pstorage_store(&m_storage_handle_app,
(uint8_t *)m_storage_handle_swap.block_id,
m_start_packet.app_image_size,
0);
if (err_code == NRF_SUCCESS)
{
dfu_update_status_t update_status;
memset(&update_status, 0, sizeof(dfu_update_status_t ));
update_status.status_code = DFU_UPDATE_APP_COMPLETE;
update_status.app_crc = m_image_crc;
update_status.app_size = m_start_packet.app_image_size;
bootloader_dfu_update_process(update_status);
}
return err_code;
}
/**@brief Function for activating received Bootloader image.
*
* @note This function will not move the bootloader image.
* The bootloader settings will be marked as Bootloader update complete and the swapping of
* current bootloader will occur after system reset.
*
* @return NRF_SUCCESS on success.
*/
static uint32_t dfu_activate_bl(void)
{
dfu_update_status_t update_status;
update_status.status_code = DFU_UPDATE_BOOT_COMPLETE;
update_status.app_crc = m_image_crc;
update_status.sd_size = m_start_packet.sd_image_size;
update_status.bl_size = m_start_packet.bl_image_size;
update_status.app_size = m_start_packet.app_image_size;
bootloader_dfu_update_process(update_status);
return NRF_SUCCESS;
}
uint32_t dfu_init(void)
{
uint32_t err_code;
pstorage_module_param_t storage_module_param = {.cb = pstorage_callback_handler};
m_init_packet_length = 0;
m_image_crc = 0;
err_code = pstorage_register(&storage_module_param, &m_storage_handle_app);
if (err_code != NRF_SUCCESS)
{
m_dfu_state = DFU_STATE_INIT_ERROR;
return err_code;
}
m_storage_handle_app.block_id = DFU_BANK_0_REGION_START;
m_storage_handle_swap = m_storage_handle_app;
m_storage_handle_swap.block_id = DFU_BANK_1_REGION_START;
// Create the timer to monitor the activity by the peer doing the firmware update.
err_code = app_timer_create(&m_dfu_timer_id,
APP_TIMER_MODE_SINGLE_SHOT,
dfu_timeout_handler);
APP_ERROR_CHECK(err_code);
// Start the DFU timer.
err_code = app_timer_start(m_dfu_timer_id, DFU_TIMEOUT_INTERVAL, NULL);
APP_ERROR_CHECK(err_code);
m_data_received = 0;
m_dfu_state = DFU_STATE_IDLE;
return NRF_SUCCESS;
}
void dfu_register_callback(dfu_callback_t callback_handler)
{
m_data_pkt_cb = callback_handler;
}
uint32_t dfu_start_pkt_handle(dfu_update_packet_t * p_packet)
{
uint32_t err_code;
m_start_packet = *(p_packet->params.start_packet);
// Check that the requested update procedure is supported.
// Currently the following combinations are allowed:
// - Application
// - SoftDevice
// - Bootloader
// - SoftDevice with Bootloader
if (IS_UPDATING_APP(m_start_packet) &&
(IS_UPDATING_SD(m_start_packet) || IS_UPDATING_BL(m_start_packet)))
{
// App update is only supported independently.
return NRF_ERROR_NOT_SUPPORTED;
}
if (!(IS_WORD_SIZED(m_start_packet.sd_image_size) &&
IS_WORD_SIZED(m_start_packet.bl_image_size) &&
IS_WORD_SIZED(m_start_packet.app_image_size)))
{
// Image_sizes are not a multiple of 4 (word size).
return NRF_ERROR_NOT_SUPPORTED;
}
m_image_size = m_start_packet.sd_image_size + m_start_packet.bl_image_size +
m_start_packet.app_image_size;
if (m_start_packet.bl_image_size > DFU_BL_IMAGE_MAX_SIZE)
{
return NRF_ERROR_DATA_SIZE;
}
if (IS_UPDATING_SD(m_start_packet))
{
if (m_image_size > (DFU_IMAGE_MAX_SIZE_FULL))
{
return NRF_ERROR_DATA_SIZE;
}
m_functions.prepare = dfu_prepare_func_app_erase;
m_functions.cleared = dfu_cleared_func_app;
m_functions.activate = dfu_activate_sd;
}
else
{
if (m_image_size > DFU_IMAGE_MAX_SIZE_BANKED)
{
return NRF_ERROR_DATA_SIZE;
}
m_functions.prepare = dfu_prepare_func_swap_erase;
m_functions.cleared = dfu_cleared_func_swap;
if (IS_UPDATING_BL(m_start_packet))
{
m_functions.activate = dfu_activate_bl;
}
else
{
m_functions.activate = dfu_activate_app;
}
}
switch (m_dfu_state)
{
case DFU_STATE_IDLE:
// Valid peer activity detected. Hence restart the DFU timer.
err_code = dfu_timer_restart();
VERIFY_SUCCESS(err_code);
m_functions.prepare(m_image_size);
break;
default:
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
uint32_t dfu_data_pkt_handle(dfu_update_packet_t * p_packet)
{
uint32_t data_length;
uint32_t err_code;
uint32_t * p_data;
VERIFY_PARAM_NOT_NULL(p_packet);
// Check pointer alignment.
if (!is_word_aligned(p_packet->params.data_packet.p_data_packet))
{
// The p_data_packet is not word aligned address.
return NRF_ERROR_INVALID_ADDR;
}
switch (m_dfu_state)
{
case DFU_STATE_RDY:
case DFU_STATE_RX_INIT_PKT:
return NRF_ERROR_INVALID_STATE;
case DFU_STATE_RX_DATA_PKT:
data_length = p_packet->params.data_packet.packet_length * sizeof(uint32_t);
if ((m_data_received + data_length) > m_image_size)
{
// The caller is trying to write more bytes into the flash than the size provided to
// the dfu_image_size_set function. This is treated as a serious error condition and
// an unrecoverable one. Hence point the variable mp_app_write_address to the top of
// the flash area. This will ensure that all future application data packet writes
// will be blocked because of the above check.
m_data_received = 0xFFFFFFFF;
return NRF_ERROR_DATA_SIZE;
}
// Valid peer activity detected. Hence restart the DFU timer.
err_code = dfu_timer_restart();
VERIFY_SUCCESS(err_code);
p_data = (uint32_t *)p_packet->params.data_packet.p_data_packet;
err_code = pstorage_store(mp_storage_handle_active,
(uint8_t *)p_data,
data_length,
m_data_received);
VERIFY_SUCCESS(err_code);
m_data_received += data_length;
if (m_data_received != m_image_size)
{
// The entire image is not received yet. More data is expected.
err_code = NRF_ERROR_INVALID_LENGTH;
}
else
{
// The entire image has been received. Return NRF_SUCCESS.
err_code = NRF_SUCCESS;
}
break;
default:
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
uint32_t dfu_init_pkt_complete(void)
{
uint32_t err_code = NRF_ERROR_INVALID_STATE;
// DFU initialization has been done and a start packet has been received.
if (IMAGE_WRITE_IN_PROGRESS())
{
// Image write is already in progress. Cannot handle an init packet now.
return NRF_ERROR_INVALID_STATE;
}
if (m_dfu_state == DFU_STATE_RX_INIT_PKT)
{
err_code = dfu_init_prevalidate(m_init_packet, m_init_packet_length, m_start_packet.dfu_update_mode);
if (err_code == NRF_SUCCESS)
{
m_dfu_state = DFU_STATE_RX_DATA_PKT;
}
else
{
m_init_packet_length = 0;
}
}
return err_code;
}
uint32_t dfu_init_pkt_handle(dfu_update_packet_t * p_packet)
{
uint32_t err_code = NRF_SUCCESS;
uint32_t length;
switch (m_dfu_state)
{
case DFU_STATE_RDY:
m_dfu_state = DFU_STATE_RX_INIT_PKT;
// When receiving init packet in state ready just update and fall through this case.
case DFU_STATE_RX_INIT_PKT:
// DFU initialization has been done and a start packet has been received.
if (IMAGE_WRITE_IN_PROGRESS())
{
// Image write is already in progress. Cannot handle an init packet now.
return NRF_ERROR_INVALID_STATE;
}
// Valid peer activity detected. Hence restart the DFU timer.
err_code = dfu_timer_restart();
VERIFY_SUCCESS(err_code);
length = p_packet->params.data_packet.packet_length * sizeof(uint32_t);
if ((m_init_packet_length + length) > sizeof(m_init_packet))
{
return NRF_ERROR_INVALID_LENGTH;
}
memcpy(&m_init_packet[m_init_packet_length],
&p_packet->params.data_packet.p_data_packet[0],
length);
m_init_packet_length += length;
break;
default:
// Either the start packet was not received or dfu_init function was not called before.
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
uint32_t dfu_image_validate()
{
uint32_t err_code;
switch (m_dfu_state)
{
case DFU_STATE_RX_DATA_PKT:
// Check if the application image write has finished.
if (m_data_received != m_image_size)
{
// Image not yet fully transfered by the peer or the peer has attempted to write
// too much data. Hence the validation should fail.
err_code = NRF_ERROR_INVALID_STATE;
}
else
{
m_dfu_state = DFU_STATE_VALIDATE;
// Valid peer activity detected. Hence restart the DFU timer.
err_code = dfu_timer_restart();
if (err_code == NRF_SUCCESS)
{
err_code = dfu_init_postvalidate((uint8_t *)mp_storage_handle_active->block_id,
m_image_size);
VERIFY_SUCCESS(err_code);
m_dfu_state = DFU_STATE_WAIT_4_ACTIVATE;
}
}
break;
default:
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
uint32_t dfu_image_activate()
{
uint32_t err_code;
switch (m_dfu_state)
{
case DFU_STATE_WAIT_4_ACTIVATE:
// Stop the DFU Timer because the peer activity need not be monitored any longer.
err_code = app_timer_stop(m_dfu_timer_id);
APP_ERROR_CHECK(err_code);
err_code = m_functions.activate();
break;
default:
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
void dfu_reset(void)
{
dfu_update_status_t update_status;
update_status.status_code = DFU_RESET;
bootloader_dfu_update_process(update_status);
}
static uint32_t dfu_compare_block(uint32_t * ptr1, uint32_t * ptr2, uint32_t len)
{
sd_mbr_command_t sd_mbr_cmd;
sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE;
sd_mbr_cmd.params.compare.ptr1 = ptr1;
sd_mbr_cmd.params.compare.ptr2 = ptr2;
sd_mbr_cmd.params.compare.len = len / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}
static uint32_t dfu_copy_sd(uint32_t * src, uint32_t * dst, uint32_t len)
{
sd_mbr_command_t sd_mbr_cmd;
sd_mbr_cmd.command = SD_MBR_COMMAND_COPY_SD;
sd_mbr_cmd.params.copy_sd.src = src;
sd_mbr_cmd.params.copy_sd.dst = dst;
sd_mbr_cmd.params.copy_sd.len = len / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}
static uint32_t dfu_sd_img_block_swap(uint32_t * src,
uint32_t * dst,
uint32_t len,
uint32_t block_size)
{
// It is neccesarry to swap the new SoftDevice in 3 rounds to ensure correct copy of data
// and verifucation of data in case power reset occurs during write to flash.
// To ensure the robustness of swapping the images are compared backwards till start of
// image swap. If the back is identical everything is swapped.
uint32_t err_code = dfu_compare_block(src, dst, len);
if (err_code == NRF_SUCCESS)
{
return err_code;
}
if ((uint32_t)dst > SOFTDEVICE_REGION_START)
{
err_code = dfu_sd_img_block_swap((uint32_t *)((uint32_t)src - block_size),
(uint32_t *)((uint32_t)dst - block_size),
block_size,
block_size);
VERIFY_SUCCESS(err_code);
}
err_code = dfu_copy_sd(src, dst, len);
VERIFY_SUCCESS(err_code);
return dfu_compare_block(src, dst, len);
}
uint32_t dfu_sd_image_swap(void)
{
bootloader_settings_t boot_settings;
bootloader_settings_get(&boot_settings);
if (boot_settings.sd_image_size == 0)
{
return NRF_SUCCESS;
}
if ((SOFTDEVICE_REGION_START + boot_settings.sd_image_size) > boot_settings.sd_image_start)
{
uint32_t err_code;
uint32_t sd_start = SOFTDEVICE_REGION_START;
uint32_t block_size = (boot_settings.sd_image_start - sd_start) / 2;
/* ##### FIX START ##### */
block_size &= ~(uint32_t)(CODE_PAGE_SIZE - 1);
/* ##### FIX END ##### */
uint32_t image_end = boot_settings.sd_image_start + boot_settings.sd_image_size;
uint32_t img_block_start = boot_settings.sd_image_start + 2 * block_size;
uint32_t sd_block_start = sd_start + 2 * block_size;
if (SD_SIZE_GET(MBR_SIZE) < boot_settings.sd_image_size)
{
// This will clear a page thus ensuring the old image is invalidated before swapping.
err_code = dfu_copy_sd((uint32_t *)(sd_start + block_size),
(uint32_t *)(sd_start + block_size),
sizeof(uint32_t));
VERIFY_SUCCESS(err_code);
err_code = dfu_copy_sd((uint32_t *)sd_start, (uint32_t *)sd_start, sizeof(uint32_t));
VERIFY_SUCCESS(err_code);
}
return dfu_sd_img_block_swap((uint32_t *)img_block_start,
(uint32_t *)sd_block_start,
image_end - img_block_start,
block_size);
}
else
{
if (boot_settings.sd_image_size != 0)
{
return dfu_copy_sd((uint32_t *)boot_settings.sd_image_start,
(uint32_t *)SOFTDEVICE_REGION_START,
boot_settings.sd_image_size);
}
}
return NRF_SUCCESS;
}
uint32_t dfu_bl_image_swap(void)
{
bootloader_settings_t bootloader_settings;
sd_mbr_command_t sd_mbr_cmd;
bootloader_settings_get(&bootloader_settings);
if (bootloader_settings.bl_image_size != 0)
{
uint32_t bl_image_start = (bootloader_settings.sd_image_size == 0) ?
DFU_BANK_1_REGION_START :
bootloader_settings.sd_image_start +
bootloader_settings.sd_image_size;
sd_mbr_cmd.command = SD_MBR_COMMAND_COPY_BL;
sd_mbr_cmd.params.copy_bl.bl_src = (uint32_t *)(bl_image_start);
sd_mbr_cmd.params.copy_bl.bl_len = bootloader_settings.bl_image_size / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}
return NRF_SUCCESS;
}
uint32_t dfu_bl_image_validate(void)
{
bootloader_settings_t bootloader_settings;
sd_mbr_command_t sd_mbr_cmd;
bootloader_settings_get(&bootloader_settings);
if (bootloader_settings.bl_image_size != 0)
{
uint32_t bl_image_start = (bootloader_settings.sd_image_size == 0) ?
DFU_BANK_1_REGION_START :
bootloader_settings.sd_image_start +
bootloader_settings.sd_image_size;
sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE;
sd_mbr_cmd.params.compare.ptr1 = (uint32_t *)BOOTLOADER_REGION_START;
sd_mbr_cmd.params.compare.ptr2 = (uint32_t *)(bl_image_start);
sd_mbr_cmd.params.compare.len = bootloader_settings.bl_image_size / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}
return NRF_SUCCESS;
}
uint32_t dfu_sd_image_validate(void)
{
bootloader_settings_t bootloader_settings;
sd_mbr_command_t sd_mbr_cmd;
bootloader_settings_get(&bootloader_settings);
if (bootloader_settings.sd_image_size == 0)
{
return NRF_SUCCESS;
}
if ((SOFTDEVICE_REGION_START + bootloader_settings.sd_image_size) > bootloader_settings.sd_image_start)
{
uint32_t sd_start = SOFTDEVICE_REGION_START;
uint32_t block_size = (bootloader_settings.sd_image_start - sd_start) / 2;
uint32_t image_end = bootloader_settings.sd_image_start +
bootloader_settings.sd_image_size;
uint32_t img_block_start = bootloader_settings.sd_image_start + 2 * block_size;
uint32_t sd_block_start = sd_start + 2 * block_size;
if (SD_SIZE_GET(MBR_SIZE) < bootloader_settings.sd_image_size)
{
return NRF_ERROR_NULL;
}
return dfu_sd_img_block_swap((uint32_t *)img_block_start,
(uint32_t *)sd_block_start,
image_end - img_block_start,
block_size);
}
sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE;
sd_mbr_cmd.params.compare.ptr1 = (uint32_t *)SOFTDEVICE_REGION_START;
sd_mbr_cmd.params.compare.ptr2 = (uint32_t *)bootloader_settings.sd_image_start;
sd_mbr_cmd.params.compare.len = bootloader_settings.sd_image_size / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup nrf_dfu_init Init packet handling in DFU
* @{
*
* @brief Device Firmware Update module type and function declaration for init packet handling.
*
* @details This header contains basic functionality for performing safety checks on software
* updates for \nRFXX based devices. It provides a skeleton for pre-checking an init packet
* to ensure the following image is compatible with this device. A safety check should
* always be performed to prevent accidental flashing of unsupported applications or a
* wrong combination of application and SoftDevice.
* The device information contains information such as:
* - Device type (2 bytes), for example Heart Rate. The device type is a number defined by
* the customer. It can be located in UICR or FICR.
* - Device revision (2 bytes), for example major revision 1, minor revision 0. The device
* revision is a number defined by the customer. It can be located in UICR or FICR.
* - List of SoftDevices supported by this application, for example
* 0x0049 = S110v6_0_0
* 0xFFFE = S110 development (any SoftDevice accepted),
* - CRC or hash of firmware image
*
* @note This module does not support security features such as image signing, but the corresponding
* implementation allows for such extensions.
* If the init packet is signed by a trusted source, it must be decrypted before it can be
* processed.
*/
#ifndef DFU_INIT_H__
#define DFU_INIT_H__
#include <stdint.h>
#include "nrf.h"
/**@brief Structure contained in an init packet. Contains information on device type, revision, and
* supported SoftDevices.
*/
typedef struct
{
uint16_t device_type; /**< Device type (2 bytes), for example Heart Rate. This number must be defined by the customer before production. It can be located in UICR or FICR. */
uint16_t device_rev; /**< Device revision (2 bytes), for example major revision 1, minor revision 0. This number must be defined by the customer before production. It can be located in UICR or FICR. */
uint32_t app_version; /**< Application version for the image software. This field allows for additional checking, for example ensuring that a downgrade is not allowed. */
uint16_t softdevice_len; /**< Number of different SoftDevice revisions compatible with this application. The list of SoftDevice firmware IDs is defined in @ref softdevice. */
uint16_t softdevice[1]; /**< Variable length array of SoftDevices compatible with this application. The length of the array is specified in the length field. SoftDevice firmware id 0xFFFE indicates any SoftDevice. */
} dfu_init_packet_t;
/**@brief Structure holding basic device information settings.
*/
typedef struct
{
uint16_t device_type; /**< Device type (2 bytes), for example Heart Rate. This number must be defined by the customer before production. It can be located in UICR or FICR. */
uint16_t device_rev; /**< Device revision (2 bytes), for example major revision 1, minor revision 0. This number must be defined by the customer before production. It can be located in UICR or FICR. */
} dfu_device_info_t;
/** The device info offset can be modified to place the device info settings at a different location.
* If the customer reserved UICR location is used for other application specific data, the offset
* must be updated to avoid collision with that data.
*/
/** [DFU UICR DEV offset] */
#define UICR_CUSTOMER_DEVICE_INFO_OFFSET 0x0 /**< Device info offset inside the customer UICR reserved area. Customers may change this value to place the device information in a user-preferred location. */
/** [DFU UICR DEV offset] */
#define UICR_CUSTOMER_RESERVED_OFFSET 0x80 /**< Customer reserved area in the UICR. The area from UICR + 0x80 is reserved for customer usage. */
#define DFU_DEVICE_INFO_BASE (NRF_UICR_BASE + \
UICR_CUSTOMER_RESERVED_OFFSET + \
UICR_CUSTOMER_DEVICE_INFO_OFFSET) /**< The device information base address inside of UICR. */
#define DFU_DEVICE_INFO ((dfu_device_info_t *)DFU_DEVICE_INFO_BASE) /**< The memory mapped structure for device information data. */
#define DFU_DEVICE_TYPE_EMPTY ((uint16_t)0xFFFF) /**< Mask indicating no device type is present in UICR. 0xFFFF is default flash pattern when not written with data. */
#define DFU_DEVICE_REVISION_EMPTY ((uint16_t)0xFFFF) /**< Mask indicating no device revision is present in UICR. 0xFFFF is default flash pattern when not written with data. */
#define DFU_SOFTDEVICE_ANY ((uint16_t)0xFFFE) /**< Mask indicating that any SoftDevice is allowed for updating this application. Allows for easy development. Not to be used in production images. */
/**@brief DFU prevalidate call for pre-checking the received init packet.
*
* @details Pre-validation will safety check the firmware image to be transfered in second stage.
* The function currently checks the device type, device revision, application firmware
* version, and supported SoftDevices. More checks should be added according to
* customer-specific requirements.
*
* @param[in] p_init_data Pointer to the init packet. If the init packet is encrypted or signed,
* it must first be decrypted before being checked.
* @param[in] init_data_len Length of the init data.
*
* @retval NRF_SUCCESS If the pre-validation succeeded, that means the image is
* supported by the device and it is considered to come from a
* trusted source (signing).
* @retval NRF_ERROR_INVALID_DATA If the pre-validation failed, that means the image is not
* supported by the device or comes from an un-trusted source
* (signing).
* @retval NRF_ERROR_INVALID_LENGTH If the size of the init packet is not within the limits of
* the init packet handler.
*/
uint32_t dfu_init_prevalidate(uint8_t * p_init_data, uint32_t init_data_len, uint8_t image_type);
/**@brief DFU postvalidate call for post-checking the received image using the init packet.
*
* @details Post-validation can verify the integrity check the firmware image received before
* activating the image.
* Checks performed can be:
* - A simple CRC as shown in the corresponding implementation of this API in the file
* dfu_init_template.c
* - A hash for better verification of the image.
* - A signature to ensure the image originates from a trusted source.
* Checks are intended to be expanded for customer-specific requirements.
*
* @param[in] p_image Pointer to the received image. The init data provided in the call
* \ref dfu_init_prevalidate will be used for validating the image.
* @param[in] image_len Length of the image data.
*
* @retval NRF_SUCCESS If the post-validation succeeded, that meant the integrity of the
* image has been verified and the image originates from a trusted
* source (signing).
* @retval NRF_ERROR_INVALID_DATA If the post-validation failed, that meant the post check of the
* image failed such as the CRC is not matching the image transfered
* or the verification of the image fails (signing).
*/
uint32_t dfu_init_postvalidate(uint8_t * p_image, uint32_t image_len);
#endif // DFU_INIT_H__
/**@} */

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/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup nrf_dfu_init_template Template file with an DFU init packet handling example.
* @{
*
* @ingroup nrf_dfu
*
* @brief This file contains a template on how to implement DFU init packet handling.
*
* @details The template shows how device type and revision can be used for a safety check of the
* received image. It shows how validation can be performed in two stages:
* - Stage 1: Pre-check of firmware image before transfer to ensure the firmware matches:
* - Device Type.
* - Device Revision.
* Installed SoftDevice.
* This template can be extended with additional checks according to needs.
* For example, such a check could be the origin of the image (trusted source)
* based on a signature scheme.
* - Stage 2: Post-check of the image after image transfer but before installing firmware.
* For example, such a check could be an integrity check in form of hashing or
* verification of a signature.
* In this template, a simple CRC check is carried out.
* The CRC check can be replaced with other mechanisms, like signing.
*
* @note This module does not support security features such as image signing, but the
* implementation allows for such extension.
* If the init packet is signed by a trusted source, it must be decrypted before it can be
* processed.
*/
#include "dfu_init.h"
#include <stdint.h>
#include <string.h>
#include <dfu_types.h>
#include "nrf_error.h"
#include "crc16.h"
// ADAFRUIT
// All firmware init data must has Device Type ADAFRUIT_DEVICE_TYPE
// SD + Bootloader upgrade must have ADAFRUIT_SD_UNLOCK_CODE in Device Revision
#define ADAFRUIT_DEVICE_TYPE 0x0052 // for nrf52
#define ADAFRUIT_SD_UNLOCK_CODE 0xADAF
#define DFU_INIT_PACKET_EXT_LENGTH_MIN 2 //< Minimum length of the extended init packet. The extended init packet may contain a CRC, a HASH, or other data. This value must be changed according to the requirements of the system. The template uses a minimum value of two in order to hold a CRC. */
#define DFU_INIT_PACKET_EXT_LENGTH_MAX 10 //< Maximum length of the extended init packet. The extended init packet may contain a CRC, a HASH, or other data. This value must be changed according to the requirements of the system. The template uses a maximum value of 10 in order to hold a CRC and any padded data on transport layer without overflow. */
static uint8_t m_extended_packet[DFU_INIT_PACKET_EXT_LENGTH_MAX]; //< Data array for storage of the extended data received. The extended data follows the normal init data of type \ref dfu_init_packet_t. Extended data can be used for a CRC, hash, signature, or other data. */
static uint8_t m_extended_packet_length; //< Length of the extended data received with init packet. */
uint32_t dfu_init_prevalidate(uint8_t * p_init_data, uint32_t init_data_len, uint8_t image_type)
{
uint32_t i = 0;
// In order to support signing or encryption then any init packet decryption function / library
// should be called from here or implemented at this location.
// Length check to ensure valid data are parsed.
if (init_data_len < sizeof(dfu_init_packet_t))
{
return NRF_ERROR_INVALID_LENGTH;
}
// Current template uses clear text data so they can be casted for pre-check.
dfu_init_packet_t * p_init_packet = (dfu_init_packet_t *)p_init_data;
m_extended_packet_length = ((uint32_t)p_init_data + init_data_len) -
(uint32_t)&p_init_packet->softdevice[p_init_packet->softdevice_len];
if (m_extended_packet_length < DFU_INIT_PACKET_EXT_LENGTH_MIN)
{
return NRF_ERROR_INVALID_LENGTH;
}
if (((uint32_t)p_init_data + init_data_len) <
(uint32_t)&p_init_packet->softdevice[p_init_packet->softdevice_len])
{
return NRF_ERROR_INVALID_LENGTH;
}
memcpy(m_extended_packet,
&p_init_packet->softdevice[p_init_packet->softdevice_len],
m_extended_packet_length);
/** [DFU init application version] */
// To support application versioning, this check should be updated.
// This template allows for any application to be installed. However,
// customers can place a revision number at the bottom of the application
// to be verified by the bootloader. This can be done at a location
// relative to the application, for example the application start
// address + 0x0100.
/** [DFU init application version] */
// First check to verify the image to be transfered matches the device type.
// If no Device type is present in DFU_DEVICE_INFO then any image will be accepted.
// if ((DFU_DEVICE_INFO->device_type != DFU_DEVICE_TYPE_EMPTY) &&
// (p_init_packet->device_type != DFU_DEVICE_INFO->device_type))
// {
// return NRF_ERROR_INVALID_DATA;
// }
// Second check to verify the image to be transfered matches the device revision.
// If no Device revision is present in DFU_DEVICE_INFO then any image will be accepted.
// if ((DFU_DEVICE_INFO->device_rev != DFU_DEVICE_REVISION_EMPTY) &&
// (p_init_packet->device_rev != DFU_DEVICE_INFO->device_rev))
if ( p_init_packet->device_type != ADAFRUIT_DEVICE_TYPE )
{
return NRF_ERROR_FORBIDDEN;
}
// Adafruit unlock code must match to upgrade SoftDevice and/or Bootloader
if ( image_type & (DFU_UPDATE_SD | DFU_UPDATE_BL) )
{
if (p_init_packet->device_rev != ADAFRUIT_SD_UNLOCK_CODE)
{
return NRF_ERROR_FORBIDDEN;
}
}
// Third check: Check the array of supported SoftDevices by this application.
// If the installed SoftDevice does not match any SoftDevice in the list then an
// error is returned.
while (i < p_init_packet->softdevice_len)
{
if (p_init_packet->softdevice[i] == DFU_SOFTDEVICE_ANY ||
p_init_packet->softdevice[i++] == SD_FWID_GET(MBR_SIZE))
{
return NRF_SUCCESS;
}
}
// No matching SoftDevice found - Return NRF_ERROR_INVALID_DATA.
return NRF_ERROR_INVALID_DATA;
}
uint32_t dfu_init_postvalidate(uint8_t * p_image, uint32_t image_len)
{
uint16_t image_crc;
uint16_t received_crc;
// In order to support hashing (and signing) then the (decrypted) hash should be fetched and
// the corresponding hash should be calculated over the image at this location.
// If hashing (or signing) is added to the system then the CRC validation should be removed.
// calculate CRC from active block.
image_crc = crc16_compute(p_image, image_len, NULL);
// Decode the received CRC from extended data.
received_crc = uint16_decode((uint8_t *)&m_extended_packet[0]);
// Compare the received and calculated CRC.
if (image_crc != received_crc)
{
return NRF_ERROR_INVALID_DATA;
}
return NRF_SUCCESS;
}

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stddef.h>
#include "dfu.h"
#include <dfu_types.h>
#include "dfu_bank_internal.h"
#include "nrf.h"
#include "nrf_sdm.h"
#include "app_error.h"
#include "app_timer.h"
#include "bootloader.h"
#include "bootloader_types.h"
#include "pstorage.h"
#include "nrf_mbr.h"
#include "dfu_init.h"
#include "sdk_common.h"
static dfu_state_t m_dfu_state; /**< Current DFU state. */
static uint32_t m_image_size; /**< Size of the image that will be transmitted. */
static dfu_start_packet_t m_start_packet; /**< Start packet received for this update procedure. Contains update mode and image sizes information to be used for image transfer. */
static uint8_t m_init_packet[64]; /**< Init packet, can hold CRC, Hash, Signed Hash and similar, for image validation, integrety check and authorization checking. */
static uint8_t m_init_packet_length; /**< Length of init packet received. */
static uint16_t m_image_crc; /**< Calculated CRC of the image received. */
APP_TIMER_DEF(m_dfu_timer_id); /**< Application timer id. */
static bool m_dfu_timed_out = false; /**< Boolean flag value for tracking DFU timer timeout state. */
static pstorage_handle_t m_storage_handle_app; /**< Pstorage handle for the application area (bank 0). Bank used when updating a SoftDevice w/wo bootloader. Handle also used when swapping received application from bank 1 to bank 0. */
static pstorage_handle_t * mp_storage_handle_active; /**< Pointer to the pstorage handle for the active bank for receiving of data packets. */
static dfu_callback_t m_data_pkt_cb; /**< Callback from DFU Bank module for notification of asynchronous operation such as flash prepare. */
static dfu_bank_func_t m_functions; /**< Structure holding operations for the selected update process. */
/**@brief Function for handling callbacks from pstorage module.
*
* @details Handles pstorage results for clear and storage operation. For detailed description of
* the parameters provided with the callback, please refer to \ref pstorage_ntf_cb_t.
*/
static void pstorage_callback_handler(pstorage_handle_t * p_handle,
uint8_t op_code,
uint32_t result,
uint8_t * p_data,
uint32_t data_len)
{
switch (op_code)
{
case PSTORAGE_STORE_OP_CODE:
if ((m_dfu_state == DFU_STATE_RX_DATA_PKT) && (m_data_pkt_cb != NULL))
{
m_data_pkt_cb(DATA_PACKET, result, p_data);
}
break;
case PSTORAGE_CLEAR_OP_CODE:
if (m_dfu_state == DFU_STATE_PREPARING)
{
m_functions.cleared();
m_dfu_state = DFU_STATE_RDY;
if (m_data_pkt_cb != NULL)
{
m_data_pkt_cb(START_PACKET, result, p_data);
}
}
break;
default:
break;
}
APP_ERROR_CHECK(result);
}
/**@brief Function for handling the DFU timeout.
*
* @param[in] p_context The timeout context.
*/
static void dfu_timeout_handler(void * p_context)
{
UNUSED_PARAMETER(p_context);
dfu_update_status_t update_status;
m_dfu_timed_out = true;
update_status.status_code = DFU_TIMEOUT;
bootloader_dfu_update_process(update_status);
}
/**@brief Function for restarting the DFU Timer.
*
* @details This function will stop and restart the DFU timer. This function will be called by the
* functions handling any DFU packet received from the peer that is transferring a firmware
* image.
*/
static uint32_t dfu_timer_restart(void)
{
if (m_dfu_timed_out)
{
// The DFU timer had already timed out.
return NRF_ERROR_INVALID_STATE;
}
uint32_t err_code = app_timer_stop(m_dfu_timer_id);
APP_ERROR_CHECK(err_code);
err_code = app_timer_start(m_dfu_timer_id, DFU_TIMEOUT_INTERVAL, NULL);
APP_ERROR_CHECK(err_code);
return err_code;
}
/**@brief Function for preparing of flash before receiving SoftDevice image.
*
* @details This function will erase current application area to ensure sufficient amount of
* storage for the SoftDevice image. Upon erase complete a callback will be done.
* See \ref dfu_bank_prepare_t for further details.
*/
static void dfu_prepare_func_app_erase(uint32_t image_size)
{
uint32_t err_code;
mp_storage_handle_active = &m_storage_handle_app;
// Doing a SoftDevice update thus current application must be cleared to ensure enough space
// for new SoftDevice.
m_dfu_state = DFU_STATE_PREPARING;
err_code = pstorage_clear(&m_storage_handle_app, m_image_size);
APP_ERROR_CHECK(err_code);
}
/**@brief Function for handling behaviour when clear operation has completed.
*/
static void dfu_cleared_func_app(void)
{
dfu_update_status_t update_status = {DFU_BANK_0_ERASED, };
bootloader_dfu_update_process(update_status);
}
/**@brief Function for calculating storage offset for receiving SoftDevice image.
*
* @details When a new SoftDevice is received it will be temporary stored in flash before moved to
* address 0x0. In order to succesfully validate transfer and relocation it is important
* that temporary image and final installed image does not ovwerlap hence an offset must
* be calculated in case new image is larger than currently installed SoftDevice.
*/
uint32_t offset_calculate(uint32_t sd_image_size)
{
uint32_t offset = 0;
if (m_start_packet.sd_image_size > DFU_BANK_0_REGION_START)
{
uint32_t page_mask = (CODE_PAGE_SIZE - 1);
uint32_t diff = m_start_packet.sd_image_size - DFU_BANK_0_REGION_START;
offset = diff & ~page_mask;
// Align offset to next page if image size is not page sized.
if ((diff & page_mask) > 0)
{
offset += CODE_PAGE_SIZE;
}
}
return offset;
}
/**@brief Function for activating received SoftDevice image.
*
* @note This function will not move the SoftDevice image.
* The bootloader settings will be marked as SoftDevice update complete and the swapping of
* current SoftDevice will occur after system reset.
*
* @return NRF_SUCCESS on success.
*/
static uint32_t dfu_activate_sd(void)
{
dfu_update_status_t update_status;
update_status.status_code = DFU_UPDATE_SD_COMPLETE;
update_status.app_crc = m_image_crc;
update_status.sd_image_start = DFU_BANK_0_REGION_START;
update_status.sd_size = m_start_packet.sd_image_size;
update_status.bl_size = m_start_packet.bl_image_size;
update_status.app_size = m_start_packet.app_image_size;
bootloader_dfu_update_process(update_status);
return NRF_SUCCESS;
}
/**@brief Function for activating received Application image.
*
* @details This function will move the received application image fram swap (bank 1) to
* application area (bank 0).
*
* @return NRF_SUCCESS on success. Error code otherwise.
*/
static uint32_t dfu_activate_app(void)
{
uint32_t err_code = NRF_SUCCESS;
dfu_update_status_t update_status;
memset(&update_status, 0, sizeof(dfu_update_status_t ));
update_status.status_code = DFU_UPDATE_APP_COMPLETE;
update_status.app_crc = m_image_crc;
update_status.app_size = m_start_packet.app_image_size;
bootloader_dfu_update_process(update_status);
return err_code;
}
/**@brief Function for activating received Bootloader image.
*
* @note This function will not move the bootloader image.
* The bootloader settings will be marked as Bootloader update complete and the swapping of
* current bootloader will occur after system reset.
*
* @return NRF_SUCCESS on success.
*/
static uint32_t dfu_activate_bl(void)
{
dfu_update_status_t update_status;
update_status.status_code = DFU_UPDATE_BOOT_COMPLETE;
update_status.app_crc = m_image_crc;
update_status.sd_size = m_start_packet.sd_image_size;
update_status.bl_size = m_start_packet.bl_image_size;
update_status.app_size = m_start_packet.app_image_size;
bootloader_dfu_update_process(update_status);
return NRF_SUCCESS;
}
uint32_t dfu_init(void)
{
uint32_t err_code;
pstorage_module_param_t storage_module_param = {.cb = pstorage_callback_handler};
m_init_packet_length = 0;
m_image_crc = 0;
err_code = pstorage_register(&storage_module_param, &m_storage_handle_app);
if (err_code != NRF_SUCCESS)
{
m_dfu_state = DFU_STATE_INIT_ERROR;
return err_code;
}
m_storage_handle_app.block_id = DFU_BANK_0_REGION_START;
// Create the timer to monitor the activity by the peer doing the firmware update.
err_code = app_timer_create(&m_dfu_timer_id,
APP_TIMER_MODE_SINGLE_SHOT,
dfu_timeout_handler);
APP_ERROR_CHECK(err_code);
// Start the DFU timer.
err_code = app_timer_start(m_dfu_timer_id, DFU_TIMEOUT_INTERVAL, NULL);
APP_ERROR_CHECK(err_code);
m_data_received = 0;
m_dfu_state = DFU_STATE_IDLE;
return NRF_SUCCESS;
}
void dfu_register_callback(dfu_callback_t callback_handler)
{
m_data_pkt_cb = callback_handler;
}
uint32_t dfu_start_pkt_handle(dfu_update_packet_t * p_packet)
{
uint32_t err_code;
m_start_packet = *(p_packet->params.start_packet);
// Check that the requested update procedure is supported.
// Currently the following combinations are allowed:
// - Application
// - SoftDevice
// - Bootloader
// - SoftDevice with Bootloader
if (IS_UPDATING_APP(m_start_packet) &&
(IS_UPDATING_SD(m_start_packet) || IS_UPDATING_BL(m_start_packet)))
{
// App update is only supported independently.
return NRF_ERROR_NOT_SUPPORTED;
}
if (!(IS_WORD_SIZED(m_start_packet.sd_image_size) &&
IS_WORD_SIZED(m_start_packet.bl_image_size) &&
IS_WORD_SIZED(m_start_packet.app_image_size)))
{
// Image_sizes are not a multiple of 4 (word size).
return NRF_ERROR_NOT_SUPPORTED;
}
m_image_size = m_start_packet.sd_image_size + m_start_packet.bl_image_size +
m_start_packet.app_image_size;
if (m_start_packet.bl_image_size > DFU_BL_IMAGE_MAX_SIZE)
{
return NRF_ERROR_DATA_SIZE;
}
if (m_image_size > (DFU_IMAGE_MAX_SIZE_FULL))
{
return NRF_ERROR_DATA_SIZE;
}
m_functions.prepare = dfu_prepare_func_app_erase;
m_functions.cleared = dfu_cleared_func_app;
if (IS_UPDATING_SD(m_start_packet))
{
m_functions.activate = dfu_activate_sd;
}
else if (IS_UPDATING_BL(m_start_packet))
{
m_functions.activate = dfu_activate_bl;
}
else
{
m_functions.activate = dfu_activate_app;
}
switch (m_dfu_state)
{
case DFU_STATE_IDLE:
// Valid peer activity detected. Hence restart the DFU timer.
err_code = dfu_timer_restart();
VERIFY_SUCCESS(err_code);
m_functions.prepare(m_image_size);
break;
default:
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
uint32_t dfu_data_pkt_handle(dfu_update_packet_t * p_packet)
{
uint32_t data_length;
uint32_t err_code;
uint32_t * p_data;
VERIFY_PARAM_NOT_NULL(p_packet);
// Check pointer alignment.
if (!is_word_aligned(p_packet->params.data_packet.p_data_packet))
{
// The p_data_packet is not word aligned address.
return NRF_ERROR_INVALID_ADDR;
}
switch (m_dfu_state)
{
case DFU_STATE_RDY:
case DFU_STATE_RX_INIT_PKT:
return NRF_ERROR_INVALID_STATE;
case DFU_STATE_RX_DATA_PKT:
data_length = p_packet->params.data_packet.packet_length * sizeof(uint32_t);
if ((m_data_received + data_length) > m_image_size)
{
// The caller is trying to write more bytes into the flash than the size provided to
// the dfu_image_size_set function. This is treated as a serious error condition and
// an unrecoverable one. Hence point the variable mp_app_write_address to the top of
// the flash area. This will ensure that all future application data packet writes
// will be blocked because of the above check.
m_data_received = 0xFFFFFFFF;
return NRF_ERROR_DATA_SIZE;
}
// Valid peer activity detected. Hence restart the DFU timer.
err_code = dfu_timer_restart();
VERIFY_SUCCESS(err_code);
p_data = (uint32_t *)p_packet->params.data_packet.p_data_packet;
err_code = pstorage_store(mp_storage_handle_active,
(uint8_t *)p_data,
data_length,
m_data_received);
VERIFY_SUCCESS(err_code);
m_data_received += data_length;
if (m_data_received != m_image_size)
{
// The entire image is not received yet. More data is expected.
err_code = NRF_ERROR_INVALID_LENGTH;
}
else
{
// The entire image has been received. Return NRF_SUCCESS.
err_code = NRF_SUCCESS;
}
break;
default:
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
uint32_t dfu_init_pkt_complete(void)
{
uint32_t err_code = NRF_ERROR_INVALID_STATE;
// DFU initialization has been done and a start packet has been received.
if (IMAGE_WRITE_IN_PROGRESS())
{
// Image write is already in progress. Cannot handle an init packet now.
return NRF_ERROR_INVALID_STATE;
}
if (m_dfu_state == DFU_STATE_RX_INIT_PKT)
{
err_code = dfu_init_prevalidate(m_init_packet, m_init_packet_length, m_start_packet.dfu_update_mode);
if (err_code == NRF_SUCCESS)
{
m_dfu_state = DFU_STATE_RX_DATA_PKT;
}
else
{
m_init_packet_length = 0;
}
}
return err_code;
}
uint32_t dfu_init_pkt_handle(dfu_update_packet_t * p_packet)
{
uint32_t err_code = NRF_SUCCESS;
uint32_t length;
switch (m_dfu_state)
{
case DFU_STATE_RDY:
m_dfu_state = DFU_STATE_RX_INIT_PKT;
// When receiving init packet in state ready just update and fall through this case.
case DFU_STATE_RX_INIT_PKT:
// DFU initialization has been done and a start packet has been received.
if (IMAGE_WRITE_IN_PROGRESS())
{
// Image write is already in progress. Cannot handle an init packet now.
return NRF_ERROR_INVALID_STATE;
}
// Valid peer activity detected. Hence restart the DFU timer.
err_code = dfu_timer_restart();
VERIFY_SUCCESS(err_code);
length = p_packet->params.data_packet.packet_length * sizeof(uint32_t);
if ((m_init_packet_length + length) > sizeof(m_init_packet))
{
return NRF_ERROR_INVALID_LENGTH;
}
memcpy(&m_init_packet[m_init_packet_length],
&p_packet->params.data_packet.p_data_packet[0],
length);
m_init_packet_length += length;
break;
default:
// Either the start packet was not received or dfu_init function was not called before.
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
uint32_t dfu_image_validate()
{
uint32_t err_code;
switch (m_dfu_state)
{
case DFU_STATE_RX_DATA_PKT:
// Check if the application image write has finished.
if (m_data_received != m_image_size)
{
// Image not yet fully transfered by the peer or the peer has attempted to write
// too much data. Hence the validation should fail.
err_code = NRF_ERROR_INVALID_STATE;
}
else
{
m_dfu_state = DFU_STATE_VALIDATE;
// Valid peer activity detected. Hence restart the DFU timer.
err_code = dfu_timer_restart();
if (err_code == NRF_SUCCESS)
{
err_code = dfu_init_postvalidate((uint8_t *)mp_storage_handle_active->block_id,
m_image_size);
VERIFY_SUCCESS(err_code);
m_dfu_state = DFU_STATE_WAIT_4_ACTIVATE;
}
}
break;
default:
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
uint32_t dfu_image_activate()
{
uint32_t err_code;
switch (m_dfu_state)
{
case DFU_STATE_WAIT_4_ACTIVATE:
// Stop the DFU Timer because the peer activity need not be monitored any longer.
err_code = app_timer_stop(m_dfu_timer_id);
APP_ERROR_CHECK(err_code);
err_code = m_functions.activate();
break;
default:
err_code = NRF_ERROR_INVALID_STATE;
break;
}
return err_code;
}
void dfu_reset(void)
{
dfu_update_status_t update_status;
update_status.status_code = DFU_RESET;
bootloader_dfu_update_process(update_status);
}
static uint32_t dfu_compare_block(uint32_t * ptr1, uint32_t * ptr2, uint32_t len)
{
sd_mbr_command_t sd_mbr_cmd;
sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE;
sd_mbr_cmd.params.compare.ptr1 = ptr1;
sd_mbr_cmd.params.compare.ptr2 = ptr2;
sd_mbr_cmd.params.compare.len = len / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}
static uint32_t dfu_copy_sd(uint32_t * src, uint32_t * dst, uint32_t len)
{
sd_mbr_command_t sd_mbr_cmd;
sd_mbr_cmd.command = SD_MBR_COMMAND_COPY_SD;
sd_mbr_cmd.params.copy_sd.src = src;
sd_mbr_cmd.params.copy_sd.dst = dst;
sd_mbr_cmd.params.copy_sd.len = len / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}
static uint32_t dfu_sd_img_block_swap(uint32_t * src,
uint32_t * dst,
uint32_t len,
uint32_t block_size)
{
// It is neccesarry to swap the new SoftDevice in 3 rounds to ensure correct copy of data
// and verifucation of data in case power reset occurs during write to flash.
// To ensure the robustness of swapping the images are compared backwards till start of
// image swap. If the back is identical everything is swapped.
uint32_t err_code = dfu_compare_block(src, dst, len);
if (err_code == NRF_SUCCESS)
{
return err_code;
}
if ((uint32_t)dst > SOFTDEVICE_REGION_START)
{
err_code = dfu_sd_img_block_swap((uint32_t *)((uint32_t)src - block_size),
(uint32_t *)((uint32_t)dst - block_size),
block_size,
block_size);
VERIFY_SUCCESS(err_code);
}
err_code = dfu_copy_sd(src, dst, len);
VERIFY_SUCCESS(err_code);
return dfu_compare_block(src, dst, len);
}
uint32_t dfu_sd_image_swap(void)
{
bootloader_settings_t boot_settings;
bootloader_settings_get(&boot_settings);
if (boot_settings.sd_image_size == 0)
{
return NRF_SUCCESS;
}
if ((SOFTDEVICE_REGION_START + boot_settings.sd_image_size) > boot_settings.sd_image_start)
{
uint32_t err_code;
uint32_t sd_start = SOFTDEVICE_REGION_START;
uint32_t block_size = (boot_settings.sd_image_start - sd_start) / 2;
/* ##### FIX START ##### */
block_size &= ~(uint32_t)(CODE_PAGE_SIZE - 1);
/* ##### FIX END ##### */
uint32_t image_end = boot_settings.sd_image_start + boot_settings.sd_image_size;
uint32_t img_block_start = boot_settings.sd_image_start + 2 * block_size;
uint32_t sd_block_start = sd_start + 2 * block_size;
if (SD_SIZE_GET(MBR_SIZE) < boot_settings.sd_image_size)
{
// This will clear a page thus ensuring the old image is invalidated before swapping.
err_code = dfu_copy_sd((uint32_t *)(sd_start + block_size),
(uint32_t *)(sd_start + block_size),
sizeof(uint32_t));
VERIFY_SUCCESS(err_code);
err_code = dfu_copy_sd((uint32_t *)sd_start, (uint32_t *)sd_start, sizeof(uint32_t));
VERIFY_SUCCESS(err_code);
}
return dfu_sd_img_block_swap((uint32_t *)img_block_start,
(uint32_t *)sd_block_start,
image_end - img_block_start,
block_size);
}
else
{
if (boot_settings.sd_image_size != 0)
{
return dfu_copy_sd((uint32_t *)boot_settings.sd_image_start,
(uint32_t *)SOFTDEVICE_REGION_START,
boot_settings.sd_image_size);
}
}
return NRF_SUCCESS;
}
uint32_t dfu_bl_image_swap(void)
{
bootloader_settings_t bootloader_settings;
sd_mbr_command_t sd_mbr_cmd;
bootloader_settings_get(&bootloader_settings);
if (bootloader_settings.bl_image_size != 0)
{
uint32_t bl_image_start = (bootloader_settings.sd_image_size == 0) ?
DFU_BANK_0_REGION_START :
bootloader_settings.sd_image_start +
bootloader_settings.sd_image_size;
sd_mbr_cmd.command = SD_MBR_COMMAND_COPY_BL;
sd_mbr_cmd.params.copy_bl.bl_src = (uint32_t *)(bl_image_start);
sd_mbr_cmd.params.copy_bl.bl_len = bootloader_settings.bl_image_size / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}
return NRF_SUCCESS;
}
uint32_t dfu_bl_image_validate(void)
{
bootloader_settings_t bootloader_settings;
sd_mbr_command_t sd_mbr_cmd;
bootloader_settings_get(&bootloader_settings);
if (bootloader_settings.bl_image_size != 0)
{
uint32_t bl_image_start = (bootloader_settings.sd_image_size == 0) ?
DFU_BANK_0_REGION_START :
bootloader_settings.sd_image_start +
bootloader_settings.sd_image_size;
sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE;
sd_mbr_cmd.params.compare.ptr1 = (uint32_t *)BOOTLOADER_REGION_START;
sd_mbr_cmd.params.compare.ptr2 = (uint32_t *)(bl_image_start);
sd_mbr_cmd.params.compare.len = bootloader_settings.bl_image_size / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}
return NRF_SUCCESS;
}
uint32_t dfu_sd_image_validate(void)
{
bootloader_settings_t bootloader_settings;
sd_mbr_command_t sd_mbr_cmd;
bootloader_settings_get(&bootloader_settings);
if (bootloader_settings.sd_image_size == 0)
{
return NRF_SUCCESS;
}
if ((SOFTDEVICE_REGION_START + bootloader_settings.sd_image_size) > bootloader_settings.sd_image_start)
{
uint32_t sd_start = SOFTDEVICE_REGION_START;
uint32_t block_size = (bootloader_settings.sd_image_start - sd_start) / 2;
uint32_t image_end = bootloader_settings.sd_image_start +
bootloader_settings.sd_image_size;
uint32_t img_block_start = bootloader_settings.sd_image_start + 2 * block_size;
uint32_t sd_block_start = sd_start + 2 * block_size;
if (SD_SIZE_GET(MBR_SIZE) < bootloader_settings.sd_image_size)
{
return NRF_ERROR_NULL;
}
return dfu_sd_img_block_swap((uint32_t *)img_block_start,
(uint32_t *)sd_block_start,
image_end - img_block_start,
block_size);
}
sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE;
sd_mbr_cmd.params.compare.ptr1 = (uint32_t *)SOFTDEVICE_REGION_START;
sd_mbr_cmd.params.compare.ptr2 = (uint32_t *)bootloader_settings.sd_image_start;
sd_mbr_cmd.params.compare.len = bootloader_settings.sd_image_size / sizeof(uint32_t);
return sd_mbr_command(&sd_mbr_cmd);
}

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup nrf_dfu_transport DFU transport API.
* @{
*
* @brief DFU transport module interface.
*/
#ifndef DFU_TRANSPORT_H__
#define DFU_TRANSPORT_H__
#include <stdint.h>
/**@brief Function for starting the update of Device Firmware.
*
* @retval NRF_SUCCESS Operation success.
*/
uint32_t dfu_transport_serial_update_start(void);
/**@brief Function for closing the transport layer.
*
* @retval NRF_SUCCESS Operation success.
*/
uint32_t dfu_transport_serial_close(void);
uint32_t dfu_transport_ble_update_start(void);
uint32_t dfu_transport_ble_close();
#endif // DFU_TRANSPORT_H__
/**@} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "dfu_transport.h"
#include <stddef.h>
#include "dfu.h"
#include <dfu_types.h>
#include "app_error.h"
#include "app_util.h"
#include "hci_transport.h"
#include "app_timer.h"
#include "app_scheduler.h"
#define MAX_BUFFERS 4u /**< Maximum number of buffers that can be received queued without being consumed. */
/**
* defgroup Data Packet Queue Access Operation Macros
* @{
*/
/** Provides status showing if the queue is full or not. */
#define DATA_QUEUE_FULL() \
(((MAX_BUFFERS -1) == m_data_queue.count) ? true : false)
/** Provides status showing if the queue is empty or not */
#define DATA_QUEUE_EMPTY() \
((0 == m_data_queue.count) ? true : false)
/** Initializes an element of the data queue. */
#define DATA_QUEUE_ELEMENT_INIT(i) \
m_data_queue.data_packet[(i)].packet_type = INVALID_PACKET
/** Sets the packet type of an element of the data queue. */
#define DATA_QUEUE_ELEMENT_SET_PTYPE(i, t) \
m_data_queue.data_packet[(i)].packet_type = (t)
/** Copies a data packet pointer of an element of the data queue. */
#define DATA_QUEUE_ELEMENT_COPY_PDATA(i, dp) \
m_data_queue.data_packet[(i)].params.data_packet.p_data_packet = (uint32_t *)(dp)
/** Sets the packet length of an element in the data queue. */
#define DATA_QUEUE_ELEMENT_SET_PLEN(i, l) \
m_data_queue.data_packet[(i)].params.data_packet.packet_length = (l)
/** Gets a data packet pointer of an element in the data queue. */
#define DATA_QUEUE_ELEMENT_GET_PDATA(i) \
(m_data_queue.data_packet[(i)].params.data_packet.p_data_packet)
/** Gets the packet type of an element in the data queue. */
#define DATA_QUEUE_ELEMENT_GET_PTYPE(i) \
m_data_queue.data_packet[(i)].packet_type
/* @} */
/** Abstracts data packet queue */
typedef struct
{
dfu_update_packet_t data_packet[MAX_BUFFERS]; /**< Bootloader data packets used when processing data from the UART. */
volatile uint8_t count; /**< Counter to maintain number of elements in the queue. */
} dfu_data_queue_t;
static dfu_data_queue_t m_data_queue; /**< Received-data packet queue. */
/**@brief Initializes an element of the data buffer queue.
*
* @param[in] element_index index of the element.
*/
static void data_queue_element_init (uint8_t element_index)
{
DATA_QUEUE_ELEMENT_INIT(element_index);
DATA_QUEUE_ELEMENT_SET_PTYPE(element_index, INVALID_PACKET);
DATA_QUEUE_ELEMENT_COPY_PDATA(element_index, NULL);
DATA_QUEUE_ELEMENT_SET_PLEN(element_index, 0);
}
/** Initializes data buffer queue */
static void data_queue_init(void)
{
uint32_t index;
m_data_queue.count = 0;
for (index = 0; index < MAX_BUFFERS; index++)
{
data_queue_element_init(index);
}
}
/**@brief Function for freeing an element.
*
* @param[in] element_index index of the element.
*/
static uint32_t data_queue_element_free(uint8_t element_index)
{
uint8_t * p_data;
uint32_t retval;
retval = NRF_ERROR_INVALID_PARAM;
if (MAX_BUFFERS > element_index)
{
p_data = (uint8_t *)DATA_QUEUE_ELEMENT_GET_PDATA(element_index);
if (INVALID_PACKET != DATA_QUEUE_ELEMENT_GET_PTYPE(element_index))
{
m_data_queue.count--;
data_queue_element_init (element_index);
retval = hci_transport_rx_pkt_consume((p_data - 4));
APP_ERROR_CHECK(retval);
}
}
else
{
return NRF_ERROR_INVALID_PARAM;
}
return NRF_SUCCESS;
}
/**@brief Function for Allocating element.
*
* @param[in] packet_type packet type.
* @param[out] p_element_index index of the element.
*/
static uint32_t data_queue_element_alloc(uint8_t * p_element_index, uint8_t packet_type)
{
uint32_t retval;
uint32_t index;
retval = NRF_ERROR_NO_MEM;
if (INVALID_PACKET == packet_type)
{
retval = NRF_ERROR_INVALID_PARAM;
}
else if (true == DATA_QUEUE_FULL())
{
retval = NRF_ERROR_NO_MEM;
}
else
{
for (index = 0; index < MAX_BUFFERS; index++)
{
if (INVALID_PACKET == DATA_QUEUE_ELEMENT_GET_PTYPE(index))
{
// Found a free element: allocate, and end search.
*p_element_index = index;
DATA_QUEUE_ELEMENT_SET_PTYPE(index, packet_type);
retval = NRF_SUCCESS;
m_data_queue.count++;
break;
}
}
}
return retval;
}
// Flush everything on disconnect or stop.
static void data_queue_flush(void)
{
uint32_t index;
for (index = 0; index < MAX_BUFFERS; index++)
{
// In this case it does not matter if free succeeded or not as data packets are being flushed because DFU Trnsport was closed
(void)data_queue_element_free(index);
}
}
/**@brief Function for handling the callback events from the dfu module.
* Callbacks are expected when \ref dfu_data_pkt_handle has been executed.
*
* @param[in] packet Packet type for which this callback is related. START_PACKET, DATA_PACKET.
* @param[in] result Operation result code. NRF_SUCCESS when a queued operation was successful.
* @param[in] p_data Pointer to the data to which the operation is related.
*/
static void dfu_cb_handler(uint32_t packet, uint32_t result, uint8_t * p_data)
{
APP_ERROR_CHECK(result);
}
static void process_dfu_packet(void * p_event_data, uint16_t event_size)
{
uint32_t retval;
uint32_t index;
dfu_update_packet_t * packet;
// Adafruit modification for startup dfu
extern bool forced_startup_dfu_packet_received;
forced_startup_dfu_packet_received = true;
while (false == DATA_QUEUE_EMPTY())
{
// Fetch the element to be processed.
for (index = 0; index < MAX_BUFFERS ; index++)
{
packet = &m_data_queue.data_packet[index];
if (INVALID_PACKET != packet->packet_type)
{
extern void blinky_fast_set(bool isFast);
switch (DATA_QUEUE_ELEMENT_GET_PTYPE(index))
{
case DATA_PACKET:
(void)dfu_data_pkt_handle(packet);
break;
case START_PACKET:
packet->params.start_packet =
(dfu_start_packet_t*)packet->params.data_packet.p_data_packet;
retval = dfu_start_pkt_handle(packet);
APP_ERROR_CHECK(retval);
break;
case INIT_PACKET:
(void)dfu_init_pkt_handle(packet);
retval = dfu_init_pkt_complete();
APP_ERROR_CHECK(retval);
blinky_fast_set(true);
break;
case STOP_DATA_PACKET:
(void)dfu_image_validate();
(void)dfu_image_activate();
blinky_fast_set(false);
// Break the loop by returning.
return;
default:
// No implementation needed.
break;
}
// Free the processed element.
retval = data_queue_element_free(index);
APP_ERROR_CHECK(retval);
}
}
}
}
void rpc_transport_event_handler(hci_transport_evt_t event)
{
uint32_t retval;
uint16_t rpc_cmd_length_read = 0;
uint8_t * p_rpc_cmd_buffer = NULL;
uint8_t element_index;
retval = hci_transport_rx_pkt_extract(&p_rpc_cmd_buffer, &rpc_cmd_length_read);
if (NRF_SUCCESS == retval)
{
// Verify if the data queue can buffer the packet.
retval = data_queue_element_alloc(&element_index, p_rpc_cmd_buffer[0]);
if (NRF_SUCCESS == retval)
{
//subtract 1 since we are interested in payload length and not the type field.
DATA_QUEUE_ELEMENT_SET_PLEN(element_index,(rpc_cmd_length_read / sizeof(uint32_t)) - 1);
DATA_QUEUE_ELEMENT_COPY_PDATA(element_index, &p_rpc_cmd_buffer[4]);
retval = app_sched_event_put(NULL, 0, process_dfu_packet);
}
}
if (p_rpc_cmd_buffer != NULL && NRF_SUCCESS != retval)
{
// Free the packet that could not be processed.
retval = hci_transport_rx_pkt_consume(p_rpc_cmd_buffer);
APP_ERROR_CHECK(retval);
}
}
uint32_t dfu_transport_serial_update_start(void)
{
uint32_t err_code;
// Initialize data buffer queue.
data_queue_init();
dfu_register_callback(dfu_cb_handler);
// Open transport layer.
err_code = hci_transport_open();
APP_ERROR_CHECK(err_code);
// Register callback to be run when commands have been received by the transport layer.
err_code = hci_transport_evt_handler_reg(rpc_transport_event_handler);
APP_ERROR_CHECK(err_code);
return NRF_SUCCESS;
}
uint32_t dfu_transport_serial_close(void)
{
// Remove all buffered packets.
data_queue_flush();
return hci_transport_close();
}

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup nrf_dfu_types Types and definitions.
* @{
*
* @ingroup nrf_dfu
*
* @brief Device Firmware Update module type and definitions.
*/
#ifndef DFU_TYPES_H__
#define DFU_TYPES_H__
#include <stdint.h>
#include "nrf_sdm.h"
#include "nrf_mbr.h"
#include "nrf.h"
#include "app_util.h"
#define NRF_UICR_BOOT_START_ADDRESS (NRF_UICR_BASE + 0x14) /**< Register where the bootloader start address is stored in the UICR register. */
#if defined(NRF52)
#define NRF_UICR_MBR_PARAMS_PAGE_ADDRESS (NRF_UICR_BASE + 0x18) /**< Register where the mbr params page is stored in the UICR register. (Only in use in nRF52 MBR).*/
#endif
#define CODE_REGION_1_START SD_SIZE_GET(MBR_SIZE) /**< This field should correspond to the size of Code Region 0, (which is identical to Start of Code Region 1), found in UICR.CLEN0 register. This value is used for compile safety, as the linker will fail if application expands into bootloader. Runtime, the bootloader will use the value found in UICR.CLEN0. */
#define SOFTDEVICE_REGION_START MBR_SIZE /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */
#ifdef NRF51
#define CODE_PAGE_SIZE 0x0400 /**< Size of a flash codepage. Used for size of the reserved flash space in the bootloader region. Will be runtime checked against NRF_UICR->CODEPAGESIZE to ensure the region is correct. */
#ifdef SIGNING
#define BOOTLOADER_REGION_START 0x00039C00 /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */
#define BOOTLOADER_SETTINGS_ADDRESS 0x0003D800 /**< The field specifies the page location of the bootloader settings address. */
#else
#define BOOTLOADER_REGION_START 0x0003C000 /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */
#define BOOTLOADER_SETTINGS_ADDRESS 0x0003FC00 /**< The field specifies the page location of the bootloader settings address. */
#endif
#elif defined(NRF52)
#define BOOTLOADER_REGION_START 0x00074000 /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */
#define BOOTLOADER_SETTINGS_ADDRESS 0x0007F000 /**< The field specifies the page location of the bootloader settings address. */
#define BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS 0x0007E000 /**< The field specifies the page location of the mbr params page address. */
#define CODE_PAGE_SIZE 0x1000 /**< Size of a flash codepage. Used for size of the reserved flash space in the bootloader region. Will be runtime checked against NRF_UICR->CODEPAGESIZE to ensure the region is correct. */
#else
#error No target defined
#endif
#define DFU_REGION_TOTAL_SIZE (BOOTLOADER_REGION_START - CODE_REGION_1_START) /**< Total size of the region between SD and Bootloader. */
#ifndef DFU_APP_DATA_RESERVED
#define DFU_APP_DATA_RESERVED CODE_PAGE_SIZE * 7 /**< Size of Application Data that must be preserved between application updates. This value must be a multiple of page size. Page size is 0x400 (1024d) bytes, thus this value must be 0x0000, 0x0400, 0x0800, 0x0C00, 0x1000, etc. */
#endif
#define DFU_IMAGE_MAX_SIZE_FULL (DFU_REGION_TOTAL_SIZE - DFU_APP_DATA_RESERVED) /**< Maximum size of an application, excluding save data from the application. */
#define DFU_IMAGE_MAX_SIZE_BANKED (((DFU_IMAGE_MAX_SIZE_FULL) - \
(DFU_IMAGE_MAX_SIZE_FULL % (2 * CODE_PAGE_SIZE)))/2) /**< Maximum size of an application, excluding save data from the application. */
#define DFU_BL_IMAGE_MAX_SIZE (BOOTLOADER_SETTINGS_ADDRESS - BOOTLOADER_REGION_START) /**< Maximum size of a bootloader, excluding save data from the current bootloader. */
#define DFU_BANK_0_REGION_START CODE_REGION_1_START /**< Bank 0 region start. */
#define DFU_BANK_1_REGION_START (DFU_BANK_0_REGION_START + DFU_IMAGE_MAX_SIZE_BANKED) /**< Bank 1 region start. */
#define EMPTY_FLASH_MASK 0xFFFFFFFF /**< Bit mask that defines an empty address in flash. */
#define INVALID_PACKET 0x00 /**< Invalid packet identifies. */
#define INIT_PACKET 0x01 /**< Packet identifies for initialization packet. */
#define STOP_INIT_PACKET 0x02 /**< Packet identifies for stop initialization packet. Used when complete init packet has been received so that the init packet can be used for pre validaiton. */
#define START_PACKET 0x03 /**< Packet identifies for the Data Start Packet. */
#define DATA_PACKET 0x04 /**< Packet identifies for a Data Packet. */
#define STOP_DATA_PACKET 0x05 /**< Packet identifies for the Data Stop Packet. */
#define DFU_UPDATE_SD 0x01 /**< Bit field indicating update of SoftDevice is ongoing. */
#define DFU_UPDATE_BL 0x02 /**< Bit field indicating update of bootloader is ongoing. */
#define DFU_UPDATE_APP 0x04 /**< Bit field indicating update of application is ongoing. */
#define DFU_INIT_RX 0x00 /**< Op Code identifies for receiving init packet. */
#define DFU_INIT_COMPLETE 0x01 /**< Op Code identifies for transmission complete of init packet. */
// Safe guard to ensure during compile time that the DFU_APP_DATA_RESERVED is a multiple of page size.
STATIC_ASSERT((((DFU_APP_DATA_RESERVED) & (CODE_PAGE_SIZE - 1)) == 0x00));
/**@brief Structure holding a start packet containing update mode and image sizes.
*/
typedef struct
{
uint8_t dfu_update_mode; /**< Packet type, used to identify the content of the received packet referenced by data packet. */
uint32_t sd_image_size; /**< Size of the SoftDevice image to be transferred. Zero if no SoftDevice image will be transfered. */
uint32_t bl_image_size; /**< Size of the Bootloader image to be transferred. Zero if no Bootloader image will be transfered. */
uint32_t app_image_size; /**< Size of the application image to be transmitted. Zero if no Bootloader image will be transfered. */
} dfu_start_packet_t;
/**@brief Structure holding a bootloader init/data packet received.
*/
typedef struct
{
uint32_t packet_length; /**< Packet length of the data packet. Each data is word size, meaning length of 4 is 4 words, not bytes. */
uint32_t * p_data_packet; /**< Data Packet received. Each data is a word size entry. */
} dfu_data_packet_t;
/**@brief Structure for holding dfu update packet. Packet type indicate the type of packet.
*/
typedef struct
{
uint32_t packet_type; /**< Packet type, used to identify the content of the received packet referenced by data packet. */
union
{
dfu_data_packet_t data_packet; /**< Used when packet type is INIT_PACKET or DATA_PACKET. Packet contains data received for init or data. */
dfu_start_packet_t * start_packet; /**< Used when packet type is START_DATA_PACKET. Will contain information on software to be updtaed, i.e. SoftDevice, Bootloader and/or Application along with image sizes. */
} params;
} dfu_update_packet_t;
/**@brief DFU status error codes.
*/
typedef enum
{
DFU_UPDATE_APP_COMPLETE, /**< Status update of application complete.*/
DFU_UPDATE_SD_COMPLETE, /**< Status update of SoftDevice update complete. Note that this solely indicates that a new SoftDevice has been received and stored in bank 0 and 1. */
DFU_UPDATE_SD_SWAPPED, /**< Status update of SoftDevice update complete. Note that this solely indicates that a new SoftDevice has been received and stored in bank 0 and 1. */
DFU_UPDATE_BOOT_COMPLETE, /**< Status update complete.*/
DFU_BANK_0_ERASED, /**< Status bank 0 erased.*/
DFU_TIMEOUT, /**< Status timeout.*/
DFU_RESET /**< Status Reset to indicate current update procedure has been aborted and system should reset. */
} dfu_update_status_code_t;
/**@brief Structure holding DFU complete event.
*/
typedef struct
{
dfu_update_status_code_t status_code; /**< Device Firmware Update status. */
uint16_t app_crc; /**< CRC of the recieved application. */
uint32_t sd_size; /**< Size of the recieved SoftDevice. */
uint32_t bl_size; /**< Size of the recieved BootLoader. */
uint32_t app_size; /**< Size of the recieved Application. */
uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */
} dfu_update_status_t;
/**@brief Update complete handler type. */
typedef void (*dfu_complete_handler_t)(dfu_update_status_t dfu_update_status);
#endif // DFU_TYPES_H__
/**@} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup memory_pool_internal Memory Pool Internal
* @{
* @ingroup memory_pool
*
* @brief Memory pool internal definitions
*/
#ifndef MEM_POOL_INTERNAL_H__
#define MEM_POOL_INTERNAL_H__
#define TX_BUF_SIZE 32u /**< TX buffer size in bytes. */
#define RX_BUF_SIZE 600u /**< RX buffer size in bytes. */
#define RX_BUF_QUEUE_SIZE 2u /**< RX buffer element size. */
#endif // MEM_POOL_INTERNAL_H__
/** @} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup ble_sdk_bootloader_hci_congfig HCI Transport Layer Configuration
* @{
* @ingroup dfu_bootloader_api
* @brief Definition of HCI Transport Layer configurable parameters
*/
#ifndef HCI_TRANSPORT_CONFIG_H__
#define HCI_TRANSPORT_CONFIG_H__
#include "boards.h" /**< Default include for boards.h which means that default pin numbers will be used for RX, TX, CTS, and RTS on the UART. Other pin number can be used if desired. */
/** This section covers configurable parameters for the HCI Transport SLIP layer. */
#define HCI_SLIP_UART_RX_PIN_NUMBER RX_PIN_NUMBER /**< Defines the UART RX pin number. The default pin for the board is chosen, but can be overwritten. */
#define HCI_SLIP_UART_TX_PIN_NUMBER TX_PIN_NUMBER /**< Defines the UART TX pin number. The default pin for the board is chosen, but can be overwritten. */
#define HCI_SLIP_UART_RTS_PIN_NUMBER RTS_PIN_NUMBER /**< Defines the UART RTS pin number. The default pin for the board is chosen, but can be overwritten. */
#define HCI_SLIP_UART_CTS_PIN_NUMBER CTS_PIN_NUMBER /**< Defines the UART CTS pin number. The default pin for the board is chosen, but can be overwritten. */
#define HCI_SLIP_UART_MODE APP_UART_FLOW_CONTROL_DISABLED /**< Defines the UART mode to be used. Use UART Low Power with Flow Control - Valid values are defined in \ref app_uart_flow_control_t. For further information on the UART Low Power mode, please refer to: \ref app_uart . */
#define HCI_SLIP_UART_BAUDRATE UART_BAUDRATE_BAUDRATE_Baud115200 // UART_BAUDRATE_BAUDRATE_Baud38400 /**< Defines the UART Baud rate. Default is 38400 baud. */
/** This section covers configurable parameters for the HCI Transport layer that are used for calculating correct value for the retransmission timer timeout. */
#define MAX_PACKET_SIZE_IN_BITS 8000u /**< Maximum size of a single application packet in bits. */
#define USED_BAUD_RATE 115200u /**< The used uart baudrate. */
#endif // HCI_TRANSPORT_CONFIG_H__
/** @} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "crc16.h"
#include <stdlib.h>
uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc)
{
uint16_t crc = (p_crc == NULL) ? 0xFFFF : *p_crc;
for (uint32_t i = 0; i < size; i++)
{
crc = (uint8_t)(crc >> 8) | (crc << 8);
crc ^= p_data[i];
crc ^= (uint8_t)(crc & 0xFF) >> 4;
crc ^= (crc << 8) << 4;
crc ^= ((crc & 0xFF) << 4) << 1;
}
return crc;
}

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup crc_compute CRC compute
* @{
* @ingroup hci_transport
*
* @brief This module implements CRC-16-CCITT (polynomial 0x1021) with 0xFFFF initial value.
* The data can be passed in multiple blocks.
*/
#ifndef CRC16_H__
#define CRC16_H__
#include <stdint.h>
/**@brief Function for calculating CRC-16 in blocks.
*
* Feed each consecutive data block into this function, along with the current value of p_crc as
* returned by the previous call of this function. The first call of this function should pass NULL
* as the initial value of the crc in p_crc.
*
* @param[in] p_data The input data block for computation.
* @param[in] size The size of the input data block in bytes.
* @param[in] p_crc The previous calculated CRC-16 value or NULL if first call.
*
* @return The updated CRC-16 value, based on the input supplied.
*/
uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc);
#endif // CRC16_H__
/** @} */

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "app_fifo.h"
#include "sdk_common.h"
#include "nordic_common.h"
static __INLINE uint32_t fifo_length(app_fifo_t * p_fifo)
{
uint32_t tmp = p_fifo->read_pos;
return p_fifo->write_pos - tmp;
}
#define FIFO_LENGTH fifo_length(p_fifo) /**< Macro for calculating the FIFO length. */
/**@brief Put one byte to the FIFO. */
static __INLINE void fifo_put(app_fifo_t * p_fifo, uint8_t byte)
{
p_fifo->p_buf[p_fifo->write_pos & p_fifo->buf_size_mask] = byte;
p_fifo->write_pos++;
}
/**@brief Look at one byte in the FIFO. */
static __INLINE void fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte)
{
*p_byte = p_fifo->p_buf[(p_fifo->read_pos + index) & p_fifo->buf_size_mask];
}
/**@brief Get one byte from the FIFO. */
static __INLINE void fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte)
{
fifo_peek(p_fifo, 0, p_byte);
p_fifo->read_pos++;
}
uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size)
{
// Check buffer for null pointer.
if (p_buf == NULL)
{
return NRF_ERROR_NULL;
}
// Check that the buffer size is a power of two.
if (!IS_POWER_OF_TWO(buf_size))
{
return NRF_ERROR_INVALID_LENGTH;
}
p_fifo->p_buf = p_buf;
p_fifo->buf_size_mask = buf_size - 1;
p_fifo->read_pos = 0;
p_fifo->write_pos = 0;
return NRF_SUCCESS;
}
uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte)
{
if (FIFO_LENGTH <= p_fifo->buf_size_mask)
{
fifo_put(p_fifo, byte);
return NRF_SUCCESS;
}
return NRF_ERROR_NO_MEM;
}
uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte)
{
if (FIFO_LENGTH != 0)
{
fifo_get(p_fifo, p_byte);
return NRF_SUCCESS;
}
return NRF_ERROR_NOT_FOUND;
}
uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte)
{
if (FIFO_LENGTH > index)
{
fifo_peek(p_fifo, index, p_byte);
return NRF_SUCCESS;
}
return NRF_ERROR_NOT_FOUND;
}
uint32_t app_fifo_flush(app_fifo_t * p_fifo)
{
p_fifo->read_pos = p_fifo->write_pos;
return NRF_SUCCESS;
}
uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size)
{
VERIFY_PARAM_NOT_NULL(p_fifo);
VERIFY_PARAM_NOT_NULL(p_size);
const uint32_t byte_count = fifo_length(p_fifo);
const uint32_t requested_len = (*p_size);
uint32_t index = 0;
uint32_t read_size = MIN(requested_len, byte_count);
(*p_size) = byte_count;
// Check if the FIFO is empty.
if (byte_count == 0)
{
return NRF_ERROR_NOT_FOUND;
}
// Check if application has requested only the size.
if (p_byte_array == NULL)
{
return NRF_SUCCESS;
}
// Fetch bytes from the FIFO.
while (index < read_size)
{
fifo_get(p_fifo, &p_byte_array[index++]);
}
(*p_size) = read_size;
return NRF_SUCCESS;
}
uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size)
{
VERIFY_PARAM_NOT_NULL(p_fifo);
VERIFY_PARAM_NOT_NULL(p_size);
const uint32_t available_count = p_fifo->buf_size_mask - fifo_length(p_fifo) + 1;
const uint32_t requested_len = (*p_size);
uint32_t index = 0;
uint32_t write_size = MIN(requested_len, available_count);
(*p_size) = available_count;
// Check if the FIFO is FULL.
if (available_count == 0)
{
return NRF_ERROR_NO_MEM;
}
// Check if application has requested only the size.
if (p_byte_array == NULL)
{
return NRF_SUCCESS;
}
//Fetch bytes from the FIFO.
while (index < write_size)
{
fifo_put(p_fifo, p_byte_array[index++]);
}
(*p_size) = write_size;
return NRF_SUCCESS;
}

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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
*
* @defgroup app_fifo FIFO implementation
* @{
* @ingroup app_common
*
* @brief FIFO implementation.
*/
#ifndef APP_FIFO_H__
#define APP_FIFO_H__
#include <stdint.h>
#include <stdlib.h>
/**@brief A FIFO instance structure.
* @details Keeps track of which bytes to read and write next.
* Also, it keeps the information about which memory is allocated for the buffer
* and its size. This structure must be initialized by app_fifo_init() before use.
*/
typedef struct
{
uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */
uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */
volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */
volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */
} app_fifo_t;
/**@brief Function for initializing the FIFO.
*
* @param[out] p_fifo FIFO object.
* @param[in] p_buf FIFO buffer for storing data. The buffer size must be a power of two.
* @param[in] buf_size Size of the FIFO buffer provided. This size must be a power of two.
*
* @retval NRF_SUCCESS If initialization was successful.
* @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer.
* @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two.
*/
uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size);
/**@brief Function for adding an element to the FIFO.
*
* @param[in] p_fifo Pointer to the FIFO.
* @param[in] byte Data byte to add to the FIFO.
*
* @retval NRF_SUCCESS If an element has been successfully added to the FIFO.
* @retval NRF_ERROR_NO_MEM If the FIFO is full.
*/
uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte);
/**@brief Function for getting the next element from the FIFO.
*
* @param[in] p_fifo Pointer to the FIFO.
* @param[out] p_byte Byte fetched from the FIFO.
*
* @retval NRF_SUCCESS If an element was returned.
* @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue.
*/
uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte);
/**@brief Function for looking at an element in the FIFO, without consuming it.
*
* @param[in] p_fifo Pointer to the FIFO.
* @param[in] index Which element to look at. The lower the index, the earlier it was put.
* @param[out] p_byte Byte fetched from the FIFO.
*
* @retval NRF_SUCCESS If an element was returned.
* @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue, or the index was
* too large.
*/
uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte);
/**@brief Function for flushing the FIFO.
*
* @param[in] p_fifo Pointer to the FIFO.
*
* @retval NRF_SUCCESS If the FIFO was flushed successfully.
*/
uint32_t app_fifo_flush(app_fifo_t * p_fifo);
/**@brief Function for reading bytes from the FIFO.
*
* This function can also be used to get the number of bytes in the FIFO.
*
* @param[in] p_fifo Pointer to the FIFO. Must not be NULL.
* @param[out] p_byte_array Memory pointer where the read bytes are fetched from the FIFO.
* Can be NULL. If NULL, the number of bytes that can be read in the FIFO
* are returned in the p_size parameter.
* @param[inout] p_size Address to memory indicating the maximum number of bytes to be read.
* The provided memory is overwritten with the actual number of bytes
* read if the procedure was successful. This field must not be NULL.
* If p_byte_array is set to NULL by the application, this parameter
* returns the number of bytes in the FIFO.
*
* @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes read might
* be less than the requested maximum, depending on how many elements exist
* in the FIFO. Even if less bytes are returned, the procedure is considered
* successful.
* @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not
* be NULL.
* @retval NRF_ERROR_NOT_FOUND If the FIFO is empty.
*/
uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size);
/**@brief Function for writing bytes to the FIFO.
*
* This function can also be used to get the available size on the FIFO.
*
* @param[in] p_fifo Pointer to the FIFO. Must not be NULL.
* @param[in] p_byte_array Memory pointer containing the bytes to be written to the FIFO.
* Can be NULL. If NULL, this function returns the number of bytes
* that can be written to the FIFO.
* @param[inout] p_size Address to memory indicating the maximum number of bytes to be written.
* The provided memory is overwritten with the number of bytes that were actually
* written if the procedure is successful. This field must not be NULL.
* If p_byte_array is set to NULL by the application, this parameter
* returns the number of bytes available in the FIFO.
*
* @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes written might
* be less than the requested maximum, depending on how much room there is in
* the FIFO. Even if less bytes are written, the procedure is considered
* successful. If the write was partial, the application should use
* subsequent calls to attempt writing the data again.
* @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not
* be NULL.
* @retval NRF_ERROR_NO_MEM If the FIFO is full.
*
*/
uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size);
#endif // APP_FIFO_H__
/** @} */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef HARFAULT_H__
#define HARFAULT_H__
#include <stdint.h>
#include <stddef.h>
/**
* @defgroup hardfault_default HardFault exception
* @{
* @brief Default HardFault exception implementation.
* @ingroup app_common
*/
/**
* @brief Contents of the stack.
*
* This structure is used to re-create the stack layout after a HardFault exception was raised.
*/
typedef struct HardFault_stack
{
uint32_t r0; ///< R0 register.
uint32_t r1; ///< R1 register.
uint32_t r2; ///< R2 register.
uint32_t r3; ///< R3 register.
uint32_t r12; ///< R12 register.
uint32_t lr; ///< Link register.
uint32_t pc; ///< Program counter.
uint32_t psr; ///< Program status register.
}HardFault_stack_t;
/**
* @brief Function for processing HardFault exceptions.
*
* An application that needs to process HardFault exceptions should provide an implementation of this function.
* It will be called from the HardFault handler.
* If no implementation is provided, the library uses a default one, which just restarts the MCU.
*
* @note If the DEBUG_NRF macro is defined, the software breakpoint is set just before the call
* to this function.
*
* @param p_stack Pointer to the stack bottom.
* This pointer might be NULL if the HardFault was called when the main stack was
* the active stack and a stack overrun is detected.
* In such a situation, the stack pointer is reinitialized to the default position,
* and the stack content is lost.
*/
void HardFault_process(HardFault_stack_t *p_stack);
/** @} */
#endif /* HARFAULT_H__ */

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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "hardfault.h"
#include "nrf.h"
#include "compiler_abstraction.h"
#include "nordic_common.h"
#ifdef SOFTDEVICE_PRESENT
#include "nrf_soc.h"
#endif
#if defined(DEBUG_NRF)
/**
* @brief Pointer to the last received stack pointer.
*
* This pointer is set in the debug version of the HardFault handler.
* It helps to debug HardFault reasons.
*/
volatile HardFault_stack_t *HardFault_p_stack;
#endif
/*lint -save -e14 */
__WEAK void HardFault_process(HardFault_stack_t *p_stack)
{
// Restart the system by default
NVIC_SystemReset();
}
/*lint -restore */
void HardFault_c_handler( uint32_t *p_stack_address )
{
#if defined(DEBUG_NRF)
HardFault_p_stack = (HardFault_stack_t*)p_stack_address;
/* Generate breakpoint if debugger is connected */
__BKPT(0);
#endif
HardFault_process((HardFault_stack_t*)p_stack_address);
}

52
nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_gcc.c Normal file
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stdint.h>
void HardFault_Handler(void) __attribute__(( naked ));
void HardFault_Handler(void)
{
__asm volatile(
" .syntax unified \n"
" ldr r0, =0xFFFFFFFD \n"
" cmp r0, lr \n"
" bne HardFault_Handler_ChooseMSP \n"
/* Reading PSP into R0 */
" mrs r0, PSP \n"
" b HardFault_Handler_Continue \n"
"HardFault_Handler_ChooseMSP: \n"
/* Reading MSP into R0 */
" mrs r0, MSP \n"
/* -----------------------------------------------------------------
* If we have selected MSP check if we may use stack safetly.
* If not - reset the stack to the initial value. */
" ldr r1, =__StackTop \n"
" ldr r2, =__StackLimit \n"
/* MSP is in the range of <__StackTop, __StackLimit) */
" cmp r0, r1 \n"
" bhi HardFault_MoveSP \n"
" cmp r0, r2 \n"
" bhi HardFault_Handler_Continue \n"
/* ----------------------------------------------------------------- */
"HardFault_MoveSP: \n"
" mov SP, r1 \n"
" movs r0, #0 \n"
"HardFault_Handler_Continue: \n"
" ldr r3, =HardFault_c_handler \n"
" bx r3 \n"
" .align \n"
);
}

65
nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_iar.c Normal file
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stdint.h>
#pragma section = "CSTACK"
extern void HardFault_c_handler( uint32_t * );
__stackless void HardFault_Handler(void);
__stackless void HardFault_Handler(void)
{
__asm volatile(
" ldr r0, 100f \n"
" cmp r0, lr \n"
" bne 1f \n"
/* Reading PSP into R0 */
" mrs r0, PSP \n"
" b 3f \n"
"1: \n"
/* Reading MSP into R0 */
" mrs r0, MSP \n"
/* -----------------------------------------------------------------
* If we have selected MSP check if we may use stack safetly.
* If not - reset the stack to the initial value. */
" ldr r1, 101f \n"
" ldr r2, 102f \n"
/* MSP is in the range of <__StackTop, __StackLimit) */
" cmp r0, r1 \n"
" bhi 2f \n"
" cmp r0, r2 \n"
" bhi 3f \n"
/* ----------------------------------------------------------------- */
"2: \n"
" mov SP, r1 \n"
" movs r0, #0 \n"
"3: \n"
" ldr r3, 103f \n"
" bx r3 \n"
"100: \n"
" DC32 0xFFFFFFFD \n"
"101: \n"
" DC32 %c0 \n"
"102: \n"
" DC32 %c1 \n"
"103: \n"
" DC32 %c2 \n"
: /* Outputs */
: /* Inputs */
"i"(__section_end("CSTACK")),
"i"(__section_begin("CSTACK")),
"i"(&HardFault_c_handler)
);
}

61
nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_keil.c Normal file
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stdint.h>
//lint -save -e27 -e10 -e19 -e40
extern char STACK$$Base;
/* This variable should be static but then it cannot be used in assembly code below.
* The problem here is that the address of the section can be archived by $$ operator
* that is not allowed in assembly code. */
char const * HardFault_Handler_stack_bottom = &STACK$$Base;
//lint -restore
__asm void HardFault_Handler(void)
{
PRESERVE8
EXTERN HardFault_c_handler
EXTERN __initial_sp
EXTERN HardFault_Handler_stack_bottom
ldr r0, =0xFFFFFFFD
cmp r0, lr
bne HardFault_Handler_ChooseMSP
/* Reading PSP into R0 */
mrs r0, PSP
b HardFault_Handler_Continue
HardFault_Handler_ChooseMSP
/* Reading MSP into R0 */
mrs r0, MSP
/* -----------------------------------------------------------------
* If we have selected MSP, check if we may use stack safely.
* If not - reset the stack to the initial value. */
ldr r1, =__initial_sp
ldr r2, =HardFault_Handler_stack_bottom
ldr r2, [r2]
/* MSP is in the range of <__StackTop, __StackLimit) */
cmp r0, r1
bhi HardFault_MoveSP
cmp r0, r2
bhi HardFault_Handler_Continue
/* ----------------------------------------------------------------- */
HardFault_MoveSP
mov SP, r1
movs r0, #0
HardFault_Handler_Continue
ldr r3, =HardFault_c_handler
bx r3
ALIGN
}

49
nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_gcc.c Normal file
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stdint.h>
void HardFault_Handler(void) __attribute__(( naked ));
void HardFault_Handler(void)
{
__asm volatile(
" ldr r3, =HardFault_c_handler \n"
" tst lr, #4 \n"
/* PSP is quite simple and does not require additional handler */
" itt ne \n"
" mrsne r0, psp \n"
/* Jump to the handler, do not store LR - returning from handler just exits exception */
" bxne r3 \n"
/* Processing MSP requires stack checking */
" mrs r0, msp \n"
" ldr r1, =__StackTop \n"
" ldr r2, =__StackLimit \n"
/* MSP is in the range of <__StackTop, __StackLimit) */
" cmp r0, r1 \n"
" bhi HardFault_MoveSP \n"
" cmp r0, r2 \n"
" bhi HardFault_Handler_Continue \n"
"HardFault_MoveSP: \n"
" mov sp, r1 \n"
" mov r0, #0 \n"
"HardFault_Handler_Continue: \n"
" bx r3 \n"
" .align \n"
);
}

64
nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_iar.c Normal file
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stdint.h>
#pragma section = "CSTACK"
extern void HardFault_c_handler( uint32_t * );
__stackless void HardFault_Handler(void);
__stackless void HardFault_Handler(void)
{
__asm volatile(
" ldr.n r3, 103f \n"
" tst lr, #4 \n"
/* PSP is quite simple and does not require additional handler */
" itt ne \n"
" mrsne r0, psp \n"
/* Jump to the handler, do not store LR - returning from handler just exits exception */
" bxne r3 \n"
/* Processing MSP requires stack checking */
" mrs r0, msp \n"
" ldr.n r1, 101f \n"
" ldr.n r2, 102f \n"
/* MSP is in the range of <__StackTop, __StackLimit) */
" cmp r0, r1 \n"
" bhi.n 1f \n"
" cmp r0, r2 \n"
" bhi.n 2f \n"
"1: \n"
" mov sp, r1 \n"
" mov r0, #0 \n"
"2: \n"
" bx r3 \n"
/* Data alignment if required */
" nop \n"
"101: \n"
" DC32 %c0 \n"
"102: \n"
" DC32 %c1 \n"
"103: \n"
" DC32 %c2 \n"
: /* Outputs */
: /* Inputs */
"i"(__section_end("CSTACK")),
"i"(__section_begin("CSTACK")),
"i"(&HardFault_c_handler)
);
}

60
nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_keil.c Normal file
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include <stdint.h>
//lint -save -e27 -e10 -e19 -e40
extern char STACK$$Base;
/* This variable should be static but then it cannot be used in assembly code below.
* The problem here is that the address of the section can be archived by $$ operator
* that is not allowed in assembly code. */
char const * HardFault_Handler_stack_bottom = &STACK$$Base;
//lint -restore
__asm void HardFault_Handler(void)
{
PRESERVE8
EXTERN HardFault_c_handler
EXTERN __initial_sp
EXTERN HardFault_Handler_stack_bottom
ldr r3, =HardFault_c_handler
tst lr, #4
/* PSP is quite simple and does not require additional handler */
itt ne
mrsne r0, psp
/* Jump to the handler, do not store LR - returning from handler just exits exception */
bxne r3
/* Processing MSP requires stack checking */
mrs r0, msp
ldr r1, =__initial_sp
ldr r2, =HardFault_Handler_stack_bottom
ldr r2, [r2]
/* MSP is in the range of <__StackTop, __StackLimit) */
cmp r0, r1
bhi HardFault_MoveSP
cmp r0, r2
bhi HardFault_Handler_Continue
HardFault_MoveSP
mov sp, r1
mov r0, #0
HardFault_Handler_Continue
bx r3
ALIGN
}

253
nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.c Normal file
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/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "hci_mem_pool.h"
//#include "hci_mem_pool_internal.h"
#include "nordic_common.h"
#include <stdbool.h>
#include <stdio.h>
// Adafruit for dual transport serial + ble
#define BLE_TX_BUF_SIZE 4u /**< TX buffer size in bytes. */
#define BLE_RX_BUF_SIZE 32u /**< RX buffer size in bytes. */
#define BLE_RX_BUF_QUEUE_SIZE 8u /**< RX buffer element size. */
#define SERIAL_TX_BUF_SIZE 32u /**< TX buffer size in bytes. */
#define SERIAL_RX_BUF_SIZE 600u /**< RX buffer size in bytes. */
#define SERIAL_RX_BUF_QUEUE_SIZE 2u /**< RX buffer element size. */
extern bool is_ota(void);
#define RX_BUF_SIZE (is_ota() ? BLE_RX_BUF_SIZE : SERIAL_RX_BUF_SIZE)
#define TX_BUF_SIZE (is_ota() ? BLE_TX_BUF_SIZE : SERIAL_TX_BUF_SIZE)
#define RX_BUF_QUEUE_SIZE (is_ota() ? BLE_RX_BUF_QUEUE_SIZE : SERIAL_RX_BUF_QUEUE_SIZE)
/**@brief RX buffer element instance structure.
*/
typedef struct
{
// uint8_t rx_buffer[RX_BUF_SIZE]; /**< RX buffer memory array. */
uint8_t rx_buffer[MAX(BLE_RX_BUF_SIZE, SERIAL_RX_BUF_SIZE)];
uint32_t length; /**< Length of the RX buffer memory array. */
} rx_buffer_elem_t;
/**@brief RX buffer queue element instance structure.
*/
typedef struct
{
rx_buffer_elem_t * p_buffer; /**< Pointer to RX buffer element. */
uint32_t free_window_count; /**< Free space element count. */
uint32_t free_available_count; /**< Free area element count. */
uint32_t read_available_count; /**< Read area element count. */
uint32_t write_index; /**< Write position index. */
uint32_t read_index; /**< Read position index. */
uint32_t free_index; /**< Free position index. */
} rx_buffer_queue_t;
static bool m_is_tx_allocated; /**< Boolean value to determine if the TX buffer is allocated. */
static rx_buffer_elem_t m_rx_buffer_elem_queue[MAX(BLE_RX_BUF_QUEUE_SIZE, SERIAL_RX_BUF_QUEUE_SIZE)]; /**< RX buffer element instances. */
static rx_buffer_queue_t m_rx_buffer_queue; /**< RX buffer queue element instance. */
uint32_t hci_mem_pool_open(void)
{
m_is_tx_allocated = false;
m_rx_buffer_queue.p_buffer = m_rx_buffer_elem_queue;
m_rx_buffer_queue.free_window_count = RX_BUF_QUEUE_SIZE;
m_rx_buffer_queue.free_available_count = 0;
m_rx_buffer_queue.read_available_count = 0;
m_rx_buffer_queue.write_index = 0;
m_rx_buffer_queue.read_index = 0;
m_rx_buffer_queue.free_index = 0;
return NRF_SUCCESS;
}
uint32_t hci_mem_pool_close(void)
{
return NRF_SUCCESS;
}
uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer)
{
static uint8_t tx_buffer[MAX(BLE_TX_BUF_SIZE, SERIAL_TX_BUF_SIZE)];
uint32_t err_code;
if (pp_buffer == NULL)
{
return NRF_ERROR_NULL;
}
if (!m_is_tx_allocated)
{
m_is_tx_allocated = true;
*pp_buffer = tx_buffer;
err_code = NRF_SUCCESS;
}
else
{
err_code = NRF_ERROR_NO_MEM;
}
return err_code;
}
uint32_t hci_mem_pool_tx_free(void)
{
m_is_tx_allocated = false;
return NRF_SUCCESS;
}
uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer)
{
uint32_t err_code;
if (pp_buffer == NULL)
{
return NRF_ERROR_NULL;
}
*pp_buffer = NULL;
if (m_rx_buffer_queue.free_window_count != 0)
{
if (length <= RX_BUF_SIZE)
{
--(m_rx_buffer_queue.free_window_count);
++(m_rx_buffer_queue.read_available_count);
*pp_buffer =
m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.write_index].rx_buffer;
m_rx_buffer_queue.free_index |= (1u << m_rx_buffer_queue.write_index);
// @note: Adjust the write_index making use of the fact that the buffer size is of
// power of two and two's complement arithmetic. For details refer example to book
// "Making embedded systems: Elicia White".
m_rx_buffer_queue.write_index =
(m_rx_buffer_queue.write_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
err_code = NRF_SUCCESS;
}
else
{
err_code = NRF_ERROR_DATA_SIZE;
}
}
else
{
err_code = NRF_ERROR_NO_MEM;
}
return err_code;
}
uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer)
{
uint32_t err_code;
uint32_t consume_index;
uint32_t start_index;
if (m_rx_buffer_queue.free_available_count != 0)
{
// Find the buffer that has been freed -
// Start at read_index minus free_available_count and then increment until read index.
err_code = NRF_ERROR_INVALID_ADDR;
consume_index = (m_rx_buffer_queue.read_index - m_rx_buffer_queue.free_available_count) &
(RX_BUF_QUEUE_SIZE - 1u);
start_index = consume_index;
do
{
if (m_rx_buffer_queue.p_buffer[consume_index].rx_buffer == p_buffer)
{
m_rx_buffer_queue.free_index ^= (1u << consume_index);
err_code = NRF_SUCCESS;
break;
}
else
{
consume_index = (consume_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
}
}
while (consume_index != m_rx_buffer_queue.read_index);
while (!(m_rx_buffer_queue.free_index & (1 << start_index)) &&
(m_rx_buffer_queue.free_available_count != 0))
{
--(m_rx_buffer_queue.free_available_count);
++(m_rx_buffer_queue.free_window_count);
start_index = (consume_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
}
}
else
{
err_code = NRF_ERROR_NO_MEM;
}
return err_code;
}
uint32_t hci_mem_pool_rx_data_size_set(uint32_t length)
{
// @note: Adjust the write_index making use of the fact that the buffer size is of power
// of two and two's complement arithmetic. For details refer example to book
// "Making embedded systems: Elicia White".
const uint32_t index = (m_rx_buffer_queue.write_index - 1u) & (RX_BUF_QUEUE_SIZE - 1u);
m_rx_buffer_queue.p_buffer[index].length = length;
return NRF_SUCCESS;
}
uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length)
{
uint32_t err_code;
if ((pp_buffer == NULL) || (p_length == NULL))
{
return NRF_ERROR_NULL;
}
if (m_rx_buffer_queue.read_available_count != 0)
{
--(m_rx_buffer_queue.read_available_count);
++(m_rx_buffer_queue.free_available_count);
*pp_buffer =
m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].rx_buffer;
*p_length =
m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].length;
// @note: Adjust the write_index making use of the fact that the buffer size is of power
// of two and two's complement arithmetic. For details refer example to book
// "Making embedded systems: Elicia White".
m_rx_buffer_queue.read_index =
(m_rx_buffer_queue.read_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
err_code = NRF_SUCCESS;
}
else
{
err_code = NRF_ERROR_NO_MEM;
}
return err_code;
}

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