662 lines
26 KiB
C
662 lines
26 KiB
C
/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
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*
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* The information contained herein is property of Nordic Semiconductor ASA.
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* Terms and conditions of usage are described in detail in NORDIC
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* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
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*
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* Licensees are granted free, non-transferable use of the information. NO
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* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
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* the file.
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*
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*/
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/**
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* @defgroup nrf_pwm_hal PWM HAL
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* @{
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* @ingroup nrf_pwm
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*
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* @brief @tagAPI52 Hardware access layer for managing the Pulse Width Modulation (PWM)
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* peripheral.
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*/
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#ifndef NRF_PWM_H__
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#define NRF_PWM_H__
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#include <stddef.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "nrf.h"
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#include "nrf_assert.h"
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/**
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* @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
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* function call to specify that a given output channel shall not be
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* connected to a physical pin.
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*/
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#define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
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/**
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* @brief Number of channels in each PWM instance.
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*/
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#define NRF_PWM_CHANNEL_COUNT 4
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/**
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* @brief PWM tasks.
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*/
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typedef enum
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{
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/*lint -save -e30*/
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NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
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NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
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NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
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NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
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/*lint -restore*/
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} nrf_pwm_task_t;
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/**
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* @brief PWM events.
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*/
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typedef enum
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{
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/*lint -save -e30*/
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NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
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NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
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NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
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NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
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NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
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NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
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NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the requested number of times.
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/*lint -restore*/
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} nrf_pwm_event_t;
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/**
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* @brief PWM interrupts.
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*/
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typedef enum
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{
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NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
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NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event.
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NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event.
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NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event.
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NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event.
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NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
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NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
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} nrf_pwm_int_mask_t;
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/**
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* @brief PWM shortcuts.
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*/
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typedef enum
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{
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NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
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NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task.
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NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
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NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
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NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
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} nrf_pwm_short_mask_t;
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/**
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* @brief PWM modes of operation.
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*/
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typedef enum
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{
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NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
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NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
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} nrf_pwm_mode_t;
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/**
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* @brief PWM base clock frequencies.
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*/
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typedef enum
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{
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NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
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NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz.
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NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz.
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NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz.
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NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
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NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
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NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
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NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
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} nrf_pwm_clk_t;
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/**
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* @brief PWM decoder load modes.
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*
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* The selected mode determines how the sequence data is read from RAM and
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* spread to the compare registers.
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*/
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typedef enum
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{
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NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3).
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NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
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NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
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NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
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} nrf_pwm_dec_load_t;
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/**
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* @brief PWM decoder next step modes.
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*
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* The selected mode determines when the next value from the active sequence
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* is loaded.
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*/
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typedef enum
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{
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NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
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NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
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} nrf_pwm_dec_step_t;
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/**
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* @brief Type used for defining duty cycle values for a sequence
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* loaded in @ref NRF_PWM_LOAD_COMMON mode.
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*/
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typedef uint16_t nrf_pwm_values_common_t;
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/**
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* @brief Structure for defining duty cycle values for a sequence
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* loaded in @ref NRF_PWM_LOAD_GROUPED mode.
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*/
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typedef struct {
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uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
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uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
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} nrf_pwm_values_grouped_t;
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/**
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* @brief Structure for defining duty cycle values for a sequence
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* loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
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*/
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typedef struct
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{
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uint16_t channel_0; ///< Duty cycle value for channel 0.
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uint16_t channel_1; ///< Duty cycle value for channel 1.
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uint16_t channel_2; ///< Duty cycle value for channel 2.
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uint16_t channel_3; ///< Duty cycle value for channel 3.
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} nrf_pwm_values_individual_t;
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/**
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* @brief Structure for defining duty cycle values for a sequence
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* loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
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*/
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typedef struct {
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uint16_t channel_0; ///< Duty cycle value for channel 0.
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uint16_t channel_1; ///< Duty cycle value for channel 1.
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uint16_t channel_2; ///< Duty cycle value for channel 2.
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uint16_t counter_top; ///< Top value for the pulse generator counter.
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} nrf_pwm_values_wave_form_t;
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/**
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* @brief Union grouping pointers to arrays of duty cycle values applicable to
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* various loading modes.
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*/
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typedef union {
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nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
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nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
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nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
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nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
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uint16_t const * p_raw; ///< Pointer providing raw access to the values.
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} nrf_pwm_values_t;
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/**
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* @brief Structure for defining a sequence of PWM duty cycles.
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*
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* When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
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* provided duty cycle values are not copied. The @p values pointer is stored
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* in the peripheral's internal register, and the values are loaded from RAM
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* during the sequence playback. Therefore, you must ensure that the values
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* do not change before and during the sequence playback (for example,
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* the values cannot be placed in a local variable that is allocated on stack).
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* If the sequence is played in a loop and the values should be updated
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* before the next iteration, it is safe to modify them when the corresponding
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* event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
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* or @ref NRF_PWM_EVENT_SEQEND1, respectively).
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*
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* @note The @p repeats and @p end_delay values (which are written to the
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* SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
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* respectively) are ignored at the end of a complex sequence
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* playback, indicated by the LOOPSDONE event.
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* See the @linkProductSpecification52 for more information.
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*/
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typedef struct
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{
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nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
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/**< This field is defined as an union of pointers
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* to provide a convenient way to define duty
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* cycle values in various loading modes
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* (see @ref nrf_pwm_dec_load_t).
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* In each value, the most significant bit (15)
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* determines the polarity of the output and the
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* others (14-0) compose the 15-bit value to be
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* compared with the pulse generator counter. */
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uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
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uint32_t repeats; ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
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uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
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} nrf_pwm_sequence_t;
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/**
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* @brief Helper macro for calculating the number of 16-bit values in specified
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* array of duty cycle values.
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*/
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#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array)/sizeof(uint16_t))
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/**
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* @brief Function for activating a specific PWM task.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] task Task to activate.
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*/
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__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_pwm,
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nrf_pwm_task_t task);
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/**
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* @brief Function for getting the address of a specific PWM task register.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] task Requested task.
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*
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* @return Address of the specified task register.
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*/
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__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_pwm,
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nrf_pwm_task_t task);
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/**
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* @brief Function for clearing a specific PWM event.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] event Event to clear.
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*/
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__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_pwm,
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nrf_pwm_event_t event);
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/**
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* @brief Function for checking the state of a specific PWM event.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] event Event to check.
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*
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* @retval true If the event is set.
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* @retval false If the event is not set.
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*/
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__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_pwm,
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nrf_pwm_event_t event);
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/**
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* @brief Function for getting the address of a specific PWM event register.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] event Requested event.
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*
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* @return Address of the specified event register.
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*/
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__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_pwm,
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nrf_pwm_event_t event);
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/**
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* @brief Function for enabling specified shortcuts.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] pwm_shorts_mask Shortcuts to enable.
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*/
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__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_pwm,
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uint32_t pwm_shorts_mask);
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/**
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* @brief Function for disabling specified shortcuts.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] pwm_shorts_mask Shortcuts to disable.
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*/
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__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_pwm,
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uint32_t pwm_shorts_mask);
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/**
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* @brief Function for setting the configuration of PWM shortcuts.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] pwm_shorts_mask Shortcuts configuration to set.
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*/
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__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_pwm,
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uint32_t pwm_shorts_mask);
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/**
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* @brief Function for enabling specified interrupts.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] pwm_int_mask Interrupts to enable.
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*/
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__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_pwm,
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uint32_t pwm_int_mask);
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/**
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* @brief Function for disabling specified interrupts.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] pwm_int_mask Interrupts to disable.
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*/
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__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_pwm,
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uint32_t pwm_int_mask);
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/**
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* @brief Function for setting the configuration of PWM interrupts.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] pwm_int_mask Interrupts configuration to set.
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*/
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__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_pwm,
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uint32_t pwm_int_mask);
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/**
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* @brief Function for retrieving the state of a given interrupt.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] pwm_int Interrupt to check.
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*
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* @retval true If the interrupt is enabled.
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* @retval false If the interrupt is not enabled.
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*/
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__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_pwm,
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nrf_pwm_int_mask_t pwm_int);
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/**
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* @brief Function for enabling the PWM peripheral.
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*
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* @param[in] p_pwm PWM instance.
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*/
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__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_pwm);
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/**
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* @brief Function for disabling the PWM peripheral.
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*
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* @param[in] p_pwm PWM instance.
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*/
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__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_pwm);
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/**
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* @brief Function for assigning pins to PWM output channels.
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*
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* Usage of all PWM output channels is optional. If a given channel is not
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* needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
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* number.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] out_pins Array with pin numbers for individual PWM output channels.
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*/
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__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_pwm,
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uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
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/**
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* @brief Function for configuring the PWM peripheral.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] base_clock Base clock frequency.
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* @param[in] mode Operating mode of the pulse generator counter.
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* @param[in] top_value Value up to which the pulse generator counter counts.
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*/
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__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_pwm,
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nrf_pwm_clk_t base_clock,
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nrf_pwm_mode_t mode,
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uint16_t top_value);
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/**
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* @brief Function for defining a sequence of PWM duty cycles.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] seq_id Identifier of the sequence (0 or 1).
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* @param[in] p_seq Pointer to the sequence definition.
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*/
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__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_pwm,
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uint8_t seq_id,
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nrf_pwm_sequence_t const * p_seq);
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/**
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* @brief Function for modifying the pointer to the duty cycle values
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* in the specified sequence.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] seq_id Identifier of the sequence (0 or 1).
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* @param[in] p_values Pointer to an array with duty cycle values.
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*/
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__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_pwm,
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uint8_t seq_id,
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uint16_t const * p_values);
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/**
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* @brief Function for modifying the total number of duty cycle values
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* in the specified sequence.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] seq_id Identifier of the sequence (0 or 1).
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* @param[in] length Number of duty cycle values.
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|
*/
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__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_pwm,
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uint8_t seq_id,
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uint16_t length);
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|
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/**
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* @brief Function for modifying the additional number of PWM periods spent
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* on each duty cycle value in the specified sequence.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] seq_id Identifier of the sequence (0 or 1).
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* @param[in] refresh Number of additional PWM periods for each duty cycle value.
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|
*/
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__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_pwm,
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uint8_t seq_id,
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uint32_t refresh);
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|
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|
/**
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|
* @brief Function for modifying the additional time added after the sequence
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* is played.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] seq_id Identifier of the sequence (0 or 1).
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* @param[in] end_delay Number of PWM periods added at the end of the sequence.
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|
*/
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__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_pwm,
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uint8_t seq_id,
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uint32_t end_delay);
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|
|
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/**
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|
* @brief Function for setting the mode of loading sequence data from RAM
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* and advancing the sequence.
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*
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* @param[in] p_pwm PWM instance.
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* @param[in] dec_load Mode of loading sequence data from RAM.
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* @param[in] dec_step Mode of advancing the active sequence.
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|
*/
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__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_pwm,
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nrf_pwm_dec_load_t dec_load,
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|
nrf_pwm_dec_step_t dec_step);
|
|
|
|
/**
|
|
* @brief Function for setting the number of times the sequence playback
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|
* should be performed.
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|
*
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|
* This function applies to two-sequence playback (concatenated sequence 0 and 1).
|
|
* A single sequence can be played back only once.
|
|
*
|
|
* @param[in] p_pwm PWM instance.
|
|
* @param[in] loop_count Number of times to perform the sequence playback.
|
|
*/
|
|
__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_pwm,
|
|
uint16_t loop_count);
|
|
|
|
|
|
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
|
|
|
|
__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_pwm,
|
|
nrf_pwm_task_t task)
|
|
{
|
|
*((volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)task)) = 0x1UL;
|
|
}
|
|
|
|
__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_pwm,
|
|
nrf_pwm_task_t task)
|
|
{
|
|
return ((uint32_t)p_pwm + (uint32_t)task);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_pwm,
|
|
nrf_pwm_event_t event)
|
|
{
|
|
*((volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)event)) = 0x0UL;
|
|
}
|
|
|
|
__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_pwm,
|
|
nrf_pwm_event_t event)
|
|
{
|
|
return (bool)*(volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)event);
|
|
}
|
|
|
|
__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_pwm,
|
|
nrf_pwm_event_t event)
|
|
{
|
|
return ((uint32_t)p_pwm + (uint32_t)event);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_pwm,
|
|
uint32_t pwm_shorts_mask)
|
|
{
|
|
p_pwm->SHORTS |= pwm_shorts_mask;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_pwm,
|
|
uint32_t pwm_shorts_mask)
|
|
{
|
|
p_pwm->SHORTS &= ~(pwm_shorts_mask);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_pwm,
|
|
uint32_t pwm_shorts_mask)
|
|
{
|
|
p_pwm->SHORTS = pwm_shorts_mask;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_pwm,
|
|
uint32_t pwm_int_mask)
|
|
{
|
|
p_pwm->INTENSET = pwm_int_mask;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_pwm,
|
|
uint32_t pwm_int_mask)
|
|
{
|
|
p_pwm->INTENCLR = pwm_int_mask;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_pwm,
|
|
uint32_t pwm_int_mask)
|
|
{
|
|
p_pwm->INTEN = pwm_int_mask;
|
|
}
|
|
|
|
__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_pwm,
|
|
nrf_pwm_int_mask_t pwm_int)
|
|
{
|
|
return (bool)(p_pwm->INTENSET & pwm_int);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_pwm)
|
|
{
|
|
p_pwm->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_pwm)
|
|
{
|
|
p_pwm->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_pwm,
|
|
uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
|
|
{
|
|
uint8_t i;
|
|
for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
|
|
{
|
|
p_pwm->PSEL.OUT[i] = out_pins[i];
|
|
}
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_pwm,
|
|
nrf_pwm_clk_t base_clock,
|
|
nrf_pwm_mode_t mode,
|
|
uint16_t top_value)
|
|
{
|
|
ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
|
|
|
|
p_pwm->PRESCALER = base_clock;
|
|
p_pwm->MODE = mode;
|
|
p_pwm->COUNTERTOP = top_value;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_pwm,
|
|
uint8_t seq_id,
|
|
nrf_pwm_sequence_t const * p_seq)
|
|
{
|
|
ASSERT(p_seq != NULL);
|
|
|
|
nrf_pwm_seq_ptr_set( p_pwm, seq_id, p_seq->values.p_raw);
|
|
nrf_pwm_seq_cnt_set( p_pwm, seq_id, p_seq->length);
|
|
nrf_pwm_seq_refresh_set( p_pwm, seq_id, p_seq->repeats);
|
|
nrf_pwm_seq_end_delay_set(p_pwm, seq_id, p_seq->end_delay);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_pwm,
|
|
uint8_t seq_id,
|
|
uint16_t const * p_values)
|
|
{
|
|
ASSERT(seq_id <= 1);
|
|
ASSERT(p_values != NULL);
|
|
p_pwm->SEQ[seq_id].PTR = (uint32_t)p_values;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_pwm,
|
|
uint8_t seq_id,
|
|
uint16_t length)
|
|
{
|
|
ASSERT(seq_id <= 1);
|
|
ASSERT(length != 0);
|
|
ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
|
|
p_pwm->SEQ[seq_id].CNT = length;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_pwm,
|
|
uint8_t seq_id,
|
|
uint32_t refresh)
|
|
{
|
|
ASSERT(seq_id <= 1);
|
|
ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
|
|
p_pwm->SEQ[seq_id].REFRESH = refresh;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_pwm,
|
|
uint8_t seq_id,
|
|
uint32_t end_delay)
|
|
{
|
|
ASSERT(seq_id <= 1);
|
|
ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
|
|
p_pwm->SEQ[seq_id].ENDDELAY = end_delay;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_pwm,
|
|
nrf_pwm_dec_load_t dec_load,
|
|
nrf_pwm_dec_step_t dec_step)
|
|
{
|
|
p_pwm->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
|
|
((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_pwm,
|
|
uint16_t loop_count)
|
|
{
|
|
p_pwm->LOOP = loop_count;
|
|
}
|
|
|
|
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
|
|
|
#endif // NRF_PWM_H__
|
|
|
|
/** @} */
|