From 9f1d9f321e9f86a8ec184525708260a19e192ae5 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 7 Feb 2018 23:32:49 +0700 Subject: [PATCH] add files from nrf52832 bootloader project --- LICENSE | 21 + .../ble/ble_services/ble_dfu/ble_dfu.c | 649 + .../ble/ble_services/ble_dfu/ble_dfu.h | 239 + .../ble/ble_services/ble_dis/ble_dis.c | 277 + .../ble/ble_services/ble_dis/ble_dis.h | 98 + .../components/ble/common/ble_advdata.c | 761 + .../components/ble/common/ble_advdata.h | 212 + .../components/ble/common/ble_conn_params.c | 323 + .../components/ble/common/ble_conn_params.h | 111 + .../components/ble/common/ble_srv_common.c | 197 + .../components/ble/common/ble_srv_common.h | 367 + .../components/device/compiler_abstraction.h | 126 + .../components/device/nrf.h | 66 + .../components/device/nrf51_to_nrf52.h | 935 + .../components/device/nrf52.h | 2125 +++ .../components/device/nrf52_bitfields.h | 14861 ++++++++++++++++ .../components/device/nrf52_name_change.h | 70 + .../drivers_nrf/common/nrf_drv_common.c | 208 + .../drivers_nrf/common/nrf_drv_common.h | 194 + .../drivers_nrf/config/nrf_drv_config.h | 464 + .../config/nrf_drv_config_validation.h | 83 + .../components/drivers_nrf/delay/nrf_delay.c | 26 + .../components/drivers_nrf/delay/nrf_delay.h | 242 + .../components/drivers_nrf/hal/nrf_adc.c | 78 + .../components/drivers_nrf/hal/nrf_adc.h | 416 + .../components/drivers_nrf/hal/nrf_clock.h | 414 + .../components/drivers_nrf/hal/nrf_comp.h | 469 + .../components/drivers_nrf/hal/nrf_ecb.c | 74 + .../components/drivers_nrf/hal/nrf_ecb.h | 66 + .../components/drivers_nrf/hal/nrf_egu.h | 286 + .../components/drivers_nrf/hal/nrf_gpio.h | 647 + .../components/drivers_nrf/hal/nrf_gpiote.h | 391 + .../components/drivers_nrf/hal/nrf_i2s.h | 523 + .../components/drivers_nrf/hal/nrf_lpcomp.h | 367 + .../components/drivers_nrf/hal/nrf_nvmc.c | 117 + .../components/drivers_nrf/hal/nrf_nvmc.h | 90 + .../components/drivers_nrf/hal/nrf_pdm.h | 359 + .../components/drivers_nrf/hal/nrf_ppi.h | 402 + .../components/drivers_nrf/hal/nrf_pwm.h | 661 + .../components/drivers_nrf/hal/nrf_qdec.h | 468 + .../components/drivers_nrf/hal/nrf_rng.h | 211 + .../components/drivers_nrf/hal/nrf_rtc.h | 304 + .../components/drivers_nrf/hal/nrf_saadc.c | 31 + .../components/drivers_nrf/hal/nrf_saadc.h | 554 + .../components/drivers_nrf/hal/nrf_spi.h | 334 + .../components/drivers_nrf/hal/nrf_spim.h | 520 + .../components/drivers_nrf/hal/nrf_spis.h | 512 + .../components/drivers_nrf/hal/nrf_temp.h | 55 + .../components/drivers_nrf/hal/nrf_timer.h | 576 + .../components/drivers_nrf/hal/nrf_twi.h | 402 + .../components/drivers_nrf/hal/nrf_twim.h | 478 + .../components/drivers_nrf/hal/nrf_twis.h | 676 + .../components/drivers_nrf/hal/nrf_uart.h | 471 + .../components/drivers_nrf/hal/nrf_uarte.h | 534 + .../components/drivers_nrf/hal/nrf_wdt.h | 299 + .../drivers_nrf/pstorage/pstorage.h | 381 + .../drivers_nrf/pstorage/pstorage_raw.c | 471 + .../drivers_nrf/timer/nrf_drv_timer.c | 280 + .../drivers_nrf/timer/nrf_drv_timer.h | 372 + .../drivers_nrf/uart/nrf_drv_uart.c | 851 + .../drivers_nrf/uart/nrf_drv_uart.h | 293 + .../components/drivers_nrf/wdt/nrf_drv_wdt.c | 118 + .../components/drivers_nrf/wdt/nrf_drv_wdt.h | 124 + .../ble_transport/hci_mem_pool_internal.h | 32 + .../libraries/bootloader_dfu/bootloader.c | 457 + .../libraries/bootloader_dfu/bootloader.h | 97 + .../bootloader_dfu/bootloader_settings.c | 63 + .../bootloader_dfu/bootloader_settings.h | 35 + .../bootloader_dfu/bootloader_types.h | 59 + .../bootloader_dfu/bootloader_util.c | 152 + .../bootloader_dfu/bootloader_util.h | 38 + .../components/libraries/bootloader_dfu/dfu.h | 134 + .../bootloader_dfu/dfu_app_handler.c | 192 + .../bootloader_dfu/dfu_app_handler.h | 86 + .../bootloader_dfu/dfu_bank_internal.h | 87 + .../libraries/bootloader_dfu/dfu_ble_svc.h | 80 + .../bootloader_dfu/dfu_ble_svc_internal.h | 43 + .../libraries/bootloader_dfu/dfu_dual_bank.c | 840 + .../libraries/bootloader_dfu/dfu_init.h | 134 + .../bootloader_dfu/dfu_init_template.c | 172 + .../bootloader_dfu/dfu_single_bank.c | 788 + .../libraries/bootloader_dfu/dfu_transport.h | 44 + .../bootloader_dfu/dfu_transport_ble.c | 1155 ++ .../bootloader_dfu/dfu_transport_serial.c | 314 + .../libraries/bootloader_dfu/dfu_types.h | 168 + .../hci_transport/hci_mem_pool_internal.h | 32 + .../hci_transport/hci_transport_config.h | 45 + .../components/libraries/crc16/crc16.c | 31 + .../components/libraries/crc16/crc16.h | 44 + .../components/libraries/fifo/app_fifo.c | 186 + .../components/libraries/fifo/app_fifo.h | 145 + .../libraries/hardfault/hardfault.h | 60 + .../hardfault/hardfault_implementation.c | 47 + .../nrf51/handler/hardfault_handler_gcc.c | 52 + .../nrf51/handler/hardfault_handler_iar.c | 65 + .../nrf51/handler/hardfault_handler_keil.c | 61 + .../nrf52/handler/hardfault_handler_gcc.c | 49 + .../nrf52/handler/hardfault_handler_iar.c | 64 + .../nrf52/handler/hardfault_handler_keil.c | 60 + .../components/libraries/hci/hci_mem_pool.c | 253 + .../components/libraries/hci/hci_mem_pool.h | 132 + .../components/libraries/hci/hci_slip.c | 428 + .../components/libraries/hci/hci_slip.h | 129 + .../components/libraries/hci/hci_transport.c | 779 + .../components/libraries/hci/hci_transport.h | 220 + .../libraries/scheduler/app_scheduler.c | 227 + .../libraries/scheduler/app_scheduler.h | 163 + .../scheduler/app_scheduler_serconn.c | 262 + .../libraries/simple_timer/app_simple_timer.c | 187 + .../libraries/simple_timer/app_simple_timer.h | 98 + .../components/libraries/slip/slip.c | 112 + .../components/libraries/slip/slip.h | 66 + .../components/libraries/timer/app_timer.c | 1152 ++ .../components/libraries/timer/app_timer.h | 287 + .../libraries/timer/app_timer_appsh.c | 34 + .../libraries/timer/app_timer_appsh.h | 44 + .../components/libraries/trace/app_trace.c | 43 + .../components/libraries/trace/app_trace.h | 56 + .../components/libraries/uart/app_uart.c | 132 + .../components/libraries/uart/app_uart.h | 227 + .../components/libraries/uart/app_uart_fifo.c | 191 + .../components/libraries/uart/retarget.c | 101 + .../components/libraries/util/app_error.c | 124 + .../components/libraries/util/app_error.h | 201 + .../libraries/util/app_error_weak.c | 53 + .../libraries/util/app_error_weak.h | 51 + .../components/libraries/util/app_util.h | 493 + .../components/libraries/util/app_util_bds.h | 413 + .../libraries/util/app_util_platform.c | 60 + .../libraries/util/app_util_platform.h | 211 + .../components/libraries/util/common.h | 38 + .../components/libraries/util/nordic_common.h | 108 + .../components/libraries/util/nrf_assert.c | 28 + .../components/libraries/util/nrf_assert.h | 60 + .../components/libraries/util/nrf_log.c | 425 + .../components/libraries/util/nrf_log.h | 699 + .../components/libraries/util/sdk_common.h | 174 + .../components/libraries/util/sdk_errors.h | 115 + .../components/libraries/util/sdk_macros.h | 72 + .../libraries/util/sdk_mapped_flags.c | 161 + .../libraries/util/sdk_mapped_flags.h | 153 + .../components/libraries/util/sdk_os.h | 40 + .../components/libraries/util/sdk_resources.h | 50 + .../cmsis/include/arm_common_tables.h | 136 + .../cmsis/include/arm_const_structs.h | 79 + .../toolchain/cmsis/include/arm_math.h | 7154 ++++++++ .../toolchain/cmsis/include/cmsis_armcc.h | 734 + .../toolchain/cmsis/include/cmsis_armcc_V6.h | 1800 ++ .../toolchain/cmsis/include/cmsis_gcc.h | 1373 ++ .../toolchain/cmsis/include/core_cm0.h | 798 + .../toolchain/cmsis/include/core_cm0plus.h | 914 + .../toolchain/cmsis/include/core_cm3.h | 1763 ++ .../toolchain/cmsis/include/core_cm4.h | 1937 ++ .../toolchain/cmsis/include/core_cm7.h | 2512 +++ .../toolchain/cmsis/include/core_cmFunc.h | 87 + .../toolchain/cmsis/include/core_cmInstr.h | 87 + .../toolchain/cmsis/include/core_cmSimd.h | 96 + .../toolchain/gcc/gcc_startup_nrf52.S | 524 + .../components/toolchain/gcc/nrf52_common.ld | 160 + .../components/toolchain/gcc/nrf52_xxaa.ld | 13 + .../components/toolchain/gcc/nrf5x_common.ld | 160 + .../components/toolchain/system_nrf52.c | 301 + .../components/toolchain/system_nrf52.h | 69 + .../documentation/license.txt | 117 + .../documentation/release_notes.txt | 3267 ++++ .../ant_stack_handler_types.h | 73 + .../common/softdevice_handler/app_ram_base.h | 176 + .../ble_stack_handler_types.h | 64 + .../softdevice_handler/softdevice_handler.c | 492 + .../softdevice_handler/softdevice_handler.h | 215 + .../softdevice_handler_appsh.c | 26 + .../softdevice_handler_appsh.h | 24 + src/boards.h | 65 + src/dfu_ble_svc.c | 205 + src/dualbank/Makefile | 7 + src/feather52.h | 68 + src/license.txt | 117 + src/main.c | 516 + src/make_common.mk | 390 + src/metro52.h | 71 + src/nrf_drv_config.h | 464 + src/pstorage_platform.h | 78 + src/s132_2.0.1.ld | 78 + src/s132_5.1.0.ld | 78 + src/sdk_config.h | 3233 ++++ src/singlebank/Makefile | 7 + 186 files changed, 83021 insertions(+) create mode 100644 LICENSE create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_advdata.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_advdata.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_conn_params.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_conn_params.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/device/nrf.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/config/nrf_drv_config.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/config/nrf_drv_config_validation.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_adc.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_adc.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_clock.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_comp.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_egu.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpio.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpiote.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_i2s.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_lpcomp.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pdm.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ppi.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pwm.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_qdec.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rng.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rtc.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spi.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spim.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spis.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_temp.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_timer.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twi.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twim.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twis.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uart.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uarte.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_wdt.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage_raw.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/wdt/nrf_drv_wdt.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/wdt/nrf_drv_wdt.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/ble_transport/hci_mem_pool_internal.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_types.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.c create mode 100644 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nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_single_bank.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_ble.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_serial.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_types.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_transport_config.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.c create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.h create mode 100644 nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.c create mode 100644 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softdevice/common/softdevice_handler/softdevice_handler.c create mode 100644 softdevice/common/softdevice_handler/softdevice_handler.h create mode 100644 softdevice/common/softdevice_handler/softdevice_handler_appsh.c create mode 100644 softdevice/common/softdevice_handler/softdevice_handler_appsh.h create mode 100644 src/boards.h create mode 100644 src/dfu_ble_svc.c create mode 100644 src/dualbank/Makefile create mode 100644 src/feather52.h create mode 100644 src/license.txt create mode 100644 src/main.c create mode 100644 src/make_common.mk create mode 100644 src/metro52.h create mode 100644 src/nrf_drv_config.h create mode 100644 src/pstorage_platform.h create mode 100644 src/s132_2.0.1.ld create mode 100644 src/s132_5.1.0.ld create mode 100644 src/sdk_config.h create mode 100644 src/singlebank/Makefile diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..19a9cd8 --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2016 Adafruit Industries + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.c b/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.c new file mode 100644 index 0000000..fd36ad9 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.c @@ -0,0 +1,649 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "ble_dfu.h" +#include "ble_types.h" +#include "ble_gatts.h" +#include "ble_srv_common.h" +#include +#include "sdk_common.h" + +#define MAX_DFU_PKT_LEN 20 /**< Maximum length (in bytes) of the DFU Packet characteristic. */ +#define PKT_START_DFU_PARAM_LEN 2 /**< Length (in bytes) of the parameters for Packet Start DFU Request. */ +#define PKT_INIT_DFU_PARAM_LEN 2 /**< Length (in bytes) of the parameters for Packet Init DFU Request. */ +#define PKT_RCPT_NOTIF_REQ_LEN 3 /**< Length (in bytes) of the Packet Receipt Notification Request. */ +#define MAX_PKTS_RCPT_NOTIF_LEN 6 /**< Maximum length (in bytes) of the Packets Receipt Notification. */ +#define MAX_RESPONSE_LEN 7 /**< Maximum length (in bytes) of the response to a Control Point command. */ +#define MAX_NOTIF_BUFFER_LEN MAX(MAX_PKTS_RCPT_NOTIF_LEN, MAX_RESPONSE_LEN) /**< Maximum length (in bytes) of the buffer needed by DFU Service while sending notifications to peer. */ + +enum +{ + OP_CODE_START_DFU = 1, /**< Value of the Op code field for 'Start DFU' command.*/ + OP_CODE_RECEIVE_INIT = 2, /**< Value of the Op code field for 'Initialize DFU parameters' command.*/ + OP_CODE_RECEIVE_FW = 3, /**< Value of the Op code field for 'Receive firmware image' command.*/ + OP_CODE_VALIDATE = 4, /**< Value of the Op code field for 'Validate firmware' command.*/ + OP_CODE_ACTIVATE_N_RESET = 5, /**< Value of the Op code field for 'Activate & Reset' command.*/ + OP_CODE_SYS_RESET = 6, /**< Value of the Op code field for 'Reset System' command.*/ + OP_CODE_IMAGE_SIZE_REQ = 7, /**< Value of the Op code field for 'Report received image size' command.*/ + OP_CODE_PKT_RCPT_NOTIF_REQ = 8, /**< Value of the Op code field for 'Request packet receipt notification.*/ + OP_CODE_RESPONSE = 16, /**< Value of the Op code field for 'Response.*/ + OP_CODE_PKT_RCPT_NOTIF = 17 /**< Value of the Op code field for 'Packets Receipt Notification'.*/ +}; + +static bool m_is_dfu_service_initialized = false; /**< Variable to check if the DFU service was initialized by the application.*/ +static uint8_t m_notif_buffer[MAX_NOTIF_BUFFER_LEN]; /**< Buffer used for sending notifications to peer. */ + +/**@brief Function for adding DFU Packet characteristic to the BLE Stack. + * + * @param[in] p_dfu DFU Service structure. + * + * @return NRF_SUCCESS on success. Otherwise an error code. + */ +static uint32_t dfu_pkt_char_add(ble_dfu_t * const p_dfu) +{ + ble_gatts_char_md_t char_md; + ble_gatts_attr_t attr_char_value; + ble_uuid_t char_uuid; + ble_gatts_attr_md_t attr_md; + + memset(&char_md, 0, sizeof(char_md)); + + char_md.char_props.write_wo_resp = 1; + char_md.p_char_user_desc = NULL; + char_md.p_char_pf = NULL; + char_md.p_user_desc_md = NULL; + char_md.p_cccd_md = NULL; + char_md.p_sccd_md = NULL; + + char_uuid.type = p_dfu->uuid_type; + char_uuid.uuid = BLE_DFU_PKT_CHAR_UUID; + + memset(&attr_md, 0, sizeof(attr_md)); + + BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.read_perm); + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm); + + attr_md.vloc = BLE_GATTS_VLOC_STACK; + attr_md.rd_auth = 0; + attr_md.wr_auth = 0; + attr_md.vlen = 1; + + memset(&attr_char_value, 0, sizeof(attr_char_value)); + + attr_char_value.p_uuid = &char_uuid; + attr_char_value.p_attr_md = &attr_md; + attr_char_value.init_len = 0; + attr_char_value.init_offs = 0; + attr_char_value.max_len = MAX_DFU_PKT_LEN; + attr_char_value.p_value = NULL; + + return sd_ble_gatts_characteristic_add(p_dfu->service_handle, + &char_md, + &attr_char_value, + &p_dfu->dfu_pkt_handles); +} + + +/**@brief Function for adding DFU Revision characteristic to the BLE Stack. + * + * @param[in] p_dfu DFU Service structure. + * + * @return NRF_SUCCESS on success. Otherwise an error code. + */ +static uint32_t dfu_rev_char_add(ble_dfu_t * const p_dfu, ble_dfu_init_t const * const p_dfu_init) +{ + ble_gatts_char_md_t char_md; + ble_gatts_attr_t attr_char_value; + ble_uuid_t char_uuid; + ble_gatts_attr_md_t attr_md; + + memset(&char_md, 0, sizeof(char_md)); + + char_md.char_props.read = 1; + char_md.p_char_user_desc = NULL; + char_md.p_char_pf = NULL; + char_md.p_user_desc_md = NULL; + char_md.p_cccd_md = NULL; + char_md.p_sccd_md = NULL; + + char_uuid.type = p_dfu->uuid_type; + char_uuid.uuid = BLE_DFU_REV_CHAR_UUID; + + memset(&attr_md, 0, sizeof(attr_md)); + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.read_perm); + BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.write_perm); + + attr_md.vloc = BLE_GATTS_VLOC_STACK; + attr_md.rd_auth = 0; + attr_md.wr_auth = 0; + attr_md.vlen = 1; + + memset(&attr_char_value, 0, sizeof(attr_char_value)); + + attr_char_value.p_uuid = &char_uuid; + attr_char_value.p_attr_md = &attr_md; + attr_char_value.init_len = sizeof(uint16_t); + attr_char_value.init_offs = 0; + attr_char_value.max_len = sizeof(uint16_t); + attr_char_value.p_value = (uint8_t *)&p_dfu_init->revision; + + return sd_ble_gatts_characteristic_add(p_dfu->service_handle, + &char_md, + &attr_char_value, + &p_dfu->dfu_rev_handles); +} + + +/**@brief Function for adding DFU Control Point characteristic to the BLE Stack. + * + * @param[in] p_dfu DFU Service structure. + * + * @return NRF_SUCCESS on success. Otherwise an error code. + */ +static uint32_t dfu_ctrl_pt_add(ble_dfu_t * const p_dfu) +{ + ble_gatts_char_md_t char_md; + ble_gatts_attr_t attr_char_value; + ble_uuid_t char_uuid; + ble_gatts_attr_md_t attr_md; + + memset(&char_md, 0, sizeof(char_md)); + + char_md.char_props.write = 1; + char_md.char_props.notify = 1; + char_md.p_char_user_desc = NULL; + char_md.p_char_pf = NULL; + char_md.p_user_desc_md = NULL; + char_md.p_cccd_md = NULL; + char_md.p_sccd_md = NULL; + + char_uuid.type = p_dfu->uuid_type; + char_uuid.uuid = BLE_DFU_CTRL_PT_UUID; + + memset(&attr_md, 0, sizeof(attr_md)); + + BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.read_perm); + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm); + + attr_md.vloc = BLE_GATTS_VLOC_STACK; + attr_md.rd_auth = 0; + attr_md.wr_auth = 1; + attr_md.vlen = 1; + + memset(&attr_char_value, 0, sizeof(attr_char_value)); + + attr_char_value.p_uuid = &char_uuid; + attr_char_value.p_attr_md = &attr_md; + attr_char_value.init_len = 0; + attr_char_value.init_offs = 0; + attr_char_value.max_len = BLE_GATT_ATT_MTU_DEFAULT; + attr_char_value.p_value = NULL; + + return sd_ble_gatts_characteristic_add(p_dfu->service_handle, + &char_md, + &attr_char_value, + &p_dfu->dfu_ctrl_pt_handles); +} + + +/**@brief Function for handling the @ref BLE_GAP_EVT_CONNECTED event from the S110 SoftDevice. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] p_ble_evt Pointer to the event received from BLE stack. + */ +static void on_connect(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt) +{ + p_dfu->conn_handle = p_ble_evt->evt.gap_evt.conn_handle; +} + + +/**@brief Function for checking if the CCCD of DFU Control point is configured for Notification. + * + * @details This function checks if the CCCD of DFU Control Point characteristic is configured + * for Notification by the DFU Controller. + * + * @param[in] p_dfu DFU Service structure. + * + * @return True if the CCCD of DFU Control Point characteristic is configured for Notification. + * False otherwise. + */ +static bool is_cccd_configured(ble_dfu_t * p_dfu) +{ + // Check if the CCCDs are configured. + uint8_t cccd_val_buf[BLE_CCCD_VALUE_LEN]; + ble_gatts_value_t gatts_value; + + // Initialize value struct. + memset(&gatts_value, 0, sizeof(gatts_value)); + + gatts_value.len = BLE_CCCD_VALUE_LEN; + gatts_value.offset = 0; + gatts_value.p_value = cccd_val_buf; + + // Check the CCCD Value of DFU Control Point. + uint32_t err_code = sd_ble_gatts_value_get(p_dfu->conn_handle, + p_dfu->dfu_ctrl_pt_handles.cccd_handle, + &gatts_value); + if (err_code != NRF_SUCCESS) + { + if (p_dfu->error_handler != NULL) + { + p_dfu->error_handler(err_code); + } + return false; + } + + return ble_srv_is_notification_enabled(cccd_val_buf); +} + + +/**@brief Function for handling a Write event on the Control Point characteristic. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] p_ble_write_evt Pointer to the write event received from BLE stack. + * + * @return NRF_SUCCESS on successful processing of control point write. Otherwise an error code. + */ +static uint32_t on_ctrl_pt_write(ble_dfu_t * p_dfu, ble_gatts_evt_write_t * p_ble_write_evt) +{ + ble_gatts_rw_authorize_reply_params_t auth_reply; + + auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE; + auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE; + auth_reply.params.write.update = 1; + auth_reply.params.write.offset = p_ble_write_evt->offset; + auth_reply.params.write.len = p_ble_write_evt->len; + auth_reply.params.write.p_data = p_ble_write_evt->data; + + + if (!is_cccd_configured(p_dfu)) + { + // Send an error response to the peer indicating that the CCCD is improperly configured. + auth_reply.params.write.gatt_status = + BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR; + + return (sd_ble_gatts_rw_authorize_reply(p_dfu->conn_handle, &auth_reply)); + + } + else + { + uint32_t err_code; + + auth_reply.params.write.gatt_status = BLE_GATT_STATUS_SUCCESS; + + err_code = (sd_ble_gatts_rw_authorize_reply(p_dfu->conn_handle, &auth_reply)); + VERIFY_SUCCESS(err_code); + } + + ble_dfu_evt_t ble_dfu_evt; + + switch (p_ble_write_evt->data[0]) + { + case OP_CODE_START_DFU: + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_START; + + if (p_ble_write_evt->len < PKT_START_DFU_PARAM_LEN) + { + return ble_dfu_response_send(p_dfu, + (ble_dfu_procedure_t) p_ble_write_evt->data[0], + BLE_DFU_RESP_VAL_OPER_FAILED); + } + + ble_dfu_evt.evt.ble_dfu_pkt_write.len = 1; + ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = &(p_ble_write_evt->data[1]); + + p_dfu->evt_handler(p_dfu, &ble_dfu_evt); + break; + + case OP_CODE_RECEIVE_INIT: + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_RECEIVE_INIT_DATA; + + if (p_ble_write_evt->len < PKT_INIT_DFU_PARAM_LEN) + { + return ble_dfu_response_send(p_dfu, + (ble_dfu_procedure_t) p_ble_write_evt->data[0], + BLE_DFU_RESP_VAL_OPER_FAILED); + } + + ble_dfu_evt.evt.ble_dfu_pkt_write.len = 1; + ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = &(p_ble_write_evt->data[1]); + + p_dfu->evt_handler(p_dfu, &ble_dfu_evt); + break; + + case OP_CODE_RECEIVE_FW: + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_RECEIVE_APP_DATA; + + p_dfu->evt_handler(p_dfu, &ble_dfu_evt); + break; + + case OP_CODE_VALIDATE: + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_VALIDATE; + + p_dfu->evt_handler(p_dfu, &ble_dfu_evt); + break; + + case OP_CODE_ACTIVATE_N_RESET: + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_ACTIVATE_N_RESET; + + p_dfu->evt_handler(p_dfu, &ble_dfu_evt); + break; + + case OP_CODE_SYS_RESET: + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_SYS_RESET; + + p_dfu->evt_handler(p_dfu, &ble_dfu_evt); + break; + + case OP_CODE_PKT_RCPT_NOTIF_REQ: + if (p_ble_write_evt->len < PKT_RCPT_NOTIF_REQ_LEN) + { + return (ble_dfu_response_send(p_dfu, + BLE_DFU_PKT_RCPT_REQ_PROCEDURE, + BLE_DFU_RESP_VAL_NOT_SUPPORTED)); + } + + ble_dfu_evt.evt.pkt_rcpt_notif_req.num_of_pkts = + uint16_decode(&(p_ble_write_evt->data[1])); + + if (ble_dfu_evt.evt.pkt_rcpt_notif_req.num_of_pkts == 0) + { + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PKT_RCPT_NOTIF_DISABLED; + } + else + { + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PKT_RCPT_NOTIF_ENABLED; + } + + p_dfu->evt_handler(p_dfu, &ble_dfu_evt); + + break; + + case OP_CODE_IMAGE_SIZE_REQ: + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_BYTES_RECEIVED_SEND; + + p_dfu->evt_handler(p_dfu, &ble_dfu_evt); + break; + + default: + // Unsupported op code. + return ble_dfu_response_send(p_dfu, + (ble_dfu_procedure_t) p_ble_write_evt->data[0], + BLE_DFU_RESP_VAL_NOT_SUPPORTED); + } + return NRF_SUCCESS; +} + + +/**@brief Function for handling the @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event from the S110 + * Stack. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] p_ble_evt Pointer to the event received from BLE stack. + */ +static void on_rw_authorize_req(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt) +{ + ble_gatts_evt_rw_authorize_request_t * p_authorize_request; + + p_authorize_request = &(p_ble_evt->evt.gatts_evt.params.authorize_request); + + if ( + (p_authorize_request->type == BLE_GATTS_AUTHORIZE_TYPE_WRITE) + && + (p_authorize_request->request.write.handle == p_dfu->dfu_ctrl_pt_handles.value_handle) + && + (p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op != BLE_GATTS_OP_PREP_WRITE_REQ) + && + (p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op != BLE_GATTS_OP_EXEC_WRITE_REQ_NOW) + && + (p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op != BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL) + ) + { + uint32_t err_code; + + err_code = on_ctrl_pt_write(p_dfu, &(p_authorize_request->request.write)); + + if (err_code != NRF_SUCCESS && p_dfu->error_handler != NULL) + { + p_dfu->error_handler(err_code); + } + } +} + + +/**@brief Function for handling the @ref BLE_GATTS_EVT_WRITE event from the S110 SoftDevice. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] p_ble_evt Pointer to the event received from BLE stack. + */ +static void on_write(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt) +{ + if (p_ble_evt->evt.gatts_evt.params.write.handle == p_dfu->dfu_pkt_handles.value_handle) + { + // DFU Packet written + + ble_dfu_evt_t ble_dfu_evt; + + ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PACKET_WRITE; + ble_dfu_evt.evt.ble_dfu_pkt_write.len = p_ble_evt->evt.gatts_evt.params.write.len; + ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = p_ble_evt->evt.gatts_evt.params.write.data; + + p_dfu->evt_handler(p_dfu, &ble_dfu_evt); + } +} + + +/**@brief Function for handling the BLE_GAP_EVT_DISCONNECTED event from the S110 SoftDevice. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] p_ble_evt Pointer to the event received from BLE stack. + */ +static void on_disconnect(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt) +{ + p_dfu->conn_handle = BLE_CONN_HANDLE_INVALID; +} + + +uint32_t ble_dfu_init(ble_dfu_t * p_dfu, ble_dfu_init_t * p_dfu_init) +{ + if ((p_dfu == NULL) || (p_dfu_init == NULL) || (p_dfu_init->evt_handler == NULL)) + { + return NRF_ERROR_NULL; + } + + p_dfu->conn_handle = BLE_CONN_HANDLE_INVALID; + + ble_uuid_t service_uuid; + uint32_t err_code; + + const ble_uuid128_t base_uuid128 = + { + { + 0x23, 0xD1, 0xBC, 0xEA, 0x5F, 0x78, 0x23, 0x15, + 0xDE, 0xEF, 0x12, 0x12, 0x00, 0x00, 0x00, 0x00 + } + }; + + service_uuid.uuid = BLE_DFU_SERVICE_UUID; + + err_code = sd_ble_uuid_vs_add(&base_uuid128, &(service_uuid.type)); + VERIFY_SUCCESS(err_code); + + err_code = sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY, + &service_uuid, + &(p_dfu->service_handle)); + VERIFY_SUCCESS(err_code); + + p_dfu->uuid_type = service_uuid.type; + + err_code = dfu_pkt_char_add(p_dfu); + VERIFY_SUCCESS(err_code); + + err_code = dfu_ctrl_pt_add(p_dfu); + VERIFY_SUCCESS(err_code); + + err_code = dfu_rev_char_add(p_dfu, p_dfu_init); + VERIFY_SUCCESS(err_code); + + p_dfu->evt_handler = p_dfu_init->evt_handler; + + if (p_dfu_init->error_handler != NULL) + { + p_dfu->error_handler = p_dfu_init->error_handler; + } + + m_is_dfu_service_initialized = true; + + return NRF_SUCCESS; +} + + +void ble_dfu_on_ble_evt(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt) +{ + if ((p_dfu == NULL) || (p_ble_evt == NULL)) + { + return; + } + + if (p_dfu->evt_handler != NULL) + { + switch (p_ble_evt->header.evt_id) + { + case BLE_GAP_EVT_CONNECTED: + on_connect(p_dfu, p_ble_evt); + break; + + case BLE_GATTS_EVT_WRITE: + on_write(p_dfu, p_ble_evt); + break; + + case BLE_GAP_EVT_DISCONNECTED: + on_disconnect(p_dfu, p_ble_evt); + break; + + case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST: + on_rw_authorize_req(p_dfu, p_ble_evt); + break; + + default: + // No implementation needed. + break; + } + } +} + + +uint32_t ble_dfu_bytes_rcvd_report(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd) +{ + if (p_dfu == NULL) + { + return NRF_ERROR_NULL; + } + + if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized) + { + return NRF_ERROR_INVALID_STATE; + } + + ble_gatts_hvx_params_t hvx_params; + uint16_t index = 0; + + // Encode the Op Code. + m_notif_buffer[index++] = OP_CODE_RESPONSE; + + // Encode the Reqest Op Code. + m_notif_buffer[index++] = OP_CODE_IMAGE_SIZE_REQ; + + // Encode the Response Value. + m_notif_buffer[index++] = (uint8_t)BLE_DFU_RESP_VAL_SUCCESS; + + index += uint32_encode(num_of_firmware_bytes_rcvd, &m_notif_buffer[index]); + + memset(&hvx_params, 0, sizeof(hvx_params)); + + hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle; + hvx_params.type = BLE_GATT_HVX_NOTIFICATION; + hvx_params.offset = 0; + hvx_params.p_len = &index; + hvx_params.p_data = m_notif_buffer; + + return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params); +} + + +uint32_t ble_dfu_pkts_rcpt_notify(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd) +{ + if (p_dfu == NULL) + { + return NRF_ERROR_NULL; + } + + if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized) + { + return NRF_ERROR_INVALID_STATE; + } + + ble_gatts_hvx_params_t hvx_params; + uint16_t index = 0; + + m_notif_buffer[index++] = OP_CODE_PKT_RCPT_NOTIF; + + index += uint32_encode(num_of_firmware_bytes_rcvd, &m_notif_buffer[index]); + + memset(&hvx_params, 0, sizeof(hvx_params)); + + hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle; + hvx_params.type = BLE_GATT_HVX_NOTIFICATION; + hvx_params.offset = 0; + hvx_params.p_len = &index; + hvx_params.p_data = m_notif_buffer; + + return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params); +} + + +uint32_t ble_dfu_response_send(ble_dfu_t * p_dfu, + ble_dfu_procedure_t dfu_proc, + ble_dfu_resp_val_t resp_val) +{ + if (p_dfu == NULL) + { + return NRF_ERROR_NULL; + } + + if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized) + { + return NRF_ERROR_INVALID_STATE; + } + + ble_gatts_hvx_params_t hvx_params; + uint16_t index = 0; + + m_notif_buffer[index++] = OP_CODE_RESPONSE; + + // Encode the Request Op code + m_notif_buffer[index++] = (uint8_t)dfu_proc; + + // Encode the Response Value. + m_notif_buffer[index++] = (uint8_t)resp_val; + + memset(&hvx_params, 0, sizeof(hvx_params)); + + hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle; + hvx_params.type = BLE_GATT_HVX_NOTIFICATION; + hvx_params.offset = 0; + hvx_params.p_len = &index; + hvx_params.p_data = m_notif_buffer; + + return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.h b/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.h new file mode 100644 index 0000000..f50f1e6 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dfu/ble_dfu.h @@ -0,0 +1,239 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup ble_sdk_srv_dfu Device Firmware Update Service + * @{ + * @ingroup ble_sdk_srv + * @brief Device Firmware Update Service + * + * @details The Device Firmware Update (DFU) service is a GATT based service that can be used for + * performing firmware updates over BLE. Note that this implementation uses vendor + * specific UUIDs for service and characteristics and is intended to demonstrate the + * firmware updates over BLE. Refer @ref bledfu_transport_bleservice and @ref + * bledfu_transport_bleprofile for more information on the service and profile respectively. + */ + +#ifndef BLE_DFU_H__ +#define BLE_DFU_H__ + +#include +#include "ble_gatts.h" +#include "ble_gap.h" +#include "ble.h" +#include "ble_srv_common.h" + +#define BLE_DFU_SERVICE_UUID 0x1530 /**< The UUID of the DFU Service. */ +#define BLE_DFU_PKT_CHAR_UUID 0x1532 /**< The UUID of the DFU Packet Characteristic. */ +#define BLE_DFU_CTRL_PT_UUID 0x1531 /**< The UUID of the DFU Control Point. */ +#define BLE_DFU_STATUS_REP_UUID 0x1533 /**< The UUID of the DFU Status Report Characteristic. */ +#define BLE_DFU_REV_CHAR_UUID 0x1534 /**< The UUID of the DFU Revision Characteristic. */ + +/**@brief DFU Event type. + * + * @details This enumeration contains the types of events that will be received from the DFU Service. + */ +typedef enum +{ + BLE_DFU_START, /**< The event indicating that the peer wants the application to prepare for a new firmware update. */ + BLE_DFU_RECEIVE_INIT_DATA, /**< The event indicating that the peer wants the application to prepare to receive init parameters. */ + BLE_DFU_RECEIVE_APP_DATA, /**< The event indicating that the peer wants the application to prepare to receive the new firmware image. */ + BLE_DFU_VALIDATE, /**< The event indicating that the peer wants the application to validate the newly received firmware image. */ + BLE_DFU_ACTIVATE_N_RESET, /**< The event indicating that the peer wants the application to undergo activate new firmware and restart with new valid application */ + BLE_DFU_SYS_RESET, /**< The event indicating that the peer wants the application to undergo a reset and start the currently valid application image.*/ + BLE_DFU_PKT_RCPT_NOTIF_ENABLED, /**< The event indicating that the peer has enabled packet receipt notifications. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify each time the number of packets indicated by num_of_pkts field in @ref ble_dfu_evt_t is received.*/ + BLE_DFU_PKT_RCPT_NOTIF_DISABLED, /**< The event indicating that the peer has disabled the packet receipt notifications.*/ + BLE_DFU_PACKET_WRITE, /**< The event indicating that the peer has written a value to the 'DFU Packet' characteristic. The data received from the peer will be present in the @ref BLE_DFU_PACKET_WRITE element contained within @ref ble_dfu_evt_t.*/ + BLE_DFU_BYTES_RECEIVED_SEND /**< The event indicating that the peer is requesting for the number of bytes of firmware data last received by the application. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify in response to this event. */ +} ble_dfu_evt_type_t; + +/**@brief DFU Procedure type. + * + * @details This enumeration contains the types of DFU procedures. + */ +typedef enum +{ + BLE_DFU_START_PROCEDURE = 1, /**< DFU Start procedure.*/ + BLE_DFU_INIT_PROCEDURE = 2, /**< DFU Initialization procedure.*/ + BLE_DFU_RECEIVE_APP_PROCEDURE = 3, /**< Firmware receiving procedure.*/ + BLE_DFU_VALIDATE_PROCEDURE = 4, /**< Firmware image validation procedure .*/ + BLE_DFU_PKT_RCPT_REQ_PROCEDURE = 8 /**< Packet receipt notification request procedure. */ +} ble_dfu_procedure_t; + +/**@brief DFU Response value type. + */ +typedef enum +{ + BLE_DFU_RESP_VAL_SUCCESS = 1, /**< Success.*/ + BLE_DFU_RESP_VAL_INVALID_STATE, /**< Invalid state.*/ + BLE_DFU_RESP_VAL_NOT_SUPPORTED, /**< Operation not supported.*/ + BLE_DFU_RESP_VAL_DATA_SIZE, /**< Data size exceeds limit.*/ + BLE_DFU_RESP_VAL_CRC_ERROR, /**< CRC Error.*/ + BLE_DFU_RESP_VAL_OPER_FAILED /**< Operation failed.*/ +} ble_dfu_resp_val_t; + + +/**@brief DFU Packet structure. + * + * @details This structure contains the value of the DFU Packet characteristic as written by the + * peer and the length of the value written. It will be filled by the DFU Service when the + * peer writes to the DFU Packet characteristic. + */ +typedef struct +{ + uint8_t * p_data; /**< Pointer to the received packet. This will point to a word aligned memory location.*/ + uint8_t len; /**< Length of the packet received. */ +} ble_dfu_pkt_write_t; + +/**@brief Packet receipt notification request structure. + * + * @details This structure contains the contents of the packet receipt notification request + * sent by the DFU Controller. + */ +typedef struct +{ + uint16_t num_of_pkts; /**< The number of packets of firmware data to be received by application before sending the next Packet Receipt Notification to the peer. */ +} ble_pkt_rcpt_notif_req_t; + +/**@brief DFU Event structure. + * + * @details This structure contains the event generated by the DFU Service based on the data + * received from the peer. + */ +typedef struct +{ + ble_dfu_evt_type_t ble_dfu_evt_type; /**< Type of the event.*/ + union + { + ble_dfu_pkt_write_t ble_dfu_pkt_write; /**< The DFU packet received. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PACKET_WRITE.*/ + ble_pkt_rcpt_notif_req_t pkt_rcpt_notif_req; /**< Packet receipt notification request. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PKT_RCPT_NOTIF_ENABLED.*/ + } evt; +} ble_dfu_evt_t; + +// Forward declaration of the ble_dfu_t type. +typedef struct ble_dfu_s ble_dfu_t; + +/**@brief DFU Service event handler type. */ +typedef void (*ble_dfu_evt_handler_t) (ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt); + +/**@brief DFU service structure. + * + * @details This structure contains status information related to the service. + */ +struct ble_dfu_s +{ + uint16_t conn_handle; /**< Handle of the current connection (as provided by the SoftDevice). This will be BLE_CONN_HANDLE_INVALID when not in a connection. */ + uint16_t revision; /**< Handle of DFU Service (as provided by the SoftDevice). */ + uint16_t service_handle; /**< Handle of DFU Service (as provided by the SoftDevice). */ + uint8_t uuid_type; /**< UUID type assigned for DFU Service by the SoftDevice. */ + ble_gatts_char_handles_t dfu_pkt_handles; /**< Handles related to the DFU Packet characteristic. */ + ble_gatts_char_handles_t dfu_ctrl_pt_handles; /**< Handles related to the DFU Control Point characteristic. */ + ble_gatts_char_handles_t dfu_status_rep_handles; /**< Handles related to the DFU Status Report characteristic. */ + ble_gatts_char_handles_t dfu_rev_handles; /**< Handles related to the DFU Revision characteristic. */ + ble_dfu_evt_handler_t evt_handler; /**< The event handler to be called when an event is to be sent to the application.*/ + ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */ +}; + +/**@brief DFU service initialization structure. + * + * @details This structure contains the initialization information for the DFU Service. The + * application needs to fill this structure and pass it to the DFU Service using the + * @ref ble_dfu_init function. + */ +typedef struct +{ + uint16_t revision; /**< Revision number to be exposed by the DFU service. */ + ble_dfu_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Device Firmware Update Service. */ + ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */ +} ble_dfu_init_t; + +/**@brief Function for handling a BLE event. + * + * @details The DFU service expects the application to call this function each time an event + * is received from the SoftDevice. This function processes the event, if it is + * relevant for the DFU service and calls the DFU event handler of the application if + * necessary. + * + * @param[in] p_dfu Pointer to the DFU service structure. + * @param[in] p_ble_evt Pointer to the event received from SoftDevice. + */ +void ble_dfu_on_ble_evt(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt); + +/**@brief Function for initializing the DFU service. + * + * @param[out] p_dfu Device Firmware Update service structure. This structure will have to be + * supplied by the application. It will be initialized by this function, + * and will later be used to identify the service instance. + * @param[in] p_dfu_init Information needed to initialize the service. + * + * @return NRF_SUCCESS if the DFU service and its characteristics were successfully added to the + * SoftDevice. Otherwise an error code. + * This function returns NRF_ERROR_NULL if the value of evt_handler in p_dfu_init + * structure provided is NULL or if the pointers supplied as input are NULL. + */ +uint32_t ble_dfu_init(ble_dfu_t * p_dfu, ble_dfu_init_t * p_dfu_init); + +/**@brief Function for sending response to a control point command. + * + * @details This function will encode a DFU Control Point response using the given input + * parameters and will send a notification of the same to the peer. + * + * @param[in] p_dfu Pointer to the DFU service structure. + * @param[in] dfu_proc Procedure for which this response is to be sent. + * @param[in] resp_val Response value. + * + * @return NRF_SUCCESS if the DFU Service has successfully requested the SoftDevice to + * send the notification. Otherwise an error code. + * This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a + * peer or if the DFU service is not initialized or if the notification of the DFU + * Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL + * if the pointer p_dfu is NULL. + */ +uint32_t ble_dfu_response_send(ble_dfu_t * p_dfu, + ble_dfu_procedure_t dfu_proc, + ble_dfu_resp_val_t resp_val); + +/**@brief Function for notifying the peer about the number of bytes of firmware data received. + * + * @param[in] p_dfu Pointer to the DFU service structure. + * @param[in] num_of_firmware_bytes_rcvd Number of bytes. + * + * @return NRF_SUCCESS if the DFU Service has successfully requested the SoftDevice to send + * the notification. Otherwise an error code. + * This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a + * peer or if the DFU service is not initialized or if the notification of the DFU + * Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL + * if the pointer p_dfu is NULL. + */ +uint32_t ble_dfu_bytes_rcvd_report(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd); + +/**@brief Function for sending Packet Receipt Notification to the peer. + * + * This function will encode the number of bytes received as input parameter into a + * notification of the control point characteristic and send it to the peer. + * + * @param[in] p_dfu Pointer to the DFU service structure. + * @param[in] num_of_firmware_bytes_rcvd Number of bytes of firmware image received. + * + * @return NRF_SUCCESS if the DFU Service has successfully requested the SoftDevice to send + * the notification. Otherwise an error code. + * This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a + * peer or if the DFU service is not initialized or if the notification of the DFU + * Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL + * if the pointer p_dfu is NULL. + */ +uint32_t ble_dfu_pkts_rcpt_notify(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd); + +#endif // BLE_DFU_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.c b/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.c new file mode 100644 index 0000000..61fc1e5 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.c @@ -0,0 +1,277 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/* Attention! +* To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile +* qualification listings, this section of source code must not be modified. +*/ + +#include "ble_dis.h" + +#include +#include +#include "app_error.h" +#include "ble_gatts.h" +#include "nordic_common.h" +#include "ble_srv_common.h" +#include "app_util.h" + + +#define BLE_DIS_SYS_ID_LEN 8 /**< Length of System ID Characteristic Value. */ +#define BLE_DIS_PNP_ID_LEN 7 /**< Length of Pnp ID Characteristic Value. */ + +static uint16_t service_handle; +static ble_gatts_char_handles_t manufact_name_handles; +static ble_gatts_char_handles_t model_num_handles; +static ble_gatts_char_handles_t serial_num_handles; +static ble_gatts_char_handles_t hw_rev_handles; +static ble_gatts_char_handles_t fw_rev_handles; +static ble_gatts_char_handles_t sw_rev_handles; +static ble_gatts_char_handles_t sys_id_handles; +static ble_gatts_char_handles_t reg_cert_data_list_handles; +static ble_gatts_char_handles_t pnp_id_handles; + + +/**@brief Function for encoding a System ID. + * + * @param[out] p_encoded_buffer Buffer where the encoded data will be written. + * @param[in] p_sys_id System ID to be encoded. + */ +static void sys_id_encode(uint8_t * p_encoded_buffer, const ble_dis_sys_id_t * p_sys_id) +{ + APP_ERROR_CHECK_BOOL(p_sys_id != NULL); + APP_ERROR_CHECK_BOOL(p_encoded_buffer != NULL); + + p_encoded_buffer[0] = (p_sys_id->manufacturer_id & 0x00000000FF); + p_encoded_buffer[1] = (p_sys_id->manufacturer_id & 0x000000FF00) >> 8; + p_encoded_buffer[2] = (p_sys_id->manufacturer_id & 0x0000FF0000) >> 16; + p_encoded_buffer[3] = (p_sys_id->manufacturer_id & 0x00FF000000) >> 24; + p_encoded_buffer[4] = (p_sys_id->manufacturer_id & 0xFF00000000) >> 32; + + p_encoded_buffer[5] = (p_sys_id->organizationally_unique_id & 0x0000FF); + p_encoded_buffer[6] = (p_sys_id->organizationally_unique_id & 0x00FF00) >> 8; + p_encoded_buffer[7] = (p_sys_id->organizationally_unique_id & 0xFF0000) >> 16; +} + + +/**@brief Function for encoding a PnP ID. + * + * @param[out] p_encoded_buffer Buffer where the encoded data will be written. + * @param[in] p_pnp_id PnP ID to be encoded. + */ +static void pnp_id_encode(uint8_t * p_encoded_buffer, const ble_dis_pnp_id_t * p_pnp_id) +{ + uint8_t len = 0; + + APP_ERROR_CHECK_BOOL(p_pnp_id != NULL); + APP_ERROR_CHECK_BOOL(p_encoded_buffer != NULL); + + p_encoded_buffer[len++] = p_pnp_id->vendor_id_source; + + len += uint16_encode(p_pnp_id->vendor_id, &p_encoded_buffer[len]); + len += uint16_encode(p_pnp_id->product_id, &p_encoded_buffer[len]); + len += uint16_encode(p_pnp_id->product_version, &p_encoded_buffer[len]); + + APP_ERROR_CHECK_BOOL(len == BLE_DIS_PNP_ID_LEN); +} + + +/**@brief Function for adding the Characteristic. + * + * @param[in] uuid UUID of characteristic to be added. + * @param[in] p_char_value Initial value of characteristic to be added. + * @param[in] char_len Length of initial value. This will also be the maximum value. + * @param[in] dis_attr_md Security settings of characteristic to be added. + * @param[out] p_handles Handles of new characteristic. + * + * @return NRF_SUCCESS on success, otherwise an error code. + */ +static uint32_t char_add(uint16_t uuid, + uint8_t * p_char_value, + uint16_t char_len, + const ble_srv_security_mode_t * dis_attr_md, + ble_gatts_char_handles_t * p_handles) +{ + ble_uuid_t ble_uuid; + ble_gatts_char_md_t char_md; + ble_gatts_attr_t attr_char_value; + ble_gatts_attr_md_t attr_md; + + APP_ERROR_CHECK_BOOL(p_char_value != NULL); + APP_ERROR_CHECK_BOOL(char_len > 0); + + // The ble_gatts_char_md_t structure uses bit fields. So we reset the memory to zero. + memset(&char_md, 0, sizeof(char_md)); + + char_md.char_props.read = 1; + char_md.p_char_user_desc = NULL; + char_md.p_char_pf = NULL; + char_md.p_user_desc_md = NULL; + char_md.p_cccd_md = NULL; + char_md.p_sccd_md = NULL; + + BLE_UUID_BLE_ASSIGN(ble_uuid, uuid); + + memset(&attr_md, 0, sizeof(attr_md)); + + attr_md.read_perm = dis_attr_md->read_perm; + attr_md.write_perm = dis_attr_md->write_perm; + attr_md.vloc = BLE_GATTS_VLOC_STACK; + attr_md.rd_auth = 0; + attr_md.wr_auth = 0; + attr_md.vlen = 0; + + memset(&attr_char_value, 0, sizeof(attr_char_value)); + + attr_char_value.p_uuid = &ble_uuid; + attr_char_value.p_attr_md = &attr_md; + attr_char_value.init_len = char_len; + attr_char_value.init_offs = 0; + attr_char_value.max_len = char_len; + attr_char_value.p_value = p_char_value; + + return sd_ble_gatts_characteristic_add(service_handle, &char_md, &attr_char_value, p_handles); +} + + +uint32_t ble_dis_init(const ble_dis_init_t * p_dis_init) +{ + uint32_t err_code; + ble_uuid_t ble_uuid; + + // Add service + BLE_UUID_BLE_ASSIGN(ble_uuid, BLE_UUID_DEVICE_INFORMATION_SERVICE); + + err_code = sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY, &ble_uuid, &service_handle); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + + // Add characteristics + if (p_dis_init->manufact_name_str.length > 0) + { + err_code = char_add(BLE_UUID_MANUFACTURER_NAME_STRING_CHAR, + p_dis_init->manufact_name_str.p_str, + p_dis_init->manufact_name_str.length, + &p_dis_init->dis_attr_md, + &manufact_name_handles); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + if (p_dis_init->model_num_str.length > 0) + { + err_code = char_add(BLE_UUID_MODEL_NUMBER_STRING_CHAR, + p_dis_init->model_num_str.p_str, + p_dis_init->model_num_str.length, + &p_dis_init->dis_attr_md, + &model_num_handles); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + if (p_dis_init->serial_num_str.length > 0) + { + err_code = char_add(BLE_UUID_SERIAL_NUMBER_STRING_CHAR, + p_dis_init->serial_num_str.p_str, + p_dis_init->serial_num_str.length, + &p_dis_init->dis_attr_md, + &serial_num_handles); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + if (p_dis_init->hw_rev_str.length > 0) + { + err_code = char_add(BLE_UUID_HARDWARE_REVISION_STRING_CHAR, + p_dis_init->hw_rev_str.p_str, + p_dis_init->hw_rev_str.length, + &p_dis_init->dis_attr_md, + &hw_rev_handles); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + if (p_dis_init->fw_rev_str.length > 0) + { + err_code = char_add(BLE_UUID_FIRMWARE_REVISION_STRING_CHAR, + p_dis_init->fw_rev_str.p_str, + p_dis_init->fw_rev_str.length, + &p_dis_init->dis_attr_md, + &fw_rev_handles); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + if (p_dis_init->sw_rev_str.length > 0) + { + err_code = char_add(BLE_UUID_SOFTWARE_REVISION_STRING_CHAR, + p_dis_init->sw_rev_str.p_str, + p_dis_init->sw_rev_str.length, + &p_dis_init->dis_attr_md, + &sw_rev_handles); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + if (p_dis_init->p_sys_id != NULL) + { + uint8_t encoded_sys_id[BLE_DIS_SYS_ID_LEN]; + + sys_id_encode(encoded_sys_id, p_dis_init->p_sys_id); + err_code = char_add(BLE_UUID_SYSTEM_ID_CHAR, + encoded_sys_id, + BLE_DIS_SYS_ID_LEN, + &p_dis_init->dis_attr_md, + &sys_id_handles); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + if (p_dis_init->p_reg_cert_data_list != NULL) + { + err_code = char_add(BLE_UUID_IEEE_REGULATORY_CERTIFICATION_DATA_LIST_CHAR, + p_dis_init->p_reg_cert_data_list->p_list, + p_dis_init->p_reg_cert_data_list->list_len, + &p_dis_init->dis_attr_md, + ®_cert_data_list_handles); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + if (p_dis_init->p_pnp_id != NULL) + { + uint8_t encoded_pnp_id[BLE_DIS_PNP_ID_LEN]; + + pnp_id_encode(encoded_pnp_id, p_dis_init->p_pnp_id); + err_code = char_add(BLE_UUID_PNP_ID_CHAR, + encoded_pnp_id, + BLE_DIS_PNP_ID_LEN, + &p_dis_init->dis_attr_md, + &pnp_id_handles); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + + return NRF_SUCCESS; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.h b/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.h new file mode 100644 index 0000000..aaf3980 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/ble_services/ble_dis/ble_dis.h @@ -0,0 +1,98 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup ble_sdk_srv_dis Device Information Service + * @{ + * @ingroup ble_sdk_srv + * @brief Device Information Service module. + * + * @details This module implements the Device Information Service. + * During initialization it adds the Device Information Service to the BLE stack database. + * It then encodes the supplied information, and adds the curresponding characteristics. + * + * @note Attention! + * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile + * qualification listings, this section of source code must not be modified. + */ + +#ifndef BLE_DIS_H__ +#define BLE_DIS_H__ + +#include +#include "ble_srv_common.h" + +/** @defgroup DIS_VENDOR_ID_SRC_VALUES Vendor ID Source values + * @{ + */ +#define BLE_DIS_VENDOR_ID_SRC_BLUETOOTH_SIG 1 /**< Vendor ID assigned by Bluetooth SIG. */ +#define BLE_DIS_VENDOR_ID_SRC_USB_IMPL_FORUM 2 /**< Vendor ID assigned by USB Implementer's Forum. */ +/** @} */ + +/**@brief System ID parameters */ +typedef struct +{ + uint64_t manufacturer_id; /**< Manufacturer ID. Only 5 LSOs shall be used. */ + uint32_t organizationally_unique_id; /**< Organizationally unique ID. Only 3 LSOs shall be used. */ +} ble_dis_sys_id_t; + +/**@brief IEEE 11073-20601 Regulatory Certification Data List Structure */ +typedef struct +{ + uint8_t * p_list; /**< Pointer the byte array containing the encoded opaque structure based on IEEE 11073-20601 specification. */ + uint8_t list_len; /**< Length of the byte array. */ +} ble_dis_reg_cert_data_list_t; + +/**@brief PnP ID parameters */ +typedef struct +{ + uint8_t vendor_id_source; /**< Vendor ID Source. see @ref DIS_VENDOR_ID_SRC_VALUES. */ + uint16_t vendor_id; /**< Vendor ID. */ + uint16_t product_id; /**< Product ID. */ + uint16_t product_version; /**< Product Version. */ +} ble_dis_pnp_id_t; + +/**@brief Device Information Service init structure. This contains all possible characteristics + * needed for initialization of the service. + */ +typedef struct +{ + ble_srv_utf8_str_t manufact_name_str; /**< Manufacturer Name String. */ + ble_srv_utf8_str_t model_num_str; /**< Model Number String. */ + ble_srv_utf8_str_t serial_num_str; /**< Serial Number String. */ + ble_srv_utf8_str_t hw_rev_str; /**< Hardware Revision String. */ + ble_srv_utf8_str_t fw_rev_str; /**< Firmware Revision String. */ + ble_srv_utf8_str_t sw_rev_str; /**< Software Revision String. */ + ble_dis_sys_id_t * p_sys_id; /**< System ID. */ + ble_dis_reg_cert_data_list_t * p_reg_cert_data_list; /**< IEEE 11073-20601 Regulatory Certification Data List. */ + ble_dis_pnp_id_t * p_pnp_id; /**< PnP ID. */ + ble_srv_security_mode_t dis_attr_md; /**< Initial Security Setting for Device Information Characteristics. */ +} ble_dis_init_t; + +/**@brief Function for initializing the Device Information Service. + * + * @details This call allows the application to initialize the device information service. + * It adds the DIS service and DIS characteristics to the database, using the initial + * values supplied through the p_dis_init parameter. Characteristics which are not to be + * added, shall be set to NULL in p_dis_init. + * + * @param[in] p_dis_init The structure containing the values of characteristics needed by the + * service. + * + * @return NRF_SUCCESS on successful initialization of service. + */ +uint32_t ble_dis_init(const ble_dis_init_t * p_dis_init); + +#endif // BLE_DIS_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_advdata.c b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_advdata.c new file mode 100644 index 0000000..a13ba04 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_advdata.c @@ -0,0 +1,761 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "ble_advdata.h" +#include "ble_gap.h" +#include "ble_srv_common.h" +#include "sdk_common.h" + +// NOTE: For now, Security Manager Out of Band Flags (OOB) are omitted from the advertising data. + +// Types of LE Bluetooth Device Address AD type +#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_PUBLIC 0UL +#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_RANDOM 1UL + +static uint32_t tk_value_encode(ble_advdata_tk_value_t * p_tk_value, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + int8_t i; + + // Check for buffer overflow. + if (((*p_offset) + AD_TYPE_TK_VALUE_SIZE) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + // Encode LE Role. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_TK_VALUE_DATA_SIZE); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + + for (i = AD_TYPE_TK_VALUE_DATA_SIZE - 1; i >= 0; i--, (*p_offset)++) + { + p_encoded_data[*p_offset] = p_tk_value->tk[i]; + } + + return NRF_SUCCESS; +} + +static uint32_t le_role_encode(ble_advdata_le_role_t le_role, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + // Check for buffer overflow. + if (((*p_offset) + AD_TYPE_LE_ROLE_SIZE) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + // Encode LE Role. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_LE_ROLE_DATA_SIZE); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_LE_ROLE; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + switch(le_role) + { + case BLE_ADVDATA_ROLE_ONLY_PERIPH: + p_encoded_data[*p_offset] = 0; + break; + case BLE_ADVDATA_ROLE_ONLY_CENTRAL: + p_encoded_data[*p_offset] = 1; + break; + case BLE_ADVDATA_ROLE_BOTH_PERIPH_PREFERRED: + p_encoded_data[*p_offset] = 2; + break; + case BLE_ADVDATA_ROLE_BOTH_CENTRAL_PREFERRED: + p_encoded_data[*p_offset] = 3; + break; + default: + return NRF_ERROR_INVALID_PARAM; + } + *p_offset += AD_TYPE_LE_ROLE_DATA_SIZE; + + return NRF_SUCCESS; +} + +static uint32_t ble_device_addr_encode(uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + uint32_t err_code; + ble_gap_addr_t device_addr; + + // Check for buffer overflow. + if (((*p_offset) + AD_TYPE_BLE_DEVICE_ADDR_SIZE) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + // Get BLE address + err_code = sd_ble_gap_addr_get(&device_addr); + VERIFY_SUCCESS(err_code); + + // Encode LE Bluetooth Device Address + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + + AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + memcpy(&p_encoded_data[*p_offset], &device_addr.addr[0], BLE_GAP_ADDR_LEN); + *p_offset += BLE_GAP_ADDR_LEN; + if(BLE_GAP_ADDR_TYPE_PUBLIC == device_addr.addr_type) + { + p_encoded_data[*p_offset] = AD_TYPE_BLE_DEVICE_ADDR_TYPE_PUBLIC; + } + else + { + p_encoded_data[*p_offset] = AD_TYPE_BLE_DEVICE_ADDR_TYPE_RANDOM; + } + *p_offset += AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE; + + return NRF_SUCCESS; +} + +static uint32_t name_encode(const ble_advdata_t * p_advdata, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + uint32_t err_code; + uint16_t rem_adv_data_len; + uint16_t actual_length; + uint8_t adv_data_format; + + + // Validate parameters + if((BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) && (0 == p_advdata->short_name_len)) + { + return NRF_ERROR_INVALID_PARAM; + } + + // Check for buffer overflow. + if ( (((*p_offset) + ADV_AD_DATA_OFFSET) > max_size) || + ( (BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) && + (((*p_offset) + ADV_AD_DATA_OFFSET + p_advdata->short_name_len) > max_size))) + { + return NRF_ERROR_DATA_SIZE; + } + + rem_adv_data_len = max_size - (*p_offset) - ADV_AD_DATA_OFFSET; + actual_length = rem_adv_data_len; + + // Get GAP device name and length + err_code = sd_ble_gap_device_name_get(&p_encoded_data[(*p_offset) + ADV_AD_DATA_OFFSET], + &actual_length); + VERIFY_SUCCESS(err_code); + + // Check if device intend to use short name and it can fit available data size. + if ((p_advdata->name_type == BLE_ADVDATA_FULL_NAME) && (actual_length <= rem_adv_data_len)) + { + // Complete device name can fit, setting Complete Name in Adv Data. + adv_data_format = BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME; + } + else + { + // Else short name needs to be used. Or application has requested use of short name. + adv_data_format = BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME; + + // If application has set a preference on the short name size, it needs to be considered, + // else fit what can be fit. + if ((BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) && + (p_advdata->short_name_len <= rem_adv_data_len)) + { + // Short name fits available size. + actual_length = p_advdata->short_name_len; + } + // Else whatever can fit the data buffer will be packed. + else + { + actual_length = rem_adv_data_len; + } + } + + // There is only 1 byte intended to encode length which is (actual_length + ADV_AD_TYPE_FIELD_SIZE) + if(actual_length > (0x00FF - ADV_AD_TYPE_FIELD_SIZE)) + { + return NRF_ERROR_DATA_SIZE; + } + + // Complete name field in encoded data. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + actual_length); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = adv_data_format; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + *p_offset += actual_length; + + return NRF_SUCCESS; +} + + +static uint32_t appearance_encode(uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + uint32_t err_code; + uint16_t appearance; + + // Check for buffer overflow. + if (((*p_offset) + AD_TYPE_APPEARANCE_SIZE) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + // Get GAP appearance field. + err_code = sd_ble_gap_appearance_get(&appearance); + VERIFY_SUCCESS(err_code); + + // Encode Length, AD Type and Appearance. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_APPEARANCE_DATA_SIZE); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_APPEARANCE; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + *p_offset += uint16_encode(appearance, &p_encoded_data[*p_offset]); + + return NRF_SUCCESS; +} + +static uint32_t flags_encode(int8_t flags, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + // Check for buffer overflow. + if (((*p_offset) + AD_TYPE_FLAGS_SIZE) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + // Encode flags. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_FLAGS_DATA_SIZE); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_FLAGS; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + p_encoded_data[*p_offset] = flags; + *p_offset += AD_TYPE_FLAGS_DATA_SIZE; + + return NRF_SUCCESS; +} + +static uint32_t sec_mgr_oob_flags_encode(uint8_t oob_flags, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + // Check for buffer overflow. + if (((*p_offset) + AD_TYPE_OOB_FLAGS_SIZE) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + // Encode flags. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_OOB_FLAGS_DATA_SIZE); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + p_encoded_data[*p_offset] = oob_flags; + *p_offset += AD_TYPE_OOB_FLAGS_DATA_SIZE; + + return NRF_SUCCESS; +} + +static uint32_t tx_power_level_encode(int8_t tx_power_level, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + // Check for buffer overflow. + if (((*p_offset) + AD_TYPE_TX_POWER_LEVEL_SIZE) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + // Encode TX Power Level. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + + AD_TYPE_TX_POWER_LEVEL_DATA_SIZE); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_TX_POWER_LEVEL; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + p_encoded_data[*p_offset] = tx_power_level; + *p_offset += AD_TYPE_TX_POWER_LEVEL_DATA_SIZE; + + return NRF_SUCCESS; +} + + +static uint32_t uuid_list_sized_encode(const ble_advdata_uuid_list_t * p_uuid_list, + uint8_t adv_type, + uint8_t uuid_size, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + int i; + bool is_heading_written = false; + uint16_t start_pos = *p_offset; + uint16_t length; + + for (i = 0; i < p_uuid_list->uuid_cnt; i++) + { + uint32_t err_code; + uint8_t encoded_size; + ble_uuid_t uuid = p_uuid_list->p_uuids[i]; + + // Find encoded uuid size. + err_code = sd_ble_uuid_encode(&uuid, &encoded_size, NULL); + VERIFY_SUCCESS(err_code); + + // Check size. + if (encoded_size == uuid_size) + { + uint8_t heading_bytes = (is_heading_written) ? 0 : ADV_AD_DATA_OFFSET; + + // Check for buffer overflow + if (((*p_offset) + encoded_size + heading_bytes) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + if (!is_heading_written) + { + // Write AD structure heading. + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = adv_type; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + is_heading_written = true; + } + + // Write UUID. + err_code = sd_ble_uuid_encode(&uuid, &encoded_size, &p_encoded_data[*p_offset]); + VERIFY_SUCCESS(err_code); + *p_offset += encoded_size; + } + } + + if (is_heading_written) + { + // Write length. + length = (*p_offset) - (start_pos + ADV_LENGTH_FIELD_SIZE); + // There is only 1 byte intended to encode length + if(length > 0x00FF) + { + return NRF_ERROR_DATA_SIZE; + } + p_encoded_data[start_pos] = (uint8_t)length; + } + + return NRF_SUCCESS; +} + + +static uint32_t uuid_list_encode(const ble_advdata_uuid_list_t * p_uuid_list, + uint8_t adv_type_16, + uint8_t adv_type_128, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + uint32_t err_code; + + // Encode 16 bit UUIDs. + err_code = uuid_list_sized_encode(p_uuid_list, + adv_type_16, + sizeof(uint16_le_t), + p_encoded_data, + p_offset, + max_size); + VERIFY_SUCCESS(err_code); + + // Encode 128 bit UUIDs. + err_code = uuid_list_sized_encode(p_uuid_list, + adv_type_128, + sizeof(ble_uuid128_t), + p_encoded_data, + p_offset, + max_size); + VERIFY_SUCCESS(err_code); + + return NRF_SUCCESS; +} + + +static uint32_t conn_int_check(const ble_advdata_conn_int_t *p_conn_int) +{ + // Check Minimum Connection Interval. + if ((p_conn_int->min_conn_interval < 0x0006) || + ( + (p_conn_int->min_conn_interval > 0x0c80) && + (p_conn_int->min_conn_interval != 0xffff) + ) + ) + { + return NRF_ERROR_INVALID_PARAM; + } + + // Check Maximum Connection Interval. + if ((p_conn_int->max_conn_interval < 0x0006) || + ( + (p_conn_int->max_conn_interval > 0x0c80) && + (p_conn_int->max_conn_interval != 0xffff) + ) + ) + { + return NRF_ERROR_INVALID_PARAM; + } + + // Make sure Minimum Connection Interval is not bigger than Maximum Connection Interval. + if ((p_conn_int->min_conn_interval != 0xffff) && + (p_conn_int->max_conn_interval != 0xffff) && + (p_conn_int->min_conn_interval > p_conn_int->max_conn_interval) + ) + { + return NRF_ERROR_INVALID_PARAM; + } + + return NRF_SUCCESS; +} + + +static uint32_t conn_int_encode(const ble_advdata_conn_int_t * p_conn_int, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + uint32_t err_code; + + // Check for buffer overflow. + if (((*p_offset) + AD_TYPE_CONN_INT_SIZE) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + // Check parameters. + err_code = conn_int_check(p_conn_int); + VERIFY_SUCCESS(err_code); + + // Encode Length and AD Type. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_CONN_INT_DATA_SIZE); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + + // Encode Minimum and Maximum Connection Intervals. + *p_offset += uint16_encode(p_conn_int->min_conn_interval, &p_encoded_data[*p_offset]); + *p_offset += uint16_encode(p_conn_int->max_conn_interval, &p_encoded_data[*p_offset]); + + return NRF_SUCCESS; +} + + +static uint32_t manuf_specific_data_encode(const ble_advdata_manuf_data_t * p_manuf_sp_data, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + uint32_t data_size = AD_TYPE_MANUF_SPEC_DATA_ID_SIZE + p_manuf_sp_data->data.size; + + // Check for buffer overflow. + if (((*p_offset) + ADV_AD_DATA_OFFSET + data_size) > max_size) + { + return NRF_ERROR_DATA_SIZE; + } + + // There is only 1 byte intended to encode length which is (data_size + ADV_AD_TYPE_FIELD_SIZE) + if(data_size > (0x00FF - ADV_AD_TYPE_FIELD_SIZE)) + { + return NRF_ERROR_DATA_SIZE; + } + + // Encode Length and AD Type. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + data_size); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + + // Encode Company Identifier. + *p_offset += uint16_encode(p_manuf_sp_data->company_identifier, &p_encoded_data[*p_offset]); + + // Encode additional manufacturer specific data. + if (p_manuf_sp_data->data.size > 0) + { + if (p_manuf_sp_data->data.p_data == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + memcpy(&p_encoded_data[*p_offset], p_manuf_sp_data->data.p_data, p_manuf_sp_data->data.size); + *p_offset += p_manuf_sp_data->data.size; + } + + return NRF_SUCCESS; +} + +// Implemented only for 16-bit UUIDs +static uint32_t service_data_encode(const ble_advdata_t * p_advdata, + uint8_t * p_encoded_data, + uint16_t * p_offset, + uint16_t max_size) +{ + uint8_t i; + + // Check parameter consistency. + if (p_advdata->p_service_data_array == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + + for (i = 0; i < p_advdata->service_data_count; i++) + { + ble_advdata_service_data_t * p_service_data; + uint32_t data_size; + + p_service_data = &p_advdata->p_service_data_array[i]; + // For now implemented only for 16-bit UUIDs + data_size = AD_TYPE_SERV_DATA_16BIT_UUID_SIZE + p_service_data->data.size; + + // There is only 1 byte intended to encode length which is (data_size + ADV_AD_TYPE_FIELD_SIZE) + if(data_size > (0x00FF - ADV_AD_TYPE_FIELD_SIZE)) + { + return NRF_ERROR_DATA_SIZE; + } + + // Encode Length and AD Type. + p_encoded_data[*p_offset] = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + data_size); + *p_offset += ADV_LENGTH_FIELD_SIZE; + p_encoded_data[*p_offset] = BLE_GAP_AD_TYPE_SERVICE_DATA; + *p_offset += ADV_AD_TYPE_FIELD_SIZE; + + // Encode service 16-bit UUID. + *p_offset += uint16_encode(p_service_data->service_uuid, &p_encoded_data[*p_offset]); + + // Encode additional service data. + if (p_service_data->data.size > 0) + { + if (p_service_data->data.p_data == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + memcpy(&p_encoded_data[*p_offset], p_service_data->data.p_data, p_service_data->data.size); + *p_offset += p_service_data->data.size; + } + } + + return NRF_SUCCESS; +} + +uint32_t adv_data_encode(ble_advdata_t const * const p_advdata, + uint8_t * const p_encoded_data, + uint16_t * const p_len) +{ + uint32_t err_code = NRF_SUCCESS; + uint16_t max_size = *p_len; + *p_len = 0; + + //Encode Security Manager OOB Flags + if (p_advdata->p_sec_mgr_oob_flags != NULL) + { + err_code = sec_mgr_oob_flags_encode(*p_advdata->p_sec_mgr_oob_flags, + p_encoded_data, + p_len, + max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode Security Manager TK value + if (NULL != p_advdata->p_tk_value) + { + err_code = tk_value_encode(p_advdata->p_tk_value, p_encoded_data, p_len, max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode LE Role + if (BLE_ADVDATA_ROLE_NOT_PRESENT != p_advdata->le_role) + { + err_code = le_role_encode(p_advdata->le_role, p_encoded_data, p_len, max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode LE Bluetooth Device Address + if (p_advdata->include_ble_device_addr) + { + err_code = ble_device_addr_encode(p_encoded_data, p_len, max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode appearance. + if (p_advdata->include_appearance) + { + err_code = appearance_encode(p_encoded_data, p_len, max_size); + VERIFY_SUCCESS(err_code); + } + + //Encode Flags + if(p_advdata->flags != 0 ) + { + err_code = flags_encode(p_advdata->flags, p_encoded_data, p_len, max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode TX power level. + if (p_advdata->p_tx_power_level != NULL) + { + err_code = tx_power_level_encode(*p_advdata->p_tx_power_level, + p_encoded_data, + p_len, + max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode 'more available' uuid list. + if (p_advdata->uuids_more_available.uuid_cnt > 0) + { + err_code = uuid_list_encode(&p_advdata->uuids_more_available, + BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE, + BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE, + p_encoded_data, + p_len, + max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode 'complete' uuid list. + if (p_advdata->uuids_complete.uuid_cnt > 0) + { + err_code = uuid_list_encode(&p_advdata->uuids_complete, + BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE, + BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE, + p_encoded_data, + p_len, + max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode 'solicited service' uuid list. + if (p_advdata->uuids_solicited.uuid_cnt > 0) + { + err_code = uuid_list_encode(&p_advdata->uuids_solicited, + BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT, + BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT, + p_encoded_data, + p_len, + max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode Slave Connection Interval Range. + if (p_advdata->p_slave_conn_int != NULL) + { + err_code = conn_int_encode(p_advdata->p_slave_conn_int, p_encoded_data, p_len, max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode Manufacturer Specific Data. + if (p_advdata->p_manuf_specific_data != NULL) + { + err_code = manuf_specific_data_encode(p_advdata->p_manuf_specific_data, + p_encoded_data, + p_len, + max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode Service Data. + if (p_advdata->service_data_count > 0) + { + err_code = service_data_encode(p_advdata, p_encoded_data, p_len, max_size); + VERIFY_SUCCESS(err_code); + } + + // Encode name. WARNING: it is encoded last on purpose since too long device name is truncated. + if (p_advdata->name_type != BLE_ADVDATA_NO_NAME) + { + err_code = name_encode(p_advdata, p_encoded_data, p_len, max_size); + VERIFY_SUCCESS(err_code); + } + + return err_code; +} + + +static uint32_t advdata_check(const ble_advdata_t * p_advdata) +{ + // Flags must be included in advertising data, and the BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED flag must be set. + if ( + ((p_advdata->flags & BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) == 0) + ) + { + return NRF_ERROR_INVALID_PARAM; + } + + return NRF_SUCCESS; +} + + +static uint32_t srdata_check(const ble_advdata_t * p_srdata) +{ + // Flags shall not be included in the scan response data. + if (p_srdata->flags) + { + return NRF_ERROR_INVALID_PARAM; + } + + return NRF_SUCCESS; +} + + +uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata) +{ + uint32_t err_code; + uint16_t len_advdata = BLE_GAP_ADV_MAX_SIZE; + uint16_t len_srdata = BLE_GAP_ADV_MAX_SIZE; + uint8_t encoded_advdata[BLE_GAP_ADV_MAX_SIZE]; + uint8_t encoded_srdata[BLE_GAP_ADV_MAX_SIZE]; + uint8_t * p_encoded_advdata; + uint8_t * p_encoded_srdata; + + // Encode advertising data (if supplied). + if (p_advdata != NULL) + { + err_code = advdata_check(p_advdata); + VERIFY_SUCCESS(err_code); + + err_code = adv_data_encode(p_advdata, encoded_advdata, &len_advdata); + VERIFY_SUCCESS(err_code); + p_encoded_advdata = encoded_advdata; + } + else + { + p_encoded_advdata = NULL; + len_advdata = 0; + } + + // Encode scan response data (if supplied). + if (p_srdata != NULL) + { + err_code = srdata_check(p_srdata); + VERIFY_SUCCESS(err_code); + + err_code = adv_data_encode(p_srdata, encoded_srdata, &len_srdata); + VERIFY_SUCCESS(err_code); + p_encoded_srdata = encoded_srdata; + } + else + { + p_encoded_srdata = NULL; + len_srdata = 0; + } + + // Pass encoded advertising data and/or scan response data to the stack. + return sd_ble_gap_adv_data_set(p_encoded_advdata, len_advdata, p_encoded_srdata, len_srdata); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_advdata.h b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_advdata.h new file mode 100644 index 0000000..b811aff --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_advdata.h @@ -0,0 +1,212 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup ble_sdk_lib_advdata Advertising and Scan Response Data Encoder + * @{ + * @ingroup ble_sdk_lib + * @brief Functions for encoding data in the Advertising and Scan Response Data format, + * and for passing the data to the stack. + */ + +#ifndef BLE_ADVDATA_H__ +#define BLE_ADVDATA_H__ + +#include +#include +#include +#include "ble.h" +#include "app_util.h" + + +#define ADV_LENGTH_FIELD_SIZE 1UL /**< Advertising Data and Scan Response format contains 1 octet for the length. */ +#define ADV_AD_TYPE_FIELD_SIZE 1UL /**< Advertising Data and Scan Response format contains 1 octet for the AD type. */ +#define ADV_AD_DATA_OFFSET (ADV_LENGTH_FIELD_SIZE + \ + ADV_AD_TYPE_FIELD_SIZE) /**< Offset for the AD data field of the Advertising Data and Scan Response format. */ +#define AD_TYPE_TK_VALUE_DATA_SIZE (sizeof(ble_advdata_tk_value_t)) /**< Data size (in octets) of the Security Manager TK value AD type. */ +#define AD_TYPE_TK_VALUE_SIZE (ADV_AD_DATA_OFFSET + \ + AD_TYPE_TK_VALUE_DATA_SIZE) /**< Size (in octets) of the Security Manager TK value AD type. */ +#define AD_TYPE_LE_ROLE_DATA_SIZE 1UL /**< Data size (in octets) of the LE Bluetooth Device Address AD type. */ +#define AD_TYPE_LE_ROLE_SIZE (ADV_AD_DATA_OFFSET + \ + AD_TYPE_LE_ROLE_DATA_SIZE) /**< Size (in octets) of the LE Bluetooth Device Address AD type. */ +#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE 1UL /**< Data size (in octets) of the Address type of the LE Bluetooth Device Address AD type. */ +#define AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE (BLE_GAP_ADDR_LEN + \ + AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE) /**< Data size (in octets) of the LE Bluetooth Device Address AD type. */ +#define AD_TYPE_BLE_DEVICE_ADDR_SIZE (ADV_AD_DATA_OFFSET + \ + AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE) /**< Size (in octets) of the LE Bluetooth Device Address AD type. */ +#define AD_TYPE_APPEARANCE_DATA_SIZE 2UL /**< Data size (in octets) of the Appearance AD type. */ +#define AD_TYPE_APPEARANCE_SIZE (ADV_AD_DATA_OFFSET + \ + AD_TYPE_APPEARANCE_DATA_SIZE) /**< Size (in octets) of the Appearance AD type. */ +#define AD_TYPE_FLAGS_DATA_SIZE 1UL /**< Data size (in octets) of the Flags AD type. */ +#define AD_TYPE_FLAGS_SIZE (ADV_AD_DATA_OFFSET + \ + AD_TYPE_FLAGS_DATA_SIZE) /**< Size (in octets) of the Flags AD type. */ +#define AD_TYPE_TX_POWER_LEVEL_DATA_SIZE 1UL /**< Data size (in octets) of the TX Power Level AD type. */ +#define AD_TYPE_TX_POWER_LEVEL_SIZE (ADV_AD_DATA_OFFSET + \ + AD_TYPE_TX_POWER_LEVEL_DATA_SIZE) /**< Size (in octets) of the TX Power Level AD type. */ +#define AD_TYPE_CONN_INT_DATA_SIZE 4UL /**< Data size (in octets) of the Slave Connection Interval Range AD type. */ +#define AD_TYPE_CONN_INT_SIZE (ADV_AD_DATA_OFFSET + \ + AD_TYPE_CONN_INT_DATA_SIZE) /**< Data size (in octets) of the Slave Connection Interval Range AD type. */ +#define AD_TYPE_MANUF_SPEC_DATA_ID_SIZE 2UL /**< Size (in octets) of the Company Identifier Code, which is a part of the Manufacturer Specific Data AD type. */ +#define AD_TYPE_SERV_DATA_16BIT_UUID_SIZE 2UL /**< Size (in octets) of the 16-bit UUID, which is a part of the Service Data AD type. */ +#define AD_TYPE_OOB_FLAGS_DATA_SIZE 1UL /**< Data size (in octets) of the Security Manager OOB Flags AD type. */ +#define AD_TYPE_OOB_FLAGS_SIZE (ADV_AD_DATA_OFFSET + \ + AD_TYPE_OOB_FLAGS_DATA_SIZE) /**< Size (in octets) of the Security Manager OOB Flags AD type. */ + +#define AD_TYPE_SEC_MGR_OOB_FLAG_SET 1U /**< Security Manager OOB Flag set. Flag selection is done using _POS defines */ +#define AD_TYPE_SEC_MGR_OOB_FLAG_CLEAR 0U /**< Security Manager OOB Flag clear. Flag selection is done using _POS defines */ +#define AD_TYPE_SEC_MGR_OOB_FLAG_OOB_DATA_PRESENT_POS 0UL /**< Security Manager OOB Data Present Flag position. */ +#define AD_TYPE_SEC_MGR_OOB_FLAG_OOB_LE_SUPPORTED_POS 1UL /**< Security Manager OOB Low Energy Supported Flag position. */ +#define AD_TYPE_SEC_MGR_OOB_FLAG_SIM_LE_AND_EP_POS 2UL /**< Security Manager OOB Simultaneous LE and BR/EDR to Same Device Capable Flag position. */ +#define AD_TYPE_SEC_MGR_OOB_ADDRESS_TYPE_PUBLIC 0UL /**< Security Manager OOB Public Address type. */ +#define AD_TYPE_SEC_MGR_OOB_ADDRESS_TYPE_RANDOM 1UL /**< Security Manager OOB Random Address type. */ +#define AD_TYPE_SEC_MGR_OOB_FLAG_ADDRESS_TYPE_POS 3UL /**< Security Manager OOB Address type Flag (0 = Public Address, 1 = Random Address) position. */ + + +/**@brief Security Manager TK value. */ +typedef struct +{ + uint8_t tk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing TK value. */ +} ble_advdata_tk_value_t; + +/**@brief Advertising data LE Role types. This enumeration contains the options available for the LE role inside + * the advertising data. */ +typedef enum +{ + BLE_ADVDATA_ROLE_NOT_PRESENT = 0, /**< LE Role AD structure not present. */ + BLE_ADVDATA_ROLE_ONLY_PERIPH, /**< Only Peripheral Role supported. */ + BLE_ADVDATA_ROLE_ONLY_CENTRAL, /**< Only Central Role supported. */ + BLE_ADVDATA_ROLE_BOTH_PERIPH_PREFERRED, /**< Peripheral and Central Role supported. Peripheral Role preferred for connection establishment. */ + BLE_ADVDATA_ROLE_BOTH_CENTRAL_PREFERRED /**< Peripheral and Central Role supported. Central Role preferred for connection establishment */ +} ble_advdata_le_role_t; + +/**@brief Advertising data name type. This enumeration contains the options available for the device name inside + * the advertising data. */ +typedef enum +{ + BLE_ADVDATA_NO_NAME, /**< Include no device name in advertising data. */ + BLE_ADVDATA_SHORT_NAME, /**< Include short device name in advertising data. */ + BLE_ADVDATA_FULL_NAME /**< Include full device name in advertising data. */ +} ble_advdata_name_type_t; + +/**@brief UUID list type. */ +typedef struct +{ + uint16_t uuid_cnt; /**< Number of UUID entries. */ + ble_uuid_t * p_uuids; /**< Pointer to UUID array entries. */ +} ble_advdata_uuid_list_t; + +/**@brief Connection interval range structure. */ +typedef struct +{ + uint16_t min_conn_interval; /**< Minimum connection interval, in units of 1.25 ms, range 6 to 3200 (7.5 ms to 4 s). */ + uint16_t max_conn_interval; /**< Maximum connection interval, in units of 1.25 ms, range 6 to 3200 (7.5 ms to 4 s). The value 0xFFFF indicates no specific maximum. */ +} ble_advdata_conn_int_t; + +/**@brief Manufacturer specific data structure. */ +typedef struct +{ + uint16_t company_identifier; /**< Company identifier code. */ + uint8_array_t data; /**< Additional manufacturer specific data. */ +} ble_advdata_manuf_data_t; + +/**@brief Service data structure. */ +typedef struct +{ + uint16_t service_uuid; /**< Service UUID. */ + uint8_array_t data; /**< Additional service data. */ +} ble_advdata_service_data_t; + +/**@brief Advertising data structure. This structure contains all options and data needed for encoding and + * setting the advertising data. */ +typedef struct +{ + ble_advdata_name_type_t name_type; /**< Type of device name. */ + uint8_t short_name_len; /**< Length of short device name (if short type is specified). */ + bool include_appearance; /**< Determines if Appearance shall be included. */ + uint8_t flags; /**< Advertising data Flags field. */ + int8_t * p_tx_power_level; /**< TX Power Level field. */ + ble_advdata_uuid_list_t uuids_more_available; /**< List of UUIDs in the 'More Available' list. */ + ble_advdata_uuid_list_t uuids_complete; /**< List of UUIDs in the 'Complete' list. */ + ble_advdata_uuid_list_t uuids_solicited; /**< List of solicited UUIDs. */ + ble_advdata_conn_int_t * p_slave_conn_int; /**< Slave Connection Interval Range. */ + ble_advdata_manuf_data_t * p_manuf_specific_data; /**< Manufacturer specific data. */ + ble_advdata_service_data_t * p_service_data_array; /**< Array of Service data structures. */ + uint8_t service_data_count; /**< Number of Service data structures. */ + bool include_ble_device_addr; /**< Determines if LE Bluetooth Device Address shall be included. */ + ble_advdata_le_role_t le_role; /**< LE Role field. Included when different from @ref BLE_ADVDATA_ROLE_NOT_PRESENT. @warning This field can be used only for NFC. For BLE advertising, set it to NULL. */ + ble_advdata_tk_value_t * p_tk_value; /**< Security Manager TK value field. Included when different from NULL. @warning This field can be used only for NFC. For BLE advertising, set it to NULL.*/ + uint8_t * p_sec_mgr_oob_flags; /**< Security Manager Out Of Band Flags field. Included when different from NULL. @warning This field can be used only for NFC. For BLE advertising, set it to NULL.*/ +} ble_advdata_t; + +/**@brief Function for encoding data in the Advertising and Scan Response data format + * (AD structures). + * + * @details This function encodes data into the Advertising and Scan Response data format + * (AD structures) based on the selections in the supplied structures. This function can be used to + * create a payload of Advertising packet or Scan Response packet, or a payload of NFC + * message intended for initiating the Out-of-Band pairing. + * + * @param[in] p_advdata Pointer to the structure for specifying the content of encoded data. + * @param[out] p_encoded_data Pointer to the buffer where encoded data will be returned. + * @param[in,out] p_len \c in: Size of \p p_encoded_data buffer. + * \c out: Length of encoded data. + * + * @retval NRF_SUCCESS If the operation was successful. + * @retval NRF_ERROR_INVALID_PARAM If the operation failed because a wrong parameter was provided in \p p_advdata. + * @retval NRF_ERROR_DATA_SIZE If the operation failed because not all the requested data could fit into the + * provided buffer or some encoded AD structure is too long and its + * length cannot be encoded with one octet. + * + * @warning This API may override the application's request to use the long name and use a short name + * instead. This truncation will occur in case the long name does not fit the provided buffer size. + * The application can specify a preferred short name length if truncation is required. + * For example, if the complete device name is ABCD_HRMonitor, the application can specify the short name + * length to be 8, so that the short device name appears as ABCD_HRM instead of ABCD_HRMo or ABCD_HRMoni + * if the available size for the short name is 9 or 12 respectively, to have a more appropriate short name. + * However, it should be noted that this is just a preference that the application can specify, and + * if the preference is too large to fit in the provided buffer, the name can be truncated further. + */ +uint32_t adv_data_encode(ble_advdata_t const * const p_advdata, + uint8_t * const p_encoded_data, + uint16_t * const p_len); + +/**@brief Function for encoding and setting the advertising data and/or scan response data. + * + * @details This function encodes advertising data and/or scan response data based on the selections + * in the supplied structures, and passes the encoded data to the stack. + * + * @param[in] p_advdata Structure for specifying the content of the advertising data. + * Set to NULL if advertising data is not to be set. + * @param[in] p_srdata Structure for specifying the content of the scan response data. + * Set to NULL if scan response data is not to be set. + * + * @retval NRF_SUCCESS If the operation was successful. + * @retval NRF_ERROR_INVALID_PARAM If the operation failed because a wrong parameter was provided in \p p_advdata. + * @retval NRF_ERROR_DATA_SIZE If the operation failed because not all the requested data could fit into the + * advertising packet. The maximum size of the advertisement packet + * is @ref BLE_GAP_ADV_MAX_SIZE. + * + * @warning This API may override the application's request to use the long name and use a short name + * instead. This truncation will occur in case the long name does not fit the provided buffer size. + * The application can specify a preferred short name length if truncation is required. + * For example, if the complete device name is ABCD_HRMonitor, the application can specify the short name + * length to be 8, so that the short device name appears as ABCD_HRM instead of ABCD_HRMo or ABCD_HRMoni + * if the available size for the short name is 9 or 12 respectively, to have a more appropriate short name. + * However, it should be noted that this is just a preference that the application can specify, and + * if the preference is too large to fit in the provided buffer, the name can be truncated further. + */ +uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata); + +#endif // BLE_ADVDATA_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_conn_params.c b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_conn_params.c new file mode 100644 index 0000000..676706d --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_conn_params.c @@ -0,0 +1,323 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "ble_conn_params.h" +#include +#include "nordic_common.h" +#include "ble_hci.h" +#include "app_timer.h" +#include "ble_srv_common.h" +#include "app_util.h" + + +static ble_conn_params_init_t m_conn_params_config; /**< Configuration as specified by the application. */ +static ble_gap_conn_params_t m_preferred_conn_params; /**< Connection parameters preferred by the application. */ +static uint8_t m_update_count; /**< Number of Connection Parameter Update messages that has currently been sent. */ +static uint16_t m_conn_handle; /**< Current connection handle. */ +static ble_gap_conn_params_t m_current_conn_params; /**< Connection parameters received in the most recent Connect event. */ +APP_TIMER_DEF(m_conn_params_timer_id); /**< Connection parameters timer. */ + +static bool m_change_param = false; + +static bool is_conn_params_ok(ble_gap_conn_params_t * p_conn_params) +{ + // Check if interval is within the acceptable range. + // NOTE: Using max_conn_interval in the received event data because this contains + // the client's connection interval. + if ( + (p_conn_params->max_conn_interval >= m_preferred_conn_params.min_conn_interval) + && + (p_conn_params->max_conn_interval <= m_preferred_conn_params.max_conn_interval) + ) + { + return true; + } + else + { + return false; + } +} + + +static void update_timeout_handler(void * p_context) +{ + UNUSED_PARAMETER(p_context); + + if (m_conn_handle != BLE_CONN_HANDLE_INVALID) + { + // Check if we have reached the maximum number of attempts + m_update_count++; + if (m_update_count <= m_conn_params_config.max_conn_params_update_count) + { + uint32_t err_code; + + // Parameters are not ok, send connection parameters update request. + err_code = sd_ble_gap_conn_param_update(m_conn_handle, &m_preferred_conn_params); + if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL)) + { + m_conn_params_config.error_handler(err_code); + } + } + else + { + m_update_count = 0; + + // Negotiation failed, disconnect automatically if this has been configured + if (m_conn_params_config.disconnect_on_fail) + { + uint32_t err_code; + + err_code = sd_ble_gap_disconnect(m_conn_handle, BLE_HCI_CONN_INTERVAL_UNACCEPTABLE); + if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL)) + { + m_conn_params_config.error_handler(err_code); + } + } + + // Notify the application that the procedure has failed + if (m_conn_params_config.evt_handler != NULL) + { + ble_conn_params_evt_t evt; + + evt.evt_type = BLE_CONN_PARAMS_EVT_FAILED; + m_conn_params_config.evt_handler(&evt); + } + } + } +} + + +uint32_t ble_conn_params_init(const ble_conn_params_init_t * p_init) +{ + uint32_t err_code; + + m_conn_params_config = *p_init; + m_change_param = false; + if (p_init->p_conn_params != NULL) + { + m_preferred_conn_params = *p_init->p_conn_params; + + // Set the connection params in stack + err_code = sd_ble_gap_ppcp_set(&m_preferred_conn_params); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + else + { + // Fetch the connection params from stack + err_code = sd_ble_gap_ppcp_get(&m_preferred_conn_params); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + } + + m_conn_handle = BLE_CONN_HANDLE_INVALID; + m_update_count = 0; + + return app_timer_create(&m_conn_params_timer_id, + APP_TIMER_MODE_SINGLE_SHOT, + update_timeout_handler); +} + + +uint32_t ble_conn_params_stop(void) +{ + return app_timer_stop(m_conn_params_timer_id); +} + + +static void conn_params_negotiation(void) +{ + // Start negotiation if the received connection parameters are not acceptable + if (!is_conn_params_ok(&m_current_conn_params)) + { + uint32_t err_code; + uint32_t timeout_ticks; + + if (m_change_param) + { + // Notify the application that the procedure has failed + if (m_conn_params_config.evt_handler != NULL) + { + ble_conn_params_evt_t evt; + + evt.evt_type = BLE_CONN_PARAMS_EVT_FAILED; + m_conn_params_config.evt_handler(&evt); + } + } + else + { + if (m_update_count == 0) + { + // First connection parameter update + timeout_ticks = m_conn_params_config.first_conn_params_update_delay; + } + else + { + timeout_ticks = m_conn_params_config.next_conn_params_update_delay; + } + + err_code = app_timer_start(m_conn_params_timer_id, timeout_ticks, NULL); + if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL)) + { + m_conn_params_config.error_handler(err_code); + } + } + } + else + { + // Notify the application that the procedure has succeded + if (m_conn_params_config.evt_handler != NULL) + { + ble_conn_params_evt_t evt; + + evt.evt_type = BLE_CONN_PARAMS_EVT_SUCCEEDED; + m_conn_params_config.evt_handler(&evt); + } + } + m_change_param = false; +} + + +static void on_connect(ble_evt_t * p_ble_evt) +{ + // Save connection parameters + m_conn_handle = p_ble_evt->evt.gap_evt.conn_handle; + m_current_conn_params = p_ble_evt->evt.gap_evt.params.connected.conn_params; + m_update_count = 0; // Connection parameter negotiation should re-start every connection + + // Check if we shall handle negotiation on connect + if (m_conn_params_config.start_on_notify_cccd_handle == BLE_GATT_HANDLE_INVALID) + { + conn_params_negotiation(); + } +} + + +static void on_disconnect(ble_evt_t * p_ble_evt) +{ + uint32_t err_code; + + m_conn_handle = BLE_CONN_HANDLE_INVALID; + + // Stop timer if running + m_update_count = 0; // Connection parameters updates should happen during every connection + + err_code = app_timer_stop(m_conn_params_timer_id); + if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL)) + { + m_conn_params_config.error_handler(err_code); + } +} + + +static void on_write(ble_evt_t * p_ble_evt) +{ + ble_gatts_evt_write_t * p_evt_write = &p_ble_evt->evt.gatts_evt.params.write; + + // Check if this the correct CCCD + if ( + (p_evt_write->handle == m_conn_params_config.start_on_notify_cccd_handle) + && + (p_evt_write->len == 2) + ) + { + // Check if this is a 'start notification' + if (ble_srv_is_notification_enabled(p_evt_write->data)) + { + // Do connection parameter negotiation if necessary + conn_params_negotiation(); + } + else + { + uint32_t err_code; + + // Stop timer if running + err_code = app_timer_stop(m_conn_params_timer_id); + if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL)) + { + m_conn_params_config.error_handler(err_code); + } + } + } +} + + +static void on_conn_params_update(ble_evt_t * p_ble_evt) +{ + // Copy the parameters + m_current_conn_params = p_ble_evt->evt.gap_evt.params.conn_param_update.conn_params; + + conn_params_negotiation(); +} + + +void ble_conn_params_on_ble_evt(ble_evt_t * p_ble_evt) +{ + switch (p_ble_evt->header.evt_id) + { + case BLE_GAP_EVT_CONNECTED: + on_connect(p_ble_evt); + break; + + case BLE_GAP_EVT_DISCONNECTED: + on_disconnect(p_ble_evt); + break; + + case BLE_GATTS_EVT_WRITE: + on_write(p_ble_evt); + break; + + case BLE_GAP_EVT_CONN_PARAM_UPDATE: + on_conn_params_update(p_ble_evt); + break; + + default: + // No implementation needed. + break; + } +} + + +uint32_t ble_conn_params_change_conn_params(ble_gap_conn_params_t * new_params) +{ + uint32_t err_code; + + m_preferred_conn_params = *new_params; + // Set the connection params in stack + err_code = sd_ble_gap_ppcp_set(&m_preferred_conn_params); + if (err_code == NRF_SUCCESS) + { + if (!is_conn_params_ok(&m_current_conn_params)) + { + m_change_param = true; + err_code = sd_ble_gap_conn_param_update(m_conn_handle, &m_preferred_conn_params); + m_update_count = 1; + } + else + { + // Notify the application that the procedure has succeded + if (m_conn_params_config.evt_handler != NULL) + { + ble_conn_params_evt_t evt; + + evt.evt_type = BLE_CONN_PARAMS_EVT_SUCCEEDED; + m_conn_params_config.evt_handler(&evt); + } + err_code = NRF_SUCCESS; + } + } + return err_code; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_conn_params.h b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_conn_params.h new file mode 100644 index 0000000..2659443 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_conn_params.h @@ -0,0 +1,111 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup ble_sdk_lib_conn_params Connection Parameters Negotiation + * @{ + * @ingroup ble_sdk_lib + * @brief Module for initiating and executing a connection parameters negotiation procedure. + */ + +#ifndef BLE_CONN_PARAMS_H__ +#define BLE_CONN_PARAMS_H__ + +#include +#include "ble.h" +#include "ble_srv_common.h" + +/**@brief Connection Parameters Module event type. */ +typedef enum +{ + BLE_CONN_PARAMS_EVT_FAILED , /**< Negotiation procedure failed. */ + BLE_CONN_PARAMS_EVT_SUCCEEDED /**< Negotiation procedure succeeded. */ +} ble_conn_params_evt_type_t; + +/**@brief Connection Parameters Module event. */ +typedef struct +{ + ble_conn_params_evt_type_t evt_type; /**< Type of event. */ +} ble_conn_params_evt_t; + +/**@brief Connection Parameters Module event handler type. */ +typedef void (*ble_conn_params_evt_handler_t) (ble_conn_params_evt_t * p_evt); + +/**@brief Connection Parameters Module init structure. This contains all options and data needed for + * initialization of the connection parameters negotiation module. */ +typedef struct +{ + ble_gap_conn_params_t * p_conn_params; /**< Pointer to the connection parameters desired by the application. When calling ble_conn_params_init, if this parameter is set to NULL, the connection parameters will be fetched from host. */ + uint32_t first_conn_params_update_delay; /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (in number of timer ticks). */ + uint32_t next_conn_params_update_delay; /**< Time between each call to sd_ble_gap_conn_param_update after the first (in number of timer ticks). Recommended value 30 seconds as per BLUETOOTH SPECIFICATION Version 4.0. */ + uint8_t max_conn_params_update_count; /**< Number of attempts before giving up the negotiation. */ + uint16_t start_on_notify_cccd_handle; /**< If procedure is to be started when notification is started, set this to the handle of the corresponding CCCD. Set to BLE_GATT_HANDLE_INVALID if procedure is to be started on connect event. */ + bool disconnect_on_fail; /**< Set to TRUE if a failed connection parameters update shall cause an automatic disconnection, set to FALSE otherwise. */ + ble_conn_params_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Connection Parameters. */ + ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */ +} ble_conn_params_init_t; + + +/**@brief Function for initializing the Connection Parameters module. + * + * @note If the negotiation procedure should be triggered when notification/indication of + * any characteristic is enabled by the peer, then this function must be called after + * having initialized the services. + * + * @param[in] p_init This contains information needed to initialize this module. + * + * @return NRF_SUCCESS on successful initialization, otherwise an error code. + */ +uint32_t ble_conn_params_init(const ble_conn_params_init_t * p_init); + +/**@brief Function for stopping the Connection Parameters module. + * + * @details This function is intended to be used by the application to clean up the connection + * parameters update module. This will stop the connection parameters update timer if + * running, thereby preventing any impending connection parameters update procedure. This + * function must be called by the application when it needs to clean itself up (for + * example, before disabling the bluetooth SoftDevice) so that an unwanted timer expiry + * event can be avoided. + * + * @return NRF_SUCCESS on successful initialization, otherwise an error code. + */ +uint32_t ble_conn_params_stop(void); + +/**@brief Function for changing the current connection parameters to a new set. + * + * @details Use this function to change the connection parameters to a new set of parameter + * (ie different from the ones given at init of the module). + * This function is usefull for scenario where most of the time the application + * needs a relatively big connection interval, and just sometimes, for a temporary + * period requires shorter connection interval, for example to transfer a higher + * amount of data. + * If the given parameters does not match the current connection's parameters + * this function initiates a new negotiation. + * + * @param[in] new_params This contains the new connections parameters to setup. + * + * @return NRF_SUCCESS on successful initialization, otherwise an error code. + */ +uint32_t ble_conn_params_change_conn_params(ble_gap_conn_params_t *new_params); + +/**@brief Function for handling the Application's BLE Stack events. + * + * @details Handles all events from the BLE stack that are of interest to this module. + * + * @param[in] p_ble_evt The event received from the BLE stack. + */ +void ble_conn_params_on_ble_evt(ble_evt_t * p_ble_evt); + +#endif // BLE_CONN_PARAMS_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.c b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.c new file mode 100644 index 0000000..c239cf1 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.c @@ -0,0 +1,197 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/* Attention! +* To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile +* qualification listings, this section of source code must not be modified. +*/ + +#include "ble_srv_common.h" +#include +#include "nordic_common.h" +#include "app_error.h" +#include "ble.h" + +uint8_t ble_srv_report_ref_encode(uint8_t * p_encoded_buffer, + const ble_srv_report_ref_t * p_report_ref) +{ + uint8_t len = 0; + + p_encoded_buffer[len++] = p_report_ref->report_id; + p_encoded_buffer[len++] = p_report_ref->report_type; + + APP_ERROR_CHECK_BOOL(len == BLE_SRV_ENCODED_REPORT_REF_LEN); + return len; +} + + +void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii) +{ + p_utf8->length = (uint16_t)strlen(p_ascii); + p_utf8->p_str = (uint8_t *)p_ascii; +} + + +/**@brief Function for setting security requirements of a characteristic. + * + * @param[in] level required security level. + * @param[out] p_perm Characteristic security requirements. + * + * @return encoded security level and security mode. + */ +static inline void set_security_req(security_req_t level, ble_gap_conn_sec_mode_t * p_perm) +{ + + + BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm); + switch (level) + { + case SEC_NO_ACCESS: + BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm); + break; + case SEC_OPEN: + BLE_GAP_CONN_SEC_MODE_SET_OPEN(p_perm); + break; + case SEC_JUST_WORKS: + BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(p_perm); + break; + case SEC_MITM: + BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(p_perm); + break; + case SEC_SIGNED: + BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(p_perm); + break; + case SEC_SIGNED_MITM: + BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(p_perm); + break; + } + return; +} + + +uint32_t characteristic_add(uint16_t service_handle, + ble_add_char_params_t * p_char_props, + ble_gatts_char_handles_t * p_char_handle) +{ + ble_gatts_char_md_t char_md; + ble_gatts_attr_t attr_char_value; + ble_uuid_t char_uuid; + ble_gatts_attr_md_t attr_md; + ble_gatts_attr_md_t user_descr_attr_md; + ble_gatts_attr_md_t cccd_md; + + if (p_char_props->uuid_type == 0) + { + char_uuid.type = BLE_UUID_TYPE_BLE; + } + else + { + char_uuid.type = p_char_props->uuid_type; + } + char_uuid.uuid = p_char_props->uuid; + + memset(&attr_md, 0, sizeof(ble_gatts_attr_md_t)); + set_security_req(p_char_props->read_access, &attr_md.read_perm); + set_security_req(p_char_props->write_access, & attr_md.write_perm); + attr_md.rd_auth = (p_char_props->is_defered_read ? 1 : 0); + attr_md.wr_auth = (p_char_props->is_defered_write ? 1 : 0); + attr_md.vlen = (p_char_props->is_var_len ? 1 : 0); + attr_md.vloc = (p_char_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK); + + + memset(&char_md, 0, sizeof(ble_gatts_char_md_t)); + if ((p_char_props->char_props.notify == 1)||(p_char_props->char_props.indicate == 1)) + { + + memset(&cccd_md, 0, sizeof(cccd_md)); + set_security_req(p_char_props->cccd_write_access, &cccd_md.write_perm); + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm); + + cccd_md.vloc = BLE_GATTS_VLOC_STACK; + + char_md.p_cccd_md = &cccd_md; + } + char_md.char_props = p_char_props->char_props; + + memset(&attr_char_value, 0, sizeof(ble_gatts_attr_t)); + attr_char_value.p_uuid = &char_uuid; + attr_char_value.p_attr_md = &attr_md; + attr_char_value.max_len = p_char_props->max_len; + if (p_char_props->p_init_value != NULL) + { + attr_char_value.init_len = p_char_props->init_len; + attr_char_value.p_value = p_char_props->p_init_value; + } + if (p_char_props->p_user_descr != NULL) + { + memset(&user_descr_attr_md, 0, sizeof(ble_gatts_attr_md_t)); + char_md.char_user_desc_max_size = p_char_props->p_user_descr->max_size; + char_md.char_user_desc_size = p_char_props->p_user_descr->size; + char_md.p_char_user_desc = p_char_props->p_user_descr->p_char_user_desc; + + char_md.p_user_desc_md = &user_descr_attr_md; + + set_security_req(p_char_props->p_user_descr->read_access, &user_descr_attr_md.read_perm); + set_security_req(p_char_props->p_user_descr->write_access, &user_descr_attr_md.write_perm); + + user_descr_attr_md.rd_auth = (p_char_props->p_user_descr->is_defered_read ? 1 : 0); + user_descr_attr_md.wr_auth = (p_char_props->p_user_descr->is_defered_write ? 1 : 0); + user_descr_attr_md.vlen = (p_char_props->p_user_descr->is_var_len ? 1 : 0); + user_descr_attr_md.vloc = (p_char_props->p_user_descr->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK); + } + if (p_char_props->p_presentation_format != NULL) + { + char_md.p_char_pf = p_char_props->p_presentation_format; + } + return sd_ble_gatts_characteristic_add(service_handle, + &char_md, + &attr_char_value, + p_char_handle); +} + + +uint32_t descriptor_add(uint16_t char_handle, + ble_add_descr_params_t * p_descr_props, + uint16_t * p_descr_handle) +{ + ble_gatts_attr_t descr_params; + ble_uuid_t desc_uuid; + ble_gatts_attr_md_t attr_md; + + memset(&descr_params, 0, sizeof(descr_params)); + if (p_descr_props->uuid_type == 0) + { + desc_uuid.type = BLE_UUID_TYPE_BLE; + } + else + { + desc_uuid.type = p_descr_props->uuid_type; + } + desc_uuid.uuid = p_descr_props->uuid; + descr_params.p_uuid = &desc_uuid; + + set_security_req(p_descr_props->read_access, &attr_md.read_perm); + set_security_req(p_descr_props->write_access,&attr_md.write_perm); + + attr_md.rd_auth = (p_descr_props->is_defered_read ? 1 : 0); + attr_md.wr_auth = (p_descr_props->is_defered_write ? 1 : 0); + attr_md.vlen = (p_descr_props->is_var_len ? 1 : 0); + attr_md.vloc = (p_descr_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK); + descr_params.p_attr_md = &attr_md; + + descr_params.init_len = p_descr_props->init_len; + descr_params.init_offs = p_descr_props->init_offs; + descr_params.max_len = p_descr_props->max_len; + descr_params.p_value = p_descr_props->p_value; + + return sd_ble_gatts_descriptor_add(char_handle, &descr_params, p_descr_handle); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.h b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.h new file mode 100644 index 0000000..291038c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/ble/common/ble_srv_common.h @@ -0,0 +1,367 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup ble_sdk_srv_common Common service definitions + * @{ + * @ingroup ble_sdk_srv + * @brief Constants, type definitions, and functions that are common to all services. + */ + +#ifndef BLE_SRV_COMMON_H__ +#define BLE_SRV_COMMON_H__ + +#include +#include +#include "ble_types.h" +#include "app_util.h" +#include "ble.h" +#include "ble_gap.h" +#include "ble_gatt.h" + +/** @defgroup UUID_SERVICES Service UUID definitions + * @{ */ +#define BLE_UUID_ALERT_NOTIFICATION_SERVICE 0x1811 /**< Alert Notification service UUID. */ +#define BLE_UUID_BATTERY_SERVICE 0x180F /**< Battery service UUID. */ +#define BLE_UUID_BLOOD_PRESSURE_SERVICE 0x1810 /**< Blood Pressure service UUID. */ +#define BLE_UUID_CURRENT_TIME_SERVICE 0x1805 /**< Current Time service UUID. */ +#define BLE_UUID_CYCLING_SPEED_AND_CADENCE 0x1816 /**< Cycling Speed and Cadence service UUID. */ +#define BLE_UUID_LOCATION_AND_NAVIGATION_SERVICE 0x1819 /**< Location and Navigation service UUID. */ +#define BLE_UUID_DEVICE_INFORMATION_SERVICE 0x180A /**< Device Information service UUID. */ +#define BLE_UUID_GLUCOSE_SERVICE 0x1808 /**< Glucose service UUID. */ +#define BLE_UUID_HEALTH_THERMOMETER_SERVICE 0x1809 /**< Health Thermometer service UUID. */ +#define BLE_UUID_HEART_RATE_SERVICE 0x180D /**< Heart Rate service UUID. */ +#define BLE_UUID_HUMAN_INTERFACE_DEVICE_SERVICE 0x1812 /**< Human Interface Device service UUID. */ +#define BLE_UUID_IMMEDIATE_ALERT_SERVICE 0x1802 /**< Immediate Alert service UUID. */ +#define BLE_UUID_LINK_LOSS_SERVICE 0x1803 /**< Link Loss service UUID. */ +#define BLE_UUID_NEXT_DST_CHANGE_SERVICE 0x1807 /**< Next Dst Change service UUID. */ +#define BLE_UUID_PHONE_ALERT_STATUS_SERVICE 0x180E /**< Phone Alert Status service UUID. */ +#define BLE_UUID_REFERENCE_TIME_UPDATE_SERVICE 0x1806 /**< Reference Time Update service UUID. */ +#define BLE_UUID_RUNNING_SPEED_AND_CADENCE 0x1814 /**< Running Speed and Cadence service UUID. */ +#define BLE_UUID_SCAN_PARAMETERS_SERVICE 0x1813 /**< Scan Parameters service UUID. */ +#define BLE_UUID_TX_POWER_SERVICE 0x1804 /**< TX Power service UUID. */ +#define BLE_UUID_IPSP_SERVICE 0x1820 /**< Internet Protocol Support service UUID. */ +#define BLE_UUID_BMS_SERVICE 0x181E /**< BOND MANAGEMENT service UUID*/ +#define BLE_UUID_CGM_SERVICE 0x181F /**< Contiunous Glucose Monitoring service UUID*/ +#define BLE_UUID_PLX_SERVICE 0x1822 /**< Pulse Oximeter Service UUID*/ + + +/** @} */ + +/** @defgroup UUID_CHARACTERISTICS Characteristic UUID definitions + * @{ */ +#define BLE_UUID_REMOVABLE_CHAR 0x2A3A /**< Removable characteristic UUID. */ +#define BLE_UUID_SERVICE_REQUIRED_CHAR 0x2A3B /**< Service Required characteristic UUID. */ +#define BLE_UUID_ALERT_CATEGORY_ID_CHAR 0x2A43 /**< Alert Category Id characteristic UUID. */ +#define BLE_UUID_ALERT_CATEGORY_ID_BIT_MASK_CHAR 0x2A42 /**< Alert Category Id Bit Mask characteristic UUID. */ +#define BLE_UUID_ALERT_LEVEL_CHAR 0x2A06 /**< Alert Level characteristic UUID. */ +#define BLE_UUID_ALERT_NOTIFICATION_CONTROL_POINT_CHAR 0x2A44 /**< Alert Notification Control Point characteristic UUID. */ +#define BLE_UUID_ALERT_STATUS_CHAR 0x2A3F /**< Alert Status characteristic UUID. */ +#define BLE_UUID_BATTERY_LEVEL_CHAR 0x2A19 /**< Battery Level characteristic UUID. */ +#define BLE_UUID_BLOOD_PRESSURE_FEATURE_CHAR 0x2A49 /**< Blood Pressure Feature characteristic UUID. */ +#define BLE_UUID_BLOOD_PRESSURE_MEASUREMENT_CHAR 0x2A35 /**< Blood Pressure Measurement characteristic UUID. */ +#define BLE_UUID_BODY_SENSOR_LOCATION_CHAR 0x2A38 /**< Body Sensor Location characteristic UUID. */ +#define BLE_UUID_BOOT_KEYBOARD_INPUT_REPORT_CHAR 0x2A22 /**< Boot Keyboard Input Report characteristic UUID. */ +#define BLE_UUID_BOOT_KEYBOARD_OUTPUT_REPORT_CHAR 0x2A32 /**< Boot Keyboard Output Report characteristic UUID. */ +#define BLE_UUID_BOOT_MOUSE_INPUT_REPORT_CHAR 0x2A33 /**< Boot Mouse Input Report characteristic UUID. */ +#define BLE_UUID_CURRENT_TIME_CHAR 0x2A2B /**< Current Time characteristic UUID. */ +#define BLE_UUID_DATE_TIME_CHAR 0x2A08 /**< Date Time characteristic UUID. */ +#define BLE_UUID_DAY_DATE_TIME_CHAR 0x2A0A /**< Day Date Time characteristic UUID. */ +#define BLE_UUID_DAY_OF_WEEK_CHAR 0x2A09 /**< Day Of Week characteristic UUID. */ +#define BLE_UUID_DST_OFFSET_CHAR 0x2A0D /**< Dst Offset characteristic UUID. */ +#define BLE_UUID_EXACT_TIME_256_CHAR 0x2A0C /**< Exact Time 256 characteristic UUID. */ +#define BLE_UUID_FIRMWARE_REVISION_STRING_CHAR 0x2A26 /**< Firmware Revision String characteristic UUID. */ +#define BLE_UUID_GLUCOSE_FEATURE_CHAR 0x2A51 /**< Glucose Feature characteristic UUID. */ +#define BLE_UUID_GLUCOSE_MEASUREMENT_CHAR 0x2A18 /**< Glucose Measurement characteristic UUID. */ +#define BLE_UUID_GLUCOSE_MEASUREMENT_CONTEXT_CHAR 0x2A34 /**< Glucose Measurement Context characteristic UUID. */ +#define BLE_UUID_HARDWARE_REVISION_STRING_CHAR 0x2A27 /**< Hardware Revision String characteristic UUID. */ +#define BLE_UUID_HEART_RATE_CONTROL_POINT_CHAR 0x2A39 /**< Heart Rate Control Point characteristic UUID. */ +#define BLE_UUID_HEART_RATE_MEASUREMENT_CHAR 0x2A37 /**< Heart Rate Measurement characteristic UUID. */ +#define BLE_UUID_HID_CONTROL_POINT_CHAR 0x2A4C /**< Hid Control Point characteristic UUID. */ +#define BLE_UUID_HID_INFORMATION_CHAR 0x2A4A /**< Hid Information characteristic UUID. */ +#define BLE_UUID_IEEE_REGULATORY_CERTIFICATION_DATA_LIST_CHAR 0x2A2A /**< IEEE Regulatory Certification Data List characteristic UUID. */ +#define BLE_UUID_INTERMEDIATE_CUFF_PRESSURE_CHAR 0x2A36 /**< Intermediate Cuff Pressure characteristic UUID. */ +#define BLE_UUID_INTERMEDIATE_TEMPERATURE_CHAR 0x2A1E /**< Intermediate Temperature characteristic UUID. */ +#define BLE_UUID_LOCAL_TIME_INFORMATION_CHAR 0x2A0F /**< Local Time Information characteristic UUID. */ +#define BLE_UUID_MANUFACTURER_NAME_STRING_CHAR 0x2A29 /**< Manufacturer Name String characteristic UUID. */ +#define BLE_UUID_MEASUREMENT_INTERVAL_CHAR 0x2A21 /**< Measurement Interval characteristic UUID. */ +#define BLE_UUID_MODEL_NUMBER_STRING_CHAR 0x2A24 /**< Model Number String characteristic UUID. */ +#define BLE_UUID_UNREAD_ALERT_CHAR 0x2A45 /**< Unread Alert characteristic UUID. */ +#define BLE_UUID_NEW_ALERT_CHAR 0x2A46 /**< New Alert characteristic UUID. */ +#define BLE_UUID_PNP_ID_CHAR 0x2A50 /**< PNP Id characteristic UUID. */ +#define BLE_UUID_PROTOCOL_MODE_CHAR 0x2A4E /**< Protocol Mode characteristic UUID. */ +#define BLE_UUID_RECORD_ACCESS_CONTROL_POINT_CHAR 0x2A52 /**< Record Access Control Point characteristic UUID. */ +#define BLE_UUID_REFERENCE_TIME_INFORMATION_CHAR 0x2A14 /**< Reference Time Information characteristic UUID. */ +#define BLE_UUID_REPORT_CHAR 0x2A4D /**< Report characteristic UUID. */ +#define BLE_UUID_REPORT_MAP_CHAR 0x2A4B /**< Report Map characteristic UUID. */ +#define BLE_UUID_RINGER_CONTROL_POINT_CHAR 0x2A40 /**< Ringer Control Point characteristic UUID. */ +#define BLE_UUID_RINGER_SETTING_CHAR 0x2A41 /**< Ringer Setting characteristic UUID. */ +#define BLE_UUID_SCAN_INTERVAL_WINDOW_CHAR 0x2A4F /**< Scan Interval Window characteristic UUID. */ +#define BLE_UUID_SCAN_REFRESH_CHAR 0x2A31 /**< Scan Refresh characteristic UUID. */ +#define BLE_UUID_SERIAL_NUMBER_STRING_CHAR 0x2A25 /**< Serial Number String characteristic UUID. */ +#define BLE_UUID_SOFTWARE_REVISION_STRING_CHAR 0x2A28 /**< Software Revision String characteristic UUID. */ +#define BLE_UUID_SUPPORTED_NEW_ALERT_CATEGORY_CHAR 0x2A47 /**< Supported New Alert Category characteristic UUID. */ +#define BLE_UUID_SUPPORTED_UNREAD_ALERT_CATEGORY_CHAR 0x2A48 /**< Supported Unread Alert Category characteristic UUID. */ +#define BLE_UUID_SYSTEM_ID_CHAR 0x2A23 /**< System Id characteristic UUID. */ +#define BLE_UUID_TEMPERATURE_MEASUREMENT_CHAR 0x2A1C /**< Temperature Measurement characteristic UUID. */ +#define BLE_UUID_TEMPERATURE_TYPE_CHAR 0x2A1D /**< Temperature Type characteristic UUID. */ +#define BLE_UUID_TIME_ACCURACY_CHAR 0x2A12 /**< Time Accuracy characteristic UUID. */ +#define BLE_UUID_TIME_SOURCE_CHAR 0x2A13 /**< Time Source characteristic UUID. */ +#define BLE_UUID_TIME_UPDATE_CONTROL_POINT_CHAR 0x2A16 /**< Time Update Control Point characteristic UUID. */ +#define BLE_UUID_TIME_UPDATE_STATE_CHAR 0x2A17 /**< Time Update State characteristic UUID. */ +#define BLE_UUID_TIME_WITH_DST_CHAR 0x2A11 /**< Time With Dst characteristic UUID. */ +#define BLE_UUID_TIME_ZONE_CHAR 0x2A0E /**< Time Zone characteristic UUID. */ +#define BLE_UUID_TX_POWER_LEVEL_CHAR 0x2A07 /**< TX Power Level characteristic UUID. */ +#define BLE_UUID_CSC_FEATURE_CHAR 0x2A5C /**< Cycling Speed and Cadence Feature characteristic UUID. */ +#define BLE_UUID_CSC_MEASUREMENT_CHAR 0x2A5B /**< Cycling Speed and Cadence Measurement characteristic UUID. */ +#define BLE_UUID_RSC_FEATURE_CHAR 0x2A54 /**< Running Speed and Cadence Feature characteristic UUID. */ +#define BLE_UUID_SC_CTRLPT_CHAR 0x2A55 /**< Speed and Cadence Control Point UUID. */ +#define BLE_UUID_RSC_MEASUREMENT_CHAR 0x2A53 /**< Running Speed and Cadence Measurement characteristic UUID. */ +#define BLE_UUID_SENSOR_LOCATION_CHAR 0x2A5D /**< Sensor Location characteristic UUID. */ +#define BLE_UUID_EXTERNAL_REPORT_REF_DESCR 0x2907 /**< External Report Reference descriptor UUID. */ +#define BLE_UUID_REPORT_REF_DESCR 0x2908 /**< Report Reference descriptor UUID. */ +#define BLE_UUID_LN_FEATURE_CHAR 0x2A6A /**< Location Navigation Service, Feature characteristic UUID. */ +#define BLE_UUID_LN_POSITION_QUALITY_CHAR 0x2A69 /**< Location Navigation Service, Position quality UUID. */ +#define BLE_UUID_LN_LOCATION_AND_SPEED_CHAR 0x2A67 /**< Location Navigation Service, Location and Speed characteristic UUID. */ +#define BLE_UUID_LN_NAVIGATION_CHAR 0x2A68 /**< Location Navigation Service, Navigation characteristic UUID. */ +#define BLE_UUID_LN_CONTROL_POINT_CHAR 0x2A6B /**< Location Navigation Service, Control point characteristic UUID. */ +#define BLE_UUID_BMS_CTRLPT 0x2AA4 /**< BMS Control Point characteristic UUID. */ +#define BLE_UUID_BMS_FEATURE 0x2AA5 /**< BMS Feature characteristic UUID. */ +#define BLE_UUID_CGM_MEASUREMENT 0x2AA7 /**< CGM Service, Measurement characteristic UUID*/ +#define BLE_UUID_CGM_FEATURE 0x2AA8 /**< CGM Service, Feature characteristic UUID*/ +#define BLE_UUID_CGM_STATUS 0x2AA9 /**< CGM Service, Status characteristic UUID*/ +#define BLE_UUID_CGM_SESSION_START_TIME 0x2AAA /**< CGM Service, session start time characteristic UUID*/ +#define BLE_UUID_CGM_SESSION_RUN_TIME 0x2AAB /**< CGM Service, session run time characteristic UUID*/ +#define BLE_UUID_CGM_SPECIFIC_OPS_CTRLPT 0x2AAC /**< CGM Service, specific ops ctrlpt characteristic UUID*/ +#define BLE_UUID_PLX_SPOT_CHECK_MEAS 0x2A5E /**< PLX Service, spot check measurement characteristic UUID*/ +#define BLE_UUID_PLX_CONTINUOUS_MEAS 0x2A5F /**< PLX Service, continuous measurement characteristic UUID*/ +#define BLE_UUID_PLX_FEATURES 0x2A60 /**< PLX Service, feature characteristic UUID*/ + + + + + +/** @} */ + +/** @defgroup ALERT_LEVEL_VALUES Definitions for the Alert Level characteristic values + * @{ */ +#define BLE_CHAR_ALERT_LEVEL_NO_ALERT 0x00 /**< No Alert. */ +#define BLE_CHAR_ALERT_LEVEL_MILD_ALERT 0x01 /**< Mild Alert. */ +#define BLE_CHAR_ALERT_LEVEL_HIGH_ALERT 0x02 /**< High Alert. */ +/** @} */ + +#define BLE_SRV_ENCODED_REPORT_REF_LEN 2 /**< The length of an encoded Report Reference Descriptor. */ +#define BLE_CCCD_VALUE_LEN 2 /**< The length of a CCCD value. */ + +/**@brief Type definition for error handler function that will be called in case of an error in + * a service or a service library module. */ +typedef void (*ble_srv_error_handler_t) (uint32_t nrf_error); + + + +/**@brief Value of a Report Reference descriptor. + * + * @details This is mapping information that maps the parent characteristic to the Report ID(s) and + * Report Type(s) defined within a Report Map characteristic. + */ +typedef struct +{ + uint8_t report_id; /**< Non-zero value if there is more than one instance of the same Report Type */ + uint8_t report_type; /**< Type of Report characteristic (see @ref BLE_HIDS_REPORT_TYPE) */ +} ble_srv_report_ref_t; + +/**@brief UTF-8 string data type. + * + * @note The type can only hold a pointer to the string data (i.e. not the actual data). + */ +typedef struct +{ + uint16_t length; /**< String length. */ + uint8_t * p_str; /**< String data. */ +} ble_srv_utf8_str_t; + + +/**@brief Security settings structure. + * @details This structure contains the security options needed during initialization of the + * service. + */ +typedef struct +{ + ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ +} ble_srv_security_mode_t; + +/**@brief Security settings structure. + * @details This structure contains the security options needed during initialization of the + * service. It can be used when the characteristics contains a CCCD. + */ +typedef struct +{ + ble_gap_conn_sec_mode_t cccd_write_perm; /**< Write permissions for Client Characteristic Configuration Descriptor. */ + ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ +} ble_srv_cccd_security_mode_t; + +/**@brief Function for decoding a CCCD value, and then testing if notification is + * enabled. + * + * @param[in] p_encoded_data Buffer where the encoded CCCD is stored. + * + * @retval TRUE If notification is enabled. + * @retval FALSE Otherwise. + */ +static __INLINE bool ble_srv_is_notification_enabled(uint8_t const * p_encoded_data) +{ + uint16_t cccd_value = uint16_decode(p_encoded_data); + return ((cccd_value & BLE_GATT_HVX_NOTIFICATION) != 0); +} + +/**@brief Function for decoding a CCCD value, and then testing if indication is + * enabled. + * + * @param[in] p_encoded_data Buffer where the encoded CCCD is stored. + * + * @retval TRUE If indication is enabled. + * @retval FALSE Otherwise. + */ +static __INLINE bool ble_srv_is_indication_enabled(uint8_t const * p_encoded_data) +{ + uint16_t cccd_value = uint16_decode(p_encoded_data); + return ((cccd_value & BLE_GATT_HVX_INDICATION) != 0); +} + +/**@brief Function for encoding a Report Reference Descriptor. + * + * @param[in] p_encoded_buffer The buffer of the encoded data. + * @param[in] p_report_ref Report Reference value to be encoded. + * + * @return Length of the encoded data. + */ +uint8_t ble_srv_report_ref_encode(uint8_t * p_encoded_buffer, + const ble_srv_report_ref_t * p_report_ref); + +/**@brief Function for making a UTF-8 structure refer to an ASCII string. + * + * @param[out] p_utf8 UTF-8 structure to be set. + * @param[in] p_ascii ASCII string to be referred to. + */ +void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii); + + +/**@brief Security Access enumeration. + * @details This enumeration gives the possible requirements for accessing a characteristic value. + */ +typedef enum +{ + SEC_NO_ACCESS = 0, /**< Not possible to access. */ + SEC_OPEN = 1, /**< Access open. */ + SEC_JUST_WORKS = 2, /**< Access possible with 'Just Works' security at least. */ + SEC_MITM = 3, /**< Access possible with 'MITM' security at least. */ + SEC_SIGNED = 4, /**< Access possible with 'signed' security at least. */ + SEC_SIGNED_MITM = 5 /**< Access possible with 'signed and MITM' security at least. */ +}security_req_t; + + +/**@brief Characteristic User Descriptor parameters. + * @details This structure contains the parameters for User Descriptor. + */ +typedef struct +{ + uint16_t max_size; /**< Maximum size of the user descriptor*/ + uint16_t size; /**< Size of the user descriptor*/ + uint8_t *p_char_user_desc; /**< User descriptor content, pointer to a UTF-8 encoded string (non-NULL terminated)*/ + bool is_var_len; /**< Indicates if the user descriptor has variable length.*/ + ble_gatt_char_props_t char_props; /**< user descriptor properties.*/ + bool is_defered_read; /**< Indicate if deferred read operations are supported.*/ + bool is_defered_write; /**< Indicate if deferred write operations are supported.*/ + security_req_t read_access; /**< Security requirement for reading the user descriptor.*/ + security_req_t write_access; /**< Security requirement for writing the user descriptor.*/ + bool is_value_user; /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/ +}ble_add_char_user_desc_t; + + +/**@brief Add characteristic parameters structure. + * @details This structure contains the parameters needed to use the @ref characteristic_add function. + */ +typedef struct +{ + uint16_t uuid; /**< Characteristic UUID (16 bits UUIDs).*/ + uint8_t uuid_type; /**< Base UUID. If 0, the Bluetooth SIG UUID will be used. Otherwise, this should be a value returned by @ref sd_ble_uuid_vs_add when adding the base UUID.*/ + uint16_t max_len; /**< Maximum length of the characteristic value.*/ + uint16_t init_len; /**< Initial length of the characteristic value.*/ + uint8_t * p_init_value; /**< Initial encoded value of the characteristic.*/ + bool is_var_len; /**< Indicates if the characteristic value has variable length.*/ + ble_gatt_char_props_t char_props; /**< Characteristic properties.*/ + bool is_defered_read; /**< Indicate if deferred read operations are supported.*/ + bool is_defered_write; /**< Indicate if deferred write operations are supported.*/ + security_req_t read_access; /**< Security requirement for reading the characteristic value.*/ + security_req_t write_access; /**< Security requirement for writing the characteristic value.*/ + security_req_t cccd_write_access; /**< Security requirement for writing the characteristic's CCCD.*/ + bool is_value_user; /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/ + ble_add_char_user_desc_t *p_user_descr; /**< Pointer to user descriptor if needed*/ + ble_gatts_char_pf_t *p_presentation_format; /**< Pointer to characteristic format if needed*/ +} ble_add_char_params_t; + + +/**@brief Add descriptor parameters structure. + * @details This structure contains the parameters needed to use the @ref descriptor_add function. + */ +typedef struct +{ + uint16_t uuid; /**< descriptor UUID (16 bits UUIDs).*/ + uint8_t uuid_type; /**< Base UUID. If 0, the Bluetooth SIG UUID will be used. Otherwise, this should be a value returned by @ref sd_ble_uuid_vs_add when adding the base UUID.*/ + bool is_defered_read; /**< Indicate if deferred read operations are supported.*/ + bool is_defered_write; /**< Indicate if deferred write operations are supported.*/ + bool is_var_len; /**< Indicates if the descriptor value has variable length.*/ + security_req_t read_access; /**< Security requirement for reading the descriptor value.*/ + security_req_t write_access; /**< Security requirement for writing the descriptor value.*/ + bool is_value_user; /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/ + uint16_t init_len; /**< Initial descriptor value length in bytes. */ + uint16_t init_offs; /**< Initial descriptor value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ + uint16_t max_len; /**< Maximum descriptor value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ + uint8_t* p_value; /**< Pointer to the value of the descriptor*/ +} ble_add_descr_params_t; + + +/**@brief Function for adding a characteristic to a given service. + * + * If no pointer is given for the initial value, + * the initial length parameter will be ignored and the initial length will be 0. + * + * @param[in] service_handle Handle of the service to which the characteristic is to be added. + * @param[in] p_char_props Information needed to add the characteristic. + * @param[out] p_char_handle Handle of the added characteristic. + * + * @retval NRF_SUCCESS If the characteristic was added successfully. Otherwise, an error code is returned. + */ +uint32_t characteristic_add(uint16_t service_handle, + ble_add_char_params_t * p_char_props, + ble_gatts_char_handles_t * p_char_handle); + + +/**@brief Function for adding a characteristic's descriptor to a given characteristic. + * + * @param[in] char_handle Handle of the characteristic to which the descriptor is to be added, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] p_descr_props Information needed to add the descriptor. + * @param[out] p_descr_handle Handle of the added descriptor. + * + * @retval NRF_SUCCESS If the characteristic was added successfully. Otherwise, an error code is returned. + */ +uint32_t descriptor_add(uint16_t char_handle, + ble_add_descr_params_t * p_descr_props, + uint16_t * p_descr_handle); + + +#endif // BLE_SRV_COMMON_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h b/nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h new file mode 100644 index 0000000..6a41e8e --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h @@ -0,0 +1,126 @@ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef _COMPILER_ABSTRACTION_H +#define _COMPILER_ABSTRACTION_H + +/*lint ++flb "Enter library region" */ + +#if defined ( __CC_ARM ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + #define GET_SP() __current_sp() + +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + /* Not defined for IAR since it requires a new line to work, and C preprocessor does not allow that. */ + #ifndef __ALIGN + #define __ALIGN(n) + #endif + + #define GET_SP() __get_SP() + +#elif defined ( __GNUC__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #define GET_SP() gcc_current_sp() + + static inline unsigned int gcc_current_sp(void) + { + register unsigned sp __ASM("sp"); + return sp; + } + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + #define GET_SP() __get_MSP() + +#endif + +/*lint --flb "Leave library region" */ + +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h new file mode 100644 index 0000000..adbb763 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h @@ -0,0 +1,66 @@ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_H +#define NRF_H + +/* MDK version */ +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 5 +#define MDK_MICRO_VERSION 0 + +#if defined(_WIN32) + /* Do not include nrf51 specific files when building for PC host */ +//#elif defined(__unix) + /* Do not include nrf51 specific files when building for PC host */ +#elif defined(__APPLE__) + /* Do not include nrf51 specific files when building for PC host */ +#else + + /* Family selection for family includes. */ + #if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + #elif defined (NRF52) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" + #else + #error "Device family must be defined. See nrf.h." + #endif /* NRF51, NRF52 */ + + #include "compiler_abstraction.h" + +#endif /* _WIN32 || __unix || __APPLE__ */ + +#endif /* NRF_H */ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h new file mode 100644 index 0000000..16ae6f7 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h @@ -0,0 +1,935 @@ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF51_TO_NRF52_H +#define NRF51_TO_NRF52_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not define, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#define UART0_IRQHandler UARTE0_UART0_IRQHandler +#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define ADC_IRQHandler SAADC_IRQHandler +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#define SWI5_IRQHandler SWI5_EGU5_IRQHandler + +#define UART0_IRQn UARTE0_UART0_IRQn +#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#define ADC_IRQn SAADC_IRQn +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define SWI0_IRQn SWI0_EGU0_IRQn +#define SWI1_IRQn SWI1_EGU1_IRQn +#define SWI2_IRQn SWI2_EGU2_IRQn +#define SWI3_IRQn SWI3_EGU3_IRQn +#define SWI4_IRQn SWI4_EGU4_IRQn +#define SWI5_IRQn SWI5_EGU5_IRQn + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#define RBPCONF APPROTECT + +#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled + + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#define NRF_GPIO NRF_P0 +#define NRF_GPIO_BASE NRF_P0_BASE + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#define PSELSCK PSEL.SCK +#define PSELMISO PSEL.MISO +#define PSELMOSI PSEL.MOSI +#define PSELCSN PSEL.CSN + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#define RXDPTR RXD.PTR +#define MAXRX RXD.MAXCNT +#define AMOUNTRX RXD.AMOUNT + +#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#define TXDPTR TXD.PTR +#define MAXTX TXD.MAXCNT +#define AMOUNTTX TXD.AMOUNT + +#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk + + +/* MPU */ +/* Part of MPU module was renamed BPROT, while the rest was eliminated. */ +#define NRF_MPU NRF_BPROT + +/* Register DISABLEINDEBUG macros were affected. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled + +/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ +#define PROTENSET0 CONFIG0 +#define PROTENSET1 CONFIG1 + +#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos +#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk +#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled +#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled +#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled + +#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos +#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk +#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled +#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled +#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled + +#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos +#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk +#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled +#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled +#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled + +#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos +#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk +#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled +#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled +#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled + +#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos +#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk +#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled +#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled +#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled + +#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos +#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk +#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled +#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled +#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled + +#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos +#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk +#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled +#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled +#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled + +#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos +#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk +#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled +#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled +#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled + +#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos +#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk +#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled +#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled +#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled + +#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos +#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk +#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled +#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled +#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled + +#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos +#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk +#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled +#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled +#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled + +#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos +#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk +#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled +#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled +#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled + +#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos +#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk +#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled +#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled +#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled + +#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos +#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk +#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled +#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled +#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled + +#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos +#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk +#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled +#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled +#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled + +#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos +#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk +#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled +#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled +#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled + +#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos +#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk +#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled +#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled +#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled + +#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos +#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk +#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled +#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled +#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled + +#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos +#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk +#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled +#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled +#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled + +#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos +#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk +#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled +#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled +#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled + +#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos +#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk +#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled +#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled +#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled + +#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos +#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk +#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled +#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled +#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled + +#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos +#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk +#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled +#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled +#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled + +#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos +#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk +#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled +#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled +#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled + +#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos +#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk +#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled +#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled +#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled + +#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos +#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk +#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled +#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled +#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled + +#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos +#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk +#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled +#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled +#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled + +#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos +#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk +#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled +#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled +#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled + +#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos +#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk +#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled +#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled +#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled + +#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos +#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk +#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled +#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled +#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled + +#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos +#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk +#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled +#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled +#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled + +#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos +#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk +#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled +#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled +#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled + +#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos +#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk +#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled +#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled +#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled + +#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos +#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk +#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled +#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled +#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled + +#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos +#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk +#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled +#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled +#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled + +#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos +#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk +#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled +#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled +#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled + +#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos +#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk +#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled +#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled +#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled + +#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos +#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk +#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled +#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled +#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled + +#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos +#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk +#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled +#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled +#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled + +#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos +#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk +#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled +#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled +#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled + +#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos +#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk +#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled +#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled +#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled + +#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos +#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk +#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled +#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled +#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled + +#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos +#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk +#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled +#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled +#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled + +#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos +#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk +#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled +#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled +#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled + +#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos +#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk +#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled +#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled +#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled + +#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos +#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk +#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled +#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled +#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled + +#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos +#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk +#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled +#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled +#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled + +#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos +#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk +#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled +#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled +#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled + +#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos +#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk +#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled +#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled +#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled + +#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos +#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk +#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled +#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled +#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled + +#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos +#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk +#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled +#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled +#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled + +#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos +#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk +#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled +#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled +#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled + +#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos +#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk +#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled +#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled +#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled + +#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos +#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk +#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled +#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled +#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled + +#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos +#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk +#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled +#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled +#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled + +#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos +#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk +#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled +#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled +#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled + +#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos +#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk +#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled +#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled +#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled + +#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos +#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk +#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled +#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled +#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled + +#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos +#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk +#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled +#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled +#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled + +#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos +#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk +#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled +#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled +#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled + +#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos +#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk +#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled +#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled +#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled + +#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos +#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk +#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled +#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled +#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled + +#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos +#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk +#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled +#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled +#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled + +#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos +#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk +#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled +#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled +#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled + + +/* From nrf51_deprecated.h */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* IRQ */ +/* COMP module was eliminated. Adapted to nrf52 headers. */ +#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn + + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52_H */ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h new file mode 100644 index 0000000..412ecef --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h @@ -0,0 +1,2125 @@ + +/****************************************************************************************************//** + * @file nrf52.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * nrf52 from Nordic Semiconductor. + * + * @version V1 + * @date 23. February 2016 + * + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nrf52.svd' Version 1, + * + * @par Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + +/** @addtogroup nrf52 + * @{ + */ + +#ifndef NRF52_H +#define NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ---------------------- nrf52 Specific Interrupt Numbers ---------------------- */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38 /*!< 38 FPU */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_nrf52.h" /*!< nrf52 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + +typedef struct { + __I uint32_t PART; /*!< Part code */ + __I uint32_t VARIANT; /*!< Part Variant, Hardware version and Production configuration */ + __I uint32_t PACKAGE; /*!< Package option */ + __I uint32_t RAM; /*!< RAM variant */ + __I uint32_t FLASH; /*!< Flash variant */ + __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */ +} FICR_INFO_Type; + +typedef struct { + __I uint32_t A0; /*!< Slope definition A0. */ + __I uint32_t A1; /*!< Slope definition A1. */ + __I uint32_t A2; /*!< Slope definition A2. */ + __I uint32_t A3; /*!< Slope definition A3. */ + __I uint32_t A4; /*!< Slope definition A4. */ + __I uint32_t A5; /*!< Slope definition A5. */ + __I uint32_t B0; /*!< y-intercept B0. */ + __I uint32_t B1; /*!< y-intercept B1. */ + __I uint32_t B2; /*!< y-intercept B2. */ + __I uint32_t B3; /*!< y-intercept B3. */ + __I uint32_t B4; /*!< y-intercept B4. */ + __I uint32_t B5; /*!< y-intercept B5. */ + __I uint32_t T0; /*!< Segment end T0. */ + __I uint32_t T1; /*!< Segment end T1. */ + __I uint32_t T2; /*!< Segment end T2. */ + __I uint32_t T3; /*!< Segment end T3. */ + __I uint32_t T4; /*!< Segment end T4. */ +} FICR_TEMP_Type; + +typedef struct { + __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; + +typedef struct { + __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */ + __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */ + __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */ + __I uint32_t RESERVED0; +} POWER_RAM_Type; + +typedef struct { + __IO uint32_t CPU0; /*!< AHB bus master priority register for CPU0 */ + __IO uint32_t SPIS1; /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and + TWIS1 */ + __IO uint32_t RADIO; /*!< AHB bus master priority register for RADIO */ + __IO uint32_t ECB; /*!< AHB bus master priority register for ECB */ + __IO uint32_t CCM; /*!< AHB bus master priority register for CCM */ + __IO uint32_t AAR; /*!< AHB bus master priority register for AAR */ + __IO uint32_t SAADC; /*!< AHB bus master priority register for SAADC */ + __IO uint32_t UARTE; /*!< AHB bus master priority register for UARTE */ + __IO uint32_t SERIAL0; /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and + TWIS0 */ + __IO uint32_t SERIAL2; /*!< AHB bus master priority register for SPIM2 and SPIS2 */ + __IO uint32_t NFCT; /*!< AHB bus master priority register for NFCT */ + __IO uint32_t I2S; /*!< AHB bus master priority register for I2S */ + __IO uint32_t PDM; /*!< AHB bus master priority register for PDM */ + __IO uint32_t PWM; /*!< AHB bus master priority register for PWM0, PWM1 and PWM2 */ +} AMLI_RAMPRI_Type; + +typedef struct { + __IO uint32_t RTS; /*!< Pin select for RTS signal */ + __IO uint32_t TXD; /*!< Pin select for TXD signal */ + __IO uint32_t CTS; /*!< Pin select for CTS signal */ + __IO uint32_t RXD; /*!< Pin select for RXD signal */ +} UARTE_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ +} SPIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_TXD_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t CSN; /*!< Pin select for CSN signal */ +} SPIS_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< RXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< TXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; + +typedef struct { + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_TXD_Type; + +typedef struct { + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIS_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< RXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< TXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI */ + __IO uint32_t MISO; /*!< Pin select for MISO */ +} SPI_PSEL_Type; + +typedef struct { + __IO uint32_t RX; /*!< Result of last incoming frames */ +} NFCT_FRAMESTATUS_Type; + +typedef struct { + __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */ + __IO uint32_t AMOUNT; /*!< Size of outgoing frame */ +} NFCT_TXD_Type; + +typedef struct { + __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */ + __I uint32_t AMOUNT; /*!< Size of last incoming frame */ +} NFCT_RXD_Type; + +typedef struct { + __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */ + __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; + +typedef struct { + __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */ + __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */ + __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */ + __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring + a channel */ +} SAADC_CH_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */ + __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */ +} SAADC_RESULT_Type; + +typedef struct { + __IO uint32_t LED; /*!< Pin select for LED signal */ + __IO uint32_t A; /*!< Pin select for A signal */ + __IO uint32_t B; /*!< Pin select for B signal */ +} QDEC_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence + A */ + __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence + A */ + __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between + samples loaded to compare register (load every CNT+1 PWM periods) */ + __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */ + __I uint32_t RESERVED1[4]; +} PWM_SEQ_Type; + +typedef struct { + __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel + 0 */ +} PWM_PSEL_Type; + +typedef struct { + __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */ + __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */ + __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */ +} PDM_SAMPLE_Type; + +typedef struct { + __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */ + __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */ +} PPI_TASKS_CHG_Type; + +typedef struct { + __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */ + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_CH_Type; + +typedef struct { + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_FORK_Type; + +typedef struct { + __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */ +} MWU_EVENTS_REGION_Type; + +typedef struct { + __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0 + detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */ +} MWU_EVENTS_PREGION_Type; + +typedef struct { + __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, write access detected while corresponding subregion was enabled + for watching */ + __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, read access detected while corresponding subregion was enabled + for watching */ +} MWU_PERREGION_Type; + +typedef struct { + __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */ + __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */ + __I uint32_t RESERVED2[2]; +} MWU_REGION_Type; + +typedef struct { + __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */ + __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */ + __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */ + __I uint32_t RESERVED3; +} MWU_PREGION_Type; + +typedef struct { + __IO uint32_t MODE; /*!< I2S mode. */ + __IO uint32_t RXEN; /*!< Reception (RX) enable. */ + __IO uint32_t TXEN; /*!< Transmission (TX) enable. */ + __IO uint32_t MCKEN; /*!< Master clock generator enable. */ + __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */ + __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */ + __IO uint32_t SWIDTH; /*!< Sample width. */ + __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */ + __IO uint32_t FORMAT; /*!< Frame format. */ + __IO uint32_t CHANNELS; /*!< Enable channels. */ +} I2S_CONFIG_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Receive buffer RAM start address. */ +} I2S_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */ +} I2S_TXD_Type; + +typedef struct { + __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; + +typedef struct { + __IO uint32_t MCK; /*!< Pin select for MCK signal. */ + __IO uint32_t SCK; /*!< Pin select for SCK signal. */ + __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */ + __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */ + __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */ +} I2S_PSEL_Type; + + +/* ================================================================================ */ +/* ================ FICR ================ */ +/* ================================================================================ */ + + +/** + * @brief Factory Information Configuration Registers (FICR) + */ + +typedef struct { /*!< FICR Structure */ + __I uint32_t RESERVED0[4]; + __I uint32_t CODEPAGESIZE; /*!< Code memory page size */ + __I uint32_t CODESIZE; /*!< Code memory size */ + __I uint32_t RESERVED1[18]; + __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */ + __I uint32_t RESERVED2[6]; + __I uint32_t ER[4]; /*!< Description collection[0]: Encryption Root, word 0 */ + __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */ + __I uint32_t DEVICEADDRTYPE; /*!< Device address type */ + __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */ + __I uint32_t RESERVED3[21]; + FICR_INFO_Type INFO; /*!< Device info */ + __I uint32_t RESERVED4[185]; + FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */ + __I uint32_t RESERVED5[2]; + FICR_NFC_Type NFC; /*!< Unspecified */ +} NRF_FICR_Type; + + +/* ================================================================================ */ +/* ================ UICR ================ */ +/* ================================================================================ */ + + +/** + * @brief User Information Configuration Registers (UICR) + */ + +typedef struct { /*!< UICR Structure */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t UNUSED1; /*!< Unspecified */ + __IO uint32_t UNUSED2; /*!< Unspecified */ + __I uint32_t RESERVED0; + __IO uint32_t UNUSED3; /*!< Unspecified */ + __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */ + __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */ + __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */ + __I uint32_t RESERVED1[64]; + __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function (see + POWER chapter for details) */ + __IO uint32_t APPROTECT; /*!< Access Port protection */ + __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna + or GPIO */ +} NRF_UICR_Type; + + +/* ================================================================================ */ +/* ================ BPROT ================ */ +/* ================================================================================ */ + + +/** + * @brief Block Protect (BPROT) + */ + +typedef struct { /*!< BPROT Structure */ + __I uint32_t RESERVED0[384]; + __IO uint32_t CONFIG0; /*!< Block protect configuration register 0 */ + __IO uint32_t CONFIG1; /*!< Block protect configuration register 1 */ + __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug interface mode */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t CONFIG2; /*!< Block protect configuration register 2 */ + __IO uint32_t CONFIG3; /*!< Block protect configuration register 3 */ +} NRF_BPROT_Type; + + +/* ================================================================================ */ +/* ================ POWER ================ */ +/* ================================================================================ */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< POWER Structure */ + __I uint32_t RESERVED0[30]; + __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */ + __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */ + __I uint32_t RESERVED1[34]; + __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */ + __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */ + __I uint32_t RESERVED3[122]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[61]; + __IO uint32_t RESETREAS; /*!< Reset reason */ + __I uint32_t RESERVED5[9]; + __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */ + __I uint32_t RESERVED6[53]; + __O uint32_t SYSTEMOFF; /*!< System OFF register */ + __I uint32_t RESERVED7[3]; + __IO uint32_t POFCON; /*!< Power failure comparator configuration */ + __I uint32_t RESERVED8[2]; + __IO uint32_t GPREGRET; /*!< General purpose retention register */ + __IO uint32_t GPREGRET2; /*!< General purpose retention register */ + __IO uint32_t RAMON; /*!< Deprecated register - RAM on/off register (this register is + retained) */ + __I uint32_t RESERVED9[11]; + __IO uint32_t RAMONB; /*!< Deprecated register - RAM on/off register (this register is + retained) */ + __I uint32_t RESERVED10[8]; + __IO uint32_t DCDCEN; /*!< DC/DC enable register */ + __I uint32_t RESERVED11[225]; + POWER_RAM_Type RAM[8]; /*!< Unspecified */ +} NRF_POWER_Type; + + +/* ================================================================================ */ +/* ================ CLOCK ================ */ +/* ================================================================================ */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< CLOCK Structure */ + __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */ + __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */ + __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */ + __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */ + __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC oscillator */ + __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ + __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ + __I uint32_t RESERVED0[57]; + __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */ + __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ + __I uint32_t RESERVED1; + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ + __I uint32_t RESERVED2[124]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ + __I uint32_t HFCLKSTAT; /*!< HFCLK status */ + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ + __I uint32_t LFCLKSTAT; /*!< LFCLK status */ + __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + __I uint32_t RESERVED5[62]; + __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ + __I uint32_t RESERVED6[7]; + __IO uint32_t CTIV; /*!< Calibration timer interval (retained register, same reset behaviour + as RESETREAS) */ + __I uint32_t RESERVED7[8]; + __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */ +} NRF_CLOCK_Type; + + +/* ================================================================================ */ +/* ================ AMLI ================ */ +/* ================================================================================ */ + + +/** + * @brief AHB Multi-Layer Interface (AMLI) + */ + +typedef struct { /*!< AMLI Structure */ + __I uint32_t RESERVED0[896]; + AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure */ +} NRF_AMLI_Type; + + +/* ================================================================================ */ +/* ================ RADIO ================ */ +/* ================================================================================ */ + + +/** + * @brief 2.4 GHz Radio (RADIO) + */ + +typedef struct { /*!< RADIO Structure */ + __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */ + __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */ + __O uint32_t TASKS_START; /*!< Start RADIO */ + __O uint32_t TASKS_STOP; /*!< Stop RADIO */ + __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */ + __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal + strength. */ + __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */ + __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */ + __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */ + __I uint32_t RESERVED0[55]; + __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */ + __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */ + __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */ + __IO uint32_t EVENTS_END; /*!< Packet sent or received */ + __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */ + __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */ + __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */ + __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */ + __I uint32_t RESERVED2; + __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */ + __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */ + __I uint32_t RESERVED3[50]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED4[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[61]; + __I uint32_t CRCSTATUS; /*!< CRC status */ + __I uint32_t RESERVED6; + __I uint32_t RXMATCH; /*!< Received address */ + __I uint32_t RXCRC; /*!< CRC field of previously received packet */ + __I uint32_t DAI; /*!< Device address match index */ + __I uint32_t RESERVED7[60]; + __IO uint32_t PACKETPTR; /*!< Packet pointer */ + __IO uint32_t FREQUENCY; /*!< Frequency */ + __IO uint32_t TXPOWER; /*!< Output power */ + __IO uint32_t MODE; /*!< Data rate and modulation */ + __IO uint32_t PCNF0; /*!< Packet configuration register 0 */ + __IO uint32_t PCNF1; /*!< Packet configuration register 1 */ + __IO uint32_t BASE0; /*!< Base address 0 */ + __IO uint32_t BASE1; /*!< Base address 1 */ + __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */ + __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */ + __IO uint32_t TXADDRESS; /*!< Transmit address select */ + __IO uint32_t RXADDRESSES; /*!< Receive address select */ + __IO uint32_t CRCCNF; /*!< CRC configuration */ + __IO uint32_t CRCPOLY; /*!< CRC polynomial */ + __IO uint32_t CRCINIT; /*!< CRC initial value */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */ + __I uint32_t RSSISAMPLE; /*!< RSSI sample */ + __I uint32_t RESERVED8; + __I uint32_t STATE; /*!< Current radio state */ + __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */ + __I uint32_t RESERVED9[2]; + __IO uint32_t BCC; /*!< Bit counter compare */ + __I uint32_t RESERVED10[39]; + __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */ + __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */ + __IO uint32_t DACNF; /*!< Device address match configuration */ + __I uint32_t RESERVED11[3]; + __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */ + __I uint32_t RESERVED12[618]; + __IO uint32_t POWER; /*!< Peripheral power control */ +} NRF_RADIO_Type; + + +/* ================================================================================ */ +/* ================ UARTE ================ */ +/* ================================================================================ */ + + +/** + * @brief UART with EasyDMA (UARTE) + */ + +typedef struct { /*!< UARTE Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[7]; + __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */ + __I uint32_t RESERVED1[52]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */ + __I uint32_t RESERVED3[3]; + __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */ + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */ + __I uint32_t RESERVED6; + __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */ + __I uint32_t RESERVED7[41]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[93]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED10[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED11; + UARTE_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[3]; + __IO uint32_t BAUDRATE; /*!< Baud rate */ + __I uint32_t RESERVED13[3]; + UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED14; + UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED15[7]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; + + +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART) + */ + +typedef struct { /*!< UART Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ + __I uint32_t RESERVED1[56]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ + __I uint32_t RESERVED2[4]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ + __I uint32_t RESERVED3; + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5[46]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED6[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED7[93]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED8[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED9; + __IO uint32_t PSELRTS; /*!< Pin select for RTS */ + __IO uint32_t PSELTXD; /*!< Pin select for TXD */ + __IO uint32_t PSELCTS; /*!< Pin select for CTS */ + __IO uint32_t PSELRXD; /*!< Pin select for RXD */ + __I uint32_t RXD; /*!< RXD register */ + __O uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED10; + __IO uint32_t BAUDRATE; /*!< Baud rate */ + __I uint32_t RESERVED11[17]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UART_Type; + + +/* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM) + */ + +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */ + __I uint32_t RESERVED6[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started */ + __I uint32_t RESERVED7[44]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[125]; + __IO uint32_t ENABLE; /*!< Enable SPIM */ + __I uint32_t RESERVED10; + SPIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED11[4]; + __IO uint32_t FREQUENCY; /*!< SPI frequency */ + __I uint32_t RESERVED12[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED13[26]; + __IO uint32_t ORC; /*!< Over-read character. Character clocked out in case and over-read + of the TXD buffer. */ +} NRF_SPIM_Type; + + +/* ================================================================================ */ +/* ================ SPIS ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI Slave 0 (SPIS) + */ + +typedef struct { /*!< SPIS Structure */ + __I uint32_t RESERVED0[9]; + __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */ + __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */ + __I uint32_t RESERVED1[54]; + __IO uint32_t EVENTS_END; /*!< Granted transaction completed */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED3[5]; + __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */ + __I uint32_t RESERVED4[53]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED5[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED6[61]; + __I uint32_t SEMSTAT; /*!< Semaphore status register */ + __I uint32_t RESERVED7[15]; + __IO uint32_t STATUS; /*!< Status from last transaction */ + __I uint32_t RESERVED8[47]; + __IO uint32_t ENABLE; /*!< Enable SPI slave */ + __I uint32_t RESERVED9; + SPIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED10[7]; + SPIS_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED11; + SPIS_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED12; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED13; + __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored + transaction. */ + __I uint32_t RESERVED14[24]; + __IO uint32_t ORC; /*!< Over-read character */ +} NRF_SPIS_Type; + + +/* ================================================================================ */ +/* ================ TWIM ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM) + */ + +typedef struct { /*!< TWIM Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is + not suspended. */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[8]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been + issued, TWI traffic is now suspended. */ + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[2]; + __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */ + __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */ + __I uint32_t RESERVED7[39]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED10[14]; + __IO uint32_t ENABLE; /*!< Enable TWIM */ + __I uint32_t RESERVED11; + TWIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[5]; + __IO uint32_t FREQUENCY; /*!< TWI frequency */ + __I uint32_t RESERVED13[3]; + TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[13]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWIM_Type; + + +/* ================================================================================ */ +/* ================ TWIS ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS) + */ + +typedef struct { /*!< TWIS Structure */ + __I uint32_t RESERVED0[5]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED2[3]; + __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */ + __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */ + __I uint32_t RESERVED3[51]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[9]; + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_WRITE; /*!< Write command received */ + __IO uint32_t EVENTS_READ; /*!< Read command received */ + __I uint32_t RESERVED7[37]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[113]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t MATCH; /*!< Status register indicating which address had a match */ + __I uint32_t RESERVED10[10]; + __IO uint32_t ENABLE; /*!< Enable TWIS */ + __I uint32_t RESERVED11; + TWIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[9]; + TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED13; + TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[14]; + __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */ + __I uint32_t RESERVED15; + __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */ + __I uint32_t RESERVED16[10]; + __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read + of the transmit buffer. */ +} NRF_TWIS_Type; + + +/* ================================================================================ */ +/* ================ SPI ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI) + */ + +typedef struct { /*!< SPI Structure */ + __I uint32_t RESERVED0[66]; + __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ + __I uint32_t RESERVED1[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable SPI */ + __I uint32_t RESERVED3; + SPI_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED4; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED5; + __IO uint32_t FREQUENCY; /*!< SPI frequency */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CONFIG; /*!< Configuration register */ +} NRF_SPI_Type; + + +/* ================================================================================ */ +/* ================ TWI ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI) + */ + +typedef struct { /*!< TWI Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ + __I uint32_t RESERVED4[4]; + __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or + received */ + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ + __I uint32_t RESERVED8[45]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED9[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED10[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED11[14]; + __IO uint32_t ENABLE; /*!< Enable TWI */ + __I uint32_t RESERVED12; + __IO uint32_t PSELSCL; /*!< Pin select for SCL */ + __IO uint32_t PSELSDA; /*!< Pin select for SDA */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED14; + __IO uint32_t FREQUENCY; /*!< TWI frequency */ + __I uint32_t RESERVED15[24]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWI_Type; + + +/* ================================================================================ */ +/* ================ NFCT ================ */ +/* ================================================================================ */ + + +/** + * @brief NFC-A compatible radio (NFCT) + */ + +typedef struct { /*!< NFCT Structure */ + __O uint32_t TASKS_ACTIVATE; /*!< Activate NFC peripheral for incoming and outgoing frames, change + state to activated */ + __O uint32_t TASKS_DISABLE; /*!< Disable NFC peripheral */ + __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */ + __O uint32_t TASKS_STARTTX; /*!< Start transmission of a outgoing frame, change state to transmit */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */ + __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */ + __I uint32_t RESERVED2[53]; + __IO uint32_t EVENTS_READY; /*!< The NFC peripheral is ready to receive and send frames */ + __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */ + __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */ + __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */ + __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */ + __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */ + __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data have been checked (CRC, parity) and transferred + to RAM, and EasyDMA has ended accessing the RX buffer */ + __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details + on the source of the error. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains + details on the source of the error. */ + __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ + __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended + accessing the TX buffer */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */ + __I uint32_t RESERVED5[3]; + __IO uint32_t EVENTS_COLLISION; /*!< NFC Auto collision resolution error reported. */ + __IO uint32_t EVENTS_SELECTED; /*!< NFC Auto collision resolution successfully completed */ + __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */ + __I uint32_t RESERVED6[43]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED7[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED8[62]; + __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */ + __I uint32_t RESERVED9; + NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */ + __I uint32_t RESERVED10[8]; + __I uint32_t CURRENTLOADCTRL; /*!< Current value driven to the NFC Load Control */ + __I uint32_t RESERVED11[2]; + __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */ + __I uint32_t RESERVED12[49]; + __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */ + __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */ + __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */ + __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */ + __IO uint32_t MAXLEN; /*!< Size of allocated for TXD and RXD data storage buffer in Data + RAM */ + NFCT_TXD_Type TXD; /*!< Unspecified */ + NFCT_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED13[26]; + __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */ + __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */ + __I uint32_t RESERVED14; + __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */ + __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; + + +/* ================================================================================ */ +/* ================ GPIOTE ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< GPIOTE Structure */ + __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it high. */ + __I uint32_t RESERVED1[4]; + __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it low. */ + __I uint32_t RESERVED2[32]; + __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified + in CONFIG[0].PSEL */ + __I uint32_t RESERVED3[23]; + __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism + enabled */ + __I uint32_t RESERVED4[97]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[129]; + __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n] + and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; + + +/* ================================================================================ */ +/* ================ SAADC ================ */ +/* ================================================================================ */ + + +/** + * @brief Analog to Digital Converter (SAADC) + */ + +typedef struct { /*!< SAADC Structure */ + __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */ + __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */ + __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */ + __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */ + __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */ + __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode, + multiple conversions might be needed for a result to be transferred + to RAM. */ + __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */ + __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */ + __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */ + SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED1[106]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t STATUS; /*!< Status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t ENABLE; /*!< Enable or disable ADC */ + __I uint32_t RESERVED4[3]; + SAADC_CH_Type CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED5[24]; + __IO uint32_t RESOLUTION; /*!< Resolution configuration */ + __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined + with SCAN. The RESOLUTION is applied before averaging, thus + for high OVERSAMPLE a higher RESOLUTION should be used. */ + __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */ + __I uint32_t RESERVED6[12]; + SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */ +} NRF_SAADC_Type; + + +/* ================================================================================ */ +/* ================ TIMER ================ */ +/* ================================================================================ */ + + +/** + * @brief Timer/Counter 0 (TIMER) + */ + +typedef struct { /*!< TIMER Structure */ + __O uint32_t TASKS_START; /*!< Start Timer */ + __O uint32_t TASKS_STOP; /*!< Stop Timer */ + __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */ + __O uint32_t TASKS_CLEAR; /*!< Clear time */ + __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */ + __I uint32_t RESERVED0[11]; + __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */ + __I uint32_t RESERVED1[58]; + __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[42]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[126]; + __IO uint32_t MODE; /*!< Timer mode selection */ + __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */ + __I uint32_t RESERVED5; + __IO uint32_t PRESCALER; /*!< Timer prescaler register */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */ +} NRF_TIMER_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief Real time counter 0 (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __O uint32_t TASKS_START; /*!< Start RTC COUNTER */ + __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */ + __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */ + __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */ + __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */ + __I uint32_t RESERVED1[14]; + __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[109]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[13]; + __IO uint32_t EVTEN; /*!< Enable or disable event routing */ + __IO uint32_t EVTENSET; /*!< Enable event routing */ + __IO uint32_t EVTENCLR; /*!< Disable event routing */ + __I uint32_t RESERVED4[110]; + __I uint32_t COUNTER; /*!< Current COUNTER value */ + __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must + be written when RTC is stopped */ + __I uint32_t RESERVED5[13]; + __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */ +} NRF_RTC_Type; + + +/* ================================================================================ */ +/* ================ TEMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< TEMP Structure */ + __O uint32_t TASKS_START; /*!< Start temperature measurement */ + __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[127]; + __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */ + __I uint32_t RESERVED3[5]; + __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */ + __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */ + __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */ + __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */ + __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */ + __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */ + __I uint32_t RESERVED4[2]; + __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */ + __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */ + __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */ + __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */ + __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */ + __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */ + __I uint32_t RESERVED5[2]; + __IO uint32_t T0; /*!< End point of 1st piece wise linear function */ + __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */ + __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */ + __IO uint32_t T3; /*!< End point of 4th piece wise linear function */ + __IO uint32_t T4; /*!< End point of 5th piece wise linear function */ +} NRF_TEMP_Type; + + +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< RNG Structure */ + __O uint32_t TASKS_START; /*!< Task starting the random number generator */ + __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to + the VALUE register */ + __I uint32_t RESERVED1[63]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[126]; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t VALUE; /*!< Output random number */ +} NRF_RNG_Type; + + +/* ================================================================================ */ +/* ================ ECB ================ */ +/* ================================================================================ */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< ECB Structure */ + __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */ + __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */ + __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to + an error */ + __I uint32_t RESERVED1[127]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[126]; + __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */ +} NRF_ECB_Type; + + +/* ================================================================================ */ +/* ================ CCM ================ */ +/* ================================================================================ */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< CCM Structure */ + __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by + itself when completed. */ + __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself + when completed. */ + __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */ + __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */ + __IO uint32_t EVENTS_ERROR; /*!< CCM error event */ + __I uint32_t RESERVED1[61]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t MICSTATUS; /*!< MIC check result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable */ + __IO uint32_t MODE; /*!< Operation mode */ + __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */ + __IO uint32_t INPTR; /*!< Input pointer */ + __IO uint32_t OUTPTR; /*!< Output pointer */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ +} NRF_CCM_Type; + + +/* ================================================================================ */ +/* ================ AAR ================ */ +/* ================================================================================ */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< AAR Structure */ + __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK + data structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ + __I uint32_t RESERVED1[61]; + __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ + __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ + __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t STATUS; /*!< Resolution status */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable AAR */ + __IO uint32_t NIRK; /*!< Number of IRKs */ + __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ + __I uint32_t RESERVED5; + __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ +} NRF_AAR_Type; + + +/* ================================================================================ */ +/* ================ WDT ================ */ +/* ================================================================================ */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< WDT Structure */ + __O uint32_t TASKS_START; /*!< Start the watchdog */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t RUNSTATUS; /*!< Run status */ + __I uint32_t REQSTATUS; /*!< Request status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t CRV; /*!< Counter reload value */ + __IO uint32_t RREN; /*!< Enable register for reload request registers */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED4[60]; + __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */ +} NRF_WDT_Type; + + +/* ================================================================================ */ +/* ================ QDEC ================ */ +/* ================================================================================ */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< QDEC Structure */ + __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */ + __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */ + __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */ + __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */ + __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */ + __I uint32_t RESERVED0[59]; + __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to + the SAMPLE register */ + __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */ + __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */ + __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */ + __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */ + __I uint32_t RESERVED1[59]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */ + __IO uint32_t LEDPOL; /*!< LED output pin polarity */ + __IO uint32_t SAMPLEPER; /*!< Sample period */ + __I int32_t SAMPLE; /*!< Motion sample value */ + __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events + can be generated */ + __I int32_t ACC; /*!< Register accumulating the valid transitions */ + __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC + task */ + QDEC_PSEL_Type PSEL; /*!< Unspecified */ + __IO uint32_t DBFEN; /*!< Enable input debounce filters */ + __I uint32_t RESERVED4[5]; + __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */ + __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */ + __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL + task */ +} NRF_QDEC_Type; + + +/* ================================================================================ */ +/* ================ COMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< COMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< COMP enable */ + __IO uint32_t PSEL; /*!< Pin select */ + __IO uint32_t REFSEL; /*!< Reference source select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[8]; + __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */ + __IO uint32_t MODE; /*!< Mode configuration */ + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ + __IO uint32_t ISOURCE; /*!< Current source select on analog input */ +} NRF_COMP_Type; + + +/* ================================================================================ */ +/* ================ LPCOMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Low Power Comparator (LPCOMP) + */ + +typedef struct { /*!< LPCOMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable LPCOMP */ + __IO uint32_t PSEL; /*!< Input pin select */ + __IO uint32_t REFSEL; /*!< Reference select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[4]; + __IO uint32_t ANADETECT; /*!< Analog detect configuration */ + __I uint32_t RESERVED6[5]; + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ +} NRF_LPCOMP_Type; + + +/* ================================================================================ */ +/* ================ SWI ================ */ +/* ================================================================================ */ + + +/** + * @brief Software interrupt 0 (SWI) + */ + +typedef struct { /*!< SWI Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_SWI_Type; + + +/* ================================================================================ */ +/* ================ EGU ================ */ +/* ================================================================================ */ + + +/** + * @brief Event Generator Unit 0 (EGU) + */ + +typedef struct { /*!< EGU Structure */ + __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding + TRIGGERED[0] event */ + __I uint32_t RESERVED0[48]; + __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering + the corresponding TRIGGER[0] task */ + __I uint32_t RESERVED1[112]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ +} NRF_EGU_Type; + + +/* ================================================================================ */ +/* ================ PWM ================ */ +/* ================================================================================ */ + + +/** + * @brief Pulse Width Modulation Unit 0 (PWM) + */ + +typedef struct { /*!< PWM Structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current + PWM period, and stops sequence playback */ + __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all + enabled channels from sequence 0, and starts playing that sequence + at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes + PWM generation to start it was not running. */ + __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels + if DECODER.MODE=NextStep. Does not cause PWM generation to start + it was not running. */ + __I uint32_t RESERVED1[60]; + __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer + generated */ + __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence + 0 */ + __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence + 0, when last value from RAM has been applied to wave counter */ + __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */ + __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times + defined in LOOP.CNT */ + __I uint32_t RESERVED2[56]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[125]; + __IO uint32_t ENABLE; /*!< PWM module enable register */ + __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */ + __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */ + __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */ + __IO uint32_t DECODER; /*!< Configuration of the decoder */ + __IO uint32_t LOOP; /*!< Amount of playback of a loop */ + __I uint32_t RESERVED5[2]; + PWM_SEQ_Type SEQ[2]; /*!< Unspecified */ + PWM_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_PWM_Type; + + +/* ================================================================================ */ +/* ================ PDM ================ */ +/* ================================================================================ */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< PDM Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */ + __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */ + __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */ + __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT + (or the last sample after a STOP task has been received) to + Data RAM */ + __I uint32_t RESERVED1[125]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< PDM module enable register */ + __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */ + __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */ + __I uint32_t RESERVED3[3]; + __IO uint32_t GAINL; /*!< Left output gain adjustment */ + __IO uint32_t GAINR; /*!< Right output gain adjustment */ + __I uint32_t RESERVED4[8]; + PDM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED5[6]; + PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */ +} NRF_PDM_Type; + + +/* ================================================================================ */ +/* ================ NVMC ================ */ +/* ================================================================================ */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< NVMC Structure */ + __I uint32_t RESERVED0[256]; + __I uint32_t READY; /*!< Ready flag */ + __I uint32_t RESERVED1[64]; + __IO uint32_t CONFIG; /*!< Configuration register */ + + union { + __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */ + }; + __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */ + __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */ + __I uint32_t RESERVED2[10]; + __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */ + __I uint32_t RESERVED3; + __IO uint32_t IHIT; /*!< I-Code cache hit counter. */ + __IO uint32_t IMISS; /*!< I-Code cache miss counter. */ +} NRF_NVMC_Type; + + +/* ================================================================================ */ +/* ================ PPI ================ */ +/* ================================================================================ */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< PPI Structure */ + PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */ + __I uint32_t RESERVED0[308]; + __IO uint32_t CHEN; /*!< Channel enable register */ + __IO uint32_t CHENSET; /*!< Channel enable set register */ + __IO uint32_t CHENCLR; /*!< Channel enable clear register */ + __I uint32_t RESERVED1; + PPI_CH_Type CH[20]; /*!< PPI Channel */ + __I uint32_t RESERVED2[148]; + __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */ + __I uint32_t RESERVED3[62]; + PPI_FORK_Type FORK[32]; /*!< Fork */ +} NRF_PPI_Type; + + +/* ================================================================================ */ +/* ================ MWU ================ */ +/* ================================================================================ */ + + +/** + * @brief Memory Watch Unit (MWU) + */ + +typedef struct { /*!< MWU Structure */ + __I uint32_t RESERVED0[64]; + MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED1[16]; + MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED2[100]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[5]; + __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */ + __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */ + __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */ + __I uint32_t RESERVED4[53]; + MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED5[64]; + __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */ + __IO uint32_t REGIONENSET; /*!< Enable regions watch */ + __IO uint32_t REGIONENCLR; /*!< Disable regions watch */ + __I uint32_t RESERVED6[57]; + MWU_REGION_Type REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED7[32]; + MWU_PREGION_Type PREGION[2]; /*!< Unspecified */ +} NRF_MWU_Type; + + +/* ================================================================================ */ +/* ================ I2S ================ */ +/* ================================================================================ */ + + +/** + * @brief Inter-IC Sound (I2S) + */ + +typedef struct { /*!< I2S Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when + this is enabled. */ + __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this + task will cause the {event:STOPPED} event to be generated. */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __I uint32_t RESERVED2[122]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable I2S module. */ + I2S_CONFIG_Type CONFIG; /*!< Unspecified */ + __I uint32_t RESERVED4[3]; + I2S_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED5; + I2S_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED6[3]; + I2S_RXTXD_Type RXTXD; /*!< Unspecified */ + __I uint32_t RESERVED7[3]; + I2S_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_I2S_Type; + + +/* ================================================================================ */ +/* ================ FPU ================ */ +/* ================================================================================ */ + + +/** + * @brief FPU (FPU) + */ + +typedef struct { /*!< FPU Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_FPU_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO Port 1 (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __I uint32_t RESERVED0[321]; + __IO uint32_t OUT; /*!< Write GPIO port */ + __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */ + __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */ + __I uint32_t IN; /*!< Read GPIO port */ + __IO uint32_t DIR; /*!< Direction of GPIO pins */ + __IO uint32_t DIRSET; /*!< DIR set register */ + __IO uint32_t DIRCLR; /*!< DIR clear register */ + __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria + set in the PIN_CNF[n].SENSE registers */ + __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */ + __I uint32_t RESERVED1[118]; + __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */ +} NRF_GPIO_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_BPROT_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_AMLI_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_P0_BASE 0x50000000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) +#define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE) +#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) +#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) +#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) +#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE) +#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) +#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) +#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) +#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) +#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) +#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE) +#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) +#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) +#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) +#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) +#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) +#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE) +#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group nrf52 */ +/** @} */ /* End of group Nordic Semiconductor */ + +#ifdef __cplusplus +} +#endif + + +#endif /* nrf52_H */ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h new file mode 100644 index 0000000..ae959d4 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h @@ -0,0 +1,14861 @@ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef __NRF52_BITS_H +#define __NRF52_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for END event */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for END event */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: AMLI */ +/* Description: AHB Multi-Layer Interface */ + +/* Register: AMLI_RAMPRI_CPU0 */ +/* Description: AHB bus master priority register for CPU0 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_SPIS1 */ +/* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_RADIO */ +/* Description: AHB bus master priority register for RADIO */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_ECB */ +/* Description: AHB bus master priority register for ECB */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_CCM */ +/* Description: AHB bus master priority register for CCM */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_AAR */ +/* Description: AHB bus master priority register for AAR */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_SAADC */ +/* Description: AHB bus master priority register for SAADC */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_UARTE */ +/* Description: AHB bus master priority register for UARTE */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_SERIAL0 */ +/* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_SERIAL2 */ +/* Description: AHB bus master priority register for SPIM2 and SPIS2 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_NFCT */ +/* Description: AHB bus master priority register for NFCT */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_I2S */ +/* Description: AHB bus master priority register for I2S */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_PDM */ +/* Description: AHB bus master priority register for PDM */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_PWM */ +/* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */ + + +/* Peripheral: BPROT */ +/* Description: Block Protect */ + +/* Register: BPROT_CONFIG0 */ +/* Description: Block protect configuration register 0 */ + +/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */ + +/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */ + +/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */ + +/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */ + +/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */ + +/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */ + +/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */ + +/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */ + +/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */ + +/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */ + +/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */ + +/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */ + +/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */ + +/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */ + +/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */ + +/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */ + +/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */ + +/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */ + +/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */ + +/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */ + +/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */ + +/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */ + +/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */ + +/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */ + +/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */ + +/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */ + +/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */ + +/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */ + +/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */ + +/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */ + +/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */ + +/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */ + +/* Register: BPROT_CONFIG1 */ +/* Description: Block protect configuration register 1 */ + +/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */ +#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */ +#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */ +#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */ +#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */ +#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */ +#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */ +#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */ +#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */ +#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */ +#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */ +#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */ +#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */ +#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */ +#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */ +#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */ +#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */ +#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */ +#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */ +#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */ +#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */ +#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */ +#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */ +#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */ +#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */ +#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */ +#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */ +#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */ +#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */ +#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */ +#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */ +#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */ +#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_DISABLEINDEBUG */ +/* Description: Disable protection mechanism in debug interface mode */ + +/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */ + +/* Register: BPROT_CONFIG2 */ +/* Description: Block protect configuration register 2 */ + +/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */ +#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */ +#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */ +#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */ +#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */ +#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */ +#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */ +#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */ +#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */ +#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */ +#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */ +#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */ +#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */ +#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */ +#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */ +#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */ +#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */ +#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */ +#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */ +#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */ +#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */ +#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */ +#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */ +#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */ +#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */ +#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */ +#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */ +#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */ +#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */ +#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */ +#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */ +#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */ +#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */ +#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */ +#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */ +#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */ +#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */ +#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */ +#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */ +#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */ +#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */ +#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */ +#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */ +#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */ +#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */ +#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */ +#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */ +#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */ +#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */ +#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */ +#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */ +#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */ +#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */ +#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */ +#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */ +#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */ +#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */ +#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */ +#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */ +#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */ +#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */ +#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */ +#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */ +#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */ +#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_CONFIG3 */ +/* Description: Block protect configuration register 3 */ + +/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */ +#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */ +#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */ +#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */ +#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */ +#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */ +#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */ +#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */ +#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */ +#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */ +#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */ +#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */ +#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */ +#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */ +#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */ +#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */ +#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */ +#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */ +#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */ +#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */ +#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */ +#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */ +#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */ +#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */ +#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */ +#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */ +#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */ +#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */ +#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */ +#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */ +#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */ +#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */ +#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */ +#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */ +#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */ +#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */ +#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */ +#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */ +#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */ +#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */ +#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */ +#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */ +#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */ +#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */ +#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */ +#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */ +#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */ +#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */ +#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */ +#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */ +#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */ +#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */ +#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */ +#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */ +#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */ +#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */ +#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */ +#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */ +#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */ +#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */ +#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */ +#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */ +#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */ +#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */ +#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for ERROR event */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for ERROR event */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */ + +/* Bit 16 : Data rate that the CCM shall run in synch with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */ + +/* Bit 0 : The mode of operation to be used */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for CTTO event */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DONE event */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for CTTO event */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DONE event */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_TRACECONFIG */ +/* Description: Clocking options for the Trace Port debug interface */ + +/* Bits 17..16 : Pin multiplexing of trace signals. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */ + +/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for CROSS event */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for UP event */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for DOWN event */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation mode */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power mode */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + +/* Register: COMP_ISOURCE */ +/* Description: Current source select on analog input */ + +/* Bits 1..0 : Comparator hysteresis */ +#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */ +#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event Generator Unit 0 */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory Information Configuration Registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection[0]: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection[0]: Encryption Root, word 0 */ + +/* Bits 31..0 : Encryption Root, word n */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection[0]: Identity Root, word 0 */ + +/* Bits 31..0 : Identity Root, word n */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection[0]: Device address 0 */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part Variant, Hardware version and Production configuration */ + +/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ +#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: y-intercept B0. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: y-intercept B1. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: y-intercept B2. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: y-intercept B3. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: y-intercept B4. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: y-intercept B5. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_NFC_TAGHEADER0 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 3 */ +#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ +#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ + +/* Bits 23..16 : Unique identifier byte 2 */ +#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ +#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ + +/* Bits 15..8 : Unique identifier byte 1 */ +#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ +#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ + +/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ +#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ +#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ + +/* Register: FICR_NFC_TAGHEADER1 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 7 */ +#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ +#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ + +/* Bits 23..16 : Unique identifier byte 6 */ +#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ +#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ + +/* Bits 15..8 : Unique identifier byte 5 */ +#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ +#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ + +/* Bits 7..0 : Unique identifier byte 4 */ +#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ +#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ + +/* Register: FICR_NFC_TAGHEADER2 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 11 */ +#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ +#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ + +/* Bits 23..16 : Unique identifier byte 10 */ +#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ +#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ + +/* Bits 15..8 : Unique identifier byte 9 */ +#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ +#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ + +/* Bits 7..0 : Unique identifier byte 8 */ +#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ +#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ + +/* Register: FICR_NFC_TAGHEADER3 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 15 */ +#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ +#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ + +/* Bits 23..16 : Unique identifier byte 14 */ +#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ +#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ + +/* Bits 15..8 : Unique identifier byte 13 */ +#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ +#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ + +/* Bits 7..0 : Unique identifier byte 12 */ +#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ +#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to Enable interrupt for PORT event */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to Disable interrupt for PORT event */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: I2S */ +/* Description: Inter-IC Sound */ + +/* Register: I2S_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ +#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for STOPPED event */ +#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ +#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */ +#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */ +#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */ +#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ + +/* Register: I2S_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */ +#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */ +#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */ +#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Register: I2S_ENABLE */ +/* Description: Enable I2S module. */ + +/* Bit 0 : Enable I2S module. */ +#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_CONFIG_MODE */ +/* Description: I2S mode. */ + +/* Bit 0 : I2S mode. */ +#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ +#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ + +/* Register: I2S_CONFIG_RXEN */ +/* Description: Reception (RX) enable. */ + +/* Bit 0 : Reception (RX) enable. */ +#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ +#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: I2S_CONFIG_TXEN */ +/* Description: Transmission (TX) enable. */ + +/* Bit 0 : Transmission (TX) enable. */ +#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ +#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ + +/* Register: I2S_CONFIG_MCKEN */ +/* Description: Master clock generator enable. */ + +/* Bit 0 : Master clock generator enable. */ +#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ +#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ + +/* Register: I2S_CONFIG_MCKFREQ */ +/* Description: Master clock generator frequency. */ + +/* Bits 31..0 : Master clock generator frequency. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ + +/* Register: I2S_CONFIG_RATIO */ +/* Description: MCK / LRCK ratio. */ + +/* Bits 3..0 : MCK / LRCK ratio. */ +#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ +#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ +#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ +#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ +#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ +#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ +#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ +#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ +#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ + +/* Register: I2S_CONFIG_SWIDTH */ +/* Description: Sample width. */ + +/* Bits 1..0 : Sample width. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ + +/* Register: I2S_CONFIG_ALIGN */ +/* Description: Alignment of sample within a frame. */ + +/* Bit 0 : Alignment of sample within a frame. */ +#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ + +/* Register: I2S_CONFIG_FORMAT */ +/* Description: Frame format. */ + +/* Bit 0 : Frame format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ + +/* Register: I2S_CONFIG_CHANNELS */ +/* Description: Enable channels. */ + +/* Bits 1..0 : Enable channels. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ + +/* Register: I2S_RXD_PTR */ +/* Description: Receive buffer RAM start address. */ + +/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ +#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_TXD_PTR */ +/* Description: Transmit buffer RAM start address. */ + +/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ +#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_RXTXD_MAXCNT */ +/* Description: Size of RXD and TXD buffers. */ + +/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: I2S_PSEL_MCK */ +/* Description: Pin select for MCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SCK */ +/* Description: Pin select for SCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_LRCK */ +/* Description: Pin select for LRCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDIN */ +/* Description: Pin select for SDIN signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDOUT */ +/* Description: Pin select for SDOUT signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low Power Comparator */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: LPCOMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable LPCOMP */ + +/* Bits 1..0 : Enable or disable LPCOMP */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select */ + +/* Bits 2..0 : Analog pin select */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select */ + +/* Bits 3..0 : Reference select */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */ +#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration */ + +/* Bits 1..0 : Analog detect configuration */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */ + +/* Register: LPCOMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis enable */ +#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */ + + +/* Peripheral: MWU */ +/* Description: Memory Watch Unit */ + +/* Register: MWU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ +#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ +#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ +#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ +#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ +#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ +#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ +#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ +#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ +#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ +#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ +#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ +#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */ +#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */ +#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */ +#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */ +#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */ +#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */ +#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */ +#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */ +#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */ +#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */ +#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */ +#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */ +#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */ +#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */ +#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */ +#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */ +#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */ +#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */ +#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */ +#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */ +#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */ +#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */ +#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */ +#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */ +#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_NMIEN */ +/* Description: Enable or disable non-maskable interrupt */ + +/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_NMIENSET */ +/* Description: Enable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_NMIENCLR */ +/* Description: Disable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_PERREGION_SUBSTATWA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Register: MWU_PERREGION_SUBSTATRA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Register: MWU_REGIONEN */ +/* Description: Enable/disable regions watch */ + +/* Bit 27 : Enable/disable read access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable/disable write access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable/disable read access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable/disable write access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable/disable read access watch in region[3] */ +#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable/disable write access watch in region[3] */ +#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable/disable read access watch in region[2] */ +#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable/disable write access watch in region[2] */ +#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable/disable read access watch in region[1] */ +#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable/disable write access watch in region[1] */ +#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable/disable read access watch in region[0] */ +#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable/disable write access watch in region[0] */ +#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENSET */ +/* Description: Enable regions watch */ + +/* Bit 27 : Enable read access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable write access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable read access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable write access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable read access watch in region[3] */ +#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable write access watch in region[3] */ +#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable read access watch in region[2] */ +#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable write access watch in region[2] */ +#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable read access watch in region[1] */ +#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable write access watch in region[1] */ +#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable read access watch in region[0] */ +#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable write access watch in region[0] */ +#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENCLR */ +/* Description: Disable regions watch */ + +/* Bit 27 : Disable read access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 26 : Disable write access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 25 : Disable read access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 24 : Disable write access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 7 : Disable read access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 6 : Disable write access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 5 : Disable read access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 4 : Disable write access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 3 : Disable read access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 2 : Disable write access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 1 : Disable read access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 0 : Disable write access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Register: MWU_REGION_START */ +/* Description: Description cluster[0]: Start address for region 0 */ + +/* Bits 31..0 : Start address for region */ +#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_REGION_END */ +/* Description: Description cluster[0]: End address of region 0 */ + +/* Bits 31..0 : End address of region. */ +#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_START */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_PREGION_END */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_SUBS */ +/* Description: Description cluster[0]: Subregions of region 0 */ + +/* Bit 31 : Include or exclude subregion 31 in region */ +#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude subregion 30 in region */ +#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude subregion 29 in region */ +#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude subregion 28 in region */ +#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude subregion 27 in region */ +#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude subregion 26 in region */ +#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude subregion 25 in region */ +#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude subregion 24 in region */ +#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude subregion 23 in region */ +#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude subregion 22 in region */ +#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude subregion 21 in region */ +#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude subregion 20 in region */ +#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude subregion 19 in region */ +#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude subregion 18 in region */ +#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude subregion 17 in region */ +#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude subregion 16 in region */ +#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude subregion 15 in region */ +#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude subregion 14 in region */ +#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude subregion 13 in region */ +#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude subregion 12 in region */ +#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude subregion 11 in region */ +#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude subregion 10 in region */ +#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude subregion 9 in region */ +#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude subregion 8 in region */ +#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude subregion 7 in region */ +#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude subregion 6 in region */ +#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude subregion 5 in region */ +#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude subregion 4 in region */ +#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude subregion 3 in region */ +#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude subregion 2 in region */ +#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude subregion 1 in region */ +#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude subregion 0 in region */ +#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */ + + +/* Peripheral: NFCT */ +/* Description: NFC-A compatible radio */ + +/* Register: NFCT_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: NFCT_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 20 : Enable or disable interrupt for STARTED event */ +#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for SELECTED event */ +#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for COLLISION event */ +#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for ENDTX event */ +#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for ENDRX event */ +#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for RXERROR event */ +#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for ERROR event */ +#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ +#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ +#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ +#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ +#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ +#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ +#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: NFCT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 20 : Write '1' to Enable interrupt for STARTED event */ +#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */ +#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */ +#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */ +#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */ +#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */ +#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for ERROR event */ +#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */ +#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */ +#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */ +#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */ +#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */ +#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */ +#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: NFCT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 20 : Write '1' to Disable interrupt for STARTED event */ +#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */ +#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */ +#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */ +#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */ +#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */ +#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for ERROR event */ +#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */ +#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */ +#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */ +#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */ +#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */ +#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */ +#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: NFCT_ERRORSTATUS */ +/* Description: NFC Error Status register */ + +/* Bit 3 : Field level is too low at min load resistance */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */ + +/* Bit 2 : Field level is too high at max load resistance */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */ + +/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */ + +/* Register: NFCT_FRAMESTATUS_RX */ +/* Description: Result of last incoming frames */ + +/* Bit 3 : Overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */ + +/* Bit 2 : Parity status of received frame */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */ + +/* Bit 0 : No valid End of Frame detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ + +/* Register: NFCT_CURRENTLOADCTRL */ +/* Description: Current value driven to the NFC Load Control */ + +/* Bits 5..0 : Current value driven to the NFC Load Control */ +#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */ +#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */ + +/* Register: NFCT_FIELDPRESENT */ +/* Description: Indicates the presence or not of a valid field */ + +/* Bit 1 : Indicates if the low level has locked to the field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */ + +/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */ + +/* Register: NFCT_FRAMEDELAYMIN */ +/* Description: Minimum frame delay */ + +/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ + +/* Register: NFCT_FRAMEDELAYMAX */ +/* Description: Maximum frame delay */ + +/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ + +/* Register: NFCT_FRAMEDELAYMODE */ +/* Description: Configuration register for the Frame Delay Timer */ + +/* Bits 1..0 : Configuration register for the Frame Delay Timer */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */ + +/* Register: NFCT_PACKETPTR */ +/* Description: Packet pointer for TXD and RXD data storage in Data RAM */ + +/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */ +#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: NFCT_MAXLEN */ +/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */ + +/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */ +#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: NFCT_TXD_FRAMECONFIG */ +/* Description: Configuration of outgoing frames */ + +/* Bit 4 : CRC mode for outgoing frames */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */ + +/* Bit 2 : Adding SoF or not in TX frames */ +#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */ +#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */ + +/* Bit 1 : Discarding unused bits in start or at end of a Frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */ + +/* Bit 0 : Adding parity or not in the frame */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */ + +/* Register: NFCT_TXD_AMOUNT */ +/* Description: Size of outgoing frame */ + +/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ + +/* Register: NFCT_RXD_FRAMECONFIG */ +/* Description: Configuration of incoming frames */ + +/* Bit 4 : CRC mode for incoming frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */ + +/* Bit 2 : SoF expected or not in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */ + +/* Bit 0 : Parity expected or not in RX frame */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */ + +/* Register: NFCT_RXD_AMOUNT */ +/* Description: Size of last incoming frame */ + +/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ + +/* Register: NFCT_NFCID1_LAST */ +/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */ + +/* Bits 31..24 : NFCID1 byte W */ +#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */ +#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */ + +/* Bits 23..16 : NFCID1 byte X */ +#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */ +#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */ + +/* Bits 15..8 : NFCID1 byte Y */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */ + +/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */ + +/* Register: NFCT_NFCID1_2ND_LAST */ +/* Description: Second last NFCID1 part (7 or 10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte T */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */ + +/* Bits 15..8 : NFCID1 byte U */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */ + +/* Bits 7..0 : NFCID1 byte V */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */ + +/* Register: NFCT_NFCID1_3RD_LAST */ +/* Description: Third last NFCID1 part (10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte Q */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */ + +/* Bits 15..8 : NFCID1 byte R */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */ + +/* Bits 7..0 : NFCID1 byte S */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ + +/* Register: NFCT_SENSRES */ +/* Description: NFC-A SENS_RES auto-response settings */ + +/* Bits 15..12 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ +#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ + +/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ +#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ + +/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */ +#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */ + +/* Bit 5 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ +#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ + +/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */ + +/* Register: NFCT_SELRES */ +/* Description: NFC-A SEL_RES auto-response settings */ + +/* Bit 7 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ +#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ + +/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ +#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + +/* Bits 4..3 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ +#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ + +/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */ +#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */ +#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */ + +/* Bits 1..0 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ +#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in Code area */ + +/* Bits 31..0 : Register for starting erase of a page in Code area */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing User Information Configuration Registers */ + +/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ICACHECNF */ +/* Description: I-Code cache configuration register. */ + +/* Bit 8 : Cache profiling enable */ +#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ + +/* Bit 0 : Cache enable */ +#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ +#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ + +/* Register: NVMC_IHIT */ +/* Description: I-Code cache hit counter. */ + +/* Bits 31..0 : Number of cache hits */ +#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ +#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ + +/* Register: NVMC_IMISS */ +/* Description: I-Code cache miss counter. */ + +/* Bits 31..0 : Number of cache misses */ +#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ +#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port 1 */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : P0.31 pin */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : P0.30 pin */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : P0.29 pin */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : P0.28 pin */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : P0.27 pin */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : P0.26 pin */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : P0.25 pin */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : P0.24 pin */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : P0.23 pin */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : P0.22 pin */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : P0.21 pin */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : P0.20 pin */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : P0.19 pin */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : P0.18 pin */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : P0.17 pin */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : P0.16 pin */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : P0.15 pin */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : P0.14 pin */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : P0.13 pin */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : P0.12 pin */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : P0.11 pin */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : P0.10 pin */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : P0.9 pin */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : P0.8 pin */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : P0.7 pin */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : P0.6 pin */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : P0.5 pin */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : P0.4 pin */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : P0.3 pin */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : P0.2 pin */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : P0.1 pin */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : P0.0 pin */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : P0.31 pin */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : P0.30 pin */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : P0.29 pin */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : P0.28 pin */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : P0.27 pin */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : P0.26 pin */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : P0.25 pin */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : P0.24 pin */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : P0.23 pin */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : P0.22 pin */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : P0.21 pin */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : P0.20 pin */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : P0.19 pin */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : P0.18 pin */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : P0.17 pin */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : P0.16 pin */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : P0.15 pin */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : P0.14 pin */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : P0.13 pin */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : P0.12 pin */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : P0.11 pin */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : P0.10 pin */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : P0.9 pin */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : P0.8 pin */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : P0.7 pin */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : P0.6 pin */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : P0.5 pin */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : P0.4 pin */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : P0.3 pin */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : P0.2 pin */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : P0.1 pin */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : P0.0 pin */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : P0.31 pin */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : P0.30 pin */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : P0.29 pin */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : P0.28 pin */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : P0.27 pin */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : P0.26 pin */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : P0.25 pin */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : P0.24 pin */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : P0.23 pin */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : P0.22 pin */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : P0.21 pin */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : P0.20 pin */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : P0.19 pin */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : P0.18 pin */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : P0.17 pin */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : P0.16 pin */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : P0.15 pin */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : P0.14 pin */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : P0.13 pin */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : P0.12 pin */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : P0.11 pin */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : P0.10 pin */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : P0.9 pin */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : P0.8 pin */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : P0.7 pin */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : P0.6 pin */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : P0.5 pin */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : P0.4 pin */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : P0.3 pin */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : P0.2 pin */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : P0.1 pin */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : P0.0 pin */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : P0.31 pin */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : P0.30 pin */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : P0.29 pin */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : P0.28 pin */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : P0.27 pin */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : P0.26 pin */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : P0.25 pin */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : P0.24 pin */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : P0.23 pin */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : P0.22 pin */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : P0.21 pin */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : P0.20 pin */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : P0.19 pin */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : P0.18 pin */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : P0.17 pin */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : P0.16 pin */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : P0.15 pin */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : P0.14 pin */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : P0.13 pin */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : P0.12 pin */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : P0.11 pin */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : P0.10 pin */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : P0.9 pin */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : P0.8 pin */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : P0.7 pin */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : P0.6 pin */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : P0.5 pin */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : P0.4 pin */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : P0.3 pin */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : P0.2 pin */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : P0.1 pin */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : P0.0 pin */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : P0.31 pin */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : P0.30 pin */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : P0.29 pin */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : P0.28 pin */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : P0.27 pin */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : P0.26 pin */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : P0.25 pin */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : P0.24 pin */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : P0.23 pin */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : P0.22 pin */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : P0.21 pin */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : P0.20 pin */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : P0.19 pin */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : P0.18 pin */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : P0.17 pin */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : P0.16 pin */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : P0.15 pin */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : P0.14 pin */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : P0.13 pin */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : P0.12 pin */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : P0.11 pin */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : P0.10 pin */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : P0.9 pin */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : P0.8 pin */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : P0.7 pin */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : P0.6 pin */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : P0.5 pin */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : P0.4 pin */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : P0.3 pin */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : P0.2 pin */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : P0.1 pin */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : P0.0 pin */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection[0]: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for END event */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for END event */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for END event */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */ +#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */ +#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ +#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Deprecated register - RAM status register */ + +/* Bit 3 : RAM block 3 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */ + +/* Bit 2 : RAM block 2 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */ + +/* Bit 1 : RAM block 1 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ + +/* Bit 0 : RAM block 0 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power failure comparator configuration */ + +/* Bits 4..1 : Power failure comparator threshold setting */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure comparator */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_RAMON */ +/* Description: Deprecated register - RAM on/off register (this register is retained) */ + +/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */ +#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */ +#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */ +#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */ +#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */ +#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */ +#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */ +#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */ +#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */ + +/* Register: POWER_RAMONB */ +/* Description: Deprecated register - RAM on/off register (this register is retained) */ + +/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */ + +/* Register: POWER_DCDCEN */ +/* Description: DC/DC enable register */ + +/* Bit 0 : Enable or disable DC/DC converter */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster[0]: RAM0 power control register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster[0]: RAM0 power control set register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster[0]: RAM0 power control clear register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster[0]: Channel 0 event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection[0]: Channel group 0 */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: PWM */ +/* Description: Pulse Width Modulation Unit 0 */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up or up and down as wave counter mode */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Pre-scaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Amount of playback of a loop */ + +/* Bits 15..0 : Amount of playback of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */ + +/* Bits 31..0 : Beginning address in Data RAM of sequence A */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */ + +/* Bits 14..0 : Amount of values (duty cycles) in sequence A */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ + +/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster[0]: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection[0]: Output pin select for PWM channel 0 */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz Radio */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between END event and START task */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between END event and DISABLE task */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and START task */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for END event */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for END event */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power. */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bit 8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Inter Frame Spacing in us */ + +/* Bits 7..0 : Inter Frame Spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection[0]: Device address base segment 0 */ + +/* Bits 31..0 : Device address base segment 0 */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection[0]: Device address prefix 0 */ + +/* Bits 15..0 : Device address prefix 0 */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TICK event */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TICK event */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable event routing for OVRFLW event */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable event routing for TICK event */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable event routing for TICK event */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable event routing for TICK event */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection[0]: Compare register 0 */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Analog to Digital Converter */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for STOPPED event */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for DONE event */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for END event */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for DONE event */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for DONE event */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable ADC */ + +/* Bit 0 : Enable or disable ADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster[0]: Input positive pin selection for CH[0] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster[0]: Input negative pin selection for CH[0] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster[0]: Input configuration for CH[0] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster[0]: High/low limits for event monitoring a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 14..0 : Maximum number of buffer words to transfer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of buffer words transferred since last START */ + +/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for READY event */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for READY event */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bits 31..0 : Pin number configuration for SPI SCK signal */ +#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */ +#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */ +#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI */ + +/* Bits 31..0 : Pin number configuration for SPI MOSI signal */ +#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */ +#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */ +#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO */ + +/* Bits 31..0 : Pin number configuration for SPI MISO signal */ +#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */ +#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */ +#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 17 : Shortcut between END event and START task */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for STARTED event */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for END event */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for STARTED event */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for END event */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ + +/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 2 : Shortcut between END event and ACQUIRE task */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 7..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 7..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection[0]: Capture/Compare register 0 */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface 0 */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between BB event and STOP task */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between BB event and SUSPEND task */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for BB event */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for BB event */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSELSCL */ +/* Description: Pin select for SCL */ + +/* Bits 31..0 : Pin number configuration for TWI SCL signal */ +#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */ +#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */ +#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: TWI_PSELSDA */ +/* Description: Pin select for SDA */ + +/* Bits 31..0 : Pin number configuration for TWI SDA signal */ +#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */ +#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */ +#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 12 : Shortcut between LASTRX event and STOP task */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between LASTTX event and STOP task */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for LASTTX event */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for LASTRX event */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 14 : Shortcut between READ event and SUSPEND task */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for READ event */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for WRITE event */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to Enable interrupt for READ event */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for WRITE event */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to Disable interrupt for READ event */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for WRITE event */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection[0]: TWI slave address 0 */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between NCTS event and STOPRX task */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between CTS event and STARTRX task */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSELRTS */ +/* Description: Pin select for RTS */ + +/* Bits 31..0 : Pin number configuration for UART RTS signal */ +#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */ +#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */ +#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELTXD */ +/* Description: Pin select for TXD */ + +/* Bits 31..0 : Pin number configuration for UART TXD signal */ +#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */ +#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */ +#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELCTS */ +/* Description: Pin select for CTS */ + +/* Bits 31..0 : Pin number configuration for UART CTS signal */ +#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */ +#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */ +#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELRXD */ +/* Description: Pin select for RXD */ + +/* Bits 31..0 : Pin number configuration for UART RXD signal */ +#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */ +#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */ +#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate */ + +/* Bits 31..0 : Baud-rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for RXTO event */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for ENDTX event */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for ENDRX event */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for NCTS event */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for CTS event */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate */ + +/* Bits 31..0 : Baud-rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User Information Configuration Registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection[0]: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection[0]: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection[0]: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access Port protection */ + +/* Bits 7..0 : Enable or disable Access Port protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + +/* Register: UICR_NFCPINS */ +/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ + +/* Bit 0 : Setting of pins dedicated to NFC functionality */ +#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection[0]: Reload request 0 */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h new file mode 100644 index 0000000..5ce8ba4 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h @@ -0,0 +1,70 @@ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF52_NAME_CHANGE_H +#define NRF52_NAME_CHANGE_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and + * nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead. + */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right + + + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF52_NAME_CHANGE_H */ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.c new file mode 100644 index 0000000..eff432d --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.c @@ -0,0 +1,208 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include +#include "nrf_drv_common.h" +#include "nrf_assert.h" +#include "app_util_platform.h" + +#ifdef SOFTDEVICE_PRESENT +#include "nrf_soc.h" +#endif + + +#if PERIPHERAL_RESOURCE_SHARING_ENABLED + +typedef struct { + nrf_drv_irq_handler_t handler; + bool acquired; +} shared_resource_t; + +// SPIM0, SPIS0, SPI0, TWIM0, TWIS0, TWI0 +#if (SPI0_ENABLED || SPIS0_ENABLED || TWI0_ENABLED || TWIS0_ENABLED) + #define SERIAL_BOX_0_IN_USE + // [this checking may need a different form in unit tests, hence macro] + #ifndef IS_SERIAL_BOX_0 + #define IS_SERIAL_BOX_0(p_per_base) (p_per_base == NRF_SPI0) + #endif + + static shared_resource_t m_serial_box_0 = { .acquired = false }; + void SPI0_TWI0_IRQHandler(void) + { + ASSERT(m_serial_box_0.handler); + m_serial_box_0.handler(); + } +#endif // (SPI0_ENABLED || SPIS0_ENABLED || TWI0_ENABLED || TWIS0_ENABLED) + +// SPIM1, SPIS1, SPI1, TWIM1, TWIS1, TWI1 +#if (SPI1_ENABLED || SPIS1_ENABLED || TWI1_ENABLED || TWIS1_ENABLED) + #define SERIAL_BOX_1_IN_USE + // [this checking may need a different form in unit tests, hence macro] + #ifndef IS_SERIAL_BOX_1 + #define IS_SERIAL_BOX_1(p_per_base) (p_per_base == NRF_SPI1) + #endif + + static shared_resource_t m_serial_box_1 = { .acquired = false }; + void SPI1_TWI1_IRQHandler(void) + { + ASSERT(m_serial_box_1.handler); + m_serial_box_1.handler(); + } +#endif // (SPI1_ENABLED || SPIS1_ENABLED || TWI1_ENABLED || TWIS1_ENABLED) + +// SPIM2, SPIS2, SPI2 +#if (SPI2_ENABLED || SPIS2_ENABLED) + #define SERIAL_BOX_2_IN_USE + // [this checking may need a different form in unit tests, hence macro] + #ifndef IS_SERIAL_BOX_2 + #define IS_SERIAL_BOX_2(p_per_base) (p_per_base == NRF_SPI2) + #endif + + static shared_resource_t m_serial_box_2 = { .acquired = false }; + void SPIM2_SPIS2_SPI2_IRQHandler(void) + { + ASSERT(m_serial_box_2.handler); + m_serial_box_2.handler(); + } +#endif // (SPI2_ENABLED || SPIS2_ENABLED) + +// COMP, LPCOMP +#if (COMP_ENABLED || LPCOMP_ENABLED) + #define COMP_LPCOMP_IN_USE + + #ifndef IS_COMP_LPCOMP + #define IS_COMP_LPCOMP(p_per_base) ((p_per_base) == NRF_LPCOMP) + #endif + + static shared_resource_t m_comp_lpcomp = { .acquired = false }; + void LPCOMP_IRQHandler(void) + { + ASSERT(m_comp_lpcomp.handler); + m_comp_lpcomp.handler(); + } +#endif // (COMP_ENABLED || LPCOMP_ENABLED) + +#if defined(SERIAL_BOX_0_IN_USE) || \ + defined(SERIAL_BOX_1_IN_USE) || \ + defined(SERIAL_BOX_2_IN_USE) || \ + defined(COMP_LPCOMP_IN_USE) +static ret_code_t acquire_shared_resource(shared_resource_t * p_resource, + nrf_drv_irq_handler_t handler) +{ + bool busy = false; + + CRITICAL_REGION_ENTER(); + if (p_resource->acquired) + { + busy = true; + } + else + { + p_resource->acquired = true; + } + CRITICAL_REGION_EXIT(); + + if (busy) + { + return NRF_ERROR_BUSY; + } + + p_resource->handler = handler; + return NRF_SUCCESS; +} +#endif + +ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base, + nrf_drv_irq_handler_t handler) +{ +#ifdef SERIAL_BOX_0_IN_USE + if (IS_SERIAL_BOX_0(p_per_base)) + { + return acquire_shared_resource(&m_serial_box_0, handler); + } +#endif + +#ifdef SERIAL_BOX_1_IN_USE + if (IS_SERIAL_BOX_1(p_per_base)) + { + return acquire_shared_resource(&m_serial_box_1, handler); + } +#endif + +#ifdef SERIAL_BOX_2_IN_USE + if (IS_SERIAL_BOX_2(p_per_base)) + { + return acquire_shared_resource(&m_serial_box_2, handler); + } +#endif + +#ifdef COMP_LPCOMP_IN_USE + if (IS_COMP_LPCOMP(p_per_base)) + { + return acquire_shared_resource(&m_comp_lpcomp, handler); + } +#endif + + return NRF_ERROR_INVALID_PARAM; +} + +void nrf_drv_common_per_res_release(void const * p_per_base) +{ +#ifdef SERIAL_BOX_0_IN_USE + if (IS_SERIAL_BOX_0(p_per_base)) + { + m_serial_box_0.acquired = false; + } + else +#endif + +#ifdef SERIAL_BOX_1_IN_USE + if (IS_SERIAL_BOX_1(p_per_base)) + { + m_serial_box_1.acquired = false; + } + else +#endif + +#ifdef SERIAL_BOX_2_IN_USE + if (IS_SERIAL_BOX_2(p_per_base)) + { + m_serial_box_2.acquired = false; + } + else +#endif + +#ifdef COMP_LPCOMP_IN_USE + if (IS_COMP_LPCOMP(p_per_base)) + { + m_comp_lpcomp.acquired = false; + } + else +#endif + + {} +} + +#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED + + +void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority) +{ + +#ifdef SOFTDEVICE_PRESENT + ASSERT((priority == APP_IRQ_PRIORITY_LOW) || (priority == APP_IRQ_PRIORITY_HIGH)); +#endif + + NVIC_SetPriority(IRQn, priority); + NVIC_ClearPendingIRQ(IRQn); + NVIC_EnableIRQ(IRQn); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.h new file mode 100644 index 0000000..927f401 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/common/nrf_drv_common.h @@ -0,0 +1,194 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_DRV_COMMON_H__ +#define NRF_DRV_COMMON_H__ + +#include +#include +#include "nrf.h" +#include "sdk_errors.h" +#include "nrf_drv_config.h" + + +/** + * @brief Offset of event registers in every peripheral instance + * + * This is the offset where event registers start in the every peripheral. + */ +#define NRF_DRV_COMMON_EVREGS_OFFSET 0x100U + +/** + * @brief Driver state. + */ +typedef enum +{ + NRF_DRV_STATE_UNINITIALIZED, /**< Uninitialized. */ + NRF_DRV_STATE_INITIALIZED, /**< Initialized but powered off. */ + NRF_DRV_STATE_POWERED_ON +} nrf_drv_state_t; + +/** + * @brief Driver power state selection. + */ +typedef enum +{ + NRF_DRV_PWR_CTRL_ON, /**< Power on request. */ + NRF_DRV_PWR_CTRL_OFF /**< Power off request. */ +} nrf_drv_pwr_ctrl_t; + +/** + * @brief IRQ handler type. + */ +typedef void (*nrf_drv_irq_handler_t)(void); + + +#if PERIPHERAL_RESOURCE_SHARING_ENABLED + +/** + * @brief Function for acquiring shared peripheral resources associated with + * the specified peripheral. + * + * Certain resources and registers are shared among peripherals that have + * the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0). + * Only one of them can be utilized at a given time. This function reserves + * proper resources to be used by the specified peripheral. + * If PERIPHERAL_RESOURCE_SHARING_ENABLED is set to a non-zero value, IRQ + * handlers for peripherals that are sharing resources with others are + * implemented by the nrf_drv_common module instead of individual drivers. + * The drivers must then specify their interrupt handling routines and + * register them by using this function. + * + * @param[in] p_per_base Requested peripheral base pointer. + * @param[in] handler Interrupt handler to register. May be NULL + * if interrupts are not used for the peripheral. + * + * @retval NRF_SUCCESS If resources were acquired successfully. + * @retval NRF_ERROR_BUSY If resources were already acquired. + * @retval NRF_ERROR_INVALID_PARAM If the specified peripheral is not enabled + * or the peripheral does not share resources + * with other peripherals. + */ +ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base, + nrf_drv_irq_handler_t handler); + +/** + * @brief Function for releasing shared resources reserved previously by + * @ref nrf_drv_common_per_res_acquire() for the specified peripheral. + * + * @param[in] p_per_base Requested peripheral base pointer. + */ +void nrf_drv_common_per_res_release(void const * p_per_base); + +#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED + + +/** + * @brief Function sets priority and enables NVIC interrupt + * + * @note Function checks if correct priority is used when softdevice is present + * + * @param[in] IRQn Interrupt id + * @param[in] priority Interrupt priority + */ +void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority); + +/** + * @brief Function disables NVIC interrupt + * + * @param[in] IRQn Interrupt id + */ +__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn); + +/** + * @brief Convert bit position to event code + * + * Function for converting the bit position in INTEN register to event code + * that is equivalent to the offset of the event register from the beginning + * of peripheral instance. + * + * For example the result of this function can be casted directly to + * the types like @ref nrf_twis_event_t or @ref nrf_rng_events_t... + * + * @param bit Bit position in INTEN register + * @return Event code to be casted to the right enum type or to be used in functions like + * @ref nrf_rng_event_get + * + * @sa nrf_drv_event_to_bitpos + */ +__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit); + +/** + * @brief Convert event code to bit position + * + * This function can be used to get bit position in INTEN register from event code. + * + * @param event Event code that may be casted from enum values from types like + * @ref nrf_twis_event_t or @ref nrf_rng_events_t + * @return Bit position in INTEN register that corresponds to the given code. + * + * @sa nrf_drv_bitpos_to_event + */ +__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event); + +/** + * @brief Get interrupt number connected with given instance + * + * Function returns interrupt number for a given instance of any peripheral. + * @param[in] pinst Pointer to peripheral registry + * @return Interrupt number + */ +__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst); + +/** + * @brief Check if given object is in RAM + * + * Function for analyzing if given location is placed in RAM. + * This function is used to determine if we have address that can be supported by EasyDMA. + * @param[in] ptr Pointer to the object + * @retval true Object is located in RAM + * @retval false Object is not located in RAM + */ +__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn) +{ + NVIC_DisableIRQ(IRQn); +} + +__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit) +{ + return NRF_DRV_COMMON_EVREGS_OFFSET + bit * sizeof(uint32_t); +} + +__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event) +{ + return (event - NRF_DRV_COMMON_EVREGS_OFFSET) / sizeof(uint32_t); +} + +__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst) +{ + uint8_t ret = (uint8_t)((uint32_t)pinst>>12U); + return (IRQn_Type) ret; +} + +__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr) +{ + return ((((uintptr_t)ptr) & 0xE0000000u) == 0x20000000u); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_DRV_COMMON_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/config/nrf_drv_config.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/config/nrf_drv_config.h new file mode 100644 index 0000000..74e18f9 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/config/nrf_drv_config.h @@ -0,0 +1,464 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_DRV_CONFIG_H +#define NRF_DRV_CONFIG_H + +/** + * Provide a non-zero value here in applications that need to use several + * peripherals with the same ID that are sharing certain resources + * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used + * simultaneously. Therefore, this definition allows to initialize the driver + * for another peripheral from a given group only after the previously used one + * is uninitialized. Normally, this is not possible, because interrupt handlers + * are implemented in individual drivers. + * This functionality requires a more complicated interrupt handling and driver + * initialization, hence it is not always desirable to use it. + */ +#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0 + +/* CLOCK */ +#define CLOCK_ENABLED 0 + +#if (CLOCK_ENABLED == 1) +#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default +#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal +#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + +/* GPIOTE */ +#define GPIOTE_ENABLED 0 + +#if (GPIOTE_ENABLED == 1) +#define GPIOTE_CONFIG_USE_SWI_EGU false +#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +/* TIMER */ +#define TIMER0_ENABLED 0 + +#if (TIMER0_ENABLED == 1) +#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit +#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER0_INSTANCE_INDEX 0 +#endif + +#define TIMER1_ENABLED 0 + +#if (TIMER1_ENABLED == 1) +#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit +#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED) +#endif + +#define TIMER2_ENABLED 0 + +#if (TIMER2_ENABLED == 1) +#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit +#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED) +#endif + +#define TIMER3_ENABLED 0 + +#if (TIMER3_ENABLED == 1) +#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit +#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) +#endif + +#define TIMER4_ENABLED 0 + +#if (TIMER4_ENABLED == 1) +#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit +#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) +#endif + + +#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED) + +/* RTC */ +#define RTC0_ENABLED 0 + +#if (RTC0_ENABLED == 1) +#define RTC0_CONFIG_FREQUENCY 32678 +#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define RTC0_CONFIG_RELIABLE false + +#define RTC0_INSTANCE_INDEX 0 +#endif + +#define RTC1_ENABLED 0 + +#if (RTC1_ENABLED == 1) +#define RTC1_CONFIG_FREQUENCY 32768 +#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define RTC1_CONFIG_RELIABLE false + +#define RTC1_INSTANCE_INDEX (RTC0_ENABLED) +#endif + +#define RTC2_ENABLED 0 + +#if (RTC2_ENABLED == 1) +#define RTC2_CONFIG_FREQUENCY 32768 +#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define RTC2_CONFIG_RELIABLE false + +#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED) +#endif + + +#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED) + +#define NRF_MAXIMUM_LATENCY_US 2000 + +/* RNG */ +#define RNG_ENABLED 0 + +#if (RNG_ENABLED == 1) +#define RNG_CONFIG_ERROR_CORRECTION true +#define RNG_CONFIG_POOL_SIZE 8 +#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + +/* PWM */ + +#define PWM0_ENABLED 0 + +#if (PWM0_ENABLED == 1) +#define PWM0_CONFIG_OUT0_PIN 2 +#define PWM0_CONFIG_OUT1_PIN 3 +#define PWM0_CONFIG_OUT2_PIN 4 +#define PWM0_CONFIG_OUT3_PIN 5 +#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz +#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP +#define PWM0_CONFIG_TOP_VALUE 1000 +#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON +#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO + +#define PWM0_INSTANCE_INDEX 0 +#endif + +#define PWM1_ENABLED 0 + +#if (PWM1_ENABLED == 1) +#define PWM1_CONFIG_OUT0_PIN 2 +#define PWM1_CONFIG_OUT1_PIN 3 +#define PWM1_CONFIG_OUT2_PIN 4 +#define PWM1_CONFIG_OUT3_PIN 5 +#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz +#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP +#define PWM1_CONFIG_TOP_VALUE 1000 +#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON +#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO + +#define PWM1_INSTANCE_INDEX (PWM0_ENABLED) +#endif + +#define PWM2_ENABLED 0 + +#if (PWM2_ENABLED == 1) +#define PWM2_CONFIG_OUT0_PIN 2 +#define PWM2_CONFIG_OUT1_PIN 3 +#define PWM2_CONFIG_OUT2_PIN 4 +#define PWM2_CONFIG_OUT3_PIN 5 +#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz +#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP +#define PWM2_CONFIG_TOP_VALUE 1000 +#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON +#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO + +#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED) +#endif + +#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED) + +/* SPI */ +#define SPI0_ENABLED 0 + +#if (SPI0_ENABLED == 1) +#define SPI0_USE_EASY_DMA 0 + +#define SPI0_CONFIG_SCK_PIN 2 +#define SPI0_CONFIG_MOSI_PIN 3 +#define SPI0_CONFIG_MISO_PIN 4 +#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPI0_INSTANCE_INDEX 0 +#endif + +#define SPI1_ENABLED 0 + +#if (SPI1_ENABLED == 1) +#define SPI1_USE_EASY_DMA 0 + +#define SPI1_CONFIG_SCK_PIN 2 +#define SPI1_CONFIG_MOSI_PIN 3 +#define SPI1_CONFIG_MISO_PIN 4 +#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPI1_INSTANCE_INDEX (SPI0_ENABLED) +#endif + +#define SPI2_ENABLED 0 + +#if (SPI2_ENABLED == 1) +#define SPI2_USE_EASY_DMA 0 + +#define SPI2_CONFIG_SCK_PIN 2 +#define SPI2_CONFIG_MOSI_PIN 3 +#define SPI2_CONFIG_MISO_PIN 4 +#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED) +#endif + +#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED) + +/* SPIS */ +#define SPIS0_ENABLED 0 + +#if (SPIS0_ENABLED == 1) +#define SPIS0_CONFIG_SCK_PIN 2 +#define SPIS0_CONFIG_MOSI_PIN 3 +#define SPIS0_CONFIG_MISO_PIN 4 +#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPIS0_INSTANCE_INDEX 0 +#endif + +#define SPIS1_ENABLED 0 + +#if (SPIS1_ENABLED == 1) +#define SPIS1_CONFIG_SCK_PIN 2 +#define SPIS1_CONFIG_MOSI_PIN 3 +#define SPIS1_CONFIG_MISO_PIN 4 +#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED +#endif + +#define SPIS2_ENABLED 0 + +#if (SPIS2_ENABLED == 1) +#define SPIS2_CONFIG_SCK_PIN 2 +#define SPIS2_CONFIG_MOSI_PIN 3 +#define SPIS2_CONFIG_MISO_PIN 4 +#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED) +#endif + +#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED) + +/* UART */ +#define UART0_ENABLED 0 + +#if (UART0_ENABLED == 1) +#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED +#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED +#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200 +#define UART0_CONFIG_PSEL_TXD 0 +#define UART0_CONFIG_PSEL_RXD 0 +#define UART0_CONFIG_PSEL_CTS 0 +#define UART0_CONFIG_PSEL_RTS 0 +#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#ifdef NRF52 +#define UART0_CONFIG_USE_EASY_DMA false +//Compile time flag +#define UART_EASY_DMA_SUPPORT 1 +#define UART_LEGACY_SUPPORT 1 +#endif //NRF52 +#endif + +#define TWI0_ENABLED 0 + +#if (TWI0_ENABLED == 1) +#define TWI0_USE_EASY_DMA 0 + +#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K +#define TWI0_CONFIG_SCL 0 +#define TWI0_CONFIG_SDA 1 +#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TWI0_INSTANCE_INDEX 0 +#endif + +#define TWI1_ENABLED 0 + +#if (TWI1_ENABLED == 1) +#define TWI1_USE_EASY_DMA 0 + +#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K +#define TWI1_CONFIG_SCL 0 +#define TWI1_CONFIG_SDA 1 +#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TWI1_INSTANCE_INDEX (TWI0_ENABLED) +#endif + +#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED) + +/* TWIS */ +#define TWIS0_ENABLED 0 + +#if (TWIS0_ENABLED == 1) + #define TWIS0_CONFIG_ADDR0 0 + #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */ + #define TWIS0_CONFIG_SCL 0 + #define TWIS0_CONFIG_SDA 1 + #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + + #define TWIS0_INSTANCE_INDEX 0 +#endif + +#define TWIS1_ENABLED 0 + +#if (TWIS1_ENABLED == 1) + #define TWIS1_CONFIG_ADDR0 0 + #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */ + #define TWIS1_CONFIG_SCL 0 + #define TWIS1_CONFIG_SDA 1 + #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + + #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED) +#endif + +#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED) +/* For more documentation see nrf_drv_twis.h file */ +#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +/* For more documentation see nrf_drv_twis.h file */ +#define TWIS_NO_SYNC_MODE 0 + +/* QDEC */ +#define QDEC_ENABLED 0 + +#if (QDEC_ENABLED == 1) +#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10 +#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us +#define QDEC_CONFIG_PIO_A 1 +#define QDEC_CONFIG_PIO_B 2 +#define QDEC_CONFIG_PIO_LED 3 +#define QDEC_CONFIG_LEDPRE 511 +#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH +#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define QDEC_CONFIG_DBFEN false +#define QDEC_CONFIG_SAMPLE_INTEN false +#endif + +/* ADC */ +#define ADC_ENABLED 0 + +#if (ADC_ENABLED == 1) +#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + + +/* SAADC */ +#define SAADC_ENABLED 0 + +#if (SAADC_ENABLED == 1) +#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT +#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED +#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + +/* PDM */ +#define PDM_ENABLED 0 + +#if (PDM_ENABLED == 1) +#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO +#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING +#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K +#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + +/* COMP */ +#define COMP_ENABLED 0 + +#if (COMP_ENABLED == 1) +#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8 +#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE +#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High +#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst +#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off +#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0 +#endif + +/* LPCOMP */ +#define LPCOMP_ENABLED 0 + +#if (LPCOMP_ENABLED == 1) +#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8 +#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN +#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0 +#endif + +/* WDT */ +#define WDT_ENABLED 0 + +#if (WDT_ENABLED == 1) +#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP +#define WDT_CONFIG_RELOAD_VALUE 2000 +#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH +#endif + +/* SWI EGU */ +#ifdef NRF52 + #define EGU_ENABLED 0 +#endif + +/* I2S */ +#define I2S_ENABLED 0 + +#if (I2S_ENABLED == 1) +#define I2S_CONFIG_SCK_PIN 22 +#define I2S_CONFIG_LRCK_PIN 23 +#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED +#define I2S_CONFIG_SDOUT_PIN 24 +#define I2S_CONFIG_SDIN_PIN 25 +#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH +#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER +#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S +#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT +#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT +#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO +#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8 +#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X +#endif + +#include "nrf_drv_config_validation.h" + +#endif // NRF_DRV_CONFIG_H diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/config/nrf_drv_config_validation.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/config/nrf_drv_config_validation.h new file mode 100644 index 0000000..f2b6adc --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/config/nrf_drv_config_validation.h @@ -0,0 +1,83 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_DRV_CONFIG_VALIDATION_H +#define NRF_DRV_CONFIG_VALIDATION_H + +#ifdef NRF52 + +#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \ + ((SPI0_ENABLED + SPIS0_ENABLED + TWI0_ENABLED + TWIS0_ENABLED) > 1) +#error "Peripherals overlap. SPI0, SPIS0, TWI0, TWIS0 - only one of these can be enabled." +#endif + +#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \ + ((SPI1_ENABLED + SPIS1_ENABLED + TWI1_ENABLED + TWIS1_ENABLED) > 1) +#error "Peripherals overlap. SPI1, SPIS1, TWI1, TWIS1 - only one of these can be enabled." +#endif + +#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \ + ((SPI2_ENABLED + SPIS2_ENABLED) > 1) +#error "Peripherals overlap. SPI2, SPIS2 - only one of these can be enabled." +#endif + +#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \ + ((COMP_ENABLED + LPCOMP_ENABLED) > 1) +#error "COMP and LPCOMP cannot be enabled together. Peripherals overlap." +#endif + +#else //NRF51 + +#if (TWIS0_ENABLED + TWIS1_ENABLED) > 0 +#error "TWIS not present in nRF51." +#endif + +#if SPIS0_ENABLED > 0 +#error "SPIS0 instance not present in nRF51." +#endif + +#if (SPI2_ENABLED + SPIS2_ENABLED) > 0 +#error "SPI2/SPIS2 instance not present in nRF51." +#endif + +#if RTC2_ENABLED +#error "RTC2 not present in NRF51." +#endif + +#if (TIMER3_ENABLED + TIMER4_ENABLED) > 0 +#error "TIMER3 and TIMER4 not present in nRF51." +#endif + +#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \ + ((SPI0_ENABLED + TWI0_ENABLED) > 1) +#error "Peripherals overlap. SPI0, TWI0 - only one of these can be enabled." +#endif + +#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \ + ((SPI1_ENABLED + SPIS1_ENABLED + TWI1_ENABLED) > 1) +#error "Peripherals overlap. SPI1, SPIS1, TWI1 - only one of these can be enabled." +#endif + +#if SAADC_ENABLED > 0 +#error "SAADC not present in nRF51." +#endif + +#if I2S_ENABLED > 0 +#error "I2S not present in nRF51." +#endif +#if COMP_ENABLED > 0 +#error "COMP not present in nRF51." +#endif + +#endif //NRF51 + +#endif // NRF_DRV_CONFIG_VALIDATION_H diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.c new file mode 100644 index 0000000..a77e641 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.c @@ -0,0 +1,26 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include +#include "compiler_abstraction.h" +#include "nrf.h" +#include "nrf_delay.h" + +/*lint --e{438} "Variable not used" */ +void nrf_delay_ms(uint32_t volatile number_of_ms) +{ + while(number_of_ms != 0) + { + number_of_ms--; + nrf_delay_us(999); + } +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.h new file mode 100644 index 0000000..30ccc1a --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/delay/nrf_delay.h @@ -0,0 +1,242 @@ +#ifndef _NRF_DELAY_H +#define _NRF_DELAY_H + +#include "nrf.h" + +/** + * @brief Function for delaying execution for number of microseconds. + * + * @note NRF52 has instruction cache and because of that delay is not precise. + * + * @param number_of_ms + */ +/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */ +#if defined ( __CC_ARM ) + +static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us) +{ +loop + SUBS R0, R0, #1 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP +#ifdef NRF52 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP +#endif + BNE loop + BX LR +} + +#elif defined ( __ICCARM__ ) + +static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) +{ +__ASM ( +"loop:\n\t" + " SUBS R0, R0, #1\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" +#ifdef NRF52 + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" +#endif + " BNE.n loop\n\t"); +} + +#elif defined ( _WIN32 ) /*|| defined ( __unix )*/ || defined( __APPLE__ ) + +__STATIC_INLINE void nrf_delay_us(uint32_t volatile number_of_us); + +#ifndef CUSTOM_NRF_DELAY_US +__STATIC_INLINE void nrf_delay_us(uint32_t volatile number_of_us) +{} +#endif + +#elif defined ( __GNUC__ ) + +static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline)); +static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) +{ +register uint32_t delay __ASM ("r0") = number_of_us; +__ASM volatile ( +#ifdef NRF51 + ".syntax unified\n" +#endif + "1:\n" + " SUBS %0, %0, #1\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" +#ifdef NRF52 + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" +#endif + " BNE 1b\n" +#ifdef NRF51 + ".syntax divided\n" +#endif + : "+r" (delay)); +} +#endif + +void nrf_delay_ms(uint32_t volatile number_of_ms); + +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_adc.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_adc.c new file mode 100644 index 0000000..259db2c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_adc.c @@ -0,0 +1,78 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @file + * @brief ADC HAL implementation + */ + +#include "nrf_adc.h" + +#ifndef NRF52 + +/** + * @brief Function for configuring ADC. + * + * This function powers on ADC and configures it. ADC is in DISABLE state after configuration, + * so it should be enabled before using it. + * + * @param[in] config Requested configuration. + */ +void nrf_adc_configure(nrf_adc_config_t * config) +{ + uint32_t config_reg = 0; + + config_reg |= ((uint32_t)config->resolution << ADC_CONFIG_RES_Pos) & ADC_CONFIG_RES_Msk; + config_reg |= ((uint32_t)config->scaling << ADC_CONFIG_INPSEL_Pos) & ADC_CONFIG_INPSEL_Msk; + config_reg |= ((uint32_t)config->reference << ADC_CONFIG_REFSEL_Pos) & ADC_CONFIG_REFSEL_Msk; + + if (config->reference & ADC_CONFIG_EXTREFSEL_Msk) + { + config_reg |= config->reference & ADC_CONFIG_EXTREFSEL_Msk; + } + + /* select input */ + nrf_adc_input_select(NRF_ADC_CONFIG_INPUT_DISABLED); + + /* set new configuration keeping selected input */ + NRF_ADC->CONFIG = config_reg | (NRF_ADC->CONFIG & ADC_CONFIG_PSEL_Msk); +} + + +/** + * @brief Blocking function for executing single ADC conversion. + * + * This function selects the desired input, starts a single conversion, + * waits for it to finish, and returns the result. + * ADC is left in STOP state, the given input is selected. + * This function does not check if ADC is initialized and powered. + * + * @param[in] input Requested input to be selected. + * + * @return Conversion result + */ +int32_t nrf_adc_convert_single(nrf_adc_config_input_t input) +{ + int32_t val; + + nrf_adc_input_select(input); + nrf_adc_start(); + + while (!nrf_adc_conversion_finished()) + { + } + nrf_adc_conversion_event_clean(); + val = nrf_adc_result_get(); + nrf_adc_stop(); + return val; +} +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_adc.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_adc.h new file mode 100644 index 0000000..66da0e6 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_adc.h @@ -0,0 +1,416 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_ADC_H_ +#define NRF_ADC_H_ + +/** + * @defgroup nrf_adc_hal ADC HAL + * @{ + * @ingroup nrf_adc + * @brief @tagAPI51 Hardware access layer for managing the analog-to-digital converter (ADC). + */ + +#include +#include + +#include "nrf.h" + +#ifndef NRF52 +/** + * @enum nrf_adc_config_resolution_t + * @brief Resolution of the analog-to-digital converter. + */ + +/** + * @brief ADC interrupts. + */ +typedef enum +{ + NRF_ADC_INT_END_MASK = ADC_INTENSET_END_Msk, /**< ADC interrupt on END event. */ +} nrf_adc_int_mask_t; + +typedef enum +{ + NRF_ADC_CONFIG_RES_8BIT = ADC_CONFIG_RES_8bit, /**< 8 bit resolution. */ + NRF_ADC_CONFIG_RES_9BIT = ADC_CONFIG_RES_9bit, /**< 9 bit resolution. */ + NRF_ADC_CONFIG_RES_10BIT = ADC_CONFIG_RES_10bit, /**< 10 bit resolution. */ +} nrf_adc_config_resolution_t; + + +/** + * @enum nrf_adc_config_scaling_t + * @brief Scaling factor of the analog-to-digital conversion. + */ +typedef enum +{ + NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE = ADC_CONFIG_INPSEL_AnalogInputNoPrescaling, /**< Full scale input. */ + NRF_ADC_CONFIG_SCALING_INPUT_TWO_THIRDS = ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling, /**< 2/3 scale input. */ + NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD = ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling, /**< 1/3 scale input. */ + NRF_ADC_CONFIG_SCALING_SUPPLY_TWO_THIRDS = ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling, /**< 2/3 of supply. */ + NRF_ADC_CONFIG_SCALING_SUPPLY_ONE_THIRD = ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling /**< 1/3 of supply. */ +} nrf_adc_config_scaling_t; + +/** + * @enum nrf_adc_config_reference_t + * @brief Reference selection of the analog-to-digital converter. + */ +typedef enum +{ + NRF_ADC_CONFIG_REF_VBG = ADC_CONFIG_REFSEL_VBG, /**< 1.2 V reference. */ + NRF_ADC_CONFIG_REF_SUPPLY_ONE_HALF = ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling, /**< 1/2 of power supply. */ + NRF_ADC_CONFIG_REF_SUPPLY_ONE_THIRD = ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling, /**< 1/3 of power supply. */ + NRF_ADC_CONFIG_REF_EXT_REF0 = ADC_CONFIG_REFSEL_External | + ADC_CONFIG_EXTREFSEL_AnalogReference0 << + ADC_CONFIG_EXTREFSEL_Pos, /**< External reference 0. */ + NRF_ADC_CONFIG_REF_EXT_REF1 = ADC_CONFIG_REFSEL_External | + ADC_CONFIG_EXTREFSEL_AnalogReference1 << ADC_CONFIG_EXTREFSEL_Pos, /**< External reference 0. */ +} nrf_adc_config_reference_t; + +/** + * @enum nrf_adc_config_input_t + * @brief Input selection of the analog-to-digital converter. + */ +typedef enum +{ + NRF_ADC_CONFIG_INPUT_DISABLED = ADC_CONFIG_PSEL_Disabled, /**< No input selected. */ + NRF_ADC_CONFIG_INPUT_0 = ADC_CONFIG_PSEL_AnalogInput0, /**< Input 0. */ + NRF_ADC_CONFIG_INPUT_1 = ADC_CONFIG_PSEL_AnalogInput1, /**< Input 1. */ + NRF_ADC_CONFIG_INPUT_2 = ADC_CONFIG_PSEL_AnalogInput2, /**< Input 2. */ + NRF_ADC_CONFIG_INPUT_3 = ADC_CONFIG_PSEL_AnalogInput3, /**< Input 3. */ + NRF_ADC_CONFIG_INPUT_4 = ADC_CONFIG_PSEL_AnalogInput4, /**< Input 4. */ + NRF_ADC_CONFIG_INPUT_5 = ADC_CONFIG_PSEL_AnalogInput5, /**< Input 5. */ + NRF_ADC_CONFIG_INPUT_6 = ADC_CONFIG_PSEL_AnalogInput6, /**< Input 6. */ + NRF_ADC_CONFIG_INPUT_7 = ADC_CONFIG_PSEL_AnalogInput7, /**< Input 7. */ +} nrf_adc_config_input_t; + +/** + * @enum nrf_adc_task_t + * @brief Analog-to-digital converter tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_ADC_TASK_START = offsetof(NRF_ADC_Type, TASKS_START), /**< ADC start sampling task. */ + NRF_ADC_TASK_STOP = offsetof(NRF_ADC_Type, TASKS_STOP) /**< ADC stop sampling task. */ + /*lint -restore*/ +} nrf_adc_task_t; + +/** + * @enum nrf_adc_event_t + * @brief Analog-to-digital converter events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + /*lint -save -e30*/ + NRF_ADC_EVENT_END = offsetof(NRF_ADC_Type, EVENTS_END) /**< End of conversion event. */ + /*lint -restore*/ +} nrf_adc_event_t; + +/**@brief Analog-to-digital converter configuration. */ +typedef struct +{ + nrf_adc_config_resolution_t resolution; /**< ADC resolution. */ + nrf_adc_config_scaling_t scaling; /**< ADC scaling factor. */ + nrf_adc_config_reference_t reference; /**< ADC reference. */ +} nrf_adc_config_t; + +/** Default ADC configuration. */ +#define NRF_ADC_CONFIG_DEFAULT { NRF_ADC_CONFIG_RES_10BIT, \ + NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD, \ + NRF_ADC_CONFIG_REF_VBG } + +/** + * @brief Function for configuring ADC. + * + * This function powers on the analog-to-digital converter and configures it. + * After the configuration, the ADC is in DISABLE state and must be + * enabled before using it. + * + * @param[in] config Configuration parameters. + */ +void nrf_adc_configure(nrf_adc_config_t * config); + +/** + * @brief Blocking function for executing a single ADC conversion. + * + * This function selects the desired input, starts a single conversion, + * waits for it to finish, and returns the result. + * After the input is selected, the analog-to-digital converter + * is left in STOP state. + * The function does not check if the ADC is initialized and powered. + * + * @param[in] input Input to be selected. + * + * @return Conversion result. + */ +int32_t nrf_adc_convert_single(nrf_adc_config_input_t input); + +/** + * @brief Function for selecting ADC input. + * + * This function selects the active input of ADC. Ensure that + * the ADC is powered on and in IDLE state before calling this function. + * + * @param[in] input Input to be selected. + */ +__STATIC_INLINE void nrf_adc_input_select(nrf_adc_config_input_t input) +{ + NRF_ADC->CONFIG = + ((uint32_t)input << ADC_CONFIG_PSEL_Pos) | (NRF_ADC->CONFIG & ~ADC_CONFIG_PSEL_Msk); + + if (input != NRF_ADC_CONFIG_INPUT_DISABLED) + { + NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos; + } + else + { + NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos; + } +} + + +/** + * @brief Function for retrieving the ADC conversion result. + * + * This function retrieves and returns the last analog-to-digital conversion result. + * + * @return Last conversion result. + */ +__STATIC_INLINE int32_t nrf_adc_result_get(void) +{ + return (int32_t)NRF_ADC->RESULT; +} + + +/** + * @brief Function for checking whether the ADC is busy. + * + * This function checks whether the analog-to-digital converter is busy with a conversion. + * + * @retval true If the ADC is busy. + * @retval false If the ADC is not busy. + */ +__STATIC_INLINE bool nrf_adc_is_busy(void) +{ + return ( (NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) == ADC_BUSY_BUSY_Msk); +} + +/** + * @brief Function for getting the ADC's enabled interrupts. + * + * @param[in] mask Mask of interrupts to check. + * + * @return State of the interrupts selected by the mask. + * + * @sa nrf_adc_int_enable() + * @sa nrf_adc_int_disable() + */ +__STATIC_INLINE uint32_t nrf_adc_int_get(uint32_t mask) +{ + return (NRF_ADC->INTENSET & mask); // when read this register will return the value of INTEN. +} + + +/** + * @brief Function for starting conversion. + * + * @sa nrf_adc_stop() + * + */ +__STATIC_INLINE void nrf_adc_start(void) +{ + NRF_ADC->TASKS_START = 1; +} + + +/** + * @brief Function for stopping conversion. + * + * If the analog-to-digital converter is in inactive state, power consumption is reduced. + * + * @sa nrf_adc_start() + * + */ +__STATIC_INLINE void nrf_adc_stop(void) +{ + NRF_ADC->TASKS_STOP = 1; +} + + +/** + * @brief Function for checking if the requested ADC conversion has ended. + * + * @retval true If the task has finished. + * @retval false If the task is still running. + */ +__STATIC_INLINE bool nrf_adc_conversion_finished(void) +{ + return ((bool)NRF_ADC->EVENTS_END); +} + +/** + * @brief Function for clearing the conversion END event. + */ +__STATIC_INLINE void nrf_adc_conversion_event_clean(void) +{ + NRF_ADC->EVENTS_END = 0; +} + +/** + * @brief Function for getting the address of an ADC task register. + * + * @param[in] adc_task ADC task. + * + * @return Address of the specified ADC task. + */ +__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task); + +/** + * @brief Function for getting the address of a specific ADC event register. + * + * @param[in] adc_event ADC event. + * + * @return Address of the specified ADC event. + */ +__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event); + +/** + * @brief Function for setting the CONFIG register in ADC. + * + * @param[in] configuration Value to be written to the CONFIG register. + */ +__STATIC_INLINE void nrf_adc_config_set(uint32_t configuration); + +/** + * @brief Function for clearing an ADC event. + * + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event); + +/** + * @brief Function for checking state of an ADC event. + * + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] int_mask Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_adc_int_enable_check(nrf_adc_int_mask_t int_mask); + +/** + * @brief Function for activating a specific ADC task. + * + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task); + +/** + * @brief Function for enabling ADC. + * + */ +__STATIC_INLINE void nrf_adc_enable(void); + +/** + * @brief Function for disabling ADC. + * + */ +__STATIC_INLINE void nrf_adc_disable(void); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task) +{ + return (uint32_t)((uint8_t *)NRF_ADC + adc_task); +} + +__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event) +{ + return (uint32_t)((uint8_t *)NRF_ADC + adc_event); +} + +__STATIC_INLINE void nrf_adc_config_set(uint32_t configuration) +{ + NRF_ADC->CONFIG = configuration; +} + +__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event); +} + +__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask) +{ + NRF_ADC->INTENSET = int_mask; +} + +__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask) +{ + NRF_ADC->INTENCLR = int_mask; +} + +__STATIC_INLINE bool nrf_adc_int_enable_check(nrf_adc_int_mask_t int_mask) +{ + return (bool)(NRF_ADC->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE void nrf_adc_enable(void) +{ + NRF_ADC->ENABLE = 1; +} + +__STATIC_INLINE void nrf_adc_disable(void) +{ + NRF_ADC->ENABLE = 0; +} +#endif +#endif /* NRF52 */ +/** + *@} + **/ + +#endif /* NRF_ADC_H_ */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_clock.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_clock.h new file mode 100644 index 0000000..902442c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_clock.h @@ -0,0 +1,414 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_CLOCK_H__ +#define NRF_CLOCK_H__ + +#include +#include + +#include "nrf.h" + +/** + * @defgroup nrf_clock_hal Clock HAL + * @{ + * @ingroup nrf_clock + * @brief Hardware access layer for managing the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK). + */ + +#define NRF_CLOCK_TASK_TRIGGER (1UL) +#define NRF_CLOCK_EVENT_CLEAR (0UL) + +/** + * @brief Low-frequency clock sources. + * @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers. + */ +typedef enum +{ + NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */ + NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */ + NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth /**< Internal 32 kHz synthesizer from HFCLK system clock. */ +} nrf_clock_lfclk_t; + +/** + * @brief High-frequency clock sources. + */ +typedef enum +{ + NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_RC, /**< Internal 16 MHz RC oscillator. */ + NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */ +} nrf_clock_hfclk_t; + +/** + * @brief Trigger status of task LFCLKSTART/HFCLKSTART. + * @details Used by LFCLKRUN and HFCLKRUN registers. + */ +typedef enum +{ + NRF_CLOCK_START_TASK_NOT_TRIGGERED = CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */ + NRF_CLOCK_START_TASK_TRIGGERED = CLOCK_LFCLKRUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */ +} nrf_clock_start_task_status_t; + +/** + * @brief Crystal frequency selection. + */ +typedef enum +{ +#ifdef NRF51 + NRF_CLOCK_XTALFREQ_Default = CLOCK_XTALFREQ_XTALFREQ_16MHz, /**< Default. 32 MHz. */ + NRF_CLOCK_XTALFREQ_16MHz = CLOCK_XTALFREQ_XTALFREQ_16MHz, /**< 16 MHz crystal. */ + NRF_CLOCK_XTALFREQ_32MHz = CLOCK_XTALFREQ_XTALFREQ_32MHz /**< 32 MHz crystal. */ +#elif defined NRF52 + NRF_CLOCK_XTALFREQ_Default, /**< Default. 64MHz. */ +#endif +} nrf_clock_xtalfreq_t; + +/** + * @brief Interrupts. + */ +typedef enum +{ + NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */ + NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */ + NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */ + NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk /**< Interrupt on CTTO event. */ +} nrf_clock_int_mask_t; + +/** + * @brief Tasks. + * + * @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running. + * The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/ + NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source.*/ + NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source.*/ + NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source.*/ + NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator.*/ + NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer.*/ + NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer.*/ +} nrf_clock_task_t; /*lint -restore */ + +/** + * @brief Events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/ + NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/ + NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed.*/ + NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO) /**< Calibration timer time-out.*/ +} nrf_clock_event_t; /*lint -restore */ + +/** + * @brief Function for enabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask); + +/** + * @brief Function for disabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a specific interrupt. + * + * @param[in] int_mask Interrupt. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask); + +/** + * @brief Function for retrieving the address of a specific task. + * @details This function can be used by the PPI module. + * + * @param[in] task Task. + * + * @return Address of the requested task register. + */ +__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task); + +/** + * @brief Function for setting a specific task. + * + * @param[in] task Task. + */ +__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task); + +/** + * @brief Function for retrieving the address of a specific event. + * @details This function can be used by the PPI module. + * + * @param[in] event Event. + * + * @return Address of the requested event register. + */ +__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event); + +/** + * @brief Function for clearing a specific event. + * + * @param[in] event Event. + */ +__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event); + +/** + * @brief Function for retrieving the state of a specific event. + * + * @param[in] event Event. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event); + +/** + * @brief Function for changing the low-frequency clock source. + * @details This function cannot be called when the low-frequency clock is running. + * + * @param[in] source New low-frequency clock source. + * + */ +__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source); + +/** + * @brief Function for retrieving the selected source for the low-frequency clock. + * + * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the selected source for the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the selected source for the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the selected source for the low-frequency clock. + */ +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void); + +/** + * @brief Function for retrieving the active source of the low-frequency clock. + * + * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the active source of the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the active source of the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the active source of the low-frequency clock. + */ +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void); + +/** + * @brief Function for retrieving the clock source for the LFCLK clock when the task LKCLKSTART is triggered. + * + * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is running and generating the LFCLK clock. + * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is running and generating the LFCLK clock. + * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is running and generating the LFCLK clock. + */ +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void); + +/** + * @brief Function for retrieving the state of the LFCLK clock. + * + * @retval false If the LFCLK clock is not running. + * @retval true If the LFCLK clock is running. + */ +__STATIC_INLINE bool nrf_clock_lf_is_running(void); + +/** + * @brief Function for retrieving the trigger status of the task LFCLKSTART. + * + * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task LFCLKSTART has not been triggered. + * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task LFCLKSTART has been triggered. + */ +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void); + +/** + * @brief Function for retrieving the active source of the high-frequency clock. + * + * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY If the internal 16 MHz RC oscillator is the active source of the high-frequency clock. + * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY If an external 16 MHz/32 MHz crystal oscillator is the active source of the high-frequency clock. + */ +__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void); + +/** + * @brief Function for retrieving the state of the HFCLK clock. + * + * @param[in] clk_src Clock source to be checked. + * + * @retval false If the HFCLK clock is not running. + * @retval true If the HFCLK clock is running. + */ +__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src); + +/** + * @brief Function for retrieving the trigger status of the task HFCLKSTART. + * + * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task HFCLKSTART has not been triggered. + * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task HFCLKSTART has been triggered. + */ +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void); + +/** + * @brief Function for retrieving the frequency selection of the external crystal. + * + * @retval NRF_CLOCK_XTALFREQ_16MHz If a 16 MHz crystal is used as source for the HFCLK oscillator. + * @retval NRF_CLOCK_XTALFREQ_32MHz If a 32 MHz crystal is used as source for the HFCLK oscillator. + */ +__STATIC_INLINE nrf_clock_xtalfreq_t nrf_clock_xtalfreq_get(void); + +/** + * @brief Function for changing the frequency selection of the external crystal. + * + * @param[in] xtalfreq New frequency selection for the external crystal. + */ +__STATIC_INLINE void nrf_clock_xtalfreq_set(nrf_clock_xtalfreq_t xtalfreq); + +/** + * @brief Function for changing the calibration timer interval. + * + * @param[in] interval New calibration timer interval in 0.25 s resolution (range: 0.25 seconds to 31.75 seconds). + */ +__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask) +{ + NRF_CLOCK->INTENSET = int_mask; +} + +__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask) +{ + NRF_CLOCK->INTENCLR = int_mask; +} + +__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask) +{ + return (bool)(NRF_CLOCK->INTENCLR & int_mask); +} + +__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task) +{ + return ((uint32_t )NRF_CLOCK + task); +} + +__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = NRF_CLOCK_TASK_TRIGGER; +} + +__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event) +{ + return ((uint32_t)NRF_CLOCK + event); +} + +__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = NRF_CLOCK_EVENT_CLEAR; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event) +{ + return (bool)*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)); +} + +__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source) +{ + NRF_CLOCK->LFCLKSRC = + (uint32_t)((source << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk); +} + +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void) +{ + return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRC & + CLOCK_LFCLKSRC_SRC_Msk) >> CLOCK_LFCLKSRC_SRC_Pos); +} + +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void) +{ + return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSTAT & + CLOCK_LFCLKSTAT_SRC_Msk) >> CLOCK_LFCLKSTAT_SRC_Pos); +} + +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void) +{ + return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRCCOPY & + CLOCK_LFCLKSRCCOPY_SRC_Msk) >> CLOCK_LFCLKSRCCOPY_SRC_Pos); +} + +__STATIC_INLINE bool nrf_clock_lf_is_running(void) +{ + return ((NRF_CLOCK->LFCLKSTAT & + CLOCK_LFCLKSTAT_STATE_Msk) >> CLOCK_LFCLKSTAT_STATE_Pos); +} + +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void) +{ + return (nrf_clock_start_task_status_t)((NRF_CLOCK->LFCLKRUN & + CLOCK_LFCLKRUN_STATUS_Msk) >> + CLOCK_LFCLKRUN_STATUS_Pos); +} + +__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void) +{ + return (nrf_clock_hfclk_t)((NRF_CLOCK->HFCLKSTAT & + CLOCK_HFCLKSTAT_SRC_Msk) >> CLOCK_HFCLKSTAT_SRC_Pos); +} + +__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src) +{ + return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) == + (CLOCK_HFCLKSTAT_STATE_Msk | (clk_src << CLOCK_HFCLKSTAT_SRC_Pos)); +} + +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void) +{ + return (nrf_clock_start_task_status_t)((NRF_CLOCK->HFCLKRUN & + CLOCK_HFCLKRUN_STATUS_Msk) >> + CLOCK_HFCLKRUN_STATUS_Pos); +} + +__STATIC_INLINE nrf_clock_xtalfreq_t nrf_clock_xtalfreq_get(void) +{ +#ifdef NRF51 + return (nrf_clock_xtalfreq_t)((NRF_CLOCK->XTALFREQ & + CLOCK_XTALFREQ_XTALFREQ_Msk) >> CLOCK_XTALFREQ_XTALFREQ_Pos); +#elif defined NRF52 + return NRF_CLOCK_XTALFREQ_Default; +#endif +} + +__STATIC_INLINE void nrf_clock_xtalfreq_set(nrf_clock_xtalfreq_t xtalfreq) +{ +#ifdef NRF51 + NRF_CLOCK->XTALFREQ = + (uint32_t)((xtalfreq << CLOCK_XTALFREQ_XTALFREQ_Pos) & CLOCK_XTALFREQ_XTALFREQ_Msk); +#elif defined NRF52 + return; +#endif +} + +__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval) +{ + NRF_CLOCK->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** + *@} + **/ +#endif // NRF_CLOCK_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_comp.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_comp.h new file mode 100644 index 0000000..b4c83b8 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_comp.h @@ -0,0 +1,469 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @file + * @brief COMP HAL API. + */ + +#ifndef NRF_COMP_H_ +#define NRF_COMP_H_ + +/** + * @defgroup nrf_comp_hal COMP HAL + * @{ + * @ingroup nrf_comp + * @brief @tagAPI52 Hardware access layer for managing the Comparator (COMP). + */ + +#include "nrf.h" + +#include +#include +#include + +/** + * @enum nrf_comp_input_t + * @brief COMP analog pin selection. + */ +typedef enum +{ + NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */ + NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */ + NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */ + NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */ + NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */ + NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */ + NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */ + NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7 /*!< AIN7 selected as analog input. */ +}nrf_comp_input_t; + +/** + * @enum nrf_comp_ref_t + * @brief COMP reference selection. + */ +typedef enum +{ + NRF_COMP_REF_Int1V2 = COMP_REFSEL_REFSEL_Int1V2, /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V). */ + NRF_COMP_REF_Int1V8 = COMP_REFSEL_REFSEL_Int1V8, /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V). */ + NRF_COMP_REF_Int2V4 = COMP_REFSEL_REFSEL_Int2V4, /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V). */ + NRF_COMP_REF_VDD = COMP_REFSEL_REFSEL_VDD, /*!< VREF = VDD. */ + NRF_COMP_REF_ARef = COMP_REFSEL_REFSEL_ARef /*!< VREF = AREF (VDD >= VREF >= AREFMIN). */ +}nrf_comp_ref_t; + +/** + * @enum nrf_comp_ext_ref_t + * @brief COMP external analog reference selection. + */ +typedef enum +{ + NRF_COMP_EXT_REF_0 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference0, /*!< Use AIN0 as external analog reference. */ + NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 /*!< Use AIN1 as external analog reference. */ +}nrf_comp_ext_ref_t; + +/** + * @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP. + */ +typedef struct +{ + uint8_t th_down; /*!< THDOWN value. */ + uint8_t th_up; /*!< THUP value. */ +}nrf_comp_th_t; + +/** + * @enum nrf_comp_main_mode_t + * @brief COMP main operation mode. + */ +typedef enum +{ + NRF_COMP_MAIN_MODE_SE = COMP_MODE_MAIN_SE, /*!< Single ended mode. */ + NRF_COMP_MAIN_MODE_Diff = COMP_MODE_MAIN_Diff /*!< Differential mode. */ +}nrf_comp_main_mode_t; + +/** + * @enum nrf_comp_sp_mode_t + * @brief COMP speed and power mode. + */ +typedef enum +{ + NRF_COMP_SP_MODE_Low = COMP_MODE_SP_Low, /*!< Low power mode. */ + NRF_COMP_SP_MODE_Normal = COMP_MODE_SP_Normal, /*!< Normal mode. */ + NRF_COMP_SP_MODE_High = COMP_MODE_SP_High /*!< High speed mode. */ +}nrf_comp_sp_mode_t; + +/** + * @enum nrf_comp_hyst_t + * @brief COMP comparator hysteresis. + */ +typedef enum +{ + NRF_COMP_HYST_NoHyst = COMP_HYST_HYST_NoHyst, /*!< Comparator hysteresis disabled. */ + NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV /*!< Comparator hysteresis enabled. */ +}nrf_comp_hyst_t; + +/** + * @brief COMP current source selection on analog input. + */ +typedef enum +{ + NRF_COMP_ISOURCE_Off = COMP_ISOURCE_ISOURCE_Off, /*!< Current source disabled. */ + NRF_COMP_ISOURCE_Ien2uA5 = COMP_ISOURCE_ISOURCE_Ien2mA5, /*!< Current source enabled (+/- 2.5 uA). */ + NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA, /*!< Current source enabled (+/- 5 uA). */ + NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA /*!< Current source enabled (+/- 10 uA). */ +}nrf_isource_t; + +/** + * @enum nrf_comp_task_t + * @brief COMP tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_COMP_TASK_START = offsetof(NRF_COMP_Type, TASKS_START), /*!< COMP start sampling task. */ + NRF_COMP_TASK_STOP = offsetof(NRF_COMP_Type, TASKS_STOP), /*!< COMP stop sampling task. */ + NRF_COMP_TASK_SAMPLE = offsetof(NRF_COMP_Type, TASKS_SAMPLE) /*!< Sample comparator value. */ + /*lint -restore*/ +}nrf_comp_task_t; + +/** + * @enum nrf_comp_event_t + * @brief COMP events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_COMP_EVENT_READY = offsetof(NRF_COMP_Type, EVENTS_READY), /*!< COMP is ready and output is valid. */ + NRF_COMP_EVENT_DOWN = offsetof(NRF_COMP_Type, EVENTS_DOWN), /*!< Input voltage crossed the threshold going down. */ + NRF_COMP_EVENT_UP = offsetof(NRF_COMP_Type, EVENTS_UP), /*!< Input voltage crossed the threshold going up. */ + NRF_COMP_EVENT_CROSS = offsetof(NRF_COMP_Type, EVENTS_CROSS) /*!< Input voltage crossed the threshold in any direction. */ + /*lint -restore*/ +}nrf_comp_event_t; + +/** + * @brief COMP reference configuration. + */ +typedef struct +{ + nrf_comp_ref_t reference; /*!< COMP reference selection. */ + nrf_comp_ext_ref_t external; /*!< COMP external analog reference selection. */ +}nrf_comp_ref_conf_t; + + +/** + * @brief Function for enabling the COMP peripheral. + */ +__STATIC_INLINE void nrf_comp_enable(void); + + +/** + * @brief Function for disabling the COMP peripheral. + */ + +__STATIC_INLINE void nrf_comp_disable(void); + +/** + * @brief Function for checking if the COMP peripheral is enabled. + * + * @retval true If the COMP peripheral is enabled. + * @retval false If the COMP peripheral is not enabled. + */ +__STATIC_INLINE bool nrf_comp_enable_check(void); + +/** + * @brief Function for setting the reference source. + * + * @param[in] reference COMP reference selection. + */ +__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference); + + +/** + * @brief Function for setting the external analog reference source. + * + * @param[in] ext_ref COMP external analog reference selection. + */ +__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref); + + +/** + * @brief Function for setting threshold voltages. + * + * @param[in] threshold COMP VDOWN and VUP thresholds. + */ +__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold); + + +/** + * @brief Function for setting the main mode. + * + * @param[in] main_mode COMP main operation mode. + */ +__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode); + + +/** + * @brief Function for setting the speed mode. + * + * @param[in] speed_mode COMP speed and power mode. + */ +__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode); + + +/** + * @brief Function for setting the hysteresis. + * + * @param[in] hyst COMP comparator hysteresis. + */ +__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst); + + +/** + * @brief Function for setting the current source on the analog input. + * + * @param[in] isource COMP current source selection on analog input. + */ +__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource); + + +/** + * @brief Function for selecting the active input of the COMP. + * + * @param[in] input Input to be selected. + */ +__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input); + + +/** + * @brief Function for getting the last COMP compare result. + * + * @return The last compare result. If 0, then VIN+ < VIN-. If 1, then VIN+ > VIN-. + * + * @note If VIN+ == VIN-, the return value depends on the previous result. + */ +__STATIC_INLINE uint32_t nrf_comp_result_get(void); + + +/** + * @brief Function for enabling interrupts from COMP. + * + * @param[in] comp_int_mask Mask of interrupts to be enabled. + * + * @sa nrf_comp_int_enable_check() + */ +__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask); + +/** + * @brief Function for disabling interrupts from COMP. + * + * @param[in] comp_int_mask Mask of interrupts to be disabled. + * + * @sa nrf_comp_int_enable_check() + */ +__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask); + + +/** + * @brief Function for getting the enabled interrupts of COMP. + * + * @param[in] comp_int_mask Mask of interrupts to be checked. + * + * @retval true If any interrupts of the specified mask are enabled. + */ +__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask); + + + +/** + * @brief Function for getting the address of a specific COMP task register. + * + * @param[in] comp_task COMP task. + * + * @return Address of the specified COMP task. + */ +__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task); + + +/** + * @brief Function for getting the address of a specific COMP event register. + * + * @param[in] comp_event COMP event. + * + * @return Address of the specified COMP event. + */ +__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event); + + +/** + * @brief Function for setting COMP shorts. + * + * @param[in] comp_short_mask COMP shorts by mask. + * + */ +__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask); + + +/** + * @brief Function for clearing COMP shorts by mask. + * + * @param[in] comp_short_mask COMP shorts to be cleared. + * + */ +__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask); + + +/** + * @brief Function for setting a specific COMP task. + * + * @param[in] comp_task COMP task to be set. + * + */ +__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task); + + +/** + * @brief Function for clearing a specific COMP event. + * + * @param[in] comp_event COMP event to be cleared. + * + */ +__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event); + + +/** + * @brief Function for getting the state of a specific COMP event. + * + * @retval true If the specified COMP event is active. + * + */ +__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_comp_enable(void) +{ + NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Enabled << COMP_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_comp_disable(void) +{ + NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Disabled << COMP_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE bool nrf_comp_enable_check(void) +{ + return ((NRF_COMP->ENABLE) & COMP_ENABLE_ENABLE_Enabled); +} + +__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference) +{ + NRF_COMP->REFSEL = (reference << COMP_REFSEL_REFSEL_Pos); +} + +__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref) +{ + NRF_COMP->EXTREFSEL = (ext_ref << COMP_EXTREFSEL_EXTREFSEL_Pos); +} + +__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold) +{ + NRF_COMP->TH = + ((threshold.th_down << COMP_TH_THDOWN_Pos) & COMP_TH_THDOWN_Msk) | + ((threshold.th_up << COMP_TH_THUP_Pos) & COMP_TH_THUP_Msk); +} + +__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode) +{ + NRF_COMP->MODE |= (main_mode << COMP_MODE_MAIN_Pos); +} + +__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode) +{ + NRF_COMP->MODE |= (speed_mode << COMP_MODE_SP_Pos); +} + +__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst) +{ + NRF_COMP->HYST = (hyst << COMP_HYST_HYST_Pos) & COMP_HYST_HYST_Msk; +} + +__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource) +{ + NRF_COMP->ISOURCE = (isource << COMP_ISOURCE_ISOURCE_Pos) & COMP_ISOURCE_ISOURCE_Msk; +} + +__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input) +{ + NRF_COMP->PSEL = ((uint32_t)input << COMP_PSEL_PSEL_Pos); +} + +__STATIC_INLINE uint32_t nrf_comp_result_get(void) +{ + return (uint32_t)NRF_COMP->RESULT; +} + +__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask) +{ + NRF_COMP->INTENSET = comp_int_mask; +} + +__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask) +{ + NRF_COMP->INTENCLR = comp_int_mask; +} + +__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask) +{ + return (NRF_COMP->INTENSET & comp_int_mask); // when read this register will return the value of INTEN. +} + +__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task) +{ + return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_task); +} + +__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event) +{ + return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event); +} + +__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask) +{ + NRF_COMP->SHORTS |= comp_short_mask; +} + +__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask) +{ + NRF_COMP->SHORTS &= ~comp_short_mask; +} + +__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_task) ) = 1; +} + +__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)comp_event) ) = 0; +} + +__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event) +{ + return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_event)); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** + *@} + **/ + +#endif // NRF_COMP_H_ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.c new file mode 100644 index 0000000..aef68c3 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.c @@ -0,0 +1,74 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. +* +* The information contained herein is property of Nordic Semiconductor ASA. +* Terms and conditions of usage are described in detail in NORDIC +* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. NO +* WARRANTY of ANY KIND is provided. This heading must NOT be removed from +* the file. +* +* $LastChangedRevision: 25419 $ +*/ + +/** + * @file + * @brief Implementation of AES ECB driver + */ + + +//lint -e438 + +#include +#include +#include +#include "nrf.h" +#include "nrf_ecb.h" + +static uint8_t ecb_data[48]; ///< ECB data structure for RNG peripheral to access. +static uint8_t* ecb_key; ///< Key: Starts at ecb_data +static uint8_t* ecb_cleartext; ///< Cleartext: Starts at ecb_data + 16 bytes. +static uint8_t* ecb_ciphertext; ///< Ciphertext: Starts at ecb_data + 32 bytes. + +bool nrf_ecb_init(void) +{ + ecb_key = ecb_data; + ecb_cleartext = ecb_data + 16; + ecb_ciphertext = ecb_data + 32; + + NRF_ECB->ECBDATAPTR = (uint32_t)ecb_data; + return true; +} + + +bool nrf_ecb_crypt(uint8_t * dest_buf, const uint8_t * src_buf) +{ + uint32_t counter = 0x1000000; + if(src_buf != ecb_cleartext) + { + memcpy(ecb_cleartext,src_buf,16); + } + NRF_ECB->EVENTS_ENDECB = 0; + NRF_ECB->TASKS_STARTECB = 1; + while(NRF_ECB->EVENTS_ENDECB == 0) + { + counter--; + if(counter == 0) + { + return false; + } + } + NRF_ECB->EVENTS_ENDECB = 0; + if(dest_buf != ecb_ciphertext) + { + memcpy(dest_buf,ecb_ciphertext,16); + } + return true; +} + +void nrf_ecb_set_key(const uint8_t * key) +{ + memcpy(ecb_key,key,16); +} + + diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.h new file mode 100644 index 0000000..4c88f60 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ecb.h @@ -0,0 +1,66 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is confidential property of Nordic + * Semiconductor ASA.Terms and conditions of usage are described in detail + * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + * $LastChangedRevision: 13999 $ + */ + +/** + * @file + * @brief ECB driver API. + */ + +#ifndef NRF_ECB_H__ +#define NRF_ECB_H__ + +/** + * @defgroup nrf_ecb AES ECB encryption + * @{ + * @ingroup nrf_drivers + * @brief Driver for the AES Electronic Code Book (ECB) peripheral. + * + * To encrypt and decrypt data, the peripheral must first be powered on + * using @ref nrf_ecb_init. Next, the key must be set using @ref nrf_ecb_set_key. + */ + +#include + +/** + * @brief Function for initializing and powering on the ECB peripheral. + * + * This function allocates memory for the ECBDATAPTR. + * @retval true If initialization was successful. + * @retval false If powering on failed. + */ +bool nrf_ecb_init(void); + +/** + * @brief Function for encrypting and decrypting 16-byte data using current key. + * + * This function avoids unnecessary copying of data if the parameters point to the + * correct locations in the ECB data structure. + * + * @param dst Result of encryption/decryption. 16 bytes will be written. + * @param src Source with 16-byte data to be encrypted/decrypted. + * + * @retval true If the encryption operation completed. + * @retval false If the encryption operation did not complete. + */ +bool nrf_ecb_crypt(uint8_t * dst, const uint8_t * src); + +/** + * @brief Function for setting the key to be used for encryption and decryption. + * + * @param key Pointer to the key. 16 bytes will be read. + */ +void nrf_ecb_set_key(const uint8_t * key); + +#endif // NRF_ECB_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_egu.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_egu.h new file mode 100644 index 0000000..1ffe714 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_egu.h @@ -0,0 +1,286 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_EGU_H__ +#define NRF_EGU_H__ + +#ifndef NRF52 + #error EGU is not supported on your chip. +#endif + +/** +* @defgroup nrf_egu EGU (Event Generator Unit) abstraction +* @{ +* @ingroup nrf_drivers +* @brief @tagAPI52 EGU (Event Generator Unit) module functions. +* +*/ + +#include +#include +#include +#include "nrf_assert.h" +#include "nrf.h" + +#define NRF_EGU_COUNT 6 /**< Number of EGU instances. */ +#define NRF_EGU_CHANNEL_COUNT 16 /**< Number of channels per EGU instance. */ + +/** + * @enum nrf_egu_task_t + * @brief EGU tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_EGU_TASK_TRIGGER0 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]), /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */ + NRF_EGU_TASK_TRIGGER1 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]), /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */ + NRF_EGU_TASK_TRIGGER2 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]), /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */ + NRF_EGU_TASK_TRIGGER3 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[3]), /**< Trigger 3 for triggering the corresponding TRIGGERED[3] event. */ + NRF_EGU_TASK_TRIGGER4 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[4]), /**< Trigger 4 for triggering the corresponding TRIGGERED[4] event. */ + NRF_EGU_TASK_TRIGGER5 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[5]), /**< Trigger 5 for triggering the corresponding TRIGGERED[5] event. */ + NRF_EGU_TASK_TRIGGER6 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[6]), /**< Trigger 6 for triggering the corresponding TRIGGERED[6] event. */ + NRF_EGU_TASK_TRIGGER7 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[7]), /**< Trigger 7 for triggering the corresponding TRIGGERED[7] event. */ + NRF_EGU_TASK_TRIGGER8 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[8]), /**< Trigger 8 for triggering the corresponding TRIGGERED[8] event. */ + NRF_EGU_TASK_TRIGGER9 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[9]), /**< Trigger 9 for triggering the corresponding TRIGGERED[9] event. */ + NRF_EGU_TASK_TRIGGER10 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[10]), /**< Trigger 10 for triggering the corresponding TRIGGERED[10] event. */ + NRF_EGU_TASK_TRIGGER11 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[11]), /**< Trigger 11 for triggering the corresponding TRIGGERED[11] event. */ + NRF_EGU_TASK_TRIGGER12 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[12]), /**< Trigger 12 for triggering the corresponding TRIGGERED[12] event. */ + NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */ + NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */ + NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15]) /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */ + /*lint -restore*/ +} nrf_egu_task_t; + + +/** + * @enum nrf_egu_event_t + * @brief EGU events. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_EGU_EVENT_TRIGGERED0 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]), /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */ + NRF_EGU_EVENT_TRIGGERED1 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]), /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */ + NRF_EGU_EVENT_TRIGGERED2 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]), /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */ + NRF_EGU_EVENT_TRIGGERED3 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[3]), /**< Event number 3 generated by triggering the corresponding TRIGGER[3] task. */ + NRF_EGU_EVENT_TRIGGERED4 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[4]), /**< Event number 4 generated by triggering the corresponding TRIGGER[4] task. */ + NRF_EGU_EVENT_TRIGGERED5 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[5]), /**< Event number 5 generated by triggering the corresponding TRIGGER[5] task. */ + NRF_EGU_EVENT_TRIGGERED6 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[6]), /**< Event number 6 generated by triggering the corresponding TRIGGER[6] task. */ + NRF_EGU_EVENT_TRIGGERED7 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[7]), /**< Event number 7 generated by triggering the corresponding TRIGGER[7] task. */ + NRF_EGU_EVENT_TRIGGERED8 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[8]), /**< Event number 8 generated by triggering the corresponding TRIGGER[8] task. */ + NRF_EGU_EVENT_TRIGGERED9 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[9]), /**< Event number 9 generated by triggering the corresponding TRIGGER[9] task. */ + NRF_EGU_EVENT_TRIGGERED10 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[10]), /**< Event number 10 generated by triggering the corresponding TRIGGER[10] task. */ + NRF_EGU_EVENT_TRIGGERED11 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[11]), /**< Event number 11 generated by triggering the corresponding TRIGGER[11] task. */ + NRF_EGU_EVENT_TRIGGERED12 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[12]), /**< Event number 12 generated by triggering the corresponding TRIGGER[12] task. */ + NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */ + NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */ + NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15]) /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */ + /*lint -restore*/ +} nrf_egu_event_t; + + +/** + * @enum nrf_egu_int_mask_t + * @brief EGU interrupts. + */ +typedef enum +{ + NRF_EGU_INT_TRIGGERED0 = EGU_INTENSET_TRIGGERED0_Msk, /**< Interrupt on EVENTS_TRIGGERED[0] event. */ + NRF_EGU_INT_TRIGGERED1 = EGU_INTENSET_TRIGGERED1_Msk, /**< Interrupt on EVENTS_TRIGGERED[1] event. */ + NRF_EGU_INT_TRIGGERED2 = EGU_INTENSET_TRIGGERED2_Msk, /**< Interrupt on EVENTS_TRIGGERED[2] event. */ + NRF_EGU_INT_TRIGGERED3 = EGU_INTENSET_TRIGGERED3_Msk, /**< Interrupt on EVENTS_TRIGGERED[3] event. */ + NRF_EGU_INT_TRIGGERED4 = EGU_INTENSET_TRIGGERED4_Msk, /**< Interrupt on EVENTS_TRIGGERED[4] event. */ + NRF_EGU_INT_TRIGGERED5 = EGU_INTENSET_TRIGGERED5_Msk, /**< Interrupt on EVENTS_TRIGGERED[5] event. */ + NRF_EGU_INT_TRIGGERED6 = EGU_INTENSET_TRIGGERED6_Msk, /**< Interrupt on EVENTS_TRIGGERED[6] event. */ + NRF_EGU_INT_TRIGGERED7 = EGU_INTENSET_TRIGGERED7_Msk, /**< Interrupt on EVENTS_TRIGGERED[7] event. */ + NRF_EGU_INT_TRIGGERED8 = EGU_INTENSET_TRIGGERED8_Msk, /**< Interrupt on EVENTS_TRIGGERED[8] event. */ + NRF_EGU_INT_TRIGGERED9 = EGU_INTENSET_TRIGGERED9_Msk, /**< Interrupt on EVENTS_TRIGGERED[9] event. */ + NRF_EGU_INT_TRIGGERED10 = EGU_INTENSET_TRIGGERED10_Msk, /**< Interrupt on EVENTS_TRIGGERED[10] event. */ + NRF_EGU_INT_TRIGGERED11 = EGU_INTENSET_TRIGGERED11_Msk, /**< Interrupt on EVENTS_TRIGGERED[11] event. */ + NRF_EGU_INT_TRIGGERED12 = EGU_INTENSET_TRIGGERED12_Msk, /**< Interrupt on EVENTS_TRIGGERED[12] event. */ + NRF_EGU_INT_TRIGGERED13 = EGU_INTENSET_TRIGGERED13_Msk, /**< Interrupt on EVENTS_TRIGGERED[13] event. */ + NRF_EGU_INT_TRIGGERED14 = EGU_INTENSET_TRIGGERED14_Msk, /**< Interrupt on EVENTS_TRIGGERED[14] event. */ + NRF_EGU_INT_TRIGGERED15 = EGU_INTENSET_TRIGGERED15_Msk, /**< Interrupt on EVENTS_TRIGGERED[15] event. */ + NRF_EGU_INT_ALL = 0xFFFFuL +} nrf_egu_int_mask_t; + + +/** + * @brief Function for triggering a specific EGU task. + * + * @param NRF_EGUx EGU instance. + * @param egu_task EGU task. + */ +__STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task)) = 0x1UL; +} + + +/** + * @brief Function for returning the address of a specific EGU task register. + * + * @param NRF_EGUx EGU instance. + * @param egu_task EGU task. + */ +__STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx, + nrf_egu_task_t egu_task) +{ + return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task); +} + + +/** + * @brief Function for returning the address of a specific EGU TRIGGER task register. + * + * @param NRF_EGUx EGU instance. + * @param channel Channel number. + */ +__STATIC_INLINE uint32_t * nrf_egu_task_trigger_addres_get(NRF_EGU_Type * NRF_EGUx, + uint8_t channel) +{ + ASSERT(channel < NRF_EGU_CHANNEL_COUNT); + return (uint32_t*)&NRF_EGUx->TASKS_TRIGGER[channel]; +} + + +/** + * @brief Function for returning the specific EGU TRIGGER task. + * + * @param channel Channel number. + */ +__STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(uint8_t channel) +{ + ASSERT(channel <= NRF_EGU_CHANNEL_COUNT); + return (nrf_egu_task_t)((uint32_t) NRF_EGU_TASK_TRIGGER0 + (channel * sizeof(uint32_t))); +} + + +/** + * @brief Function for returning the state of a specific EGU event. + * + * @param NRF_EGUx EGU instance. + * @param egu_event EGU event to check. + */ +__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx, + nrf_egu_event_t egu_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event); +} + + +/** + * @brief Function for clearing a specific EGU event. + * + * @param NRF_EGUx EGU instance. + * @param egu_event EGU event to clear. + */ +__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx, + nrf_egu_event_t egu_event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event)) = 0x0UL; +} + + +/** + * @brief Function for returning the address of a specific EGU event register. + * + * @param NRF_EGUx EGU instance. + * @param egu_event EGU event. + */ +__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx, + nrf_egu_event_t egu_event) +{ + return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event); +} + + +/** + * @brief Function for returning the address of a specific EGU TRIGGERED event register. + * + * @param NRF_EGUx EGU instance. + * @param channel Channel number. + */ +__STATIC_INLINE uint32_t * nrf_egu_event_triggered_addres_get(NRF_EGU_Type * NRF_EGUx, + uint8_t channel) +{ + ASSERT(channel < NRF_EGU_CHANNEL_COUNT); + return (uint32_t*)&NRF_EGUx->EVENTS_TRIGGERED[channel]; +} + + +/** + * @brief Function for returning the specific EGU TRIGGERED event. + * + * @param channel Channel number. + */ +__STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(uint8_t channel) +{ + ASSERT(channel < NRF_EGU_CHANNEL_COUNT); + return (nrf_egu_event_t)((uint32_t) NRF_EGU_EVENT_TRIGGERED0 + (channel * sizeof(uint32_t))); +} + + +/** + * @brief Function for enabling one or more specific EGU interrupts. + * + * @param NRF_EGUx EGU instance. + * @param egu_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask) +{ + NRF_EGUx->INTENSET = egu_int_mask; +} + + +/** + * @brief Function for retrieving the state of one or more EGU interrupts. + * + * @param NRF_EGUx EGU instance. + * @param egu_int_mask Interrupts to check. + * + * @retval true If all of the specified interrupts are enabled. + * @retval false If at least one of the specified interrupts is disabled. + */ +__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask) +{ + return (bool)(NRF_EGUx->INTENSET & egu_int_mask); +} + + +/** + * @brief Function for disabling one or more specific EGU interrupts. + * + * @param NRF_EGUx EGU instance. + * @param egu_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask) +{ + NRF_EGUx->INTENCLR = egu_int_mask; +} + +/** + * @brief Function for retrieving one or more specific EGU interrupts. + * + * @param channel Channel number. + * + * @returns EGU interrupt mask. + */ +__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(uint8_t channel) +{ + ASSERT(channel < NRF_EGU_CHANNEL_COUNT); + return (nrf_egu_int_mask_t)((uint32_t) (EGU_INTENSET_TRIGGERED0_Msk << channel)); +} + +/** @} */ + +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpio.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpio.h new file mode 100644 index 0000000..0d2de6b --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpio.h @@ -0,0 +1,647 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. +* +* The information contained herein is property of Nordic Semiconductor ASA. +* Terms and conditions of usage are described in detail in NORDIC +* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. NO +* WARRANTY of ANY KIND is provided. This heading must NOT be removed from +* the file. +* +*/ +#ifndef NRF_GPIO_H__ +#define NRF_GPIO_H__ + +#include "nrf.h" +#include + +/** + * @defgroup nrf_gpio GPIO abstraction + * @{ + * @ingroup nrf_drivers + * @brief GPIO pin abstraction and port abstraction for reading and writing byte-wise to GPIO ports. + * + * Here, the GPIO ports are defined as follows: + * - Port 0 -> pin 0-7 + * - Port 1 -> pin 8-15 + * - Port 2 -> pin 16-23 + * - Port 3 -> pin 24-31 + */ + +#define NUMBER_OF_PINS 32 + +/** + * @brief Enumerator used for selecting between port 0 - 3. + */ +typedef enum +{ + NRF_GPIO_PORT_SELECT_PORT0 = 0, ///< Port 0 (GPIO pin 0-7) + NRF_GPIO_PORT_SELECT_PORT1, ///< Port 1 (GPIO pin 8-15) + NRF_GPIO_PORT_SELECT_PORT2, ///< Port 2 (GPIO pin 16-23) + NRF_GPIO_PORT_SELECT_PORT3, ///< Port 3 (GPIO pin 24-31) +} nrf_gpio_port_select_t; + +/** + * @brief Enumerator used for setting the direction of a GPIO port. + */ +typedef enum +{ + NRF_GPIO_PORT_DIR_OUTPUT, ///< Output + NRF_GPIO_PORT_DIR_INPUT ///< Input +} nrf_gpio_port_dir_t; + +/** + * @brief Pin direction definitions. + */ +typedef enum +{ + NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input + NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output +} nrf_gpio_pin_dir_t; + +/** + * @brief Connection of input buffer + */ +typedef enum +{ + NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer + NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer +} nrf_gpio_pin_input_t; + +/** + * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration + */ +typedef enum +{ + NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pullup resistor disabled + NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pulldown resistor enabled + NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pullup resistor enabled +} nrf_gpio_pin_pull_t; + +/** + * @brief Enumerator used for selecting output drive mode + */ +typedef enum +{ + NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1' + NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High drive '0', standard '1' + NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high drive '1' + NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high 'drive '1'' + NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1' + NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high drive '1' + NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0'. disconnect '1' + NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High drive '0', disconnect '1' +} nrf_gpio_pin_drive_t; + +/** + * @brief Enumerator used for selecting the pin to sense high or low level on the pin input. + */ +typedef enum +{ + NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled. + NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level. + NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level. +} nrf_gpio_pin_sense_t; + + +/** + * @brief Function for configuring the GPIO pin range as outputs with normal drive strength. + * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * + * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30) + * + * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30) + * + * @note For configuring only one pin as output use @ref nrf_gpio_cfg_output + * Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output. + */ +__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); + +/** + * @brief Function for configuring the GPIO pin range as inputs with given initial value set, hiding inner details. + * This function can be used to configure pin range as simple input. + * + * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30) + * + * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30) + * + * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high) + * + * @note For configuring only one pin as input use @ref nrf_gpio_cfg_input + * Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable + */ +__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config); + +/** + * @brief Pin configuration function + * + * The main pin configuration function. + * This function allows to set any aspect in PIN_CNF register. + * @param pin_number Specifies the pin number (allowed values 0-31). + * @param dir Pin direction + * @param input Connect or disconnect input buffer + * @param pull Pull configuration + * @param drive Drive configuration + * @param sense Pin sensing mechanism + */ +__STATIC_INLINE void nrf_gpio_cfg( + uint32_t pin_number, + nrf_gpio_pin_dir_t dir, + nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, + nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense); + +/** + * @brief Function for configuring the given GPIO pin number as output with given initial value set, hiding inner details. + * This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * + * @param pin_number specifies the pin number (allowed values 0-31) + * + * @note Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output. + */ +__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details. + * This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * + * @param pin_number Specifies the pin number (allowed values 0-30). + * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high). + * + * @note Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable + */ +__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config); + +/** + * @brief Function for reseting pin configuration to its default state. + * + * @param pin_number Specifies the pin number (allowed values 0-31). + */ +__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected. + * + * @param pin_number Specifies the pin number (allowed values 0-31). + * + */ +__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number); + +/** + * @brief Function for disconnecting input for the given GPIO. + * + * @param pin_number Specifies the pin number (allowed values 0-31). + * + */ +__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details. + * This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * Sense capability on the pin is configurable, and input is connected to buffer so that the GPIO->IN register is readable. + * + * @param pin_number Specifies the pin number (allowed values 0-30). + * @param pull_config State of the pin pull resistor (no pull, pulled down or pulled high). + * @param sense_config Sense level of the pin (no sense, sense low or sense high). + */ +__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config); + +/** + * @brief Function for configuring sense level for the given GPIO. + * + * @param pin_number Specifies the pin number of gpio pin numbers to be configured (allowed values 0-30). + * @param sense_config Sense configuration. + * + */ +__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config); + +/** + * @brief Function for setting the direction for a GPIO pin. + * + * @param pin_number specifies the pin number (0-31) for which to + * set the direction. + * + * @param direction specifies the direction + */ +__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction); + +/** + * @brief Function for setting a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number Specifies the pin number (0-31) to set. + */ +__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); + +/** + * @brief Function for setting GPIO pins. + * + * Note that the pins must be configured as outputs for this + * function to have any effect. + * + * @param pin_mask Specifies the pins to set. + */ +__STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask); + +/** + * @brief Function for clearing a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number Specifies the pin number (0-31) to clear. + */ +__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); + +/** + * @brief Function for clearing GPIO pins. + * + * Note that the pins must be configured as outputs for this + * function to have any effect. + * + * @param pin_mask Specifies the pins to clear. + */ +__STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask); + +/** + * @brief Function for toggling a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number Specifies the pin number (0-31) to toggle. + */ +__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); + +/** + * @brief Function for toggling GPIO pins. + * + * Note that the pins must be configured as outputs for this + * function to have any effect. + * + * @param pin_mask Specifies the pins to toggle. + */ +__STATIC_INLINE void nrf_gpio_pins_toggle(uint32_t pin_mask); + +/** + * @brief Function for writing a value to a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number specifies the pin number (0-31) to + * write. + * + * @param value specifies the value to be written to the pin. + * @arg 0 clears the pin + * @arg >=1 sets the pin. + */ +__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); + +/** + * @brief Function for reading the input level of a GPIO pin. + * + * Note that the pin must have input connected for the value + * returned from this function to be valid. + * + * @param pin_number specifies the pin number (0-31) to + * read. + * + * @return + * @retval 0 if the pin input level is low. + * @retval 1 if the pin input level is high. + * @retval > 1 should never occur. + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); + +/** + * @brief Function for reading the input level of all GPIO pins. + * + * Note that the pin must have input connected for the value + * returned from this function to be valid. + * + * @retval Status of input of all pins + */ +__STATIC_INLINE uint32_t nrf_gpio_pins_read(void); + +/** + * @brief Function for reading the sense configuration of a GPIO pin. + * + * @param pin_number specifies the pin number (0-31) to + * read. + * + * @retval Sense configuration + */ +__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number); + +/** + * @brief Generic function for writing a single byte of a 32 bit word at a given + * address. + * + * This function should not be called from outside the nrf_gpio + * abstraction layer. + * + * @param word_address is the address of the word to be written. + * + * @param byte_no is the word byte number (0-3) to be written. + * + * @param value is the value to be written to byte "byte_no" of word + * at address "word_address" + */ +__STATIC_INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value); + +/** + * @brief Generic function for reading a single byte of a 32 bit word at a given + * address. + * + * This function should not be called from outside the nrf_gpio + * abstraction layer. + * + * @param word_address is the address of the word to be read. + * + * @param byte_no is the byte number (0-3) of the word to be read. + * + * @return byte "byte_no" of word at address "word_address". + */ +__STATIC_INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no); + +/** + * @brief Function for setting the direction of a port. + * + * @param port is the port for which to set the direction. + * + * @param dir direction to be set for this port. + */ +__STATIC_INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir); + +/** + * @brief Function for reading a GPIO port. + * + * @param port is the port to read. + * + * @return the input value on this port. + */ +__STATIC_INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port); + +/** + * @brief Function for writing to a GPIO port. + * + * @param port is the port to write. + * + * @param value is the value to write to this port. + * + * @sa nrf_gpio_port_dir_set() + */ +__STATIC_INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value); + +/** + * @brief Function for setting individual pins on GPIO port. + * + * @param port is the port for which to set the pins. + * + * @param set_mask is a mask specifying which pins to set. A bit + * set to 1 indicates that the corresponding port pin shall be + * set. + * + * @sa nrf_gpio_port_dir_set() + */ +__STATIC_INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask); + +/** + * @brief Function for clearing individual pins on GPIO port. + * + * @param port is the port for which to clear the pins. + * + * @param clr_mask is a mask specifying which pins to clear. A bit + * set to 1 indicates that the corresponding port pin shall be + * cleared. + * + * @sa nrf_gpio_port_dir_set() + */ +__STATIC_INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + for (; pin_range_start <= pin_range_end; pin_range_start++) + { + nrf_gpio_cfg_output(pin_range_start); + } +} + +__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + for (; pin_range_start <= pin_range_end; pin_range_start++) + { + nrf_gpio_cfg_input(pin_range_start, pull_config); + } +} + +__STATIC_INLINE void nrf_gpio_cfg( + uint32_t pin_number, + nrf_gpio_pin_dir_t dir, + nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, + nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense) +{ + NRF_GPIO->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); +} + +__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + +__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + pull_config, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + +__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + +__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + NRF_GPIO->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); +} + +__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + NRF_GPIO->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); +} + +__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + pull_config, + NRF_GPIO_PIN_S0S1, + sense_config); +} + +__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + //uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk; + NRF_GPIO->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk; + NRF_GPIO->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos); +} + +__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) +{ + if(direction == NRF_GPIO_PIN_DIR_INPUT) + { + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + } + else + { + NRF_GPIO->DIRSET = (1UL << pin_number); + } +} + +__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) +{ + NRF_GPIO->OUTSET = (1UL << pin_number); +} + +__STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask) +{ + NRF_GPIO->OUTSET = pin_mask; +} + +__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) +{ + NRF_GPIO->OUTCLR = (1UL << pin_number); +} + +__STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask) +{ + NRF_GPIO->OUTCLR = pin_mask; +} + +__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) +{ + nrf_gpio_pins_toggle(1UL << pin_number); +} + +__STATIC_INLINE void nrf_gpio_pins_toggle(uint32_t pin_mask) +{ + uint32_t pins_state = NRF_GPIO->OUT; + NRF_GPIO->OUTSET = (~pins_state & pin_mask); + NRF_GPIO->OUTCLR = ( pins_state & pin_mask); +} + +__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) +{ + if (value == 0) + { + nrf_gpio_pin_clear(pin_number); + } + else + { + nrf_gpio_pin_set(pin_number); + } +} + +__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) +{ + return ((NRF_GPIO->IN >> pin_number) & 1UL); +} + +__STATIC_INLINE uint32_t nrf_gpio_pins_read(void) +{ + return NRF_GPIO->IN; +} + +__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) +{ + return (nrf_gpio_pin_sense_t)((NRF_GPIO->PIN_CNF[pin_number] & GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos); +} + +__STATIC_INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value) +{ + *((volatile uint8_t*)(word_address) + byte_no) = value; +} + +__STATIC_INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no) +{ + return (*((const volatile uint8_t*)(word_address) + byte_no)); +} + +__STATIC_INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir) +{ + if (dir == NRF_GPIO_PORT_DIR_OUTPUT) + { + nrf_gpio_word_byte_write(&NRF_GPIO->DIRSET, port, 0xFF); + } + else + { + nrf_gpio_range_cfg_input(port*8, (port+1)*8-1, NRF_GPIO_PIN_NOPULL); + } +} + +__STATIC_INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port) +{ + return nrf_gpio_word_byte_read(&NRF_GPIO->IN, port); +} + +__STATIC_INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value) +{ + nrf_gpio_word_byte_write(&NRF_GPIO->OUT, port, value); +} + +__STATIC_INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask) +{ + nrf_gpio_word_byte_write(&NRF_GPIO->OUTSET, port, set_mask); +} + +__STATIC_INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask) +{ + nrf_gpio_word_byte_write(&NRF_GPIO->OUTCLR, port, clr_mask); +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION +/** @} */ + +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpiote.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpiote.h new file mode 100644 index 0000000..a525f6e --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_gpiote.h @@ -0,0 +1,391 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#ifndef NRF_GPIOTE_H__ +#define NRF_GPIOTE_H__ + +#include "nrf.h" +#include +#include +#include + +/** +* @defgroup nrf_gpiote_abs GPIOTE abstraction +* @{ +* @ingroup nrf_gpiote +* @brief GPIOTE abstraction for configuration of channels. +*/ +#ifdef NRF51 +#define NUMBER_OF_GPIO_TE 4 +#elif defined(NRF52) +#define NUMBER_OF_GPIO_TE 8 +#else +#error "Chip family not specified" +#endif + + /** + * @enum nrf_gpiote_polarity_t + * @brief Polarity for the GPIOTE channel. + */ +typedef enum +{ + NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high. + NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low. + NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle ///< Toggle. +} nrf_gpiote_polarity_t; + + + /** + * @enum nrf_gpiote_outinit_t + * @brief Initial output value for the GPIOTE channel. + */ +typedef enum +{ + NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high. + NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High ///< High to low. +} nrf_gpiote_outinit_t; + +/** + * @brief Tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_GPIOTE_TASKS_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/ + NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/ + NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/ + NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/ +#if (NUMBER_OF_GPIO_TE == 8) + NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/ + NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/ + NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/ + NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/ +#endif +#ifdef NRF52 + NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/ + NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/ + NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/ + NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/ + NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/ + NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/ + NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/ + NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/ + NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/ + NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/ + NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/ + NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/ + NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/ + NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/ + NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/ + NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/ +#endif + /*lint -restore*/ +} nrf_gpiote_tasks_t; + +/** + * @brief Events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_GPIOTE_EVENTS_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/ + NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/ + NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/ + NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/ +#if (NUMBER_OF_GPIO_TE == 8) + NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/ + NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/ + NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/ + NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/ +#endif + NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event.*/ + /*lint -restore*/ +} nrf_gpiote_events_t; + +/** + * @enum nrf_gpiote_int_t + * @brief GPIOTE interrupts. + */ +typedef enum +{ + NRF_GPIOTE_INT_IN0_MASK = GPIOTE_INTENSET_IN0_Msk, /**< GPIOTE interrupt from IN0. */ + NRF_GPIOTE_INT_IN1_MASK = GPIOTE_INTENSET_IN1_Msk, /**< GPIOTE interrupt from IN1. */ + NRF_GPIOTE_INT_IN2_MASK = GPIOTE_INTENSET_IN2_Msk, /**< GPIOTE interrupt from IN2. */ + NRF_GPIOTE_INT_IN3_MASK = GPIOTE_INTENSET_IN3_Msk, /**< GPIOTE interrupt from IN3. */ +#if (NUMBER_OF_GPIO_TE == 8) + NRF_GPIOTE_INT_IN4_MASK = GPIOTE_INTENSET_IN4_Msk, /**< GPIOTE interrupt from IN4. */ + NRF_GPIOTE_INT_IN5_MASK = GPIOTE_INTENSET_IN5_Msk, /**< GPIOTE interrupt from IN5. */ + NRF_GPIOTE_INT_IN6_MASK = GPIOTE_INTENSET_IN6_Msk, /**< GPIOTE interrupt from IN6. */ + NRF_GPIOTE_INT_IN7_MASK = GPIOTE_INTENSET_IN7_Msk, /**< GPIOTE interrupt from IN7. */ +#endif + NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */ +} nrf_gpiote_int_t; + +#if (NUMBER_OF_GPIO_TE == 4) +#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\ + NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK) +#elif (NUMBER_OF_GPIO_TE == 8) +#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\ + NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\ + NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\ + NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK) +#else +#error "Unexpected number of GPIO Tasks and Events" +#endif +/** + * @brief Function for activating a specific GPIOTE task. + * + * @param[in] task Task. + */ +__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task); + +/** + * @brief Function for getting the address of a specific GPIOTE task. + * + * @param[in] task Task. + * + * @returns Address. + */ +__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task); + +/** + * @brief Function for getting the state of a specific GPIOTE event. + * + * @param[in] event Event. + */ +__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event); + +/** + * @brief Function for clearing a specific GPIOTE event. + * + * @param[in] event Event. + */ +__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event); + +/** + * @brief Function for getting the address of a specific GPIOTE event. + * + * @param[in] event Event. + * + * @return Address + */ +__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event); + +/**@brief Function for enabling interrupts. + * + * @param[in] mask Interrupt mask to be enabled. + */ +__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask); + +/**@brief Function for disabling interrupts. + * + * @param[in] mask Interrupt mask to be disabled. + */ +__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask); + +/**@brief Function for checking if interrupts are enabled. + * + * @param[in] mask Mask of interrupt flags to check. + * + * @return Mask with enabled interrupts. + */ +__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask); + +/**@brief Function for enabling a GPIOTE event. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx); + +/**@brief Function for disabling a GPIOTE event. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx); + +/**@brief Function for configuring a GPIOTE event. + * + * @param[in] idx Task-Event index. + * @param[in] pin Pin associated with event. + * @param[in] polarity Transition that should generate an event. + */ +__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, + nrf_gpiote_polarity_t polarity); + +/**@brief Function for getting the pin associated with a GPIOTE event. + * + * @param[in] idx Task-Event index. + * + * @return Pin number. + */ +__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx); + +/**@brief Function for getting the polarity associated with a GPIOTE event. + * + * @param[in] idx Task-Event index. + * + * @return Polarity. + */ +__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx); + +/**@brief Function for enabling a GPIOTE task. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx); + +/**@brief Function for disabling a GPIOTE task. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx); + +/**@brief Function for configuring a GPIOTE task. + * @note Function is not configuring mode field so task is disabled after this function is called. + * + * @param[in] idx Task-Event index. + * @param[in] pin Pin associated with event. + * @param[in] polarity Transition that should generate an event. + * @param[in] init_val Initial value of pin. + */ +__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin, + nrf_gpiote_polarity_t polarity, + nrf_gpiote_outinit_t init_val); + +/**@brief Function for forcing a specific state on the pin connected to GPIOTE. + * + * @param[in] idx Task-Event index. + * @param[in] init_val Pin state. + */ +__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val); + +/**@brief Function for resetting a GPIOTE task event configuration to the default state. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task) +{ + *(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task) +{ + return ((uint32_t)NRF_GPIOTE + task); +} + +__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event) +{ + return (*(uint32_t *)nrf_gpiote_event_addr_get(event) == 0x1UL) ? true : false; +} + +__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event) +{ + *(uint32_t *)nrf_gpiote_event_addr_get(event) = 0; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_addr_get(event)); + (void)dummy; +#endif +} + +__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event) +{ + return ((uint32_t)NRF_GPIOTE + event); +} + +__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask) +{ + NRF_GPIOTE->INTENSET = mask; +} + +__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask) +{ + NRF_GPIOTE->INTENCLR = mask; +} + +__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask) +{ + return (NRF_GPIOTE->INTENSET & mask); +} + +__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event; +} + +__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event; +} + +__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, nrf_gpiote_polarity_t polarity) +{ + NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); +} + +__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx) +{ + return ((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_PSEL_Msk) >> GPIOTE_CONFIG_PSEL_Pos); +} + +__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx) +{ + return (nrf_gpiote_polarity_t)((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos); +} + +__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx) +{ + uint32_t final_config = NRF_GPIOTE->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task; + /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens + on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the + correct state in GPIOTE but not in the OUT register. */ + /* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */ + NRF_GPIOTE->CONFIG[idx] = final_config | ((31 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk); + __NOP(); + __NOP(); + __NOP(); + NRF_GPIOTE->CONFIG[idx] = final_config; +} + +__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task; +} + +__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin, + nrf_gpiote_polarity_t polarity, + nrf_gpiote_outinit_t init_val) +{ + NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PSEL_Msk | + GPIOTE_CONFIG_POLARITY_Msk | + GPIOTE_CONFIG_OUTINIT_Msk); + + NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) | + ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk); +} + +__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val) +{ + NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk) + | ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk); +} + +__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] = 0; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION +/** @} */ + +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_i2s.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_i2s.h new file mode 100644 index 0000000..f464dbc --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_i2s.h @@ -0,0 +1,523 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @defgroup nrf_i2s_hal I2S HAL + * @{ + * @ingroup nrf_i2s + * + * @brief @tagAPI52 Hardware access layer for managing the Inter-IC Sound (I2S) peripheral. + */ + +#ifndef NRF_I2S_H__ +#define NRF_I2S_H__ + +#include +#include +#include + +#include "nrf.h" + + +/** + * @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set + * function call to specify that a given I2S signal (SDOUT, SDIN, or MCK) + * shall not be connected to a physical pin. + */ +#define NRF_I2S_PIN_NOT_CONNECTED 0xFFFFFFFF + + +/** + * @brief I2S tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled. + NRF_I2S_TASK_STOP = offsetof(NRF_I2S_Type, TASKS_STOP) ///< Stops I2S transfer. Also stops the MCK generator. + /*lint -restore*/ +} nrf_i2s_task_t; + +/** + * @brief I2S events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double-buffers. + NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double-buffers. + NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED) ///< I2S transfer stopped. + /*lint -restore*/ +} nrf_i2s_event_t; + +/** + * @brief I2S interrupts. + */ +typedef enum +{ + NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event. + NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event. + NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk ///< Interrupt on STOPPED event. +} nrf_i2s_int_mask_t; + +/** + * @brief I2S modes of operation. + */ +typedef enum +{ + NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode. + NRF_I2S_MODE_SLAVE = I2S_CONFIG_MODE_MODE_Slave ///< Slave mode. +} nrf_i2s_mode_t; + +/** + * @brief I2S master clock generator settings. + */ +typedef enum +{ + NRF_I2S_MCK_DISABLED = 0, ///< MCK disabled. + // [conversion to 'int' needed to prevent compilers from complaining + // that the provided value (0x80000000UL) is out of range of "int"] + NRF_I2S_MCK_32MDIV2 = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz. + NRF_I2S_MCK_32MDIV3 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3, ///< 32 MHz / 3 = 10.6666667 MHz. + NRF_I2S_MCK_32MDIV4 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4, ///< 32 MHz / 4 = 8.0 MHz. + NRF_I2S_MCK_32MDIV5 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5, ///< 32 MHz / 5 = 6.4 MHz. + NRF_I2S_MCK_32MDIV6 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6, ///< 32 MHz / 6 = 5.3333333 MHz. + NRF_I2S_MCK_32MDIV8 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, ///< 32 MHz / 8 = 4.0 MHz. + NRF_I2S_MCK_32MDIV10 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, ///< 32 MHz / 10 = 3.2 MHz. + NRF_I2S_MCK_32MDIV11 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11, ///< 32 MHz / 11 = 2.9090909 MHz. + NRF_I2S_MCK_32MDIV15 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15, ///< 32 MHz / 15 = 2.1333333 MHz. + NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz. + NRF_I2S_MCK_32MDIV21 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21, ///< 32 MHz / 21 = 1.5238095 MHz. + NRF_I2S_MCK_32MDIV23 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23, ///< 32 MHz / 23 = 1.3913043 MHz. + NRF_I2S_MCK_32MDIV31 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31, ///< 32 MHz / 31 = 1.0322581 MHz. + NRF_I2S_MCK_32MDIV42 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42, ///< 32 MHz / 42 = 0.7619048 MHz. + NRF_I2S_MCK_32MDIV63 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63, ///< 32 MHz / 63 = 0.5079365 MHz. + NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 ///< 32 MHz / 125 = 0.256 MHz. +} nrf_i2s_mck_t; + +/** + * @brief I2S MCK/LRCK ratios. + */ +typedef enum +{ + NRF_I2S_RATIO_32X = I2S_CONFIG_RATIO_RATIO_32X, ///< LRCK = MCK / 32. + NRF_I2S_RATIO_48X = I2S_CONFIG_RATIO_RATIO_48X, ///< LRCK = MCK / 48. + NRF_I2S_RATIO_64X = I2S_CONFIG_RATIO_RATIO_64X, ///< LRCK = MCK / 64. + NRF_I2S_RATIO_96X = I2S_CONFIG_RATIO_RATIO_96X, ///< LRCK = MCK / 96. + NRF_I2S_RATIO_128X = I2S_CONFIG_RATIO_RATIO_128X, ///< LRCK = MCK / 128. + NRF_I2S_RATIO_192X = I2S_CONFIG_RATIO_RATIO_192X, ///< LRCK = MCK / 192. + NRF_I2S_RATIO_256X = I2S_CONFIG_RATIO_RATIO_256X, ///< LRCK = MCK / 256. + NRF_I2S_RATIO_384X = I2S_CONFIG_RATIO_RATIO_384X, ///< LRCK = MCK / 384. + NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X ///< LRCK = MCK / 512. +} nrf_i2s_ratio_t; + +/** + * @brief I2S sample widths. + */ +typedef enum +{ + NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit. + NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit. + NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit ///< 24 bit. +} nrf_i2s_swidth_t; + +/** + * @brief I2S alignments of sample within a frame. + */ +typedef enum +{ + NRF_I2S_ALIGN_LEFT = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned. + NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned. +} nrf_i2s_align_t; + +/** + * @brief I2S frame formats. + */ +typedef enum +{ + NRF_I2S_FORMAT_I2S = I2S_CONFIG_FORMAT_FORMAT_I2S, ///< Original I2S format. + NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left- or right-aligned) format. +} nrf_i2s_format_t; + +/** + * @brief I2S enabled channels. + */ +typedef enum +{ + NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo. + NRF_I2S_CHANNELS_LEFT = I2S_CONFIG_CHANNELS_CHANNELS_Left, ///< Left only. + NRF_I2S_CHANNELS_RIGHT = I2S_CONFIG_CHANNELS_CHANNELS_Right ///< Right only. +} nrf_i2s_channels_t; + + +/** + * @brief Function for activating a specific I2S task. + * + * @param[in] p_i2s I2S instance. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s, + nrf_i2s_task_t task); + +/** + * @brief Function for getting the address of a specific I2S task register. + * + * @param[in] p_i2s I2S instance. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s, + nrf_i2s_task_t task); + +/** + * @brief Function for clearing a specific I2S event. + * + * @param[in] p_i2s I2S instance. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s, + nrf_i2s_event_t event); + +/** + * @brief Function for checking the state of a specific I2S event. + * + * @param[in] p_i2s I2S instance. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s, + nrf_i2s_event_t event); + +/** + * @brief Function for getting the address of a specific I2S event register. + * + * @param[in] p_i2s I2S instance. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s, + nrf_i2s_event_t event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_i2s I2S instance. + * @param[in] mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_i2s I2S instance. + * @param[in] mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_i2s I2S instance. + * @param[in] i2s_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s, + nrf_i2s_int_mask_t i2s_int); + +/** + * @brief Function for enabling the I2S peripheral. + * + * @param[in] p_i2s I2S instance. + */ +__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s); + +/** + * @brief Function for disabling the I2S peripheral. + * + * @param[in] p_i2s I2S instance. + */ +__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s); + +/** + * @brief Function for configuring I2S pins. + * + * Usage of the SDOUT, SDIN, and MCK signals is optional. + * If a given signal is not needed, pass the @ref NRF_I2S_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_i2s I2S instance. + * @param[in] sck_pin SCK pin number. + * @param[in] lrck_pin LRCK pin number. + * @param[in] mck_pin MCK pin number. + * @param[in] sdout_pin SDOUT pin number. + * @param[in] sdin_pin SDIN pin number. + */ +__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s, + uint32_t sck_pin, + uint32_t lrck_pin, + uint32_t mck_pin, + uint32_t sdout_pin, + uint32_t sdin_pin); + +/** + * @brief Function for setting the I2S peripheral configuration. + * + * @param[in] p_i2s I2S instance. + * @param[in] mode Mode of operation (master or slave). + * @param[in] format I2S frame format. + * @param[in] alignment Alignment of sample within a frame. + * @param[in] sample_width Sample width. + * @param[in] channels Enabled channels. + * @param[in] mck_setup Master clock generator setup. + * @param[in] ratio MCK/LRCK ratio. + * + * @retval true If the configuration has been set successfully. + * @retval false If the requested configuration is not allowed. + */ +__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s, + nrf_i2s_mode_t mode, + nrf_i2s_format_t format, + nrf_i2s_align_t alignment, + nrf_i2s_swidth_t sample_width, + nrf_i2s_channels_t channels, + nrf_i2s_mck_t mck_setup, + nrf_i2s_ratio_t ratio); + +/** + * @brief Function for setting up the I2S transfer. + * + * This function sets up the RX and TX buffers and enables reception and/or + * transmission accordingly. If the transfer in a given direction is not + * required, pass NULL instead of the pointer to the corresponding buffer. + * + * @param[in] p_i2s I2S instance. + * @param[in] size Size of the buffers (in 32-bit words). + * @param[in] p_rx_buffer Pointer to the receive buffer. + * Pass NULL to disable reception. + * @param[in] p_tx_buffer Pointer to the transmit buffer. + * Pass NULL to disable transmission. + */ +__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s, + uint16_t size, + uint32_t * p_rx_buffer, + uint32_t const * p_tx_buffer); + +/** + * @brief Function for setting the pointer to the receive buffer. + * + * @note The size of the buffer can be set only by calling + * @ref nrf_i2s_transfer_set. + * + * @param[in] p_i2s I2S instance. + * @param[in] p_buffer Pointer to the receive buffer. + */ +__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s, + uint32_t * p_buffer); + +/** + * @brief Function for getting the pointer to the receive buffer. + * + * @param[in] p_i2s I2S instance. + * + * @return Pointer to the receive buffer. + */ +__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s); + +/** + * @brief Function for setting the pointer to the transmit buffer. + * + * @note The size of the buffer can be set only by calling + * @ref nrf_i2s_transfer_set. + * + * @param[in] p_i2s I2S instance. + * @param[in] p_buffer Pointer to the transmit buffer. + */ +__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s, + uint32_t const * p_buffer); + +/** + * @brief Function for getting the pointer to the transmit buffer. + * + * @param[in] p_i2s I2S instance. + * + * @return Pointer to the transmit buffer. + */ +__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s, + nrf_i2s_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s, + nrf_i2s_task_t task) +{ + return ((uint32_t)p_i2s + (uint32_t)task); +} + +__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s, + nrf_i2s_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s, + nrf_i2s_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s, + nrf_i2s_event_t event) +{ + return ((uint32_t)p_i2s + (uint32_t)event); +} + +__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask) +{ + p_i2s->INTENSET = mask; +} + +__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask) +{ + p_i2s->INTENCLR = mask; +} + +__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s, + nrf_i2s_int_mask_t i2s_int) +{ + return (bool)(p_i2s->INTENSET & i2s_int); +} + +__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s) +{ + p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Enabled << I2S_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s) +{ + p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Disabled << I2S_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s, + uint32_t sck_pin, + uint32_t lrck_pin, + uint32_t mck_pin, + uint32_t sdout_pin, + uint32_t sdin_pin) +{ + p_i2s->PSEL.SCK = sck_pin; + p_i2s->PSEL.LRCK = lrck_pin; + p_i2s->PSEL.MCK = mck_pin; + p_i2s->PSEL.SDOUT = sdout_pin; + p_i2s->PSEL.SDIN = sdin_pin; +} + +__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s, + nrf_i2s_mode_t mode, + nrf_i2s_format_t format, + nrf_i2s_align_t alignment, + nrf_i2s_swidth_t sample_width, + nrf_i2s_channels_t channels, + nrf_i2s_mck_t mck_setup, + nrf_i2s_ratio_t ratio) +{ + if (mode == NRF_I2S_MODE_MASTER) + { + // The MCK/LRCK ratio shall be a multiple of 2 * sample width. + if (((sample_width == NRF_I2S_SWIDTH_16BIT) && + (ratio == NRF_I2S_RATIO_48X)) + || + ((sample_width == NRF_I2S_SWIDTH_24BIT) && + ((ratio == NRF_I2S_RATIO_32X) || + (ratio == NRF_I2S_RATIO_64X) || + (ratio == NRF_I2S_RATIO_128X) || + (ratio == NRF_I2S_RATIO_256X) || + (ratio == NRF_I2S_RATIO_512X)))) + { + return false; + } + } + + p_i2s->CONFIG.MODE = mode; + p_i2s->CONFIG.FORMAT = format; + p_i2s->CONFIG.ALIGN = alignment; + p_i2s->CONFIG.SWIDTH = sample_width; + p_i2s->CONFIG.CHANNELS = channels; + p_i2s->CONFIG.RATIO = ratio; + + if (mck_setup == NRF_I2S_MCK_DISABLED) + { + p_i2s->CONFIG.MCKEN = + (I2S_CONFIG_MCKEN_MCKEN_Disabled << I2S_CONFIG_MCKEN_MCKEN_Pos); + } + else + { + p_i2s->CONFIG.MCKFREQ = mck_setup; + p_i2s->CONFIG.MCKEN = + (I2S_CONFIG_MCKEN_MCKEN_Enabled << I2S_CONFIG_MCKEN_MCKEN_Pos); + } + + return true; +} + +__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s, + uint16_t size, + uint32_t * p_buffer_rx, + uint32_t const * p_buffer_tx) +{ + p_i2s->RXTXD.MAXCNT = size; + + nrf_i2s_rx_buffer_set(p_i2s, p_buffer_rx); + p_i2s->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0; + + nrf_i2s_tx_buffer_set(p_i2s, p_buffer_tx); + p_i2s->CONFIG.TXEN = (p_buffer_tx != NULL) ? 1 : 0; +} + +__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s, + uint32_t * p_buffer) +{ + p_i2s->RXD.PTR = (uint32_t)p_buffer; +} + +__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s) +{ + return (uint32_t *)(p_i2s->RXD.PTR); +} + +__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s, + uint32_t const * p_buffer) +{ + p_i2s->TXD.PTR = (uint32_t)p_buffer; +} + +__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s) +{ + return (uint32_t *)(p_i2s->TXD.PTR); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_I2S_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_lpcomp.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_lpcomp.h new file mode 100644 index 0000000..8aadb15 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_lpcomp.h @@ -0,0 +1,367 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @file + * @brief LPCOMP HAL API. + */ + +#ifndef NRF_LPCOMP_H_ +#define NRF_LPCOMP_H_ + +/** + * @defgroup nrf_lpcomp_hal LPCOMP HAL + * @{ + * @ingroup nrf_lpcomp + * @brief Hardware access layer for managing the Low Power Comparator (LPCOMP). + */ + +#include "nrf.h" + +#include +#include +#include + +/** + * @enum nrf_lpcomp_ref_t + * @brief LPCOMP reference selection. + */ +typedef enum +{ +#ifdef NRF51 + NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling, /**< Use supply with a 1/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling, /**< Use supply with a 2/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling, /**< Use supply with a 3/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling, /**< Use supply with a 4/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling, /**< Use supply with a 5/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling, /**< Use supply with a 6/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling, /**< Use supply with a 7/8 prescaler as reference. */ +#elif defined NRF52 + NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, /**< Use supply with a 1/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, /**< Use supply with a 2/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, /**< Use supply with a 3/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, /**< Use supply with a 4/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, /**< Use supply with a 5/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, /**< Use supply with a 6/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, /**< Use supply with a 7/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_1_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 1/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_3_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 3/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_5_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 5/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_7_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 7/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_9_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 9/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_11_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 11/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_13_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 13/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_15_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 15/16 prescaler as reference. */ +#endif + NRF_LPCOMP_REF_EXT_REF0 = LPCOMP_REFSEL_REFSEL_ARef | + (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), /**< External reference 0. */ + NRF_LPCOMP_CONFIG_REF_EXT_REF1 = LPCOMP_REFSEL_REFSEL_ARef | + (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 << 16), /**< External reference 1. */ +} nrf_lpcomp_ref_t; + +/** + * @enum nrf_lpcomp_input_t + * @brief LPCOMP input selection. + */ +typedef enum +{ + NRF_LPCOMP_INPUT_0 = LPCOMP_PSEL_PSEL_AnalogInput0, /**< Input 0. */ + NRF_LPCOMP_INPUT_1 = LPCOMP_PSEL_PSEL_AnalogInput1, /**< Input 1. */ + NRF_LPCOMP_INPUT_2 = LPCOMP_PSEL_PSEL_AnalogInput2, /**< Input 2. */ + NRF_LPCOMP_INPUT_3 = LPCOMP_PSEL_PSEL_AnalogInput3, /**< Input 3. */ + NRF_LPCOMP_INPUT_4 = LPCOMP_PSEL_PSEL_AnalogInput4, /**< Input 4. */ + NRF_LPCOMP_INPUT_5 = LPCOMP_PSEL_PSEL_AnalogInput5, /**< Input 5. */ + NRF_LPCOMP_INPUT_6 = LPCOMP_PSEL_PSEL_AnalogInput6, /**< Input 6. */ + NRF_LPCOMP_INPUT_7 = LPCOMP_PSEL_PSEL_AnalogInput7 /**< Input 7. */ +} nrf_lpcomp_input_t; + +/** + * @enum nrf_lpcomp_detect_t + * @brief LPCOMP detection type selection. + */ +typedef enum +{ + NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, /**< Generate ANADETEC on crossing, both upwards and downwards crossing. */ + NRF_LPCOMP_DETECT_UP = LPCOMP_ANADETECT_ANADETECT_Up, /**< Generate ANADETEC on upwards crossing only. */ + NRF_LPCOMP_DETECT_DOWN = LPCOMP_ANADETECT_ANADETECT_Down /**< Generate ANADETEC on downwards crossing only. */ +} nrf_lpcomp_detect_t; + +/** + * @enum nrf_lpcomp_task_t + * @brief LPCOMP tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_LPCOMP_TASK_START = offsetof(NRF_LPCOMP_Type, TASKS_START), /**< LPCOMP start sampling task. */ + NRF_LPCOMP_TASK_STOP = offsetof(NRF_LPCOMP_Type, TASKS_STOP), /**< LPCOMP stop sampling task. */ + NRF_LPCOMP_TASK_SAMPLE = offsetof(NRF_LPCOMP_Type, TASKS_SAMPLE) /**< Sample comparator value. */ +} nrf_lpcomp_task_t; /*lint -restore*/ + + +/** + * @enum nrf_lpcomp_event_t + * @brief LPCOMP events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_LPCOMP_EVENT_READY = offsetof(NRF_LPCOMP_Type, EVENTS_READY), /**< LPCOMP is ready and output is valid. */ + NRF_LPCOMP_EVENT_DOWN = offsetof(NRF_LPCOMP_Type, EVENTS_DOWN), /**< Input voltage crossed the threshold going down. */ + NRF_LPCOMP_EVENT_UP = offsetof(NRF_LPCOMP_Type, EVENTS_UP), /**< Input voltage crossed the threshold going up. */ + NRF_LPCOMP_EVENT_CROSS = offsetof(NRF_LPCOMP_Type, EVENTS_CROSS) /**< Input voltage crossed the threshold in any direction. */ +} nrf_lpcomp_event_t; /*lint -restore*/ + +/** + * @enum nrf_lpcomp_short_mask_t + * @brief LPCOMP shorts masks. + */ +typedef enum +{ + NRF_LPCOMP_SHORT_CROSS_STOP_MASK = LPCOMP_SHORTS_CROSS_STOP_Msk, /*!< Short between CROSS event and STOP task. */ + NRF_LPCOMP_SHORT_UP_STOP_MASK = LPCOMP_SHORTS_UP_STOP_Msk, /*!< Short between UP event and STOP task. */ + NRF_LPCOMP_SHORT_DOWN_STOP_MASK = LPCOMP_SHORTS_DOWN_STOP_Msk, /*!< Short between DOWN event and STOP task. */ + NRF_LPCOMP_SHORT_READY_STOP_MASK = LPCOMP_SHORTS_READY_STOP_Msk, /*!< Short between READY event and STOP task. */ + NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Short between READY event and SAMPLE task. */ +} nrf_lpcomp_short_mask_t; + + +/** @brief LPCOMP configuration. */ +typedef struct +{ + nrf_lpcomp_ref_t reference; /**< LPCOMP reference. */ + nrf_lpcomp_detect_t detection; /**< LPCOMP detection type. */ +} nrf_lpcomp_config_t; + +/** Default LPCOMP configuration. */ +#define NRF_LPCOMP_CONFIG_DEFAULT { NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT, NRF_LPCOMP_DETECT_DOWN } + +/** + * @brief Function for configuring LPCOMP. + * + * This function powers on LPCOMP and configures it. LPCOMP is in DISABLE state after configuration, + * so it must be enabled before using it. All shorts are inactive, events are cleared, and LPCOMP is stopped. + * + * @param[in] p_config Configuration. + */ +__STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config) +{ + NRF_LPCOMP->TASKS_STOP = 1; + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; + NRF_LPCOMP->REFSEL = + (p_config->reference << LPCOMP_REFSEL_REFSEL_Pos) & LPCOMP_REFSEL_REFSEL_Msk; + + //If external source is choosen extract analog reference index. + if ((p_config->reference & LPCOMP_REFSEL_REFSEL_ARef)==LPCOMP_REFSEL_REFSEL_ARef) + { + uint32_t extref = p_config->reference >> 16; + NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) & LPCOMP_EXTREFSEL_EXTREFSEL_Msk; + } + + NRF_LPCOMP->ANADETECT = + (p_config->detection << LPCOMP_ANADETECT_ANADETECT_Pos) & LPCOMP_ANADETECT_ANADETECT_Msk; + NRF_LPCOMP->SHORTS = 0; + NRF_LPCOMP->INTENCLR = LPCOMP_INTENCLR_CROSS_Msk | LPCOMP_INTENCLR_UP_Msk | + LPCOMP_INTENCLR_DOWN_Msk | LPCOMP_INTENCLR_READY_Msk; +} + + +/** + * @brief Function for selecting the LPCOMP input. + * + * This function selects the active input of LPCOMP. + * + * @param[in] input Input to be selected. + */ +__STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input) +{ + uint32_t lpcomp_enable_state = NRF_LPCOMP->ENABLE; + + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; + NRF_LPCOMP->PSEL = + ((uint32_t)input << LPCOMP_PSEL_PSEL_Pos) | (NRF_LPCOMP->PSEL & ~LPCOMP_PSEL_PSEL_Msk); + NRF_LPCOMP->ENABLE = lpcomp_enable_state; +} + + +/** + * @brief Function for enabling the Low Power Comparator. + * + * This function enables LPCOMP. + * + */ +__STATIC_INLINE void nrf_lpcomp_enable(void) +{ + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos; + NRF_LPCOMP->EVENTS_READY = 0; + NRF_LPCOMP->EVENTS_DOWN = 0; + NRF_LPCOMP->EVENTS_UP = 0; + NRF_LPCOMP->EVENTS_CROSS = 0; +} + + +/** + * @brief Function for disabling the Low Power Comparator. + * + * This function disables LPCOMP. + * + */ +__STATIC_INLINE void nrf_lpcomp_disable(void) +{ + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; +} + + +/** + * @brief Function for getting the last LPCOMP compare result. + * + * @return The last compare result. If 0 then VIN+ < VIN-, if 1 then the opposite. + */ +__STATIC_INLINE uint32_t nrf_lpcomp_result_get(void) +{ + return (uint32_t)NRF_LPCOMP->RESULT; +} + + +/** + * @brief Function for enabling interrupts from LPCOMP. + * + * @param[in] lpcomp_int_mask Mask of interrupts to be enabled. + * + * @sa nrf_lpcomp_int_disable() + * @sa nrf_lpcomp_int_enable_check() + */ +__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t lpcomp_int_mask) +{ + NRF_LPCOMP->INTENSET = lpcomp_int_mask; +} + + +/** + * @brief Function for disabling interrupts from LPCOMP. + * + * @param[in] lpcomp_int_mask Mask of interrupts to be disabled. + * + * @sa nrf_lpcomp_int_enable() + * @sa nrf_lpcomp_int_enable_check() + */ +__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask) +{ + NRF_LPCOMP->INTENCLR = lpcomp_int_mask; +} + + +/** + * @brief Function for getting the enabled interrupts of LPCOMP. + * + * @param[in] lpcomp_int_mask Mask of interrupts to be checked. + * + * @retval true If any of interrupts of the specified mask are enabled. + * + * @sa nrf_lpcomp_int_enable() + * @sa nrf_lpcomp_int_disable() + */ +__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t lpcomp_int_mask) +{ + return (NRF_LPCOMP->INTENSET & lpcomp_int_mask); // when read this register will return the value of INTEN. +} + + +/** + * @brief Function for getting the address of a specific LPCOMP task register. + * + * @param[in] lpcomp_task LPCOMP task. + * + * @return The address of the specified LPCOMP task. + */ +__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t lpcomp_task) +{ + return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_task); +} + + +/** + * @brief Function for getting the address of a specific LPCOMP event register. + * + * @param[in] lpcomp_event LPCOMP event. + * + * @return The address of the specified LPCOMP event. + */ +__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t lpcomp_event) +{ + return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event); +} + + +/** + * @brief Function for setting LPCOMP shorts. + * + * @param[in] lpcomp_short_mask LPCOMP shorts by mask. + * + */ +__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t lpcomp_short_mask) +{ + NRF_LPCOMP->SHORTS |= lpcomp_short_mask; +} + + +/** + * @brief Function for clearing LPCOMP shorts by mask. + * + * @param[in] lpcomp_short_mask LPCOMP shorts to be cleared. + * + */ +__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t lpcomp_short_mask) +{ + NRF_LPCOMP->SHORTS &= ~lpcomp_short_mask; +} + + +/** + * @brief Function for setting a specific LPCOMP task. + * + * @param[in] lpcomp_task LPCOMP task to be set. + * + */ +__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t lpcomp_task) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_task) ) = 1; +} + + +/** + * @brief Function for clearing a specific LPCOMP event. + * + * @param[in] lpcomp_event LPCOMP event to be cleared. + * + */ +__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t lpcomp_event) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event) ) = 0; +} + + +/** + * @brief Function for getting the state of a specific LPCOMP event. + * + * @retval true If the specified LPCOMP event is active. + * + */ +__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t lpcomp_event) +{ + return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event)); +} + + +/** + *@} + **/ + +#endif /* NRF_LPCOMP_H_ */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.c new file mode 100644 index 0000000..312795f --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.c @@ -0,0 +1,117 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. +* +* The information contained herein is property of Nordic Semiconductor ASA. +* Terms and conditions of usage are described in detail in NORDIC +* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. NO +* WARRANTY of ANY KIND is provided. This heading must NOT be removed from +* the file. +* +* $LastChangedRevision: 17685 $ +*/ + +/** + *@file + *@brief NMVC driver implementation + */ + +#include +#include "nrf.h" +#include "nrf_nvmc.h" + + +void nrf_nvmc_page_erase(uint32_t address) +{ + // Enable erase. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) + { + } + + // Erase the page + NRF_NVMC->ERASEPAGE = address; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) + { + } + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) + { + } +} + + +void nrf_nvmc_write_byte(uint32_t address, uint8_t value) +{ + uint32_t byte_shift = address & (uint32_t)0x03; + uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in. + uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3))); + value32 = value32 + ((uint32_t)value << (byte_shift << 3)); + + // Enable write. + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos); + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) + { + } + + *(uint32_t*)address32 = value32; + while(NRF_NVMC->READY == NVMC_READY_READY_Busy) + { + } + + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos); + { + } +} + +void nrf_nvmc_write_word(uint32_t address, uint32_t value) +{ + // Enable write. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){ + } + + *(uint32_t*)address = value; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){ + } + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) + { + } +} + +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes) +{ + uint32_t i; + for(i=0;iCONFIG = NVMC_CONFIG_WEN_Wen; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) + { + } + + for(i=0;iREADY == NVMC_READY_READY_Busy) + { + } + } + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) + { + } +} + diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.h new file mode 100644 index 0000000..95ff228 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_nvmc.h @@ -0,0 +1,90 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is confidential property of Nordic + * Semiconductor ASA.Terms and conditions of usage are described in detail + * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + * $LastChangedRevision: 17685 $ + */ + +/** + * @file + * @brief NMVC driver API. + */ + +#ifndef NRF_NVMC_H__ +#define NRF_NVMC_H__ + +#include + + +/** + * @defgroup nrf_nvmc Non-volatile memory controller + * @{ + * @ingroup nrf_drivers + * @brief Driver for the NVMC peripheral. + * + * This driver allows writing to the non-volatile memory (NVM) regions + * of the chip. In order to write to NVM the controller must be powered + * on and the relevant page must be erased. + * + */ + + +/** + * @brief Erase a page in flash. This is required before writing to any + * address in the page. + * + * @param address Start address of the page. + */ +void nrf_nvmc_page_erase(uint32_t address); + + +/** + * @brief Write a single byte to flash. + * + * The function reads the word containing the byte, and then + * rewrites the entire word. + * + * @param address Address to write to. + * @param value Value to write. + */ +void nrf_nvmc_write_byte(uint32_t address , uint8_t value); + + +/** + * @brief Write a 32-bit word to flash. + * @param address Address to write to. + * @param value Value to write. + */ +void nrf_nvmc_write_word(uint32_t address, uint32_t value); + + +/** + * @brief Write consecutive bytes to flash. + * + * @param address Address to write to. + * @param src Pointer to data to copy from. + * @param num_bytes Number of bytes in src to write. + */ +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes); + + +/** + * @brief Write consecutive words to flash. + * + * @param address Address to write to. + * @param src Pointer to data to copy from. + * @param num_words Number of bytes in src to write. + */ +void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words); + + +#endif // NRF_NVMC_H__ +/** @} */ + + diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pdm.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pdm.h new file mode 100644 index 0000000..2b7a4ec --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pdm.h @@ -0,0 +1,359 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + + +#ifndef NRF_PDM_H_ +#define NRF_PDM_H_ + +/** + * @defgroup nrf_pdm_hal PDM HAL + * @{ + * @ingroup nrf_pdm + * + * @brief @tagAPI52 Hardware abstraction layer for accessing the pulse density modulation (PDM) peripheral. + */ + +#include +#include +#include "nrf.h" +#include "nrf_assert.h" + + +#define NRF_PDM_GAIN_MINIMUM 0x00 +#define NRF_PDM_GAIN_DEFAULT 0x28 +#define NRF_PDM_GAIN_MAXIMUM 0x50 + +typedef uint8_t nrf_pdm_gain_t; + + +/** + * @brief PDM tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_PDM_TASK_START = offsetof(NRF_PDM_Type, TASKS_START), ///< Starts continuous PDM transfer. + NRF_PDM_TASK_STOP = offsetof(NRF_PDM_Type, TASKS_STOP) ///< Stops PDM transfer. +} nrf_pdm_task_t; + + +/** + * @brief PDM events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_PDM_EVENT_STARTED = offsetof(NRF_PDM_Type, EVENTS_STARTED), ///< PDM transfer has started. + NRF_PDM_EVENT_STOPPED = offsetof(NRF_PDM_Type, EVENTS_STOPPED), ///< PDM transfer has finished. + NRF_PDM_EVENT_END = offsetof(NRF_PDM_Type, EVENTS_END) ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM. +} nrf_pdm_event_t; + + +/** + * @brief PDM interrupt masks. + */ +typedef enum +{ + NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event. + NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event. + NRF_PDM_INT_END = PDM_INTENSET_END_Msk ///< Interrupt on EVENTS_END event. +} nrf_pdm_int_mask_t; + +/** + * @brief PDM clock frequency. + */ +typedef enum +{ + NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K, ///< PDM_CLK = 1.000 MHz. + NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default, ///< PDM_CLK = 1.032 MHz. + NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K ///< PDM_CLK = 1.067 MHz. +} nrf_pdm_freq_t; + + +/** + * @brief PDM operation mode. + */ +typedef enum +{ + NRF_PDM_MODE_STEREO = PDM_MODE_OPERATION_Stereo, ///< Sample and store one pair (Left + Right) of 16-bit samples per RAM word. + NRF_PDM_MODE_MONO = PDM_MODE_OPERATION_Mono ///< Sample and store two successive Left samples (16 bit each) per RAM word. +} nrf_pdm_mode_t; + + +/** + * @brief PDM sampling mode. + */ +typedef enum +{ + NRF_PDM_EDGE_LEFTFALLING = PDM_MODE_EDGE_LeftFalling, ///< Left (or mono) is sampled on falling edge of PDM_CLK. + NRF_PDM_EDGE_LEFTRISING = PDM_MODE_EDGE_LeftRising ///< Left (or mono) is sampled on rising edge of PDM_CLK. +} nrf_pdm_edge_t; + + +/** + * @brief Function for triggering a PDM task. + * + * @param[in] pdm_task PDM task. + */ +__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t pdm_task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_task)) = 0x1UL; +} + + +/** + * @brief Function for getting the address of a PDM task register. + * + * @param[in] pdm_task PDM task. + * + * @return Address of the specified PDM task. + */ +__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t pdm_task) +{ + return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)pdm_task); +} + + +/** + * @brief Function for getting the state of a PDM event. + * + * @param[in] pdm_event PDM event. + * + * @return State of the specified PDM event. + */ +__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t pdm_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event); +} + + +/** + * @brief Function for clearing a PDM event. + * + * @param[in] pdm_event PDM event. + */ +__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t pdm_event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)) = 0x0UL; +} + + +/** + * @brief Function for getting the address of a PDM event register. + * + * @param[in] pdm_event PDM event. + * + * @return Address of the specified PDM event. + */ +__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t pdm_event) +{ + return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event); +} + + +/** + * @brief Function for enabling PDM interrupts. + * + * @param[in] pdm_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_pdm_int_enable(uint32_t pdm_int_mask) +{ + NRF_PDM->INTENSET = pdm_int_mask; +} + + +/** + * @brief Function for retrieving the state of PDM interrupts. + * + * @param[in] pdm_int_mask Interrupts to check. + * + * @retval true If all specified interrupts are enabled. + * @retval false If at least one of the given interrupts is not enabled. + */ +__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t pdm_int_mask) +{ + return (bool)(NRF_PDM->INTENSET & pdm_int_mask); +} + + +/** + * @brief Function for disabling interrupts. + * + * @param pdm_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_pdm_int_disable(uint32_t pdm_int_mask) +{ + NRF_PDM->INTENCLR = pdm_int_mask; +} + + +/** + * @brief Function for enabling the PDM peripheral. + * + * The PDM peripheral must be enabled before use. + */ +__STATIC_INLINE void nrf_pdm_enable(void) +{ + NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos); +} + + +/** + * @brief Function for disabling the PDM peripheral. + */ +__STATIC_INLINE void nrf_pdm_disable(void) +{ + NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Disabled << PDM_ENABLE_ENABLE_Pos); +} + + +/** + * @brief Function for checking if the PDM peripheral is enabled. + * + * @retval true If the PDM peripheral is enabled. + * @retval false If the PDM peripheral is not enabled. + */ +__STATIC_INLINE bool nrf_pdm_enable_check(void) +{ + return (NRF_PDM->ENABLE == (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos)); +} + + +/** + * @brief Function for setting the PDM operation mode. + * + * @param[in] pdm_mode PDM operation mode. + * @param[in] pdm_edge PDM sampling mode. + */ +__STATIC_INLINE void nrf_pdm_mode_set(nrf_pdm_mode_t pdm_mode, nrf_pdm_edge_t pdm_edge) +{ + NRF_PDM->MODE = ((pdm_mode << PDM_MODE_OPERATION_Pos) & PDM_MODE_OPERATION_Msk) + | ((pdm_edge << PDM_MODE_EDGE_Pos) & PDM_MODE_EDGE_Msk); +} + + +/** + * @brief Function for getting the PDM operation mode. + * + * @param[out] p_pdm_mode PDM operation mode. + * @param[out] p_pdm_edge PDM sampling mode. + */ +__STATIC_INLINE void nrf_pdm_mode_get(nrf_pdm_mode_t * p_pdm_mode, nrf_pdm_edge_t * p_pdm_edge) +{ + uint32_t mode = NRF_PDM->MODE; + *p_pdm_mode = (nrf_pdm_mode_t)((mode & PDM_MODE_OPERATION_Msk ) >> PDM_MODE_OPERATION_Pos); + *p_pdm_edge = (nrf_pdm_edge_t)((mode & PDM_MODE_EDGE_Msk ) >> PDM_MODE_EDGE_Pos); +} + + +/** + * @brief Function for setting the PDM clock frequency. + * + * @param[in] pdm_freq PDM clock frequency. + */ +__STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq) +{ + NRF_PDM->PDMCLKCTRL = ((pdm_freq << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk); +} + + +/** + * @brief Function for getting the PDM clock frequency. + */ +__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void) +{ + return (nrf_pdm_freq_t) ((NRF_PDM->PDMCLKCTRL << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk); +} + + +/** + * @brief Function for setting up the PDM pins. + * + * @param[in] psel_clk CLK pin number. + * @param[in] psel_din DIN pin number. + */ +__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din) +{ + NRF_PDM->PSEL.CLK = ((psel_clk << PDM_PSEL_CLK_PIN_Pos) & PDM_PSEL_CLK_PIN_Msk) + | ((PDM_PSEL_CLK_CONNECT_Connected << PDM_PSEL_CLK_CONNECT_Pos) & PDM_PSEL_CLK_CONNECT_Msk); + NRF_PDM->PSEL.DIN = ((psel_din << PDM_PSEL_DIN_PIN_Pos) & PDM_PSEL_DIN_PIN_Msk) + | ((PDM_PSEL_DIN_CONNECT_Connected << PDM_PSEL_CLK_CONNECT_Pos) & PDM_PSEL_DIN_CONNECT_Msk); +} + +/** + * @brief Function for disconnecting the PDM pins. + */ +__STATIC_INLINE void nrf_pdm_psel_disconnect() +{ + NRF_PDM->PSEL.CLK = ((PDM_PSEL_CLK_CONNECT_Disconnected << PDM_PSEL_CLK_CONNECT_Pos) + & PDM_PSEL_CLK_CONNECT_Msk); + NRF_PDM->PSEL.DIN = ((PDM_PSEL_DIN_CONNECT_Disconnected << PDM_PSEL_DIN_CONNECT_Pos) + & PDM_PSEL_DIN_CONNECT_Msk); +} + + +/** + * @brief Function for setting the PDM gain. + * + * @param[in] gain_l Left channel gain. + * @param[in] gain_r Right channel gain. + */ +__STATIC_INLINE void nrf_pdm_gain_set(nrf_pdm_gain_t gain_l, nrf_pdm_gain_t gain_r) +{ + NRF_PDM->GAINL = gain_l; + NRF_PDM->GAINR = gain_r; +} + + +/** + * @brief Function for getting the PDM gain. + * + * @param[out] p_gain_l Left channel gain. + * @param[out] p_gain_r Right channel gain. + */ +__STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t * p_gain_r) +{ + *p_gain_l = NRF_PDM->GAINL; + *p_gain_r = NRF_PDM->GAINR; +} + + +/** + * @brief Function for setting the PDM sample buffer. + * + * @param[in] p_buffer Pointer to the RAM address where samples should be written with EasyDMA. + * @param[in] num Number of samples to allocate memory for in EasyDMA mode. + * + * The amount of allocated RAM depends on the operation mode. + * - For stereo mode: N 32-bit words. + * - For mono mode: Ceil(N/2) 32-bit words. + */ +__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num) +{ + NRF_PDM->SAMPLE.PTR = (uint32_t)p_buffer; + NRF_PDM->SAMPLE.MAXCNT = num; +} + +/** + * @brief Function for getting the current PDM sample buffer address. + * + * @return Pointer to the current sample buffer. + */ +__STATIC_INLINE uint32_t * nrf_pdm_buffer_get() +{ + return (uint32_t *)NRF_PDM->SAMPLE.PTR; +} + + +/** + *@} + **/ + +#endif /* NRF_PDM_H_ */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ppi.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ppi.h new file mode 100644 index 0000000..60541db --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_ppi.h @@ -0,0 +1,402 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_PPI_H__ +#define NRF_PPI_H__ + +#include +#include "nrf.h" + +/** + * @defgroup nrf_ppi_hal PPI HAL + * @{ + * @ingroup nrf_ppi + * @brief Hardware access layer for setting up Programmable Peripheral Interconnect (PPI) channels. + */ + +#define NRF_PPI_TASK_SET (1UL) + +/** + * @enum nrf_ppi_channel_t + * @brief PPI channels. + */ +typedef enum +{ + NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */ + NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */ + NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */ + NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */ + NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */ + NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */ + NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */ + NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */ + NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */ + NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */ + NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */ + NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */ + NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */ + NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */ + NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */ + NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */ +#ifdef NRF52 + NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */ + NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */ + NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */ + NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */ +#endif + NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */ + NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */ + NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */ + NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */ + NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */ + NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */ + NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */ + NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */ + NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */ + NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */ + NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */ + NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */ +} nrf_ppi_channel_t; + +/** + * @enum nrf_ppi_channel_group_t + * @brief PPI channel groups. + */ +typedef enum +{ + NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */ + NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */ + NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */ + NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */ +#ifdef NRF52 + NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */ + NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */ +#endif +} nrf_ppi_channel_group_t; + +/** + * @enum nrf_ppi_channel_include_t + * @brief Definition of which PPI channels belong to a group. + */ +typedef enum +{ + NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */ + NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */ +} nrf_ppi_channel_include_t; + +/** + * @enum nrf_ppi_channel_enable_t + * @brief Definition if a PPI channel is enabled. + */ +typedef enum +{ + NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */ + NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */ +} nrf_ppi_channel_enable_t; + +/** + * @enum nrf_ppi_task_t + * @brief PPI tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0 */ + NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */ + NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1 */ + NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */ + NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2 */ + NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */ + NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3 */ + NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */ +#ifdef NRF52 + NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4 */ + NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */ + NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5 */ + NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5 */ +#endif + /*lint -restore*/ +} nrf_ppi_task_t; + +/** + * @brief Function for enabling a given PPI channel. + * + * @details This function enables only one channel. + * + * @param[in] channel Channel to enable. + * + * */ +__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel) +{ + NRF_PPI->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel); +} + + +/** + * @brief Function for disabling a given PPI channel. + * + * @details This function disables only one channel. + * + * @param[in] channel Channel to disable. + */ +__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel) +{ + NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel); +} + + +/** + * @brief Function for checking if a given PPI channel is enabled. + * + * @details This function checks only one channel. + * + * @param[in] channel Channel to check. + * + * @retval NRF_PPI_CHANNEL_ENABLED If the channel is enabled. + * @retval NRF_PPI_CHANNEL_DISABLED If the channel is not enabled. + * + */ +__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel) +{ + if (NRF_PPI->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel))) + { + return NRF_PPI_CHANNEL_ENABLED; + } + else + { + return NRF_PPI_CHANNEL_DISABLED; + } +} + + +/** + * @brief Function for disabling all PPI channels. + */ +__STATIC_INLINE void nrf_ppi_channel_disable_all(void) +{ + NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL); +} + +/** + * @brief Function for disabling multiple PPI channels. + * + * @param[in] mask Channel mask. + */ +__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask) +{ + NRF_PPI->CHENCLR = mask; +} + +/** + * @brief Function for setting up event and task endpoints for a given PPI channel. + * + * @param[in] eep Event register address. + * + * @param[in] tep Task register address. + * + * @param[in] channel Channel to which the given endpoints are assigned. + */ +__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t eep, + uint32_t tep) +{ + NRF_PPI->CH[(uint32_t) channel].EEP = eep; + NRF_PPI->CH[(uint32_t) channel].TEP = tep; +} + +#ifdef NRF52 +/** + * @brief Function for setting up task endpoint for a given PPI fork. + * + * @param[in] fork_tep Task register address. + * + * @param[in] channel Channel to which the given fork endpoint is assigned. + */ +__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t fork_tep) +{ + NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep; +} + +/** + * @brief Function for setting up event and task endpoints for a given PPI channel and fork. + * + * @param[in] eep Event register address. + * + * @param[in] tep Task register address. + * + * @param[in] fork_tep Fork task register address (register value). + * + * @param[in] channel Channel to which the given endpoints are assigned. + */ +__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t eep, + uint32_t tep, + uint32_t fork_tep) +{ + nrf_ppi_channel_endpoint_setup(channel, eep, tep); + nrf_ppi_fork_endpoint_setup(channel, fork_tep); +} +#endif + +/** + * @brief Function for including a PPI channel in a channel group. + * + * @details This function adds only one channel to the group. + * + * @param[in] channel Channel to be included in the group. + * + * @param[in] channel_group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel, + nrf_ppi_channel_group_t channel_group) +{ + NRF_PPI->CHG[(uint32_t) channel_group] = + NRF_PPI->CHG[(uint32_t) channel_group] | (PPI_CHG_CH0_Included << ((uint32_t) channel)); +} + +/** + * @brief Function for including multiple PPI channels in a channel group. + * + * @details This function adds all specified channels to the group. + * + * @param[in] channel_mask Channels to be included in the group. + * + * @param[in] channel_group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask, + nrf_ppi_channel_group_t channel_group) +{ + NRF_PPI->CHG[(uint32_t) channel_group] = + NRF_PPI->CHG[(uint32_t) channel_group] | (channel_mask); +} + + +/** + * @brief Function for removing a PPI channel from a channel group. + * + * @details This function removes only one channel from the group. + * + * @param[in] channel Channel to be removed from the group. + * + * @param[in] channel_group Channel group. + */ +__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel, + nrf_ppi_channel_group_t channel_group) +{ + NRF_PPI->CHG[(uint32_t) channel_group] = + NRF_PPI->CHG[(uint32_t) channel_group] & ~(PPI_CHG_CH0_Included << ((uint32_t) channel)); +} + +/** + * @brief Function for removing multiple PPI channels from a channel group. + * + * @details This function removes all specified channels from the group. + * + * @param[in] channel_mask Channels to be removed from the group. + * + * @param[in] channel_group Channel group. + */ +__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask, + nrf_ppi_channel_group_t channel_group) +{ + NRF_PPI->CHG[(uint32_t) channel_group] = + NRF_PPI->CHG[(uint32_t) channel_group] & ~(channel_mask); +} + + +/** + * @brief Function for removing all PPI channels from a channel group. + * + * @param[in] group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group) +{ + NRF_PPI->CHG[(uint32_t) group] = 0; +} + + +/** + * @brief Function for enabling a channel group. + * + * @param[in] group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group) +{ + NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET; +} + + +/** + * @brief Function for disabling a channel group. + * + * @param[in] group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group) +{ + NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET; +} + + +/** + * @brief Function for setting a PPI task. + * + * @param[in] ppi_task PPI task to set. + */ +__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task) +{ + *((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET; +} + + +/** + * @brief Function for returning the address of a specific PPI task register. + * + * @param[in] ppi_task PPI task. + */ +__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task) +{ + return (uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task); +} + +/** + * @brief Function for returning the PPI enable task address of a specific group. + * + * @param[in] group PPI group. + */ +__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group) +{ + return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].EN; +} + +/** + * @brief Function for returning the PPI disable task address of a specific group. + * + * @param[in] group PPI group. + */ +__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group) +{ + return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS; +} + + +/** + *@} + **/ + +/*lint --flb "Leave library region" */ +#endif // NRF_PPI_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pwm.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pwm.h new file mode 100644 index 0000000..13296d7 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_pwm.h @@ -0,0 +1,661 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @defgroup nrf_pwm_hal PWM HAL + * @{ + * @ingroup nrf_pwm + * + * @brief @tagAPI52 Hardware access layer for managing the Pulse Width Modulation (PWM) + * peripheral. + */ + +#ifndef NRF_PWM_H__ +#define NRF_PWM_H__ + +#include +#include +#include + +#include "nrf.h" +#include "nrf_assert.h" + + +/** + * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set + * function call to specify that a given output channel shall not be + * connected to a physical pin. + */ +#define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF + +/** + * @brief Number of channels in each PWM instance. + */ +#define NRF_PWM_CHANNEL_COUNT 4 + + +/** + * @brief PWM tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback. + NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0. + NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1. + NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode. + /*lint -restore*/ +} nrf_pwm_task_t; + +/** + * @brief PWM events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated. + NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0. + NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1. + NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM. + NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM. + NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period. + NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the requested number of times. + /*lint -restore*/ +} nrf_pwm_event_t; + +/** + * @brief PWM interrupts. + */ +typedef enum +{ + NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. + NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event. + NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event. + NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event. + NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event. + NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event. + NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event. +} nrf_pwm_int_mask_t; + +/** + * @brief PWM shortcuts. + */ +typedef enum +{ + NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task. + NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task. + NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task. + NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task. + NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task. +} nrf_pwm_short_mask_t; + +/** + * @brief PWM modes of operation. + */ +typedef enum +{ + NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle). + NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle). +} nrf_pwm_mode_t; + +/** + * @brief PWM base clock frequencies. + */ +typedef enum +{ + NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz. + NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz. + NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz. + NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz. + NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz. + NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz. + NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz. + NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz. +} nrf_pwm_clk_t; + +/** + * @brief PWM decoder load modes. + * + * The selected mode determines how the sequence data is read from RAM and + * spread to the compare registers. + */ +typedef enum +{ + NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3). + NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3. + NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3. + NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter. +} nrf_pwm_dec_load_t; + +/** + * @brief PWM decoder next step modes. + * + * The selected mode determines when the next value from the active sequence + * is loaded. + */ +typedef enum +{ + NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times. + NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered. +} nrf_pwm_dec_step_t; + + +/** + * @brief Type used for defining duty cycle values for a sequence + * loaded in @ref NRF_PWM_LOAD_COMMON mode. + */ +typedef uint16_t nrf_pwm_values_common_t; + +/** + * @brief Structure for defining duty cycle values for a sequence + * loaded in @ref NRF_PWM_LOAD_GROUPED mode. + */ +typedef struct { + uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1). + uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3). +} nrf_pwm_values_grouped_t; + +/** + * @brief Structure for defining duty cycle values for a sequence + * loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode. + */ +typedef struct +{ + uint16_t channel_0; ///< Duty cycle value for channel 0. + uint16_t channel_1; ///< Duty cycle value for channel 1. + uint16_t channel_2; ///< Duty cycle value for channel 2. + uint16_t channel_3; ///< Duty cycle value for channel 3. +} nrf_pwm_values_individual_t; + +/** + * @brief Structure for defining duty cycle values for a sequence + * loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode. + */ +typedef struct { + uint16_t channel_0; ///< Duty cycle value for channel 0. + uint16_t channel_1; ///< Duty cycle value for channel 1. + uint16_t channel_2; ///< Duty cycle value for channel 2. + uint16_t counter_top; ///< Top value for the pulse generator counter. +} nrf_pwm_values_wave_form_t; + +/** + * @brief Union grouping pointers to arrays of duty cycle values applicable to + * various loading modes. + */ +typedef union { + nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode. + nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode. + nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode. + nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode. + uint16_t const * p_raw; ///< Pointer providing raw access to the values. +} nrf_pwm_values_t; + +/** + * @brief Structure for defining a sequence of PWM duty cycles. + * + * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the + * provided duty cycle values are not copied. The @p values pointer is stored + * in the peripheral's internal register, and the values are loaded from RAM + * during the sequence playback. Therefore, you must ensure that the values + * do not change before and during the sequence playback (for example, + * the values cannot be placed in a local variable that is allocated on stack). + * If the sequence is played in a loop and the values should be updated + * before the next iteration, it is safe to modify them when the corresponding + * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0 + * or @ref NRF_PWM_EVENT_SEQEND1, respectively). + * + * @note The @p repeats and @p end_delay values (which are written to the + * SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral, + * respectively) are ignored at the end of a complex sequence + * playback, indicated by the LOOPSDONE event. + * See the @linkProductSpecification52 for more information. + */ +typedef struct +{ + nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM. + /**< This field is defined as an union of pointers + * to provide a convenient way to define duty + * cycle values in various loading modes + * (see @ref nrf_pwm_dec_load_t). + * In each value, the most significant bit (15) + * determines the polarity of the output and the + * others (14-0) compose the 15-bit value to be + * compared with the pulse generator counter. */ + uint16_t length; ///< Number of 16-bit values in the array pointed by @p values. + uint32_t repeats; ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode. + uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode. +} nrf_pwm_sequence_t; + +/** + * @brief Helper macro for calculating the number of 16-bit values in specified + * array of duty cycle values. + */ +#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array)/sizeof(uint16_t)) + + +/** + * @brief Function for activating a specific PWM task. + * + * @param[in] p_pwm PWM instance. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_pwm, + nrf_pwm_task_t task); + +/** + * @brief Function for getting the address of a specific PWM task register. + * + * @param[in] p_pwm PWM instance. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_pwm, + nrf_pwm_task_t task); + +/** + * @brief Function for clearing a specific PWM event. + * + * @param[in] p_pwm PWM instance. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_pwm, + nrf_pwm_event_t event); + +/** + * @brief Function for checking the state of a specific PWM event. + * + * @param[in] p_pwm PWM instance. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_pwm, + nrf_pwm_event_t event); + +/** + * @brief Function for getting the address of a specific PWM event register. + * + * @param[in] p_pwm PWM instance. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_pwm, + nrf_pwm_event_t event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_pwm PWM instance. + * @param[in] pwm_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_pwm, + uint32_t pwm_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_pwm PWM instance. + * @param[in] pwm_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_pwm, + uint32_t pwm_shorts_mask); + +/** + * @brief Function for setting the configuration of PWM shortcuts. + * + * @param[in] p_pwm PWM instance. + * @param[in] pwm_shorts_mask Shortcuts configuration to set. + */ +__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_pwm, + uint32_t pwm_shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_pwm PWM instance. + * @param[in] pwm_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_pwm, + uint32_t pwm_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_pwm PWM instance. + * @param[in] pwm_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_pwm, + uint32_t pwm_int_mask); + +/** + * @brief Function for setting the configuration of PWM interrupts. + * + * @param[in] p_pwm PWM instance. + * @param[in] pwm_int_mask Interrupts configuration to set. + */ +__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_pwm, + uint32_t pwm_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_pwm PWM instance. + * @param[in] pwm_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_pwm, + nrf_pwm_int_mask_t pwm_int); + +/** + * @brief Function for enabling the PWM peripheral. + * + * @param[in] p_pwm PWM instance. + */ +__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_pwm); + +/** + * @brief Function for disabling the PWM peripheral. + * + * @param[in] p_pwm PWM instance. + */ +__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_pwm); + +/** + * @brief Function for assigning pins to PWM output channels. + * + * Usage of all PWM output channels is optional. If a given channel is not + * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin + * number. + * + * @param[in] p_pwm PWM instance. + * @param[in] out_pins Array with pin numbers for individual PWM output channels. + */ +__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_pwm, + uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]); + +/** + * @brief Function for configuring the PWM peripheral. + * + * @param[in] p_pwm PWM instance. + * @param[in] base_clock Base clock frequency. + * @param[in] mode Operating mode of the pulse generator counter. + * @param[in] top_value Value up to which the pulse generator counter counts. + */ +__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_pwm, + nrf_pwm_clk_t base_clock, + nrf_pwm_mode_t mode, + uint16_t top_value); + +/** + * @brief Function for defining a sequence of PWM duty cycles. + * + * @param[in] p_pwm PWM instance. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] p_seq Pointer to the sequence definition. + */ +__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + nrf_pwm_sequence_t const * p_seq); + +/** + * @brief Function for modifying the pointer to the duty cycle values + * in the specified sequence. + * + * @param[in] p_pwm PWM instance. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] p_values Pointer to an array with duty cycle values. + */ +__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + uint16_t const * p_values); + +/** + * @brief Function for modifying the total number of duty cycle values + * in the specified sequence. + * + * @param[in] p_pwm PWM instance. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] length Number of duty cycle values. + */ +__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + uint16_t length); + +/** + * @brief Function for modifying the additional number of PWM periods spent + * on each duty cycle value in the specified sequence. + * + * @param[in] p_pwm PWM instance. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] refresh Number of additional PWM periods for each duty cycle value. + */ +__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + uint32_t refresh); + +/** + * @brief Function for modifying the additional time added after the sequence + * is played. + * + * @param[in] p_pwm PWM instance. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] end_delay Number of PWM periods added at the end of the sequence. + */ +__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + uint32_t end_delay); + +/** + * @brief Function for setting the mode of loading sequence data from RAM + * and advancing the sequence. + * + * @param[in] p_pwm PWM instance. + * @param[in] dec_load Mode of loading sequence data from RAM. + * @param[in] dec_step Mode of advancing the active sequence. + */ +__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_pwm, + nrf_pwm_dec_load_t dec_load, + nrf_pwm_dec_step_t dec_step); + +/** + * @brief Function for setting the number of times the sequence playback + * should be performed. + * + * This function applies to two-sequence playback (concatenated sequence 0 and 1). + * A single sequence can be played back only once. + * + * @param[in] p_pwm PWM instance. + * @param[in] loop_count Number of times to perform the sequence playback. + */ +__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_pwm, + uint16_t loop_count); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_pwm, + nrf_pwm_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_pwm, + nrf_pwm_task_t task) +{ + return ((uint32_t)p_pwm + (uint32_t)task); +} + +__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_pwm, + nrf_pwm_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_pwm, + nrf_pwm_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_pwm, + nrf_pwm_event_t event) +{ + return ((uint32_t)p_pwm + (uint32_t)event); +} + +__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_pwm, + uint32_t pwm_shorts_mask) +{ + p_pwm->SHORTS |= pwm_shorts_mask; +} + +__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_pwm, + uint32_t pwm_shorts_mask) +{ + p_pwm->SHORTS &= ~(pwm_shorts_mask); +} + +__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_pwm, + uint32_t pwm_shorts_mask) +{ + p_pwm->SHORTS = pwm_shorts_mask; +} + +__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_pwm, + uint32_t pwm_int_mask) +{ + p_pwm->INTENSET = pwm_int_mask; +} + +__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_pwm, + uint32_t pwm_int_mask) +{ + p_pwm->INTENCLR = pwm_int_mask; +} + +__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_pwm, + uint32_t pwm_int_mask) +{ + p_pwm->INTEN = pwm_int_mask; +} + +__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_pwm, + nrf_pwm_int_mask_t pwm_int) +{ + return (bool)(p_pwm->INTENSET & pwm_int); +} + +__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_pwm) +{ + p_pwm->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_pwm) +{ + p_pwm->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_pwm, + uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]) +{ + uint8_t i; + for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i) + { + p_pwm->PSEL.OUT[i] = out_pins[i]; + } +} + +__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_pwm, + nrf_pwm_clk_t base_clock, + nrf_pwm_mode_t mode, + uint16_t top_value) +{ + ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk); + + p_pwm->PRESCALER = base_clock; + p_pwm->MODE = mode; + p_pwm->COUNTERTOP = top_value; +} + +__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + nrf_pwm_sequence_t const * p_seq) +{ + ASSERT(p_seq != NULL); + + nrf_pwm_seq_ptr_set( p_pwm, seq_id, p_seq->values.p_raw); + nrf_pwm_seq_cnt_set( p_pwm, seq_id, p_seq->length); + nrf_pwm_seq_refresh_set( p_pwm, seq_id, p_seq->repeats); + nrf_pwm_seq_end_delay_set(p_pwm, seq_id, p_seq->end_delay); +} + +__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + uint16_t const * p_values) +{ + ASSERT(seq_id <= 1); + ASSERT(p_values != NULL); + p_pwm->SEQ[seq_id].PTR = (uint32_t)p_values; +} + +__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + uint16_t length) +{ + ASSERT(seq_id <= 1); + ASSERT(length != 0); + ASSERT(length <= PWM_SEQ_CNT_CNT_Msk); + p_pwm->SEQ[seq_id].CNT = length; +} + +__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + uint32_t refresh) +{ + ASSERT(seq_id <= 1); + ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk); + p_pwm->SEQ[seq_id].REFRESH = refresh; +} + +__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_pwm, + uint8_t seq_id, + uint32_t end_delay) +{ + ASSERT(seq_id <= 1); + ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk); + p_pwm->SEQ[seq_id].ENDDELAY = end_delay; +} + +__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_pwm, + nrf_pwm_dec_load_t dec_load, + nrf_pwm_dec_step_t dec_step) +{ + p_pwm->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) | + ((uint32_t)dec_step << PWM_DECODER_MODE_Pos); +} + +__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_pwm, + uint16_t loop_count) +{ + p_pwm->LOOP = loop_count; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_PWM_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_qdec.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_qdec.h new file mode 100644 index 0000000..92de8fc --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_qdec.h @@ -0,0 +1,468 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#ifndef NRF_QDEC_H__ +#define NRF_QDEC_H__ + +#include +#include "nrf_error.h" +#include "nrf.h" + +/*lint ++flb "Enter library region" */ + +/** + * @defgroup nrf_qdec_hal QDEC HAL + * @{ + * @ingroup nrf_qdec + * @brief Hardware access layer for accessing the quadrature decoder (QDEC) peripheral. + */ + +/** + * @enum nrf_qdec_task_t + * @brief QDEC tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_QDEC_TASK_START = offsetof(NRF_QDEC_Type, TASKS_START), /**< Starting the quadrature decoder. */ + NRF_QDEC_TASK_STOP = offsetof(NRF_QDEC_Type, TASKS_STOP), /**< Stopping the quadrature decoder. */ + NRF_QDEC_TASK_READCLRACC = offsetof(NRF_QDEC_Type, TASKS_READCLRACC) /**< Reading and clearing ACC and ACCDBL registers. */ +} nrf_qdec_task_t; + +/** + * @enum nrf_qdec_event_t + * @brief QDEC events. + */ +typedef enum +{ + NRF_QDEC_EVENT_SAMPLERDY = offsetof(NRF_QDEC_Type, EVENTS_SAMPLERDY), /**< Event generated for every new sample. */ + NRF_QDEC_EVENT_REPORTRDY = offsetof(NRF_QDEC_Type, EVENTS_REPORTRDY), /**< Event generated for every new report. */ + NRF_QDEC_EVENT_ACCOF = offsetof(NRF_QDEC_Type, EVENTS_ACCOF) /**< Event generated for every accumulator overflow. */ +} nrf_qdec_event_t; /*lint -restore */ + +/** + * @enum nrf_qdec_short_mask_t + * @brief QDEC shortcuts. + */ +typedef enum +{ + NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK = QDEC_SHORTS_REPORTRDY_READCLRACC_Msk, /**< Shortcut between REPORTRDY event and READCLRACC task. */ + NRF_QDEC_SHORT_SAMPLERDY_STOP_MASK = QDEC_SHORTS_SAMPLERDY_STOP_Msk /**< Shortcut between SAMPLERDY event and STOP task. */ +} nrf_qdec_short_mask_t; + +/** + * @enum nrf_qdec_int_mask_t + * @brief QDEC interrupts. + */ +typedef enum +{ + NRF_QDEC_INT_SAMPLERDY_MASK = QDEC_INTENSET_SAMPLERDY_Msk, /**< Mask for enabling or disabling an interrupt on SAMPLERDY event. */ + NRF_QDEC_INT_REPORTRDY_MASK = QDEC_INTENSET_REPORTRDY_Msk, /**< Mask for enabling or disabling an interrupt on REPORTRDY event. */ + NRF_QDEC_INT_ACCOF_MASK = QDEC_INTENSET_ACCOF_Msk /**< Mask for enabling or disabling an interrupt on ACCOF event. */ +} nrf_qdec_int_mask_t; + +/** + * @enum nrf_qdec_enable_t + * @brief States of the enable bit. + */ +typedef enum +{ + NRF_QDEC_DISABLE = QDEC_ENABLE_ENABLE_Disabled, /**< Mask for disabling the QDEC periperal. When disabled, the QDEC decoder pins are not active. */ + NRF_QDEC_ENABLE = QDEC_ENABLE_ENABLE_Enabled /**< Mask for enabling the QDEC periperal. When enabled, the QDEC pins are active. */ +} nrf_qdec_enable_t; + + +/** + * @enum nrf_qdec_dbfen_t + * @brief States of the debounce filter enable bit. + */ +typedef enum +{ + NRF_QDEC_DBFEN_DISABLE = QDEC_DBFEN_DBFEN_Disabled, /**< Mask for disabling the debounce filter. */ + NRF_QDEC_DBFEN_ENABLE = QDEC_DBFEN_DBFEN_Enabled /**< Mask for enabling the debounce filter. */ +} nrf_qdec_dbfen_t; + +/** + * @enum nrf_qdec_ledpol_t + * @brief Active LED polarity. + */ +typedef enum +{ + NRF_QDEC_LEPOL_ACTIVE_LOW = QDEC_LEDPOL_LEDPOL_ActiveLow, /**< QDEC LED active on output pin low. */ + NRF_QDEC_LEPOL_ACTIVE_HIGH = QDEC_LEDPOL_LEDPOL_ActiveHigh /**< QDEC LED active on output pin high. */ +} nrf_qdec_ledpol_t; + + +/** + * @enum nrf_qdec_sampleper_t + * @brief Available sampling periods. + */ +typedef enum +{ + NRF_QDEC_SAMPLEPER_128us = QDEC_SAMPLEPER_SAMPLEPER_128us, /**< QDEC sampling period 128 microseconds. */ + NRF_QDEC_SAMPLEPER_256us = QDEC_SAMPLEPER_SAMPLEPER_256us, /**< QDEC sampling period 256 microseconds. */ + NRF_QDEC_SAMPLEPER_512us = QDEC_SAMPLEPER_SAMPLEPER_512us, /**< QDEC sampling period 512 microseconds. */ + NRF_QDEC_SAMPLEPER_1024us = QDEC_SAMPLEPER_SAMPLEPER_1024us, /**< QDEC sampling period 1024 microseconds. */ + NRF_QDEC_SAMPLEPER_2048us = QDEC_SAMPLEPER_SAMPLEPER_2048us, /**< QDEC sampling period 2048 microseconds. */ + NRF_QDEC_SAMPLEPER_4096us = QDEC_SAMPLEPER_SAMPLEPER_4096us, /**< QDEC sampling period 4096 microseconds. */ + NRF_QDEC_SAMPLEPER_8192us = QDEC_SAMPLEPER_SAMPLEPER_8192us, /**< QDEC sampling period 8192 microseconds. */ + NRF_QDEC_SAMPLEPER_16384us = QDEC_SAMPLEPER_SAMPLEPER_16384us /**< QDEC sampling period 16384 microseconds. */ +} nrf_qdec_sampleper_t; + +/** + * @enum nrf_qdec_reportper_t + * @brief Available report periods. + */ +typedef enum +{ + NRF_QDEC_REPORTPER_10 = QDEC_REPORTPER_REPORTPER_10Smpl, /**< QDEC report period 10 samples. */ + NRF_QDEC_REPORTPER_40 = QDEC_REPORTPER_REPORTPER_40Smpl, /**< QDEC report period 40 samples. */ + NRF_QDEC_REPORTPER_80 = QDEC_REPORTPER_REPORTPER_80Smpl, /**< QDEC report period 80 samples. */ + NRF_QDEC_REPORTPER_120 = QDEC_REPORTPER_REPORTPER_120Smpl, /**< QDEC report period 120 samples. */ + NRF_QDEC_REPORTPER_160 = QDEC_REPORTPER_REPORTPER_160Smpl, /**< QDEC report period 160 samples. */ + NRF_QDEC_REPORTPER_200 = QDEC_REPORTPER_REPORTPER_200Smpl, /**< QDEC report period 200 samples. */ + NRF_QDEC_REPORTPER_240 = QDEC_REPORTPER_REPORTPER_240Smpl, /**< QDEC report period 240 samples. */ + NRF_QDEC_REPORTPER_280 = QDEC_REPORTPER_REPORTPER_280Smpl, /**< QDEC report period 280 samples. */ + NRF_QDEC_REPORTPER_DISABLED /**< QDEC reporting disabled. */ +} nrf_qdec_reportper_t; + +/** + * @brief Function for enabling QDEC. + */ +__STATIC_INLINE void nrf_qdec_enable(void) +{ + NRF_QDEC->ENABLE = NRF_QDEC_ENABLE; +} + + +/** + * @brief Function for disabling QDEC. + */ +__STATIC_INLINE void nrf_qdec_disable(void) +{ + NRF_QDEC->ENABLE = NRF_QDEC_DISABLE; +} + + +/** + * @brief Function for returning the enable state of QDEC. + * @return State of the register. + */ +__STATIC_INLINE uint32_t nrf_qdec_enable_get(void) +{ + return NRF_QDEC->ENABLE; +} + + +/** + * @brief Function for enabling QDEC interrupts by mask. + * @param[in] qdec_int_mask Sources of the interrupts to enable. + */ +__STATIC_INLINE void nrf_qdec_int_enable(uint32_t qdec_int_mask) +{ + NRF_QDEC->INTENSET = qdec_int_mask; // writing 0 has no effect +} + + +/** + * @brief Function for disabling QDEC interrupts by mask. + * @param[in] qdec_int_mask Sources of the interrupts to disable. + * + */ +__STATIC_INLINE void nrf_qdec_int_disable(uint32_t qdec_int_mask) +{ + NRF_QDEC->INTENCLR = qdec_int_mask; // writing 0 has no effect +} + + +/** + * @brief Function for getting the enabled interrupts of the QDEC. + */ +__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t qdec_int_mask) +{ + return NRF_QDEC->INTENSET & qdec_int_mask; // when read this register will return the value of INTEN. +} + + +/** + * @brief Function for enabling the debouncing filter of the QED. + */ +__STATIC_INLINE void nrf_qdec_dbfen_enable(void) +{ + NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_ENABLE; +} + + +/** + * @brief Function for disabling the debouncing filter of the QED. + */ +__STATIC_INLINE void nrf_qdec_dbfen_disable(void) +{ + NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_DISABLE; +} + + +/** + * @brief Function for getting the state of the QDEC's debouncing filter. + * @retval NRF_QDEC_DBFEN_DISABLE If the debouncing filter is disabled. + * @retval NRF_QDEC_DBFEN_ENABLE If the debouncing filter is enabled. + */ +__STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void) +{ + return NRF_QDEC->DBFEN; +} + + +/** + * @brief Function for assigning QDEC pins. + * @param[in] psela Pin number. + * @param[in] pselb Pin number. + * @param[in] pselled Pin number. + */ +__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled) +{ +#ifdef NRF51 + NRF_QDEC->PSELA = psela; + NRF_QDEC->PSELB = pselb; + NRF_QDEC->PSELLED = pselled; +#elif defined NRF52 + NRF_QDEC->PSEL.A = psela; + NRF_QDEC->PSEL.B = pselb; + NRF_QDEC->PSEL.LED = pselled; +#endif +} + +/** + * @brief Function for setting a specific QDEC task. + * @param[in] qdec_task QDEC task to be set. + */ +__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task) ) = 1; +} + + +/** + * @brief Function for retrieving the address of a QDEC task register. + * @param[in] qdec_task QDEC task. + */ +__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t qdec_task) +{ + return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task); +} + + +/** + * @brief Function for clearing a specific QDEC event. + * @param[in] qdec_event QDEC event to clear. + */ +__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t qdec_event) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event) ) = 0; +} + + +/** + * @brief Function for retrieving the state of a specific QDEC event. + * @return State of the QDEC event. + */ +__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t qdec_event) +{ + return *(volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event); +} + + +/** + * @brief Function for retrieving the address of a specific QDEC event register. + * @param[in] qdec_event QDEC event. + * @return Address of the specified QDEC event. + */ +__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t qdec_event) +{ + return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event); +} + + +/** + * @brief Function for setting QDEC shortcuts. + * @param[in] qdec_short_mask QDEC shortcut by mask. + */ +__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t qdec_short_mask) +{ + NRF_QDEC->SHORTS |= qdec_short_mask; +} + + +/** + * @brief Function for clearing shortcuts of the QDEC by mask. + * @param[in] qdec_short_mask QDEC shortcute to be cleared. + */ +__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t qdec_short_mask) +{ + NRF_QDEC->SHORTS &= ~qdec_short_mask; +} + + +/** + * @brief Function for retrieving the value of QDEC's SAMPLEPER register. + * @return Value of the SAMPLEPER register. + */ +__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void) +{ + return NRF_QDEC->SAMPLEPER; +} + + +/** + * @brief Function for converting the value of QDEC's SAMPLE PERIOD to microseconds. + * @retval sampling period in microseconds. + */ +__STATIC_INLINE uint32_t nrf_qdec_sampleper_to_value(uint32_t sampleper) +{ + return (1 << (7+sampleper)); +} + +/** + * @brief Function for setting the value of QDEC's SAMPLEPER register. + * @param[in] sample_per Sampling period. + */ +__STATIC_INLINE void nrf_qdec_sampleper_set(nrf_qdec_sampleper_t sample_per) +{ + NRF_QDEC->SAMPLEPER = sample_per; +} + + +/** + * @brief Function for retrieving the value of QDEC's SAMPLE register. + * @return Value of the SAMPLE register. + */ +__STATIC_INLINE int32_t nrf_qdec_sample_get(void) +{ + return NRF_QDEC->SAMPLE; +} + + +/** + * @brief Function for retrieving the value of QDEC's ACC register. + * @return Value of the ACC register. + */ +__STATIC_INLINE int32_t nrf_qdec_acc_get(void) +{ + return NRF_QDEC->ACC; +} + + +/** + * @brief Function for retrieving the value of QDEC's ACCREAD register. + * @return Value of the ACCREAD register. + */ +__STATIC_INLINE int32_t nrf_qdec_accread_get(void) +{ + return NRF_QDEC->ACCREAD; +} + + +/** + * @brief Function for retrieving the value of QDEC's ACCDBL register. + * @return Value of the ACCDBL register. + */ +__STATIC_INLINE uint32_t nrf_qdec_accdbl_get(void) +{ + return NRF_QDEC->ACCDBL; +} + + +/** + * @brief Function for retrieving the value of QDEC's ACCDBLREAD register. + * @return Value of the ACCDBLREAD register. + */ +__STATIC_INLINE uint32_t nrf_qdec_accdblread_get(void) +{ + return NRF_QDEC->ACCDBLREAD; +} + + +/** + * @brief Function for setting how long the LED is switched on before sampling. + * @param[in] time_us Time (in microseconds) how long the LED is switched on before sampling. + */ +__STATIC_INLINE void nrf_qdec_ledpre_set(uint32_t time_us) +{ + NRF_QDEC->LEDPRE = time_us; +} + + +/** + * @brief Function for retrieving how long the LED is switched on before sampling. + * @retval time_us Time (in microseconds) how long the LED is switched on before sampling. + */ +__STATIC_INLINE uint32_t nrf_qdec_ledpre_get(void) +{ + return NRF_QDEC->LEDPRE; +} + + +/** + * @brief Function for setting the report period (in samples). + * @param[in] reportper Number of samples. + */ +__STATIC_INLINE void nrf_qdec_reportper_set(nrf_qdec_reportper_t reportper) +{ + NRF_QDEC->REPORTPER = reportper; +} + + +/** + * @brief Function for retrieving the report period. + * @retval reportper Number of samples as encoded in the register. + */ +__STATIC_INLINE uint32_t nrf_qdec_reportper_reg_get(void) +{ + return NRF_QDEC->REPORTPER; +} + + +/** + * @brief Function for retrieving the value of QDEC's SAMPLEPER register. + * @param [in] reportper Reportper to be converted to amount of samples per report. + + */ +__STATIC_INLINE uint32_t nrf_qdec_reportper_to_value(uint32_t reportper) +{ + return (reportper == NRF_QDEC_REPORTPER_10) ? 10 : reportper*40; +} + + +/** + * @brief Function for setting the active level for the LED. + * @param[in] pol Active level for the LED. + */ +__STATIC_INLINE void nrf_qdec_ledpol_set(nrf_qdec_ledpol_t pol) +{ + NRF_QDEC->LEDPOL = pol; +} + + +/** + * @brief Function for retrieving the active level for the LED. + * @return Active level for the LED. + */ +__STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void) +{ + return NRF_QDEC->LEDPOL; +} + + +/** + *@} + **/ + +/*lint --flb "Leave library region" */ +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rng.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rng.h new file mode 100644 index 0000000..b696588 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rng.h @@ -0,0 +1,211 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @file + * @brief RNG HAL API. + */ + +#ifndef NRF_RNG_H__ +#define NRF_RNG_H__ +/** + * @defgroup nrf_rng_hal RNG HAL + * @{ + * @ingroup nrf_rng + * @brief Hardware access layer for managing the random number generator (RNG). + */ + +#include +#include +#include +#include "nrf.h" + +#define NRF_RNG_TASK_SET (1UL) +#define NRF_RNG_EVENT_CLEAR (0UL) +/** + * @enum nrf_rng_task_t + * @brief RNG tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_RNG_TASK_START = offsetof(NRF_RNG_Type, TASKS_START), /**< Start the random number generator. */ + NRF_RNG_TASK_STOP = offsetof(NRF_RNG_Type, TASKS_STOP) /**< Stop the random number generator. */ +} nrf_rng_task_t; /*lint -restore */ + +/** + * @enum nrf_rng_event_t + * @brief RNG events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_RNG_EVENT_VALRDY = offsetof(NRF_RNG_Type, EVENTS_VALRDY) /**< New random number generated event. */ +} nrf_rng_event_t; /*lint -restore */ + +/** + * @enum nrf_rng_int_mask_t + * @brief RNG interrupts. + */ +typedef enum +{ + NRF_RNG_INT_VALRDY_MASK = RNG_INTENSET_VALRDY_Msk /**< Mask for enabling or disabling an interrupt on VALRDY event. */ +} nrf_rng_int_mask_t; + +/** + * @enum nrf_rng_short_mask_t + * @brief Types of RNG shortcuts. + */ +typedef enum +{ + NRF_RNG_SHORT_VALRDY_STOP_MASK = RNG_SHORTS_VALRDY_STOP_Msk /**< Mask for setting shortcut between EVENT_VALRDY and TASK_STOP. */ +} nrf_rng_short_mask_t; + +/** + * @brief Function for enabling interrupts. + * + * @param[in] rng_int_mask Mask of interrupts. + */ +__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask) +{ + NRF_RNG->INTENSET = rng_int_mask; +} + +/** + * @brief Function for disabling interrupts. + * + * @param[in] rng_int_mask Mask of interrupts. + */ +__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask) +{ + NRF_RNG->INTENCLR = rng_int_mask; +} + +/** + * @brief Function for getting the state of a specific interrupt. + * + * @param[in] rng_int_mask Interrupt. + * + * @retval true If the interrupt is not enabled. + * @retval false If the interrupt is enabled. + */ +__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask) +{ + return (bool)(NRF_RNG->INTENCLR & rng_int_mask); +} + +/** + * @brief Function for getting the address of a specific task. + * + * This function can be used by the PPI module. + * + * @param[in] rng_task Task. + */ +__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task) +{ + return (uint32_t *)((uint8_t *)NRF_RNG + rng_task); +} + +/** + * @brief Function for setting a specific task. + * + * @param[in] rng_task Task. + */ +__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_task)) = NRF_RNG_TASK_SET; +} + +/** + * @brief Function for getting address of a specific event. + * + * This function can be used by the PPI module. + * + * @param[in] rng_event Event. + */ +__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event) +{ + return (uint32_t *)((uint8_t *)NRF_RNG + rng_event); +} + +/** + * @brief Function for clearing a specific event. + * + * @param[in] rng_event Event. + */ +__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)) = NRF_RNG_EVENT_CLEAR; +} + +/** + * @brief Function for getting the state of a specific event. + * + * @param[in] rng_event Event. + * + * @retval true If the event is not set. + * @retval false If the event is set. + */ +__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event) +{ + return (bool)*((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)); +} + +/** + * @brief Function for setting shortcuts. + * + * @param[in] rng_short_mask Mask of shortcuts. + * + */ +__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask) +{ + NRF_RNG->SHORTS |= rng_short_mask; +} + +/** + * @brief Function for clearing shortcuts. + * + * @param[in] rng_short_mask Mask of shortcuts. + * + */ +__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask) +{ + NRF_RNG->SHORTS &= ~rng_short_mask; +} + +/** + * @brief Function for getting the previously generated random value. + * + * @return Previously generated random value. + */ +__STATIC_INLINE uint8_t nrf_rng_random_value_get(void) +{ + return (uint8_t)(NRF_RNG->VALUE & RNG_VALUE_VALUE_Msk); +} + +/** + * @brief Function for enabling digital error correction. + */ +__STATIC_INLINE void nrf_rng_error_correction_enable(void) +{ + NRF_RNG->CONFIG |= RNG_CONFIG_DERCEN_Msk; +} + +/** + * @brief Function for disabling digital error correction. + */ +__STATIC_INLINE void nrf_rng_error_correction_disable(void) +{ + NRF_RNG->CONFIG &= ~RNG_CONFIG_DERCEN_Msk; +} +/** + *@} + **/ +#endif /* NRF_RNG_H__ */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rtc.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rtc.h new file mode 100644 index 0000000..814da83 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_rtc.h @@ -0,0 +1,304 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @file + * @brief RTC HAL API. + */ + +#ifndef NRF_RTC_H +#define NRF_RTC_H + +/** + * @defgroup nrf_rtc_hal RTC HAL + * @{ + * @ingroup nrf_rtc + * @brief Hardware access layer for managing the real time counter (RTC). + */ + +#include +#include +#include +#include "nrf.h" +#include "nrf_assert.h" + +/** + * @brief Macro for getting the number of compare channels available + * in a given RTC instance. + */ +#ifdef NRF51 + #define NRF_RTC_CC_CHANNEL_COUNT(id) 4 +#else + #define NRF_RTC_CC_CHANNEL_COUNT(id) ((id) == 0 ? 3 : 4) +#endif + +#define RTC_INPUT_FREQ 32768 /**< Input frequency of the RTC instance. */ + +/**< Macro for wrapping values to RTC capacity. */ +#define RTC_WRAP(val) (val & RTC_COUNTER_COUNTER_Msk) + +#define RTC_CHANNEL_INT_MASK(ch) ((uint32_t)NRF_RTC_INT_COMPARE0_MASK << ch) +#define RTC_CHANNEL_EVENT_ADDR(ch) (nrf_rtc_event_t)(NRF_RTC_EVENT_COMPARE_0 + ch*sizeof(uint32_t)) +/** + * @enum nrf_rtc_task_t + * @brief RTC tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_RTC_TASK_START = offsetof(NRF_RTC_Type,TASKS_START), /**< Start. */ + NRF_RTC_TASK_STOP = offsetof(NRF_RTC_Type,TASKS_STOP), /**< Stop. */ + NRF_RTC_TASK_CLEAR = offsetof(NRF_RTC_Type,TASKS_CLEAR), /**< Clear. */ + NRF_RTC_TASK_TRIGGER_OVERFLOW = offsetof(NRF_RTC_Type,TASKS_TRIGOVRFLW),/**< Trigger overflow. */ + /*lint -restore*/ +} nrf_rtc_task_t; + +/** + * @enum nrf_rtc_event_t + * @brief RTC events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_RTC_EVENT_TICK = offsetof(NRF_RTC_Type,EVENTS_TICK), /**< Tick event. */ + NRF_RTC_EVENT_OVERFLOW = offsetof(NRF_RTC_Type,EVENTS_OVRFLW), /**< Overflow event. */ + NRF_RTC_EVENT_COMPARE_0 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[0]), /**< Compare 0 event. */ + NRF_RTC_EVENT_COMPARE_1 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[1]), /**< Compare 1 event. */ + NRF_RTC_EVENT_COMPARE_2 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[2]), /**< Compare 2 event. */ + NRF_RTC_EVENT_COMPARE_3 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[3]) /**< Compare 3 event. */ + /*lint -restore*/ +} nrf_rtc_event_t; + +/** + * @enum nrf_rtc_int_t + * @brief RTC interrupts. + */ +typedef enum +{ + NRF_RTC_INT_TICK_MASK = RTC_INTENSET_TICK_Msk, /**< RTC interrupt from tick event. */ + NRF_RTC_INT_OVERFLOW_MASK = RTC_INTENSET_OVRFLW_Msk, /**< RTC interrupt from overflow event. */ + NRF_RTC_INT_COMPARE0_MASK = RTC_INTENSET_COMPARE0_Msk, /**< RTC interrupt from compare event on channel 0. */ + NRF_RTC_INT_COMPARE1_MASK = RTC_INTENSET_COMPARE1_Msk, /**< RTC interrupt from compare event on channel 1. */ + NRF_RTC_INT_COMPARE2_MASK = RTC_INTENSET_COMPARE2_Msk, /**< RTC interrupt from compare event on channel 2. */ + NRF_RTC_INT_COMPARE3_MASK = RTC_INTENSET_COMPARE3_Msk /**< RTC interrupt from compare event on channel 3. */ +} nrf_rtc_int_t; + +/**@brief Function for setting a compare value for a channel. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] ch Channel. + * @param[in] cc_val Compare value to set. + */ +__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val); + +/**@brief Function for returning the compare value for a channel. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] ch Channel. + * + * @return COMPARE[ch] value. + */ +__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch); + +/**@brief Function for enabling interrupts. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] mask Interrupt mask to be enabled. + */ +__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask); + +/**@brief Function for disabling interrupts. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] mask Interrupt mask to be disabled. + */ +__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask); + +/**@brief Function for checking if interrupts are enabled. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] mask Mask of interrupt flags to check. + * + * @return Mask with enabled interrupts. + */ +__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask); + +/**@brief Function for returning the status of currently enabled interrupts. + * + * @param[in] p_rtc Pointer to the instance register structure. + * + * @return Value in INTEN register. + */ +__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc); + +/**@brief Function for checking if an event is pending. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] event Address of the event. + * + * @return Mask of pending events. + */ +__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event); + +/**@brief Function for clearing an event. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event); + +/**@brief Function for returning a counter value. + * + * @param[in] p_rtc Pointer to the instance register structure. + * + * @return Counter value. + */ +__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc); + +/**@brief Function for setting a prescaler value. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] val Value to set the prescaler to. + */ +__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val); + +/**@brief Function for returning the address of an event. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] event Requested event. + * + * @return Address of the requested event register. + */ +__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event); + +/**@brief Function for returning the address of a task. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] task Requested task. + * + * @return Address of the requested task register. + */ +__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task); + +/**@brief Function for starting a task. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] task Requested task. + */ +__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task); + +/**@brief Function for enabling events. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] mask Mask of event flags to enable. + */ +__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask); + +/**@brief Function for disabling an event. + * + * @param[in] p_rtc Pointer to the instance register structure. + * @param[in] event Requested event. + */ +__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t event); + +/** + *@} + **/ + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val) +{ + p_rtc->CC[ch] = cc_val; +} + +__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch) +{ + return p_rtc->CC[ch]; +} + +__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + p_rtc->INTENSET = mask; +} + +__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + p_rtc->INTENCLR = mask; +} + +__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + return (p_rtc->INTENSET & mask); +} + +__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc) +{ + return p_rtc->INTENSET; +} + +__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event) +{ + return *(volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event); +} + +__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)) = 0; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc) +{ + return p_rtc->COUNTER; +} + +__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val) +{ + ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos)); + p_rtc->PRESCALER = val; +} +__STATIC_INLINE uint32_t rtc_prescaler_get(NRF_RTC_Type * p_rtc) +{ + return p_rtc->PRESCALER; +} + +__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event) +{ + return (uint32_t)p_rtc + event; +} + +__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task) +{ + return (uint32_t)p_rtc + task; +} + +__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task) +{ + *(__IO uint32_t *)((uint32_t)p_rtc + task) = 1; +} + +__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + p_rtc->EVTENSET = mask; +} +__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + p_rtc->EVTENCLR = mask; +} +#endif + +#endif /* NRF_RTC_H */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.c new file mode 100644 index 0000000..849c3bd --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.c @@ -0,0 +1,31 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @file + * @brief SAADC HAL implementation + */ + +#include "nrf_saadc.h" + +void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config) +{ + NRF_SAADC->CH[channel].CONFIG = + ((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk) + | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk) + | ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk) + | ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk) + | ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk) + | ((config->mode << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk); + nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n); + return; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.h new file mode 100644 index 0000000..6824c30 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_saadc.h @@ -0,0 +1,554 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + + +#ifndef NRF_SAADC_H_ +#define NRF_SAADC_H_ + +/** + * @defgroup nrf_saadc_hal SAADC HAL + * @{ + * @ingroup nrf_saadc + * + * @brief @tagAPI52 Hardware access layer for accessing the SAADC peripheral. + */ + +#include +#include +#include "nrf.h" +#include "nrf_assert.h" + +#define NRF_SAADC_CHANNEL_COUNT 8 + +/** + * @brief Resolution of the analog-to-digital converter. + */ +typedef enum +{ + NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution. + NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution. + NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution. + NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution. +} nrf_saadc_resolution_t; + + +/** + * @brief Input selection for the analog-to-digital converter. + */ +typedef enum +{ + NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected. + NRF_SAADC_INPUT_AIN0 = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0). + NRF_SAADC_INPUT_AIN1 = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1). + NRF_SAADC_INPUT_AIN2 = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2). + NRF_SAADC_INPUT_AIN3 = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3). + NRF_SAADC_INPUT_AIN4 = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4). + NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5). + NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6). + NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7). + NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD ///< VDD as input. +} nrf_saadc_input_t; + + +/** + * @brief Analog-to-digital converter oversampling mode. + */ +typedef enum +{ + NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling. + NRF_SAADC_OVERSAMPLE_2X = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x, ///< Oversample 2x. + NRF_SAADC_OVERSAMPLE_4X = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x, ///< Oversample 4x. + NRF_SAADC_OVERSAMPLE_8X = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x, ///< Oversample 8x. + NRF_SAADC_OVERSAMPLE_16X = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x, ///< Oversample 16x. + NRF_SAADC_OVERSAMPLE_32X = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x, ///< Oversample 32x. + NRF_SAADC_OVERSAMPLE_64X = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x, ///< Oversample 64x. + NRF_SAADC_OVERSAMPLE_128X = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x. + NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x. +} nrf_saadc_oversample_t; + + +/** + * @brief Analog-to-digital converter channel resistor control. + */ +typedef enum +{ + NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder. + NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND. + NRF_SAADC_RESISTOR_PULLUP = SAADC_CH_CONFIG_RESP_Pullup, ///< Pull-up to VDD. + NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2 ///< Set input at VDD/2. +} nrf_saadc_resistor_t; + + +/** + * @brief Gain factor of the analog-to-digital converter input. + */ +typedef enum +{ + NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6. + NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5. + NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4. + NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3. + NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2. + NRF_SAADC_GAIN1 = SAADC_CH_CONFIG_GAIN_Gain1, ///< Gain factor 1. + NRF_SAADC_GAIN2 = SAADC_CH_CONFIG_GAIN_Gain2, ///< Gain factor 2. + NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4. +} nrf_saadc_gain_t; + + +/** + * @brief Reference selection for the analog-to-digital converter. + */ +typedef enum +{ + NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference (0.6 V). + NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference. +} nrf_saadc_reference_t; + + +/** + * @brief Analog-to-digital converter acquisition time. + */ +typedef enum +{ + NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us. + NRF_SAADC_ACQTIME_5US = SAADC_CH_CONFIG_TACQ_5us, ///< 5 us. + NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us. + NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us. + NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us. + NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us. +} nrf_saadc_acqtime_t; + + +/** + * @brief Analog-to-digital converter channel mode. + */ +typedef enum +{ + NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single ended, PSELN will be ignored, negative input to ADC shorted to GND. + NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode. +} nrf_saadc_mode_t; + + +/** + * @brief Analog-to-digital converter tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM. + NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled. + NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any on-going conversion. + NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration. +} nrf_saadc_task_t; + + +/** + * @brief Analog-to-digital converter events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started. + NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer. + NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete. + NRF_SAADC_EVENT_STOPPED = offsetof(NRF_SAADC_Type, EVENTS_STOPPED), ///< The ADC has stopped. + NRF_SAADC_EVENT_CH0_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH), ///< Last result is equal or above CH[0].LIMIT.HIGH. + NRF_SAADC_EVENT_CH0_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL), ///< Last result is equal or below CH[0].LIMIT.LOW. + NRF_SAADC_EVENT_CH1_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH), ///< Last result is equal or above CH[1].LIMIT.HIGH. + NRF_SAADC_EVENT_CH1_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL), ///< Last result is equal or below CH[1].LIMIT.LOW. + NRF_SAADC_EVENT_CH2_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH), ///< Last result is equal or above CH[2].LIMIT.HIGH. + NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW. + NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH. + NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW. + NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH. + NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW. + NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH. + NRF_SAADC_EVENT_CH5_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL), ///< Last result is equal or below CH[5].LIMIT.LOW. + NRF_SAADC_EVENT_CH6_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH), ///< Last result is equal or above CH[6].LIMIT.HIGH. + NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW. + NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH. + NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW. +} nrf_saadc_event_t; + + +/** + * @brief Analog-to-digital converter interrupt masks. + */ +typedef enum +{ + NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event. + NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event. + NRF_SAADC_INT_STOPPED = SAADC_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event. + NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event. + NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event. + NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event. + NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event. + NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event. + NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event. + NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event. + NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event. + NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event. + NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event. + NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event. + NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event. + NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event. + NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event. + NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event. + NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event. + NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts. +} nrf_saadc_int_mask_t; + + +/** + * @brief Analog-to-digital converter value limit type. + */ +typedef enum +{ + NRF_SAADC_LIMIT_LOW = 0, + NRF_SAADC_LIMIT_HIGH = 1 +} nrf_saadc_limit_t; + + +typedef int16_t nrf_saadc_value_t; ///< Type of a single ADC conversion result. + + +/** + * @brief Analog-to-digital converter configuration structure. + */ +typedef struct +{ + nrf_saadc_resolution_t resolution; + nrf_saadc_oversample_t oversample; + nrf_saadc_value_t * buffer; + uint32_t buffer_size; +} nrf_saadc_config_t; + + +/** + * @brief Analog-to-digital converter channel configuration structure. + */ +typedef struct +{ + nrf_saadc_resistor_t resistor_p; + nrf_saadc_resistor_t resistor_n; + nrf_saadc_gain_t gain; + nrf_saadc_reference_t reference; + nrf_saadc_acqtime_t acq_time; + nrf_saadc_mode_t mode; + nrf_saadc_input_t pin_p; + nrf_saadc_input_t pin_n; +} nrf_saadc_channel_config_t; + + +/** + * @brief Function for triggering a specific SAADC task. + * + * @param[in] saadc_task SAADC task. + */ +__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task)) = 0x1UL; +} + + +/** + * @brief Function for getting the address of a specific SAADC task register. + * + * @param[in] saadc_task SAADC task. + * + * @return Address of the specified SAADC task. + */ +__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task) +{ + return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task); +} + + +/** + * @brief Function for getting the state of a specific SAADC event. + * + * @param[in] saadc_event SAADC event. + * + * @return State of the specified SAADC event. + */ +__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event); +} + + +/** + * @brief Function for clearing the specific SAADC event. + * + * @param[in] saadc_event SAADC event. + */ +__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)) = 0x0UL; +} + + +/** + * @brief Function for getting the address of a specific SAADC event register. + * + * @param[in] saadc_event SAADC event. + * + * @return Address of the specified SAADC event. + */ +__STATIC_INLINE volatile uint32_t * nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event) +{ + return (volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event); +} + + +/** + * @brief Function for getting the address of a specific SAADC limit event register. + * + * @param[in] channel Channel number. + * @param[in] limit_type Low limit or high limit. + * + * @return Address of the specified SAADC limit event. + */ +__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type) +{ + ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); + if (limit_type == NRF_SAADC_LIMIT_HIGH) + { + return &NRF_SAADC->EVENTS_CH[channel].LIMITH; + } + else + { + return &NRF_SAADC->EVENTS_CH[channel].LIMITL; + } +} + + +/** + * @brief Function for getting the SAADC channel monitoring limit events. + * + * @param[in] channel Channel number. + * @param[in] limit_type Low limit or high limit. + */ +__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type) +{ + if (limit_type == NRF_SAADC_LIMIT_HIGH) + { + return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITH + + (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITH - NRF_SAADC_EVENT_CH0_LIMITH) + * (uint32_t) channel ); + } + else + { + return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITL + + (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITL - NRF_SAADC_EVENT_CH0_LIMITL) + * (uint32_t) channel ); + } +} + + +/** + * @brief Function for configuring the input pins for a specific SAADC channel. + * + * @param[in] channel Channel number. + * @param[in] pselp Positive input. + * @param[in] pseln Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode. + */ +__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel, + nrf_saadc_input_t pselp, + nrf_saadc_input_t pseln) +{ + NRF_SAADC->CH[channel].PSELN = pseln; + NRF_SAADC->CH[channel].PSELP = pselp; +} + + +/** + * @brief Function for setting the SAADC channel monitoring limits. + * + * @param[in] channel Channel number. + * @param[in] low Low limit. + * @param[in] high High limit. + */ +__STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low, int16_t high) +{ + NRF_SAADC->CH[channel].LIMIT = ( + (((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk) + | (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk)); +} + + +/** + * @brief Function for enabling specified SAADC interrupts. + * + * @param[in] saadc_int_mask Interrupt(s) to enable. + */ +__STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask) +{ + NRF_SAADC->INTENSET = saadc_int_mask; +} + + +/** + * @brief Function for retrieving the state of specified SAADC interrupts. + * + * @param[in] saadc_int_mask Interrupt(s) to check. + * + * @retval true If all specified interrupts are enabled. + * @retval false If at least one of the given interrupts is not enabled. + */ +__STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask) +{ + return (bool)(NRF_SAADC->INTENSET & saadc_int_mask); +} + + +/** + * @brief Function for disabling specified interrupts. + * + * @param saadc_int_mask Interrupt(s) to disable. + */ +__STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask) +{ + NRF_SAADC->INTENCLR = saadc_int_mask; +} + + +/** + * @brief Function for generating masks for SAADC channel limit interrupts. + * + * @param[in] channel SAADC channel number. + * @param[in] limit_type Limit type. + * + * @returns Interrupt mask. + */ +__STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type) +{ + ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); + uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ? NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH; + return mask << (channel * 2); +} + + +/** + * @brief Function for checking whether the SAADC is busy. + * + * This function checks whether the analog-to-digital converter is busy with a conversion. + * + * @retval true If the SAADC is busy. + * @retval false If the SAADC is not busy. + */ +__STATIC_INLINE bool nrf_saadc_busy_check(void) +{ + //return ((NRF_SAADC->STATUS & SAADC_STATUS_STATUS_Msk) == SAADC_STATUS_STATUS_Msk); + //simplified for performance + return NRF_SAADC->STATUS; +} + + +/** + * @brief Function for enabling the SAADC. + * + * The analog-to-digital converter must be enabled before use. + */ +__STATIC_INLINE void nrf_saadc_enable(void) +{ + NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos); +} + + +/** + * @brief Function for disabling the SAADC. + */ +__STATIC_INLINE void nrf_saadc_disable(void) +{ + NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos); +} + + +/** + * @brief Function for checking if the SAADC is enabled. + * + * @retval true If the SAADC is enabled. + * @retval false If the SAADC is not enabled. + */ +__STATIC_INLINE bool nrf_saadc_enable_check(void) +{ + //simplified for performance + return NRF_SAADC->ENABLE; +} + + +/** + * @brief Function for initializing the SAADC result buffer. + * + * @param[in] buffer Pointer to the result buffer. + * @param[in] num Size of buffer in words. + */ +__STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * buffer, uint32_t num) +{ + NRF_SAADC->RESULT.PTR = (uint32_t)buffer; + NRF_SAADC->RESULT.MAXCNT = num; +} + +/** + * @brief Function for getting the number of buffer words transferred since last START operation. + * + * @returns Number of words transferred. + */ +__STATIC_INLINE uint16_t nrf_saadc_amount_get(void) +{ + return NRF_SAADC->RESULT.AMOUNT; +} + + +/** + * @brief Function for setting the SAADC sample resolution. + * + * @param[in] resolution Bit resolution. + */ +__STATIC_INLINE void nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution) +{ + NRF_SAADC->RESOLUTION = resolution; +} + + +/** + * @brief Function for configuring the oversampling feature. + * + * @param[in] oversample Oversampling mode. + */ +__STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample) +{ + NRF_SAADC->OVERSAMPLE = oversample; +} + +/** + * @brief Function for getting the oversampling feature configuration. + * + * @return Oversampling configuration. + */ +__STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void) +{ + return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE; +} + +/** + * @brief Function for initializing the SAADC channel. + * + * @param[in] channel Channel number. + * @param[in] config Pointer to the channel configuration structure. + */ +void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config); + +/** + *@} + **/ + +#endif /* NRF_SAADC_H_ */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spi.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spi.h new file mode 100644 index 0000000..a571ed1 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spi.h @@ -0,0 +1,334 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @defgroup nrf_spi_hal SPI HAL + * @{ + * @ingroup nrf_spi_master + * + * @brief Hardware access layer for accessing the SPI peripheral. + */ + +#ifndef NRF_SPI_H__ +#define NRF_SPI_H__ + +#include +#include +#include + +#include "nrf.h" + + +/** + * @brief This value can be used as a parameter for the @ref nrf_spi_pins_set + * function to specify that a given SPI signal (SCK, MOSI, or MISO) + * shall not be connected to a physical pin. + */ +#define NRF_SPI_PIN_NOT_CONNECTED 0xFFFFFFFF + + +/** + * @brief SPI events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPI_EVENT_READY = offsetof(NRF_SPI_Type, EVENTS_READY) ///< TXD byte sent and RXD byte received. + /*lint -restore*/ +} nrf_spi_event_t; + +/** + * @brief SPI interrupts. + */ +typedef enum +{ + NRF_SPI_INT_READY_MASK = SPI_INTENSET_READY_Msk ///< Interrupt on READY event. +} nrf_spi_int_mask_t; + +/** + * @brief SPI data rates. + */ +typedef enum +{ + NRF_SPI_FREQ_125K = SPI_FREQUENCY_FREQUENCY_K125, ///< 125 kbps. + NRF_SPI_FREQ_250K = SPI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_SPI_FREQ_500K = SPI_FREQUENCY_FREQUENCY_K500, ///< 500 kbps. + NRF_SPI_FREQ_1M = SPI_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps. + NRF_SPI_FREQ_2M = SPI_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps. + NRF_SPI_FREQ_4M = SPI_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps. + // [conversion to 'int' needed to prevent compilers from complaining + // that the provided value (0x80000000UL) is out of range of "int"] + NRF_SPI_FREQ_8M = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps. +} nrf_spi_frequency_t; + +/** + * @brief SPI modes. + */ +typedef enum +{ + NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock. + NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock. + NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock. + NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock. +} nrf_spi_mode_t; + +/** + * @brief SPI bit orders. + */ +typedef enum +{ + NRF_SPI_BIT_ORDER_MSB_FIRST = SPI_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. + NRF_SPI_BIT_ORDER_LSB_FIRST = SPI_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. +} nrf_spi_bit_order_t; + + +/** + * @brief Function for clearing a specific SPI event. + * + * @param[in] p_spi SPI instance. + * @param[in] spi_event Event to clear. + */ +__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_spi, + nrf_spi_event_t spi_event); + +/** + * @brief Function for checking the state of a specific SPI event. + * + * @param[in] p_spi SPI instance. + * @param[in] spi_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_spi, + nrf_spi_event_t spi_event); + +/** + * @brief Function for getting the address of a specific SPI event register. + * + * @param[in] p_spi SPI instance. + * @param[in] spi_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_spi, + nrf_spi_event_t spi_event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_spi SPI instance. + * @param[in] spi_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_spi, + uint32_t spi_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_spi SPI instance. + * @param[in] spi_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_spi, + uint32_t spi_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_spi SPI instance. + * @param[in] spi_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_spi, + nrf_spi_int_mask_t spi_int); + +/** + * @brief Function for enabling the SPI peripheral. + * + * @param[in] p_spi SPI instance. + */ +__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_spi); + +/** + * @brief Function for disabling the SPI peripheral. + * + * @param[in] p_spi SPI instance. + */ +__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_spi); + +/** + * @brief Function for configuring SPI pins. + * + * If a given signal is not needed, pass the @ref NRF_SPI_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_spi SPI instance. + * @param[in] sck_pin SCK pin number. + * @param[in] mosi_pin MOSI pin number. + * @param[in] miso_pin MISO pin number. + */ +__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_spi, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin); + +/** + * @brief Function for writing data to the SPI transmitter register. + * + * @param[in] p_spi SPI instance. + * @param[in] data TX data to send. + */ +__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_spi, uint8_t data); + +/** + * @brief Function for reading data from the SPI receiver register. + * + * @param[in] p_spi SPI instance. + * + * @return RX data received. + */ +__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_spi); + +/** + * @brief Function for setting the SPI master data rate. + * + * @param[in] p_spi SPI instance. + * @param[in] frequency SPI frequency. + */ +__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_spi, + nrf_spi_frequency_t frequency); + +/** + * @brief Function for setting the SPI configuration. + * + * @param[in] p_spi SPI instance. + * @param[in] spi_mode SPI mode. + * @param[in] spi_bit_order SPI bit order. + */ +__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_spi, + nrf_spi_mode_t spi_mode, + nrf_spi_bit_order_t spi_bit_order); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_spi, + nrf_spi_event_t spi_event) +{ + *((volatile uint32_t *)((uint8_t *)p_spi + (uint32_t)spi_event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_spi, + nrf_spi_event_t spi_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_spi + (uint32_t)spi_event); +} + +__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_spi, + nrf_spi_event_t spi_event) +{ + return (uint32_t *)((uint8_t *)p_spi + (uint32_t)spi_event); +} + +__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_spi, + uint32_t spi_int_mask) +{ + p_spi->INTENSET = spi_int_mask; +} + +__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_spi, + uint32_t spi_int_mask) +{ + p_spi->INTENCLR = spi_int_mask; +} + +__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_spi, + nrf_spi_int_mask_t spi_int) +{ + return (bool)(p_spi->INTENSET & spi_int); +} + +__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_spi) +{ + p_spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_spi) +{ + p_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_spi, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin) +{ + p_spi->PSELSCK = sck_pin; + p_spi->PSELMOSI = mosi_pin; + p_spi->PSELMISO = miso_pin; +} + +__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_spi, uint8_t data) +{ + p_spi->TXD = data; +} + +__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_spi) +{ + return p_spi->RXD; +} + +__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_spi, + nrf_spi_frequency_t frequency) +{ + p_spi->FREQUENCY = frequency; +} + +__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_spi, + nrf_spi_mode_t spi_mode, + nrf_spi_bit_order_t spi_bit_order) +{ + uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ? + SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst); + switch (spi_mode) + { + default: + case NRF_SPI_MODE_0: + config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos); + break; + + case NRF_SPI_MODE_1: + config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos); + break; + + case NRF_SPI_MODE_2: + config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos); + break; + + case NRF_SPI_MODE_3: + config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos); + break; + } + p_spi->CONFIG = config; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_SPI_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spim.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spim.h new file mode 100644 index 0000000..f76aaad --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spim.h @@ -0,0 +1,520 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @defgroup nrf_spim_hal SPIM HAL + * @{ + * @ingroup nrf_spi_master + * + * @brief Hardware access layer for accessing the SPIM peripheral. + */ + +#ifndef NRF_SPIM_H__ +#define NRF_SPIM_H__ + +#include +#include +#include + +#include "nrf.h" + + +/** + * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set + * function to specify that a given SPI signal (SCK, MOSI, or MISO) + * shall not be connected to a physical pin. + */ +#define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF + + +/** + * @brief SPIM tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction. + NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction. + NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction. + NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME) ///< Resume SPI transaction. + /*lint -restore*/ +} nrf_spim_task_t; + +/** + * @brief SPIM events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped. + NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached. +#ifdef NRF52 + NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END), ///< End of RXD buffer and TXD buffer reached. +#endif + NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached. + NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED) ///< Transaction started. + /*lint -restore*/ +} nrf_spim_event_t; + +#ifdef NRF52 +/** + * @brief SPIM shortcuts. + */ +typedef enum +{ + NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk ///< Shortcut between END event and START task. +} nrf_spim_short_mask_t; +#endif + +/** + * @brief SPIM interrupts. + */ +typedef enum +{ + NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. + NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event. +#ifdef NRF52 + NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event. +#endif + NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event. + NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk ///< Interrupt on STARTED event. +} nrf_spim_int_mask_t; + +/** + * @brief SPI master data rates. + */ +typedef enum +{ + NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps. + NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps. + NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps. + NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps. + NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps. + // [conversion to 'int' needed to prevent compilers from complaining + // that the provided value (0x80000000UL) is out of range of "int"] + NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps. +} nrf_spim_frequency_t; + +/** + * @brief SPI modes. + */ +typedef enum +{ + NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock. + NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock. + NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock. + NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock. +} nrf_spim_mode_t; + +/** + * @brief SPI bit orders. + */ +typedef enum +{ + NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. + NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. +} nrf_spim_bit_order_t; + + +/** + * @brief Function for activating a specific SPIM task. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_task Task to activate. + */ +__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_spim, + nrf_spim_task_t spim_task); + +/** + * @brief Function for getting the address of a specific SPIM task register. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_spim, + nrf_spim_task_t spim_task); + +/** + * @brief Function for clearing a specific SPIM event. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_event Event to clear. + */ +__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_spim, + nrf_spim_event_t spim_event); + +/** + * @brief Function for checking the state of a specific SPIM event. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_spim, + nrf_spim_event_t spim_event); + +/** + * @brief Function for getting the address of a specific SPIM event register. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_spim, + nrf_spim_event_t spim_event); +#ifdef NRF52 +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_spim, + uint32_t spim_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_spim, + uint32_t spim_shorts_mask); + +/** + * @brief Function for getting shorts setting. + * + * @param[in] p_spim SPIM instance. + */ +__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_spim); +#endif +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_spim, + uint32_t spim_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_spim, + uint32_t spim_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_spim SPIM instance. + * @param[in] spim_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_spim, + nrf_spim_int_mask_t spim_int); + +/** + * @brief Function for enabling the SPIM peripheral. + * + * @param[in] p_spim SPIM instance. + */ +__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_spim); + +/** + * @brief Function for disabling the SPIM peripheral. + * + * @param[in] p_spim SPIM instance. + */ +__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_spim); + +/** + * @brief Function for configuring SPIM pins. + * + * If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_spim SPIM instance. + * @param[in] sck_pin SCK pin number. + * @param[in] mosi_pin MOSI pin number. + * @param[in] miso_pin MISO pin number. + */ +__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_spim, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin); + +/** + * @brief Function for setting the SPI master data rate. + * + * @param[in] p_spim SPIM instance. + * @param[in] frequency SPI frequency. + */ +__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_spim, + nrf_spim_frequency_t frequency); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_spim SPIM instance. + * @param[in] p_buffer Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_spim, + uint8_t const * p_buffer, + uint8_t length); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_spim SPIM instance. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_spim, + uint8_t * p_buffer, + uint8_t length); + +/** + * @brief Function for setting the SPI configuration. + * + * @param[in] p_spim SPIM instance. + * @param[in] spi_mode SPI mode. + * @param[in] spi_bit_order SPI bit order. + */ +__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_spim, + nrf_spim_mode_t spi_mode, + nrf_spim_bit_order_t spi_bit_order); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_spim SPIM instance. + * @param[in] orc Over-read character that is clocked out in case of + * an over-read of the TXD buffer. + */ +__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_spim, + uint8_t orc); + +#ifdef NRF52 +/** + * @brief Function for enabling the TX list feature. + * + * @param[in] p_spim SPIM instance. + */ +__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_spim); + +/** + * @brief Function for disabling the TX list feature. + * + * @param[in] p_spim SPIM instance. + */ +__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_spim); + +/** + * @brief Function for enabling the RX list feature. + * + * @param[in] p_spim SPIM instance. + */ +__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_spim); + +/** + * @brief Function for disabling the RX list feature. + * + * @param[in] p_spim SPIM instance. + */ +__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_spim); +#endif +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_spim, + nrf_spim_task_t spim_task) +{ + *((volatile uint32_t *)((uint8_t *)p_spim + (uint32_t)spim_task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_spim, + nrf_spim_task_t spim_task) +{ + return (uint32_t)((uint8_t *)p_spim + (uint32_t)spim_task); +} + +__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_spim, + nrf_spim_event_t spim_event) +{ + *((volatile uint32_t *)((uint8_t *)p_spim + (uint32_t)spim_event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_spim, + nrf_spim_event_t spim_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_spim + (uint32_t)spim_event); +} + +__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_spim, + nrf_spim_event_t spim_event) +{ + return (uint32_t)((uint8_t *)p_spim + (uint32_t)spim_event); +} + +#ifdef NRF52 +__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_spim, + uint32_t spim_shorts_mask) +{ + p_spim->SHORTS |= spim_shorts_mask; +} + +__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_spim, + uint32_t spim_shorts_mask) +{ + p_spim->SHORTS &= ~(spim_shorts_mask); +} + +__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_spim) +{ + return p_spim->SHORTS; +} +#endif +__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_spim, + uint32_t spim_int_mask) +{ + p_spim->INTENSET = spim_int_mask; +} + +__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_spim, + uint32_t spim_int_mask) +{ + p_spim->INTENCLR = spim_int_mask; +} + +__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_spim, + nrf_spim_int_mask_t spim_int) +{ + return (bool)(p_spim->INTENSET & spim_int); +} + +__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_spim) +{ + p_spim->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_spim) +{ + p_spim->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_spim, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin) +{ + p_spim->PSEL.SCK = sck_pin; + p_spim->PSEL.MOSI = mosi_pin; + p_spim->PSEL.MISO = miso_pin; +} + +__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_spim, + nrf_spim_frequency_t frequency) +{ + p_spim->FREQUENCY = frequency; +} + +__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_spim, + uint8_t const * p_buffer, + uint8_t length) +{ + p_spim->TXD.PTR = (uint32_t)p_buffer; + p_spim->TXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_spim, + uint8_t * p_buffer, + uint8_t length) +{ + p_spim->RXD.PTR = (uint32_t)p_buffer; + p_spim->RXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_spim, + nrf_spim_mode_t spi_mode, + nrf_spim_bit_order_t spi_bit_order) +{ + uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ? + SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst); + switch (spi_mode) + { + default: + case NRF_SPIM_MODE_0: + config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); + break; + + case NRF_SPIM_MODE_1: + config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); + break; + + case NRF_SPIM_MODE_2: + config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); + break; + + case NRF_SPIM_MODE_3: + config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); + break; + } + p_spim->CONFIG = config; +} + +__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_spim, + uint8_t orc) +{ + p_spim->ORC = orc; +} + +#ifdef NRF52 +__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_spim) +{ + p_spim->TXD.LIST = 1; +} + +__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_spim) +{ + p_spim->TXD.LIST = 0; +} + +__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_spim) +{ + p_spim->RXD.LIST = 1; +} + +__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_spim) +{ + p_spim->RXD.LIST = 0; +} +#endif +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_SPIM_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spis.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spis.h new file mode 100644 index 0000000..1f250b5 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_spis.h @@ -0,0 +1,512 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @defgroup nrf_spis_hal SPIS HAL + * @{ + * @ingroup nrf_spis + * + * @brief Hardware access layer for accessing the SPIS peripheral. + */ + +#ifndef NRF_SPIS_H__ +#define NRF_SPIS_H__ + +#include +#include +#include + +#include "nrf.h" + + +/** + * @brief This value can be used as a parameter for the @ref nrf_spis_pins_set + * function to specify that a given SPI signal (SCK, MOSI, or MISO) + * shall not be connected to a physical pin. + */ +#define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF + + +/** + * @brief SPIS tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore. + NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it. + /*lint -restore*/ +} nrf_spis_task_t; + +/** + * @brief SPIS events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed. + NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired. + /*lint -restore*/ +} nrf_spis_event_t; + +/** + * @brief SPIS shortcuts. + */ +typedef enum +{ + NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task. +} nrf_spis_short_mask_t; + +/** + * @brief SPIS interrupts. + */ +typedef enum +{ + NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event. + NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event. +} nrf_spis_int_mask_t; + +/** + * @brief SPI modes. + */ +typedef enum +{ + NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock. + NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock. + NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock. + NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock. +} nrf_spis_mode_t; + +/** + * @brief SPI bit orders. + */ +typedef enum +{ + NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. + NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. +} nrf_spis_bit_order_t; + +/** + * @brief SPI semaphore status. + */ +typedef enum +{ + NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free. + NRF_SPIS_SEMSTAT_CPU = 1, ///< Semaphore is assigned to the CPU. + NRF_SPIS_SEMSTAT_SPIS = 2, ///< Semaphore is assigned to the SPI slave. + NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending. +} nrf_spis_semstat_t; + +/** + * @brief SPIS status. + */ +typedef enum +{ + NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented. + NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented. +} nrf_spis_status_mask_t; + +/** + * @brief Function for activating a specific SPIS task. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_task Task to activate. + */ +__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_spis, + nrf_spis_task_t spis_task); + +/** + * @brief Function for getting the address of a specific SPIS task register. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_spis, + nrf_spis_task_t spis_task); + +/** + * @brief Function for clearing a specific SPIS event. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_event Event to clear. + */ +__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_spis, + nrf_spis_event_t spis_event); + +/** + * @brief Function for checking the state of a specific SPIS event. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_spis, + nrf_spis_event_t spis_event); + +/** + * @brief Function for getting the address of a specific SPIS event register. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_spis, + nrf_spis_event_t spis_event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_spis, + uint32_t spis_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_spis, + uint32_t spis_shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_spis, + uint32_t spis_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_spis, + uint32_t spis_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_spis SPIS instance. + * @param[in] spis_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_spis, + nrf_spis_int_mask_t spis_int); + +/** + * @brief Function for enabling the SPIS peripheral. + * + * @param[in] p_spis SPIS instance. + */ +__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_spis); + +/** + * @brief Function for disabling the SPIS peripheral. + * + * @param[in] p_spis SPIS instance. + */ +__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_spis); + +/** + * @brief Function for retrieving the SPIS semaphore status. + * + * @param[in] p_spis SPIS instance. + * + * @returns Current semaphore status. + */ +__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_spis); + +/** + * @brief Function for retrieving the SPIS status. + * + * @param[in] p_spis SPIS instance. + * + * @returns Current SPIS status. + */ +__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_spis); + +/** + * @brief Function for configuring SPIS pins. + * + * If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_spis SPIS instance. + * @param[in] sck_pin SCK pin number. + * @param[in] mosi_pin MOSI pin number. + * @param[in] miso_pin MISO pin number. + * @param[in] csn_pin CSN pin number. + */ +__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_spis, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin, + uint32_t csn_pin); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_spis SPIS instance. + * @param[in] p_buffer Pointer to the buffer that contains the data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_spis, + uint8_t const * p_buffer, + uint8_t length); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_spis SPIS instance. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_spis, + uint8_t * p_buffer, + uint8_t length); + +/** + * @brief Function for getting the number of bytes transmitted + * in the last granted transaction. + * + * @param[in] p_spis SPIS instance. + * + * @returns Number of bytes transmitted. + */ +__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_spis); + +/** + * @brief Function for getting the number of bytes received + * in the last granted transaction. + * + * @param[in] p_spis SPIS instance. + * + * @returns Number of bytes received. + */ +__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_spis); + +/** + * @brief Function for setting the SPI configuration. + * + * @param[in] p_spis SPIS instance. + * @param[in] spi_mode SPI mode. + * @param[in] spi_bit_order SPI bit order. + */ +__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_spis, + nrf_spis_mode_t spi_mode, + nrf_spis_bit_order_t spi_bit_order); + +/** + * @brief Function for setting the default character. + * + * @param[in] p_spis SPIS instance. + * @param[in] def Default character that is clocked out in case of + * an overflow of the RXD buffer. + */ +__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_spis, + uint8_t def); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_spis SPIS instance. + * @param[in] orc Over-read character that is clocked out in case of + * an over-read of the TXD buffer. + */ +__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_spis, + uint8_t orc); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_spis, + nrf_spis_task_t spis_task) +{ + *((volatile uint32_t *)((uint8_t *)p_spis + (uint32_t)spis_task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_spis, + nrf_spis_task_t spis_task) +{ + return (uint32_t)p_spis + (uint32_t)spis_task; +} + +__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_spis, + nrf_spis_event_t spis_event) +{ + *((volatile uint32_t *)((uint8_t *)p_spis + (uint32_t)spis_event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_spis, + nrf_spis_event_t spis_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_spis + (uint32_t)spis_event); +} + +__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_spis, + nrf_spis_event_t spis_event) +{ + return (uint32_t)p_spis + (uint32_t)spis_event; +} + +__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_spis, + uint32_t spis_shorts_mask) +{ + p_spis->SHORTS |= spis_shorts_mask; +} + +__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_spis, + uint32_t spis_shorts_mask) +{ + p_spis->SHORTS &= ~(spis_shorts_mask); +} + +__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_spis, + uint32_t spis_int_mask) +{ + p_spis->INTENSET = spis_int_mask; +} + +__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_spis, + uint32_t spis_int_mask) +{ + p_spis->INTENCLR = spis_int_mask; +} + +__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_spis, + nrf_spis_int_mask_t spis_int) +{ + return (bool)(p_spis->INTENSET & spis_int); +} + +__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_spis) +{ + p_spis->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_spis) +{ + p_spis->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_spis) +{ + return (nrf_spis_semstat_t) ((p_spis->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk) + >> SPIS_SEMSTAT_SEMSTAT_Pos); +} + +__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_spis) +{ + return (nrf_spis_status_mask_t) p_spis->STATUS; +} + +__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_spis, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin, + uint32_t csn_pin) +{ + p_spis->PSELSCK = sck_pin; + p_spis->PSELMOSI = mosi_pin; + p_spis->PSELMISO = miso_pin; + p_spis->PSELCSN = csn_pin; +} + +__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_spis, + uint8_t const * p_buffer, + uint8_t length) +{ + p_spis->TXDPTR = (uint32_t)p_buffer; + p_spis->MAXTX = length; +} + +__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_spis, + uint8_t * p_buffer, + uint8_t length) +{ + p_spis->RXDPTR = (uint32_t)p_buffer; + p_spis->MAXRX = length; +} + +__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_spis) +{ + return (uint8_t) p_spis->AMOUNTRX; +} + +__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_spis) +{ + return (uint8_t) p_spis->AMOUNTTX; +} + +__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_spis, + nrf_spis_mode_t spi_mode, + nrf_spis_bit_order_t spi_bit_order) +{ + uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ? + SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst); + + switch (spi_mode) + { + default: + case NRF_SPIS_MODE_0: + config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); + break; + + case NRF_SPIS_MODE_1: + config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); + break; + + case NRF_SPIS_MODE_2: + config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); + break; + + case NRF_SPIS_MODE_3: + config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); + break; + } + p_spis->CONFIG = config; +} + +__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_spis, + uint8_t orc) +{ + p_spis->ORC = orc; +} + +__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_spis, + uint8_t def) +{ + p_spis->DEF = def; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_SPIS_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_temp.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_temp.h new file mode 100644 index 0000000..d108072 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_temp.h @@ -0,0 +1,55 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_TEMP_H__ +#define NRF_TEMP_H__ + +#include "nrf.h" + +/** +* @defgroup nrf_temperature TEMP (temperature) abstraction +* @{ +* @ingroup nrf_drivers temperature_example +* @brief Temperature module init and read functions. +* +*/ + +/**@cond NO_DOXYGEN */ +#define MASK_SIGN (0x00000200UL) +#define MASK_SIGN_EXTENSION (0xFFFFFC00UL) + +/** + * @brief Function for preparing the temp module for temperature measurement. + * + * This function initializes the TEMP module and writes to the hidden configuration register. + */ +static __INLINE void nrf_temp_init(void) +{ + /**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */ + *(uint32_t *) 0x4000C504 = 0; +} + +/** + * @brief Function for reading temperature measurement. + * + * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value. + */ +static __INLINE int32_t nrf_temp_read(void) +{ + /**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */ + return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP); +} +/**@endcond */ + +/** @} */ + +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_timer.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_timer.h new file mode 100644 index 0000000..2568d5f --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_timer.h @@ -0,0 +1,576 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @defgroup nrf_timer_hal Timer HAL + * @{ + * @ingroup nrf_timer + * + * @brief Hardware access layer for accessing the timer peripheral. + */ + +#ifndef NRF_TIMER_H__ +#define NRF_TIMER_H__ + +#include +#include +#include + +#include "nrf.h" +#include "nrf_assert.h" + + +/** + * @brief Macro for validating the correctness of the BIT_WIDTH setting. + */ +#ifdef NRF51 + /** + * In the nRF51 Series, timer instance 0 supports all available bit widths. + * The other two instances support only 8 and 16 bits. + */ + #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_timer, bit_width) \ + ((p_timer == NRF_TIMER0) || (bit_width <= NRF_TIMER_BIT_WIDTH_16)) +#else + /** + * In the nRF52 Series, all timer instances support all available bit widths. + */ + #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_timer, bit_width) true +#endif + +/** + * @brief Macro for getting the number of capture/compare channels available + * in a given timer instance. + */ +#ifdef NRF51 + #define NRF_TIMER_CC_CHANNEL_COUNT(id) 4 +#else + #define NRF_TIMER_CC_CHANNEL_COUNT(id) ((id) <= 2 ? 4 : 6) +#endif + + +/** + * @brief Timer tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_TIMER_TASK_START = offsetof(NRF_TIMER_Type, TASKS_START), ///< Task for starting the timer. + NRF_TIMER_TASK_STOP = offsetof(NRF_TIMER_Type, TASKS_STOP), ///< Task for stopping the timer. + NRF_TIMER_TASK_COUNT = offsetof(NRF_TIMER_Type, TASKS_COUNT), ///< Task for incrementing the timer (in counter mode). + NRF_TIMER_TASK_CLEAR = offsetof(NRF_TIMER_Type, TASKS_CLEAR), ///< Task for resetting the timer value. + NRF_TIMER_TASK_SHUTDOWN = offsetof(NRF_TIMER_Type, TASKS_SHUTDOWN), ///< Task for powering off the timer. + NRF_TIMER_TASK_CAPTURE0 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[0]), ///< Task for capturing the timer value on channel 0. + NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1. + NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2. + NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3. +#ifdef NRF52 + NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4. + NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5. +#endif + /*lint -restore*/ +} nrf_timer_task_t; + +/** + * @brief Timer events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TIMER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0. + NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1. + NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2. + NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3. +#ifdef NRF52 + NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4. + NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5. +#endif + /*lint -restore*/ +} nrf_timer_event_t; + +/** + * @brief Types of timer shortcuts. + */ +typedef enum +{ + NRF_TIMER_SHORT_COMPARE0_STOP_MASK = TIMER_SHORTS_COMPARE0_STOP_Msk, ///< Shortcut for stopping the timer based on compare 0. + NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk, ///< Shortcut for stopping the timer based on compare 1. + NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk, ///< Shortcut for stopping the timer based on compare 2. + NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk, ///< Shortcut for stopping the timer based on compare 3. +#ifdef NRF52 + NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk, ///< Shortcut for stopping the timer based on compare 4. + NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk, ///< Shortcut for stopping the timer based on compare 5. +#endif + NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0. + NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1. + NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2. + NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3. +#ifdef NRF52 + NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4. + NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5. +#endif +} nrf_timer_short_mask_t; + +/** + * @brief Timer modes. + */ +typedef enum +{ + NRF_TIMER_MODE_TIMER = TIMER_MODE_MODE_Timer, ///< Timer mode: timer. + NRF_TIMER_MODE_COUNTER = TIMER_MODE_MODE_Counter, ///< Timer mode: counter. +#ifdef NRF52 + NRF_TIMER_MODE_LOW_POWER_COUNTER = TIMER_MODE_MODE_LowPowerCounter, ///< Timer mode: low-power counter. +#endif +} nrf_timer_mode_t; + +/** + * @brief Timer bit width. + */ +typedef enum +{ + NRF_TIMER_BIT_WIDTH_8 = TIMER_BITMODE_BITMODE_08Bit, ///< Timer bit width 8 bit. + NRF_TIMER_BIT_WIDTH_16 = TIMER_BITMODE_BITMODE_16Bit, ///< Timer bit width 16 bit. + NRF_TIMER_BIT_WIDTH_24 = TIMER_BITMODE_BITMODE_24Bit, ///< Timer bit width 24 bit. + NRF_TIMER_BIT_WIDTH_32 = TIMER_BITMODE_BITMODE_32Bit ///< Timer bit width 32 bit. +} nrf_timer_bit_width_t; + +/** + * @brief Timer prescalers. + */ +typedef enum +{ + NRF_TIMER_FREQ_16MHz = 0, ///< Timer frequency 16 MHz. + NRF_TIMER_FREQ_8MHz, ///< Timer frequency 8 MHz. + NRF_TIMER_FREQ_4MHz, ///< Timer frequency 4 MHz. + NRF_TIMER_FREQ_2MHz, ///< Timer frequency 2 MHz. + NRF_TIMER_FREQ_1MHz, ///< Timer frequency 1 MHz. + NRF_TIMER_FREQ_500kHz, ///< Timer frequency 500 kHz. + NRF_TIMER_FREQ_250kHz, ///< Timer frequency 250 kHz. + NRF_TIMER_FREQ_125kHz, ///< Timer frequency 125 kHz. + NRF_TIMER_FREQ_62500Hz, ///< Timer frequency 62500 Hz. + NRF_TIMER_FREQ_31250Hz ///< Timer frequency 31250 Hz. +} nrf_timer_frequency_t; + +/** + * @brief Timer capture/compare channels. + */ +typedef enum +{ + NRF_TIMER_CC_CHANNEL0 = 0, ///< Timer capture/compare channel 0. + NRF_TIMER_CC_CHANNEL1, ///< Timer capture/compare channel 1. + NRF_TIMER_CC_CHANNEL2, ///< Timer capture/compare channel 2. + NRF_TIMER_CC_CHANNEL3, ///< Timer capture/compare channel 3. +#ifdef NRF52 + NRF_TIMER_CC_CHANNEL4, ///< Timer capture/compare channel 4. + NRF_TIMER_CC_CHANNEL5, ///< Timer capture/compare channel 5. +#endif +} nrf_timer_cc_channel_t; + +/** + * @brief Timer interrupts. + */ +typedef enum +{ + NRF_TIMER_INT_COMPARE0_MASK = TIMER_INTENSET_COMPARE0_Msk, ///< Timer interrupt from compare event on channel 0. + NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1. + NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2. + NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3. +#ifdef NRF52 + NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4. + NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5. +#endif +} nrf_timer_int_mask_t; + + +/** + * @brief Function for activating a specific timer task. + * + * @param[in] p_timer Timer instance. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_timer, + nrf_timer_task_t task); + +/** + * @brief Function for getting the address of a specific timer task register. + * + * @param[in] p_timer Timer instance. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_timer, + nrf_timer_task_t task); + +/** + * @brief Function for clearing a specific timer event. + * + * @param[in] p_timer Timer instance. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_timer, + nrf_timer_event_t event); + +/** + * @brief Function for checking the state of a specific timer event. + * + * @param[in] p_timer Timer instance. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_timer, + nrf_timer_event_t event); + +/** + * @brief Function for getting the address of a specific timer event register. + * + * @param[in] p_timer Timer instance. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_timer, + nrf_timer_event_t event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_timer Timer instance. + * @param[in] timer_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_timer, + uint32_t timer_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_timer Timer instance. + * @param[in] timer_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_timer, + uint32_t timer_shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_timer Timer instance. + * @param[in] timer_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_timer, + uint32_t timer_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_timer Timer instance. + * @param[in] timer_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_timer, + uint32_t timer_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_timer Timer instance. + * @param[in] timer_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_timer, + uint32_t timer_int); + +/** + * @brief Function for setting the timer mode. + * + * @param[in] p_timer Timer instance. + * @param[in] mode Timer mode. + */ +__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_timer, + nrf_timer_mode_t mode); + +/** + * @brief Function for retrieving the timer mode. + * + * @param[in] p_timer Timer instance. + * + * @return Timer mode. + */ +__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_timer); + +/** + * @brief Function for setting the timer bit width. + * + * @param[in] p_timer Timer instance. + * @param[in] bit_width Timer bit width. + */ +__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_timer, + nrf_timer_bit_width_t bit_width); + +/** + * @brief Function for retrieving the timer bit width. + * + * @param[in] p_timer Timer instance. + * + * @return Timer bit width. + */ +__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_timer); + +/** + * @brief Function for setting the timer frequency. + * + * @param[in] p_timer Timer instance. + * @param[in] frequency Timer frequency. + */ +__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_timer, + nrf_timer_frequency_t frequency); + +/** + * @brief Function for retrieving the timer frequency. + * + * @param[in] p_timer Timer instance. + * + * @return Timer frequency. + */ +__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_timer); + +/** + * @brief Function for writing the capture/compare register for a specified channel. + * + * @param[in] p_timer Timer instance. + * @param[in] cc_channel Requested capture/compare channel. + * @param[in] cc_value Value to write to the capture/compare register. + */ +__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_timer, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value); + +/** + * @brief Function for retrieving the capture/compare value for a specified channel. + * + * @param[in] p_timer Timer instance. + * @param[in] cc_channel Requested capture/compare channel. + * + * @return Value from the requested capture/compare register. + */ +__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_timer, + nrf_timer_cc_channel_t cc_channel); + +/** + * @brief Function for getting a specific timer capture task. + * + * @param[in] channel Capture channel. + * + * @return Capture task. + */ +__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel); + +/** + * @brief Function for getting a specific timer compare event. + * + * @param[in] channel Compare channel. + * + * @return Compare event. + */ +__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel); + +/** + * @brief Function for getting a specific timer compare interrupt. + * + * @param[in] channel Compare channel. + * + * @return Compare interrupt. + */ +__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel); + +/** + * @brief Function for calculating the number of timer ticks for a given time + * (in microseconds) and timer frequency. + * + * @param[in] time_us Time in microseconds. + * @param[in] frequency Timer frequency. + * + * @return Number of timer ticks. + */ +__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us, + nrf_timer_frequency_t frequency); + +/** + * @brief Function for calculating the number of timer ticks for a given time + * (in milliseconds) and timer frequency. + * + * @param[in] time_ms Time in milliseconds. + * @param[in] frequency Timer frequency. + * + * @return Number of timer ticks. + */ +__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms, + nrf_timer_frequency_t frequency); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_timer, + nrf_timer_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_timer + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_timer, + nrf_timer_task_t task) +{ + return (uint32_t *)((uint8_t *)p_timer + (uint32_t)task); +} + +__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_timer, + nrf_timer_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_timer + (uint32_t)event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_timer, + nrf_timer_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_timer + (uint32_t)event); +} + +__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_timer, + nrf_timer_event_t event) +{ + return (uint32_t *)((uint8_t *)p_timer + (uint32_t)event); +} + +__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_timer, + uint32_t timer_shorts_mask) +{ + p_timer->SHORTS |= timer_shorts_mask; +} + +__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_timer, + uint32_t timer_shorts_mask) +{ + p_timer->SHORTS &= ~(timer_shorts_mask); +} + +__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_timer, + uint32_t timer_int_mask) +{ + p_timer->INTENSET = timer_int_mask; +} + +__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_timer, + uint32_t timer_int_mask) +{ + p_timer->INTENCLR = timer_int_mask; +} + +__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_timer, + uint32_t timer_int) +{ + return (bool)(p_timer->INTENSET & timer_int); +} + +__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_timer, + nrf_timer_mode_t mode) +{ + p_timer->MODE = (p_timer->MODE & ~TIMER_MODE_MODE_Msk) | + ((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk); +} + +__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_timer) +{ + return (nrf_timer_mode_t)(p_timer->MODE); +} + +__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_timer, + nrf_timer_bit_width_t bit_width) +{ + p_timer->BITMODE = (p_timer->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) | + ((bit_width << TIMER_BITMODE_BITMODE_Pos) & + TIMER_BITMODE_BITMODE_Msk); +} + +__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_timer) +{ + return (nrf_timer_bit_width_t)(p_timer->BITMODE); +} + +__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_timer, + nrf_timer_frequency_t frequency) +{ + p_timer->PRESCALER = (p_timer->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) | + ((frequency << TIMER_PRESCALER_PRESCALER_Pos) & + TIMER_PRESCALER_PRESCALER_Msk); +} + +__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_timer) +{ + return (nrf_timer_frequency_t)(p_timer->PRESCALER); +} + +__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_timer, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value) +{ + p_timer->CC[cc_channel] = cc_value; +} + +__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_timer, + nrf_timer_cc_channel_t cc_channel) +{ + return (uint32_t)p_timer->CC[cc_channel]; +} + +__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel) +{ + return (nrf_timer_task_t) + ((uint32_t)NRF_TIMER_TASK_CAPTURE0 + (channel * sizeof(uint32_t))); +} + +__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel) +{ + return (nrf_timer_event_t) + ((uint32_t)NRF_TIMER_EVENT_COMPARE0 + (channel * sizeof(uint32_t))); +} + +__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel) +{ + return (nrf_timer_int_mask_t) + ((uint32_t)NRF_TIMER_INT_COMPARE0_MASK << channel); +} + +__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us, + nrf_timer_frequency_t frequency) +{ + // The "frequency" parameter here is actually the prescaler value, and the + // timer runs at the following frequency: f = 16 MHz / 2^prescaler. + uint32_t prescaler = (uint32_t)frequency; + ASSERT(time_us <= (UINT32_MAX / 16UL)); + return ((time_us * 16UL) >> prescaler); +} + +__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms, + nrf_timer_frequency_t frequency) +{ + // The "frequency" parameter here is actually the prescaler value, and the + // timer runs at the following frequency: f = 16000 kHz / 2^prescaler. + uint32_t prescaler = (uint32_t)frequency; + ASSERT(time_ms <= (UINT32_MAX / 16000UL)); + return ((time_ms * 16000UL) >> prescaler); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_TIMER_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twi.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twi.h new file mode 100644 index 0000000..4f38df2 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twi.h @@ -0,0 +1,402 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_TWI_H__ +#define NRF_TWI_H__ + +/** + * @defgroup nrf_twi_hal TWI HAL + * @{ + * @ingroup nrf_twi_master + * + * @brief Hardware access layer for managing the TWI peripheral. + */ + +#include +#include +#include + +#include "nrf.h" + +/** + * @brief TWI tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWI_TASK_STARTRX = offsetof(NRF_TWI_Type, TASKS_STARTRX), ///< Start TWI receive sequence. + NRF_TWI_TASK_STARTTX = offsetof(NRF_TWI_Type, TASKS_STARTTX), ///< Start TWI transmit sequence. + NRF_TWI_TASK_STOP = offsetof(NRF_TWI_Type, TASKS_STOP), ///< Stop TWI transaction. + NRF_TWI_TASK_SUSPEND = offsetof(NRF_TWI_Type, TASKS_SUSPEND), ///< Suspend TWI transaction. + NRF_TWI_TASK_RESUME = offsetof(NRF_TWI_Type, TASKS_RESUME) ///< Resume TWI transaction. + /*lint -restore*/ +} nrf_twi_task_t; + +/** + * @brief TWI events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWI_EVENT_STOPPED = offsetof(NRF_TWI_Type, EVENTS_STOPPED), ///< TWI stopped. + NRF_TWI_EVENT_RXDREADY = offsetof(NRF_TWI_Type, EVENTS_RXDREADY), ///< TWI RXD byte received. + NRF_TWI_EVENT_TXDSENT = offsetof(NRF_TWI_Type, EVENTS_TXDSENT), ///< TWI TXD byte sent. + NRF_TWI_EVENT_ERROR = offsetof(NRF_TWI_Type, EVENTS_ERROR), ///< TWI error. + NRF_TWI_EVENT_BB = offsetof(NRF_TWI_Type, EVENTS_BB), ///< TWI byte boundary, generated before each byte that is sent or received. + NRF_TWI_EVENT_SUSPENDED = offsetof(NRF_TWI_Type, EVENTS_SUSPENDED) ///< TWI entered the suspended state. + /*lint -restore*/ +} nrf_twi_event_t; + +/** + * @brief TWI shortcuts. + */ +typedef enum +{ + NRF_TWI_SHORT_BB_SUSPEND_MASK = TWI_SHORTS_BB_SUSPEND_Msk, ///< Shortcut between BB event and SUSPEND task. + NRF_TWI_SHORT_BB_STOP_MASK = TWI_SHORTS_BB_STOP_Msk, ///< Shortcut between BB event and STOP task. +} nrf_twi_short_mask_t; + +/** + * @brief TWI interrupts. + */ +typedef enum +{ + NRF_TWI_INT_STOPPED_MASK = TWI_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. + NRF_TWI_INT_RXDREADY_MASK = TWI_INTENSET_RXDREADY_Msk, ///< Interrupt on RXDREADY event. + NRF_TWI_INT_TXDSENT_MASK = TWI_INTENSET_TXDSENT_Msk, ///< Interrupt on TXDSENT event. + NRF_TWI_INT_ERROR_MASK = TWI_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. + NRF_TWI_INT_BB_MASK = TWI_INTENSET_BB_Msk, ///< Interrupt on BB event. + NRF_TWI_INT_SUSPENDED_MASK = TWI_INTENSET_SUSPENDED_Msk ///< Interrupt on SUSPENDED event. +} nrf_twi_int_mask_t; + +/** + * @brief TWI error source. + */ +typedef enum +{ + NRF_TWI_ERROR_ADDRESS_NACK = TWI_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address. + NRF_TWI_ERROR_DATA_NACK = TWI_ERRORSRC_DNACK_Msk, ///< NACK received after sending a data byte. + NRF_TWI_ERROR_OVERRUN = TWI_ERRORSRC_OVERRUN_Msk ///< Overrun error. + /**< A new byte was received before the previous byte was read + * from the RXD register (previous data is lost). */ +} nrf_twi_error_t; + +/** + * @brief TWI master clock frequency. + */ +typedef enum +{ + NRF_TWI_FREQ_100K = TWI_FREQUENCY_FREQUENCY_K100, ///< 100 kbps. + NRF_TWI_FREQ_250K = TWI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_TWI_FREQ_400K = TWI_FREQUENCY_FREQUENCY_K400 ///< 400 kbps. +} nrf_twi_frequency_t; + + +/** + * @brief Function for activating a specific TWI task. + * + * @param[in] p_twi TWI instance. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_twi, + nrf_twi_task_t task); + +/** + * @brief Function for getting the address of a specific TWI task register. + * + * @param[in] p_twi TWI instance. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_twi, + nrf_twi_task_t task); + +/** + * @brief Function for clearing a specific TWI event. + * + * @param[in] p_twi TWI instance. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_twi, + nrf_twi_event_t event); + +/** + * @brief Function for checking the state of a specific event. + * + * @param[in] p_twi TWI instance. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_twi, + nrf_twi_event_t event); + +/** + * @brief Function for getting the address of a specific TWI event register. + * + * @param[in] p_twi TWI instance. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_twi, + nrf_twi_event_t event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_twi TWI instance. + * @param[in] shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_twi, + uint32_t shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_twi TWI instance. + * @param[in] shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_twi, + uint32_t shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_twi TWI instance. + * @param[in] int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_twi, + uint32_t int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_twi TWI instance. + * @param[in] int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_twi, + uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_twi TWI instance. + * @param[in] int_mask Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_twi, + nrf_twi_int_mask_t int_mask); + +/** + * @brief Function for enabling the TWI peripheral. + * + * @param[in] p_twi TWI instance. + */ +__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_twi); + +/** + * @brief Function for disabling the TWI peripheral. + * + * @param[in] p_twi TWI instance. + */ +__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_twi); + +/** + * @brief Function for configuring TWI pins. + * + * + * @param[in] p_twi TWI instance. + * @param[in] scl_pin SCL pin number. + * @param[in] sda_pin SDA pin number. + */ +__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_twi, + uint32_t scl_pin, + uint32_t sda_pin); + +/** + * @brief Function for setting the TWI master clock frequency. + * + * @param[in] p_twi TWI instance. + * @param[in] frequency TWI frequency. + */ +__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_twi, + nrf_twi_frequency_t frequency); + +/** + * @brief Function for checking the TWI error source. + * + * The error flags are cleared after reading. + * + * @param[in] p_twi TWI instance. + * + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_twi); + +/** + * @brief Function for setting the address to be used in TWI transfers. + * + * @param[in] p_twi TWI instance. + * @param[in] address Address to be used in transfers. + */ +__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_twi, uint8_t address); + +/** + * @brief Function for reading data received by TWI. + * + * @param[in] p_twi TWI instance. + * + * @return Received data. + */ +__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_twi); + +/** + * @brief Function for writing data to be transmitted by TWI. + * + * @param[in] p_twi TWI instance. + * @param[in] data Data to be transmitted. + */ +__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_twi, uint8_t data); + +__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_twi, + uint32_t shorts_mask); + +/** + * @} + */ + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_twi, + nrf_twi_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_twi + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_twi, + nrf_twi_task_t task) +{ + return (uint32_t *)((uint8_t *)p_twi + (uint32_t)task); +} + +__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_twi, + nrf_twi_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_twi + (uint32_t)event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_twi, + nrf_twi_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_twi + (uint32_t)event); +} + +__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_twi, + nrf_twi_event_t event) +{ + return (uint32_t *)((uint8_t *)p_twi + (uint32_t)event); +} + +__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_twi, + uint32_t shorts_mask) +{ + p_twi->SHORTS |= shorts_mask; +} + +__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_twi, + uint32_t shorts_mask) +{ + p_twi->SHORTS &= ~(shorts_mask); +} + +__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_twi, + uint32_t int_mask) +{ + p_twi->INTENSET = int_mask; +} + +__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_twi, + uint32_t int_mask) +{ + p_twi->INTENCLR = int_mask; +} + +__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_twi, + nrf_twi_int_mask_t int_mask) +{ + return (bool)(p_twi->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_twi) +{ + p_twi->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_twi) +{ + p_twi->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_twi, + uint32_t scl_pin, + uint32_t sda_pin) +{ + p_twi->PSELSCL = scl_pin; + p_twi->PSELSDA = sda_pin; +} + +__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_twi, + nrf_twi_frequency_t frequency) +{ + p_twi->FREQUENCY = frequency; +} + +__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_twi) +{ + uint32_t error_source = p_twi->ERRORSRC; + + // [error flags are cleared by writing '1' on their position] + p_twi->ERRORSRC = error_source; + + return error_source; +} + +__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_twi, uint8_t address) +{ + p_twi->ADDRESS = address; +} + +__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_twi) +{ + return (uint8_t)p_twi->RXD; +} + +__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_twi, uint8_t data) +{ + p_twi->TXD = data; +} + +__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_twi, + uint32_t shorts_mask) +{ + p_twi->SHORTS = shorts_mask; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_TWI_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twim.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twim.h new file mode 100644 index 0000000..f54d6c6 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twim.h @@ -0,0 +1,478 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_TWIM_H__ +#define NRF_TWIM_H__ + +/** + * @defgroup nrf_twim_hal TWIM HAL + * @{ + * @ingroup nrf_twi_master + * + * @brief Hardware access layer for managing the TWIM peripheral. + */ + +#include +#include +#include + +#include "nrf.h" + +/** + * @brief TWIM tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence. + NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence. + NRF_TWIM_TASK_STOP = offsetof(NRF_TWIM_Type, TASKS_STOP), ///< Stop TWI transaction. + NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction. + NRF_TWIM_TASK_RESUME = offsetof(NRF_TWIM_Type, TASKS_RESUME) ///< Resume TWI transaction. + /*lint -restore*/ +} nrf_twim_task_t; + +/** + * @brief TWIM events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped. + NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error. + NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended. + NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started. + NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started. + NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte. + NRF_TWIM_EVENT_LASTTX = offsetof(NRF_TWIM_Type, EVENTS_LASTTX) ///< Byte boundary, starting to transmit the last byte. + /*lint -restore*/ +} nrf_twim_event_t; + +/** + * @brief TWIM shortcuts. + */ +typedef enum +{ + NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task. + NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK = TWIM_SHORTS_LASTTX_SUSPEND_Msk, ///< Shortcut between LASTTX event and SUSPEND task. + NRF_TWIM_SHORT_LASTTX_STOP_MASK = TWIM_SHORTS_LASTTX_STOP_Msk, ///< Shortcut between LASTTX event and STOP task. + NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_STARTTX_Msk, ///< Shortcut between LASTRX event and STARTTX task. + NRF_TWIM_SHORT_LASTRX_STOP_MASK = TWIM_SHORTS_LASTRX_STOP_Msk ///< Shortcut between LASTRX event and STOP task. +} nrf_twim_short_mask_t; + +/** + * @brief TWIM interrupts. + */ +typedef enum +{ + NRF_TWIM_INT_STOPPED_MASK = TWIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. + NRF_TWIM_INT_ERROR_MASK = TWIM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. + NRF_TWIM_INT_SUSPENDED_MASK = (1 << 18), ///< Interrupt on SUSPENDED event. + NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event. + NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event. + NRF_TWIM_INT_LASTRX_MASK = TWIM_INTENSET_LASTRX_Msk, ///< Interrupt on LASTRX event. + NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk ///< Interrupt on LASTTX event. +} nrf_twim_int_mask_t; + +/** + * @brief TWIM master clock frequency. + */ +typedef enum +{ + NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps. + NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400 ///< 400 kbps. +} nrf_twim_frequency_t; + +/** + * @brief TWIM error source. + */ +typedef enum +{ + NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address. + NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk ///< NACK received after sending a data byte. +} nrf_twim_error_t; + + +/** + * @brief Function for activating a specific TWIM task. + * + * @param[in] p_twim TWIM instance. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_twim, + nrf_twim_task_t task); + +/** + * @brief Function for getting the address of a specific TWIM task register. + * + * @param[in] p_twim TWIM instance. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_twim, + nrf_twim_task_t task); + +/** + * @brief Function for clearing a specific TWIM event. + * + * @param[in] p_twim TWIM instance. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_twim, + nrf_twim_event_t event); + +/** + * @brief Function for checking the state of a specific TWIM event. + * + * @param[in] p_twim TWIM instance. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_twim, + nrf_twim_event_t event); + +/** + * @brief Function for getting the address of a specific TWIM event register. + * + * @param[in] p_twim TWIM instance. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_twim, + nrf_twim_event_t event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_twim TWIM instance. + * @param[in] shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_twim, + uint32_t shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_twim TWIM instance. + * @param[in] shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_twim, + uint32_t shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_twim TWIM instance. + * @param[in] int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_twim, + uint32_t int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_twim TWIM instance. + * @param[in] int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_twim, + uint32_t int_mask); + +/** + * @brief Function for checking the state of a given interrupt. + * + * @param[in] p_twim TWIM instance. + * @param[in] int_mask Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_twim, + nrf_twim_int_mask_t int_mask); + +/** + * @brief Function for enabling the TWIM peripheral. + * + * @param[in] p_twim TWIM instance. + */ +__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_twim); + +/** + * @brief Function for disabling the TWIM peripheral. + * + * @param[in] p_twim TWIM instance. + */ +__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_twim); + +/** + * @brief Function for configuring TWI pins. + * + * + * @param[in] p_twim TWIM instance. + * @param[in] scl_pin SCL pin number. + * @param[in] sda_pin SDA pin number. + */ +__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_twim, + uint32_t scl_pin, + uint32_t sda_pin); + +/** + * @brief Function for setting the TWI master clock frequency. + * + * @param[in] p_twim TWIM instance. + * @param[in] frequency TWI frequency. + */ +__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_twim, + nrf_twim_frequency_t frequency); + +/** + * @brief Function for checking the TWI error source. + * + * The error flags are cleared after reading. + * + * @param[in] p_twim TWIM instance. + * + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_twim); + +/** + * @brief Function for setting the address to be used in TWI transfers. + * + * @param[in] p_twim TWIM instance. + * @param[in] address Address to be used in transfers. + */ +__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_twim, + uint8_t address); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_twim TWIM instance. + * @param[in] p_buffer Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_twim, + uint8_t const * p_buffer, + uint8_t length); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_twim TWIM instance. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_twim, + uint8_t * p_buffer, + uint8_t length); + +__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_twim, + uint32_t shorts_mask); + +__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_twim); + +__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_twim); + +/** + * @brief Function for enabling the TX list feature. + * + * @param[in] p_twim TWIM instance. + */ +__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_twim); + +/** + * @brief Function for disabling the TX list feature. + * + * @param[in] p_twim TWIM instance. + */ +__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_twim); + +/** + * @brief Function for enabling the RX list feature. + * + * @param[in] p_twim TWIM instance. + */ +__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_twim); + +/** + * @brief Function for disabling the RX list feature. + * + * @param[in] p_twim TWIM instance. + */ +__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_twim); + +/** + * @} + */ + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_twim, + nrf_twim_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_twim + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_twim, + nrf_twim_task_t task) +{ + return (uint32_t *)((uint8_t *)p_twim + (uint32_t)task); +} + +__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_twim, + nrf_twim_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_twim + (uint32_t)event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_twim, + nrf_twim_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_twim + (uint32_t)event); +} + +__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_twim, + nrf_twim_event_t event) +{ + return (uint32_t *)((uint8_t *)p_twim + (uint32_t)event); +} + +__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_twim, + uint32_t shorts_mask) +{ + p_twim->SHORTS |= shorts_mask; +} + +__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_twim, + uint32_t shorts_mask) +{ + p_twim->SHORTS &= ~(shorts_mask); +} + +__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_twim, + uint32_t int_mask) +{ + p_twim->INTENSET = int_mask; +} + +__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_twim, + uint32_t int_mask) +{ + p_twim->INTENCLR = int_mask; +} + +__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_twim, + nrf_twim_int_mask_t int_mask) +{ + return (bool)(p_twim->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_twim) +{ + p_twim->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_twim) +{ + p_twim->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_twim, + uint32_t scl_pin, + uint32_t sda_pin) +{ + p_twim->PSEL.SCL = scl_pin; + p_twim->PSEL.SDA = sda_pin; +} + +__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_twim, + nrf_twim_frequency_t frequency) +{ + p_twim->FREQUENCY = frequency; +} + +__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_twim) +{ + uint32_t error_source = p_twim->ERRORSRC; + + // [error flags are cleared by writing '1' on their position] + p_twim->ERRORSRC = error_source; + + return error_source; +} + +__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_twim, + uint8_t address) +{ + p_twim->ADDRESS = address; +} + +__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_twim, + uint8_t const * p_buffer, + uint8_t length) +{ + p_twim->TXD.PTR = (uint32_t)p_buffer; + p_twim->TXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_twim, + uint8_t * p_buffer, + uint8_t length) +{ + p_twim->RXD.PTR = (uint32_t)p_buffer; + p_twim->RXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_twim, + uint32_t shorts_mask) +{ + p_twim->SHORTS = shorts_mask; +} + +__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_twim) +{ + return p_twim->TXD.AMOUNT; +} + +__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_twim) +{ + return p_twim->RXD.AMOUNT; +} + +__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_twim) +{ + p_twim->TXD.LIST = 1; +} + +__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_twim) +{ + p_twim->TXD.LIST = 0; +} + +__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_twim) +{ + p_twim->RXD.LIST = 1; +} + +__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_twim) +{ + p_twim->RXD.LIST = 0; +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_TWIM_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twis.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twis.h new file mode 100644 index 0000000..0e568f7 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_twis.h @@ -0,0 +1,676 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @ingroup nrf_twis + * @defgroup nrf_twis_hal TWIS HAL + * @{ + * + * @brief @tagAPI52 Hardware access layer for Two Wire Interface Slave with EasyDMA + * (TWIS) peripheral. + */ +#ifndef NRF_TWIS_H__ +#define NRF_TWIS_H__ + +#include "nrf.h" +#include "nrf_drv_config.h" +#include +#include +#include + +/** + * @brief TWIS tasks + */ +typedef enum +{ + /*lint -save -e30*/ +#ifndef NRF52_PAN_30 /* STOP task is not functional in MPW3 (PAN-30) */ + /* Stop task is not working properly for first release */ + NRF_TWIS_TASK_STOP = offsetof(NRF_TWIS_Type, TASKS_STOP), /**< Stop TWIS transaction */ +#endif + NRF_TWIS_TASK_SUSPEND = offsetof(NRF_TWIS_Type, TASKS_SUSPEND), /**< Suspend TWIS transaction */ + NRF_TWIS_TASK_RESUME = offsetof(NRF_TWIS_Type, TASKS_RESUME), /**< Resume TWIS transaction */ + NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command */ + NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX) /**< Prepare the TWIS slave to respond to a read command */ + /*lint -restore*/ +} nrf_twis_task_t; + +/** + * @brief TWIS events + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWIS_EVENT_STOPPED = offsetof(NRF_TWIS_Type, EVENTS_STOPPED), /**< TWIS stopped */ + NRF_TWIS_EVENT_ERROR = offsetof(NRF_TWIS_Type, EVENTS_ERROR), /**< TWIS error */ + NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started */ + NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started */ + NRF_TWIS_EVENT_WRITE = offsetof(NRF_TWIS_Type, EVENTS_WRITE), /**< Write command received */ + NRF_TWIS_EVENT_READ = offsetof(NRF_TWIS_Type, EVENTS_READ) /**< Read command received */ + /*lint -restore*/ +} nrf_twis_event_t; + +/** + * @brief TWIS shortcuts + */ +typedef enum +{ + NRF_TWIS_SHORT_WRITE_SUSPEND_MASK = TWIS_SHORTS_WRITE_SUSPEND_Msk, /**< Shortcut between WRITE event and SUSPEND task */ + NRF_TWIS_SHORT_READ_SUSPEND_MASK = TWIS_SHORTS_READ_SUSPEND_Msk, /**< Shortcut between READ event and SUSPEND task */ +} nrf_twis_short_mask_t; + +/** + * @brief TWIS interrupts + */ +typedef enum +{ + NRF_TWIS_INT_STOPPED_MASK = TWIS_INTEN_STOPPED_Msk, /**< Interrupt on STOPPED event */ + NRF_TWIS_INT_ERROR_MASK = TWIS_INTEN_ERROR_Msk, /**< Interrupt on ERROR event */ + NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event */ + NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event */ + NRF_TWIS_INT_WRITE_MASK = TWIS_INTEN_WRITE_Msk, /**< Interrupt on WRITE event */ + NRF_TWIS_INT_READ_MASK = TWIS_INTEN_READ_Msk, /**< Interrupt on READ event */ +} nrf_twis_int_mask_t; + +/** + * @brief TWIS error source + */ +typedef enum +{ + NRF_TWIS_ERROR_OVERFLOW = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented */ +#ifdef NRF52_PAN_29 + /* Patched version of bit positions in ERRORSRC register (PAN-29) */ + NRF_TWIS_ERROR_DATA_NACK = 1U << 1, /**< NACK sent after receiving a data byte */ + NRF_TWIS_ERROR_OVERREAD = 1U << 2 /**< TX buffer over-read detected, and prevented */ +#else + /* Code that meets current documentation */ + NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk, /**< NACK sent after receiving a data byte */ + NRF_TWIS_ERROR_OVERREAD = TWIS_ERRORSRC_OVERREAD_Msk /**< TX buffer over-read detected, and prevented */ +#endif +} nrf_twis_error_t; + +/** + * @brief TWIS address matching configuration + */ +typedef enum +{ + NRF_TWIS_CONFIG_ADDRESS0_MASK = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0] */ + NRF_TWIS_CONFIG_ADDRESS1_MASK = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1] */ + NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching */ +} nrf_twis_config_addr_mask_t; + +/** + * @brief Variable type to hold amount of data for EasyDMA + * + * Variable of the minimum size that can hold the amount of data to transfer. + * + * @note + * Defined to make it simple to change if EasyDMA would be updated to support more data in + * the future devices to. + */ +typedef uint8_t nrf_twis_amount_t; + +/** + * @brief Smallest variable type to hold TWI address + * + * Variable of the minimum size that can hold single TWI address. + * + * @note + * Defined to make it simple to change if new TWI would support for example + * 10 bit addressing mode. + */ +typedef uint8_t nrf_twis_address_t; + + +/** + * @brief Function for activating a specific TWIS task. + * + * @param[in] p_twis TWIS instance. + * @param task Task. + */ +__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * const p_twis, nrf_twis_task_t task); + +/** + * @brief Function for returning the address of a specific TWIS task register. + * + * @param[in] p_twis TWIS instance. + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_twis_task_address_get( + NRF_TWIS_Type const * const p_twis, + nrf_twis_task_t task); + +/** + * @brief Function for clearing a specific event. + * + * @param[in] p_twis TWIS instance. + * @param event Event. + */ +__STATIC_INLINE void nrf_twis_event_clear( + NRF_TWIS_Type * const p_twis, + nrf_twis_event_t event); +/** + * @brief Function for returning the state of a specific event. + * + * @param[in] p_twis TWIS instance. + * @param event Event. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_twis_event_check( + NRF_TWIS_Type const * const p_twis, + nrf_twis_event_t event); + + +/** + * @brief Function for getting and clearing the state of specific event + * + * This function checks the state of the event and clears it. + * @param[in,out] p_twis TWIS instance + * @param event Event. + * + * @retval true If the event was set. + * @retval false If the event was not set. + */ +__STATIC_INLINE bool nrf_twis_event_get_and_clear( + NRF_TWIS_Type * const p_twis, + nrf_twis_event_t event); + + +/** + * @brief Function for returning the address of a specific TWIS event register. + * + * @param[in] p_twis TWIS instance. + * @param event Event. + * + * @return Address. + */ +__STATIC_INLINE uint32_t nrf_twis_event_address_get( + NRF_TWIS_Type const * const p_twis, + nrf_twis_event_t event); + +/** + * @brief Function for setting a shortcut. + * + * @param[in] p_twis TWIS instance. + * @param short_mask Shortcuts mask. + */ +__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_twis, uint32_t short_mask); + +/** + * @brief Function for clearing shortcuts. + * + * @param[in] p_twis TWIS instance. + * @param short_mask Shortcuts mask. + */ +__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_twis, uint32_t short_mask); + +/** + * @brief Get the shorts mask + * + * Function returns shorts register. + * @param[in] p_twis TWIS instance. + * @return Flags of currently enabled shortcuts + */ +__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_twis); + +/** + * @brief Function for enabling selected interrupts. + * + * @param[in] p_twis TWIS instance. + * @param int_mask Interrupts mask. + */ +__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * const p_twis, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of selected interrupts. + * + * @param[in] p_twis TWIS instance. + * @param int_mask Interrupts mask. + * + * @retval true If any of selected interrupts is enabled. + * @retval false If none of selected interrupts is enabled. + */ +__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_twis, uint32_t int_mask); + +/** + * @brief Function for disabling selected interrupts. + * + * @param[in] p_twis TWIS instance. + * @param int_mask Interrupts mask. + */ +__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_twis, uint32_t int_mask); + +/** + * @brief Function for retrieving and clearing the TWIS error source. + * + * @attention Error sources are cleared after read. + * @param[in] p_twis TWIS instance + * @return Error source mask with values from @ref nrf_twis_error_t. + */ +__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_twis); + +/** + * @brief Get information which of addresses matched + * + * Function returns index in the address table + * that points to the address that already matched. + * @param[in] p_twis TWIS instance + * @return Index of matched address + */ +__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_twis); + +/** + * @brief Function for enabling TWIS. + * + * @param[in] p_twis TWIS instance. + */ +__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * const p_twis); + +/** + * @brief Function for disabling TWIS. + * + * @param[in] p_twis TWIS instance. + */ +__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * const p_twis); + +/** + * @brief Function for configuring TWIS pins. + * + * @param[in] p_twis TWIS instance. + * @param scl SCL pin number. + * @param sda SDA pin number. + */ +__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * const p_twis, uint32_t scl, uint32_t sda); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_twis TWIS instance. + * @param p_buf Pointer to the buffer for received data. + * @param length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_twis_rx_buffer_set( + NRF_TWIS_Type * const p_twis, + uint8_t * p_buf, + nrf_twis_amount_t length); + +/** + * @brief Function that prepares TWIS for receiving + * + * This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task. + * @param[in] p_twis TWIS instance. + * @param p_buf Pointer to the buffer for received data. + * @param length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_twis_rx_prepare( + NRF_TWIS_Type * const p_twis, + uint8_t * p_buf, + nrf_twis_amount_t length); + +/** + * @brief Function for getting number of bytes received in the last transaction. + * + * @param[in] p_twis TWIS instance. + * @return Amount of bytes received. + * */ +__STATIC_INLINE nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_twis); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_twis TWIS instance. + * @param p_buf Pointer to the buffer with data to send. + * @param length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_twis_tx_buffer_set( + NRF_TWIS_Type * const p_twis, + uint8_t const * p_buf, + nrf_twis_amount_t length); + +/** + * @brief Function that prepares TWIS for transmitting + * + * This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task. + * @param[in] p_twis TWIS instance. + * @param p_buf Pointer to the buffer with data to send. + * @param length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_twis_tx_prepare( + NRF_TWIS_Type * const p_twis, + uint8_t const * p_buf, + nrf_twis_amount_t length); + +/** + * @brief Function for getting number of bytes transmitted in the last transaction. + * + * @param[in] p_twis TWIS instance. + * @return Amount of bytes transmitted. + */ +__STATIC_INLINE nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_twis); + +/** + * @brief Function for setting slave address + * + * Function sets the selected address for this TWI interface. + * @param[in] p_twis TWIS instance. + * @param n Index of address to set + * @param addr Addres to set + * @sa nrf_twis_config_address_set + * @sa nrf_twis_config_address_get + */ +__STATIC_INLINE void nrf_twis_address_set( + NRF_TWIS_Type * const p_twis, + uint_fast8_t n, + nrf_twis_address_t addr); + +/** + * @brief Function for retrieving configured slave address + * + * Function gets the selected address for this TWI interface. + * @param[in] p_twis TWIS instance. + * @param n Index of address to get + */ +__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get( + NRF_TWIS_Type const * const p_twis, + uint_fast8_t n); + +/** + * @brief Function for setting the device address configuration. + * + * @param[in] p_twis TWIS instance. + * @param addr_mask Mask of address indexes of what device should answer to. + * + * @sa nrf_twis_address_set + */ +__STATIC_INLINE void nrf_twis_config_address_set( + NRF_TWIS_Type * const p_twis, + nrf_twis_config_addr_mask_t addr_mask); + +/** + * @brief Function for retrieving the device address configuration. + * + * @param[in] p_twis TWIS instance. + * + * @return Mask of address indexes of what device should answer to. + */ +__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get( + NRF_TWIS_Type const * const p_twis); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_twis TWIS instance. + * @param[in] orc Over-read character. Character clocked out in case of + * over-read of the TXD buffer. + */ +__STATIC_INLINE void nrf_twis_orc_set( + NRF_TWIS_Type * const p_twis, + uint8_t orc); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_twis TWIS instance. + * + * @return Over-read character configured for selected instance. + */ +__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_twis); + + +/** @} */ /* End of nrf_twis_hal */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +/* ------------------------------------------------------------------------------------------------ + * Internal functions + */ + +/** + * @internal + * @brief Internal function for getting task/event register address + * + * @param[in] p_twis TWIS instance. + * @oaram offset Offset of the register from the instance beginning + * + * @attention offset has to be modulo 4 value. In other case we can get hardware fault. + * @return Pointer to the register + */ +__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type * const p_twis, uint32_t offset) +{ + return (volatile uint32_t*)((uint8_t *)p_twis + (uint32_t)offset); +} + +/** + * @internal + * @brief Internal function for getting task/event register address - constant version + * + * @param[in] p_twis TWIS instance. + * @oaram offset Offset of the register from the instance beginning + * + * @attention offset has to be modulo 4 value. In other case we can get hardware fault. + * @return Pointer to the register + */ +__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * const p_twis, uint32_t offset) +{ + return (volatile const uint32_t*)((uint8_t *)p_twis + (uint32_t)offset); +} + + +/* ------------------------------------------------------------------------------------------------ + * Interface functions definitions + */ + + +void nrf_twis_task_trigger(NRF_TWIS_Type * const p_twis, nrf_twis_task_t task) +{ + *(nrf_twis_getRegPtr(p_twis, (uint32_t)task)) = 1UL; +} + +uint32_t nrf_twis_task_address_get( + NRF_TWIS_Type const * const p_twis, + nrf_twis_task_t task) +{ + return (uint32_t)nrf_twis_getRegPtr_c(p_twis, (uint32_t)task); +} + +void nrf_twis_event_clear( + NRF_TWIS_Type * const p_twis, + nrf_twis_event_t event) +{ + *(nrf_twis_getRegPtr(p_twis, (uint32_t)event)) = 0UL; +} + +bool nrf_twis_event_check( + NRF_TWIS_Type const * const p_twis, + nrf_twis_event_t event) +{ + return (bool)*nrf_twis_getRegPtr_c(p_twis, (uint32_t)event); +} + +bool nrf_twis_event_get_and_clear( + NRF_TWIS_Type * const p_twis, + nrf_twis_event_t event) +{ + bool ret = nrf_twis_event_check(p_twis, event); + if(ret) + { + nrf_twis_event_clear(p_twis, event); + } + return ret; +} + +uint32_t nrf_twis_event_address_get( + NRF_TWIS_Type const * const p_twis, + nrf_twis_event_t event) +{ + return (uint32_t)nrf_twis_getRegPtr_c(p_twis, (uint32_t)event); +} + +void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_twis, uint32_t short_mask) +{ + p_twis->SHORTS |= short_mask; +} + +void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_twis, uint32_t short_mask) +{ + if(~0U == short_mask) + { + /* Optimized version for "disable all" */ + p_twis->SHORTS = 0; + } + else + { + p_twis->SHORTS &= ~short_mask; + } +} + +uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_twis) +{ + return p_twis->SHORTS; +} + +void nrf_twis_int_enable(NRF_TWIS_Type * const p_twis, uint32_t int_mask) +{ + p_twis->INTENSET = int_mask; +} + +bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_twis, uint32_t int_mask) +{ + return (bool)(p_twis->INTENSET & int_mask); +} + +void nrf_twis_int_disable(NRF_TWIS_Type * const p_twis, uint32_t int_mask) +{ + p_twis->INTENCLR = int_mask; +} + +uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_twis) +{ + uint32_t ret = p_twis->ERRORSRC; + p_twis->ERRORSRC = ret; + return ret; +} + +uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_twis) +{ + return (uint_fast8_t)p_twis->MATCH; +} + +void nrf_twis_enable(NRF_TWIS_Type * const p_twis) +{ + p_twis->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos); +} + +void nrf_twis_disable(NRF_TWIS_Type * const p_twis) +{ + p_twis->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos); +} + +void nrf_twis_pins_set(NRF_TWIS_Type * const p_twis, uint32_t scl, uint32_t sda) +{ + p_twis->PSEL.SCL = scl; + p_twis->PSEL.SDA = sda; +} + +void nrf_twis_rx_buffer_set( + NRF_TWIS_Type * const p_twis, + uint8_t * p_buf, + nrf_twis_amount_t length) +{ + p_twis->RXD.PTR = (uint32_t)p_buf; + p_twis->RXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twis_rx_prepare( + NRF_TWIS_Type * const p_twis, + uint8_t * p_buf, + nrf_twis_amount_t length) +{ + nrf_twis_rx_buffer_set(p_twis, p_buf, length); + nrf_twis_task_trigger(p_twis, NRF_TWIS_TASK_PREPARERX); +} + +nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_twis) +{ + return (nrf_twis_amount_t)p_twis->RXD.AMOUNT; +} + +void nrf_twis_tx_buffer_set( + NRF_TWIS_Type * const p_twis, + uint8_t const * p_buf, + nrf_twis_amount_t length) +{ + p_twis->TXD.PTR = (uint32_t)p_buf; + p_twis->TXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twis_tx_prepare( + NRF_TWIS_Type * const p_twis, + uint8_t const * p_buf, + nrf_twis_amount_t length) +{ + nrf_twis_tx_buffer_set(p_twis, p_buf, length); + nrf_twis_task_trigger(p_twis, NRF_TWIS_TASK_PREPARETX); +} + +nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_twis) +{ + return (nrf_twis_amount_t)p_twis->TXD.AMOUNT; +} + +void nrf_twis_address_set( + NRF_TWIS_Type * const p_twis, + uint_fast8_t n, + nrf_twis_address_t addr) +{ + p_twis->ADDRESS[n] = addr; +} + +nrf_twis_address_t nrf_twis_address_get( + NRF_TWIS_Type const * const p_twis, + uint_fast8_t n) +{ + return (nrf_twis_address_t)p_twis->ADDRESS[n]; +} +void nrf_twis_config_address_set( + NRF_TWIS_Type * const p_twis, + nrf_twis_config_addr_mask_t addr_mask) +{ + /* This is the only configuration in TWIS - just write it without masking */ + p_twis->CONFIG = addr_mask; +} + +nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * const p_twis) +{ + return (nrf_twis_config_addr_mask_t)(p_twis->CONFIG & TWIS_ADDRESS_ADDRESS_Msk); +} + +void nrf_twis_orc_set( + NRF_TWIS_Type * const p_twis, + uint8_t orc) +{ + p_twis->ORC = orc; +} + +uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_twis) +{ + return (uint8_t)p_twis->ORC; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +#endif /* NRF_TWIS_H__ */ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uart.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uart.h new file mode 100644 index 0000000..87ca963 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uart.h @@ -0,0 +1,471 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#ifndef NRF_UART_H__ +#define NRF_UART_H__ + +#include "nrf.h" +#include +#include +#include + +/** + * @defgroup nrf_uart_hal UART HAL + * @{ + * @ingroup nrf_uart + * + * @brief Hardware access layer for accessing the UART peripheral. + */ + +#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF + +/** + * @enum nrf_uart_task_t + * @brief UART tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_UART_TASK_STARTRX = offsetof(NRF_UART_Type, TASKS_STARTRX), /**< Task for starting reception. */ + NRF_UART_TASK_STOPRX = offsetof(NRF_UART_Type, TASKS_STOPRX), /**< Task for stopping reception. */ + NRF_UART_TASK_STARTTX = offsetof(NRF_UART_Type, TASKS_STARTTX), /**< Task for starting transmission. */ + NRF_UART_TASK_STOPTX = offsetof(NRF_UART_Type, TASKS_STOPTX), /**< Task for stopping transmission. */ + NRF_UART_TASK_SUSPEND = offsetof(NRF_UART_Type, TASKS_SUSPEND), /**< Task for suspending UART. */ + /*lint -restore*/ +} nrf_uart_task_t; + +/** + * @enum nrf_uart_event_t + * @brief UART events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UART_EVENT_CTS = offsetof(NRF_UART_Type, EVENTS_CTS), /**< Event from CTS line activation. */ + NRF_UART_EVENT_NCTS = offsetof(NRF_UART_Type, EVENTS_NCTS), /**< Event from CTS line deactivation. */ + NRF_UART_EVENT_RXDRDY = offsetof(NRF_UART_Type, EVENTS_RXDRDY),/**< Event from data ready in RXD. */ + NRF_UART_EVENT_TXDRDY = offsetof(NRF_UART_Type, EVENTS_TXDRDY),/**< Event from data sent from TXD. */ + NRF_UART_EVENT_ERROR = offsetof(NRF_UART_Type, EVENTS_ERROR), /**< Event from error detection. */ + NRF_UART_EVENT_RXTO = offsetof(NRF_UART_Type, EVENTS_RXTO) /**< Event from receiver timeout. */ + /*lint -restore*/ +} nrf_uart_event_t; + +/** + * @enum nrf_uart_int_mask_t + * @brief UART interrupts. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UART_INT_MASK_CTS = UART_INTENCLR_CTS_Msk, /**< CTS line activation interrupt. */ + NRF_UART_INT_MASK_NCTS = UART_INTENCLR_NCTS_Msk, /**< CTS line deactivation interrupt. */ + NRF_UART_INT_MASK_RXDRDY = UART_INTENCLR_RXDRDY_Msk, /**< Data ready in RXD interrupt. */ + NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk, /**< Data sent from TXD interrupt. */ + NRF_UART_INT_MASK_ERROR = UART_INTENCLR_ERROR_Msk, /**< Error detection interrupt. */ + NRF_UART_INT_MASK_RXTO = UART_INTENCLR_RXTO_Msk /**< Receiver timeout interrupt. */ + /*lint -restore*/ +} nrf_uart_int_mask_t; + +/** + * @enum nrf_uart_baudrate_t + * @brief Baudrates supported by UART. + */ +typedef enum +{ +#ifdef NRF52 + NRF_UART_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */ + NRF_UART_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */ + NRF_UART_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */ + NRF_UART_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */ + NRF_UART_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */ + NRF_UART_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */ + NRF_UART_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */ + NRF_UART_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */ + NRF_UART_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */ + NRF_UART_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */ + NRF_UART_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */ + NRF_UART_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */ + NRF_UART_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */ + NRF_UART_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */ + NRF_UART_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */ + NRF_UART_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */ +#else + NRF_UART_BAUDRATE_1200 = UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */ + NRF_UART_BAUDRATE_2400 = UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */ + NRF_UART_BAUDRATE_4800 = UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */ + NRF_UART_BAUDRATE_9600 = UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */ + NRF_UART_BAUDRATE_14400 = UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */ + NRF_UART_BAUDRATE_19200 = UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */ + NRF_UART_BAUDRATE_28800 = UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */ + NRF_UART_BAUDRATE_38400 = UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */ + NRF_UART_BAUDRATE_57600 = UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */ + NRF_UART_BAUDRATE_76800 = UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */ + NRF_UART_BAUDRATE_115200 = UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */ + NRF_UART_BAUDRATE_230400 = UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */ + NRF_UART_BAUDRATE_250000 = UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */ + NRF_UART_BAUDRATE_460800 = UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */ + NRF_UART_BAUDRATE_921600 = UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */ + NRF_UART_BAUDRATE_1000000 = UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */ +#endif +} nrf_uart_baudrate_t; + +/** + * @enum nrf_uart_error_mask_t + * @brief Types of UART error masks. + */ +typedef enum +{ + NRF_UART_ERROR_OVERRUN_MASK = UART_ERRORSRC_OVERRUN_Msk, /**< Overrun error. */ + NRF_UART_ERROR_PARITY_MASK = UART_ERRORSRC_PARITY_Msk, /**< Parity error. */ + NRF_UART_ERROR_FRAMING_MASK = UART_ERRORSRC_FRAMING_Msk, /**< Framing error. */ + NRF_UART_ERROR_BREAK_MASK = UART_ERRORSRC_BREAK_Msk, /**< Break error. */ +} nrf_uart_error_mask_t; + +/** + * @enum nrf_uart_parity_t + * @brief Types of UART parity modes. + */ +typedef enum +{ + NRF_UART_PARITY_EXCLUDED = UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos, /**< Parity excluded. */ + NRF_UART_PARITY_INCLUDED = UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos, /**< Parity included. */ +} nrf_uart_parity_t; + +/** + * @enum nrf_uart_hwfc_t + * @brief Types of UART flow control modes. + */ +typedef enum +{ + NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< HW flow control disabled. */ + NRF_UART_HWFC_ENABLED = UART_CONFIG_HWFC_Enabled, /**< HW flow control enabled. */ +} nrf_uart_hwfc_t; + +/** + * @brief Function for clearing a specific UART event. + * + * @param[in] p_reg UART instance. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event); + +/** + * @brief Function for checking the state of a specific UART event. + * + * @param[in] p_reg UART instance. + * @param[in] event Event to check. + * + * @retval True if event is set, False otherwise. + */ +__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event); + +/** + * @brief Function for returning the address of a specific UART event register. + * + * @param[in] p_reg UART instance. + * @param[in] event Desired event. + * + * @retval Address of specified event register. + */ +__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg, + nrf_uart_event_t event); + +/** + * @brief Function for enabling a specific interrupt. + * + * @param p_reg Instance. + * @param int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param p_reg Instance. + * @param int_mask Mask of interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for disabling specific interrupts. + * + * @param p_reg Instance. + * @param int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for getting error source mask. Function is clearing error source flags after reading. + * + * @param p_reg Instance. + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg); + +/** + * @brief Function for enabling UART. + * + * @param p_reg Instance. + */ +__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg); + +/** + * @brief Function for disabling UART. + * + * @param p_reg Instance. + */ +__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg); + +/** + * @brief Function for configuring TX/RX pins. + * + * @param p_reg Instance. + * @param pseltxd TXD pin number. + * @param pselrxd RXD pin number. + */ +__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd); + +/** + * @brief Function for disconnecting TX/RX pins. + * + * @param p_reg Instance. + */ +__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting TX pin. + * + * @param p_reg Instance. + */ +__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting RX pin. + * + * @param p_reg Instance. + */ +__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting RTS pin. + * + * @param p_reg Instance. + */ +__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting CTS pin. + * + * @param p_reg Instance. + */ +__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg); + + +/** + * @brief Function for configuring flow control pins. + * + * @param p_reg Instance. + * @param pselrts RTS pin number. + * @param pselcts CTS pin number. + */ +__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, + uint32_t pselrts, + uint32_t pselcts); + +/** + * @brief Function for disconnecting flow control pins. + * + * @param p_reg Instance. + */ +__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg); + +/** + * @brief Function for reading RX data. + * + * @param p_reg Instance. + * @return Received byte. + */ +__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for setting Tx data. + * + * @param p_reg Instance. + * @param txd Byte. + */ +__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd); + +/** + * @brief Function for starting an UART task. + * + * @param p_reg Instance. + * @param task Task. + */ +__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task); + +/** + * @brief Function for returning the address of a specific task register. + * + * @param p_reg Instance. + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task); + +/** + * @brief Function for configuring UART. + * + * @param p_reg Instance. + * @param hwfc Hardware flow control. Enabled if true. + * @param parity Parity. Included if true. + */ +__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg, + nrf_uart_parity_t parity, + nrf_uart_hwfc_t hwfc); + +/** + * @brief Function for setting UART baudrate. + * + * @param p_reg Instance. + * @param baudrate Baudrate. + */ +__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; + +} + +__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg, + nrf_uart_event_t event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask) +{ + return (bool)(p_reg->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg) +{ + uint32_t errsrc_mask = p_reg->ERRORSRC; + p_reg->ERRORSRC = errsrc_mask; + return errsrc_mask; +} + +__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg) +{ + p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled; +} + +__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg) +{ + p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled; +} + +__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd) +{ + p_reg->PSELTXD = pseltxd; + p_reg->PSELRXD = pselrxd; +} + +__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg) +{ + nrf_uart_txrx_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED); +} + +__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg) +{ + return p_reg->PSELTXD; +} + +__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg) +{ + return p_reg->PSELRXD; +} + +__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg) +{ + return p_reg->PSELRTS; +} + +__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg) +{ + return p_reg->PSELCTS; +} + +__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, uint32_t pselrts, uint32_t pselcts) +{ + p_reg->PSELRTS = pselrts; + p_reg->PSELCTS = pselcts; +} + +__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg) +{ + nrf_uart_hwfc_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED); +} + +__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg) +{ + return p_reg->RXD; +} + +__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd) +{ + p_reg->TXD = txd; +} + +__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task) +{ + return (uint32_t)p_reg + (uint32_t)task; +} + +__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg, + nrf_uart_parity_t parity, + nrf_uart_hwfc_t hwfc) +{ + p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc; +} + +__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate) +{ + p_reg->BAUDRATE = baudrate; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION +/** @} */ +#endif //NRF_UART_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uarte.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uarte.h new file mode 100644 index 0000000..26784d9 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_uarte.h @@ -0,0 +1,534 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#ifndef NRF_UARTE_H__ +#define NRF_UARTE_H__ + +#include "nrf.h" +#include +#include +#include + +#define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF + +/** + * @defgroup nrf_uarte_hal UARTE HAL + * @{ + * @ingroup nrf_uart + * + * @brief Hardware access layer for accessing the UARTE peripheral. + */ + +/** + * @enum nrf_uarte_task_t + * @brief UARTE tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX),///< Start UART receiver. + NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver. + NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX),///< Start UART transmitter. + NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter. + NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer. + /*lint -restore*/ +} nrf_uarte_task_t; + +/** + * @enum nrf_uarte_event_t + * @brief UARTE events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated. + NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated. + NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up. + NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted. + NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected. + NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout. + NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED),///< Receiver has started. + NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED),///< Transmitter has started. + NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped. + /*lint -restore*/ +} nrf_uarte_event_t; + +/** + * @brief Types of UARTE shortcuts. + */ +typedef enum +{ + NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk,///< Shortcut between ENDRX event and STARTRX task. + NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk, ///< Shortcut between ENDRX event and STOPRX task. +} nrf_uarte_short_t; + + +/** + * @enum nrf_uarte_int_mask_t + * @brief UARTE interrupts. + */ +typedef enum +{ + NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event. + NRF_UARTE_INT_NCTSRX_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event. + NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event. + NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event. + NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. + NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event. + NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk,///< Interrupt on RXSTARTED event. + NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk,///< Interrupt on TXSTARTED event. + NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event. +} nrf_uarte_int_mask_t; + +/** + * @enum nrf_uarte_baudrate_t + * @brief Baudrates supported by UARTE. + */ +typedef enum +{ + NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud. + NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud. + NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud. + NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud. + NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud. + NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud. + NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud. + NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud. + NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud. + NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud. + NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud. + NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud. + NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud. + NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud. + NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud. + NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud. +} nrf_uarte_baudrate_t; + +/** + * @enum nrf_uarte_error_mask_t + * @brief Types of UARTE error masks. + */ +typedef enum +{ + NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error. + NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error. + NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error. + NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk, ///< Break error. +} nrf_uarte_error_mask_t; + +/** + * @enum nrf_uarte_parity_t + * @brief Types of UARTE parity modes. + */ +typedef enum +{ + NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded. + NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos, ///< Parity included. +} nrf_uarte_parity_t; + +/** + * @enum nrf_uarte_hwfc_t + * @brief Types of UARTE flow control modes. + */ +typedef enum +{ + NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control disabled. + NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control enabled. +} nrf_uarte_hwfc_t; + + +/** + * @brief Function for clearing a specific UARTE event. + * + * @param[in] p_reg UARTE instance. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event); + +/** + * @brief Function for checking the state of a specific UARTE event. + * + * @param[in] p_reg UARTE instance. + * @param[in] event Event to check. + * + * @retval True if event is set, False otherwise. + */ +__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event); + +/** + * @brief Function for returning the address of a specific UARTE event register. + * + * @param[in] p_reg UARTE instance. + * @param[in] event Desired event. + * + * @retval Address of specified event register. + */ +__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event); + +/** + * @brief Function for enabling UARTE shortcuts. + * + * @param p_reg UARTE instance. + * @param shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask); + +/** + * @brief Function for disabling UARTE shortcuts. + * + * @param p_reg UARTE instance. + * @param shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask); + +/** + * @brief Function for enabling UARTE interrupts. + * + * @param p_reg Instance. + * @param int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param p_reg Instance. + * @param int_mask Mask of interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask); + +/** + * @brief Function for disabling specific interrupts. + * + * @param p_reg Instance. + * @param int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for getting error source mask. Function is clearing error source flags after reading. + * + * @param p_reg Instance. + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for enabling UARTE. + * + * @param p_reg Instance. + */ +__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for disabling UARTE. + * + * @param p_reg Instance. + */ +__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for configuring TX/RX pins. + * + * @param p_reg Instance. + * @param pseltxd TXD pin number. + * @param pselrxd RXD pin number. + */ +__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd); + +/** + * @brief Function for disconnecting TX/RX pins. + * + * @param p_reg Instance. + */ +__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting TX pin. + * + * @param p_reg Instance. + */ +__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting RX pin. + * + * @param p_reg Instance. + */ +__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting RTS pin. + * + * @param p_reg Instance. + */ +__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting CTS pin. + * + * @param p_reg Instance. + */ +__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg); + + +/** + * @brief Function for configuring flow control pins. + * + * @param p_reg Instance. + * @param pselrts RTS pin number. + * @param pselcts CTS pin number. + */ +__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, + uint32_t pselrts, + uint32_t pselcts); + +/** + * @brief Function for disconnecting flow control pins. + * + * @param p_reg Instance. + */ +__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for starting an UARTE task. + * + * @param p_reg Instance. + * @param task Task. + */ +__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task); + +/** + * @brief Function for returning the address of a specific task register. + * + * @param p_reg Instance. + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task); + +/** + * @brief Function for configuring UARTE. + * + * @param p_reg Instance. + * @param hwfc Hardware flow control. Enabled if true. + * @param parity Parity. Included if true. + */ +__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg, + nrf_uarte_parity_t parity, + nrf_uarte_hwfc_t hwfc); + + +/** + * @brief Function for setting UARTE baudrate. + * + * @param p_reg Instance. + * @param baudrate Baudrate. + */ +__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_reg Instance. + * @param[in] p_buffer Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t const * p_buffer, + uint8_t length); + +/** + * @brief Function for getting number of bytes transmitted in the last transaction. + * + * @param[in] p_reg Instance. + * + * @retval Amount of bytes transmitted. + */ +__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_reg Instance. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t * p_buffer, + uint8_t length); + +/** + * @brief Function for getting number of bytes received in the last transaction. + * + * @param[in] p_reg Instance. + * + * @retval Amount of bytes received. + */ +__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; + +} + +__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask) +{ + p_reg->SHORTS |= shorts_mask; +} + +__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask) +{ + p_reg->SHORTS &= ~(shorts_mask); +} + +__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask) +{ + return (bool)(p_reg->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg) +{ + uint32_t errsrc_mask = p_reg->ERRORSRC; + p_reg->ERRORSRC = errsrc_mask; + return errsrc_mask; +} + +__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg) +{ + p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled; +} + +__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg) +{ + p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled; +} + +__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd) +{ + p_reg->PSEL.TXD = pseltxd; + p_reg->PSEL.RXD = pselrxd; +} + +__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg) +{ + nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED); +} + +__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.TXD; +} + +__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.RXD; +} + +__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.RTS; +} + +__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.CTS; +} + +__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, uint32_t pselrts, uint32_t pselcts) +{ + p_reg->PSEL.RTS = pselrts; + p_reg->PSEL.CTS = pselcts; +} + +__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg) +{ + nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED); +} + +__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task) +{ + return (uint32_t)p_reg + (uint32_t)task; +} + +__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg, + nrf_uarte_parity_t parity, + nrf_uarte_hwfc_t hwfc) +{ + p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc; +} + +__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate) +{ + p_reg->BAUDRATE = baudrate; +} + +__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t const * p_buffer, + uint8_t length) +{ + p_reg->TXD.PTR = (uint32_t)p_buffer; + p_reg->TXD.MAXCNT = length; +} + +__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->TXD.AMOUNT; +} + +__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t * p_buffer, + uint8_t length) +{ + p_reg->RXD.PTR = (uint32_t)p_buffer; + p_reg->RXD.MAXCNT = length; +} + +__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->RXD.AMOUNT; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION +/** @} */ +#endif //NRF_UARTE_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_wdt.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_wdt.h new file mode 100644 index 0000000..f2b067a --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/hal/nrf_wdt.h @@ -0,0 +1,299 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @defgroup nrf_wdt_hal WDT HAL + * @{ + * @ingroup nrf_wdt + * + * @brief Hardware access layer for accessing the watchdog timer (WDT) peripheral. + */ + +#ifndef NRF_WDT_H__ +#define NRF_WDT_H__ + +#include +#include +#include + +#include "nrf.h" + +#define NRF_WDT_CHANNEL_NUMBER 0x8UL +#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, shouldn't be modified.*/ + +#define NRF_WDT_TASK_SET 1UL +#define NRF_WDT_EVENT_CLEAR 0UL + +/** + * @enum nrf_wdt_task_t + * @brief WDT tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */ + /*lint -restore*/ +} nrf_wdt_task_t; + +/** + * @enum nrf_wdt_event_t + * @brief WDT events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */ + /*lint -restore*/ +} nrf_wdt_event_t; + +/** + * @enum nrf_wdt_behaviour_t + * @brief WDT behavior in CPU SLEEP or HALT mode. + */ +typedef enum +{ + NRF_WDT_BEHAVIOUR_RUN_SLEEP = WDT_CONFIG_SLEEP_Msk, /**< WDT will run when CPU is in SLEEP mode. */ + NRF_WDT_BEHAVIOUR_RUN_HALT = WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in HALT mode. */ + NRF_WDT_BEHAVIOUR_RUN_SLEEP_HALT = WDT_CONFIG_SLEEP_Msk | WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in SLEEP or HALT mode. */ + NRF_WDT_BEHAVIOUR_PAUSE_SLEEP_HALT = 0, /**< WDT will be paused when CPU is in SLEEP or HALT mode. */ +} nrf_wdt_behaviour_t; + +/** + * @enum nrf_wdt_rr_register_t + * @brief WDT reload request registers. + */ +typedef enum +{ + NRF_WDT_RR0 = 0, /**< Reload request register 0. */ + NRF_WDT_RR1, /**< Reload request register 1. */ + NRF_WDT_RR2, /**< Reload request register 2. */ + NRF_WDT_RR3, /**< Reload request register 3. */ + NRF_WDT_RR4, /**< Reload request register 4. */ + NRF_WDT_RR5, /**< Reload request register 5. */ + NRF_WDT_RR6, /**< Reload request register 6. */ + NRF_WDT_RR7 /**< Reload request register 7. */ +} nrf_wdt_rr_register_t; + +/** + * @enum nrf_wdt_int_mask_t + * @brief WDT interrupts. + */ +typedef enum +{ + NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */ +} nrf_wdt_int_mask_t; + +/** + * @brief Function for configuring the watchdog behavior when the CPU is sleeping or halted. + * + * @param behaviour Watchdog behavior when CPU is in SLEEP or HALT mode. + */ +__STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour) +{ + NRF_WDT->CONFIG = behaviour; +} + + +/** + * @brief Function for starting the watchdog. + * + * @param[in] task Task. + */ +__STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_WDT + task)) = NRF_WDT_TASK_SET; +} + + +/** + * @brief Function for clearing the WDT event. + * + * @param[in] event Event. + */ +__STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = NRF_WDT_EVENT_CLEAR; +} + + +/** + * @brief Function for retrieving the state of the WDT event. + * + * @param[in] event Event. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event) +{ + return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + event)); +} + + +/** + * @brief Function for enabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask) +{ + NRF_WDT->INTENSET = int_mask; +} + + +/** + * @brief Function for retrieving the state of given interrupt. + * + * @param[in] int_mask Interrupt. + * + * @retval true Interrupt is enabled. + * @retval false Interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask) +{ + return (bool)(NRF_WDT->INTENSET & int_mask); +} + + +/** + * @brief Function for disabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask) +{ + NRF_WDT->INTENCLR = int_mask; +} + + +/** + * @brief Function for returning the address of a specific WDT task register. + * + * @param[in] task Task. + */ +__STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task) +{ + return ((uint32_t)NRF_WDT + task); +} + + +/** + * @brief Function for returning the address of a specific WDT event register. + * + * @param[in] event Event. + * + * @retval address of requested event register + */ +__STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event) +{ + return ((uint32_t)NRF_WDT + event); +} + + +/** + * @brief Function for retrieving the watchdog status. + * + * @retval true If the watchdog is started. + * @retval false If the watchdog is not started. + */ +__STATIC_INLINE bool nrf_wdt_started(void) +{ + return (bool)(NRF_WDT->RUNSTATUS); +} + + +/** + * @brief Function for retrieving the watchdog reload request status. + * + * @param[in] rr_register Reload request register to check. + * + * @retval true If a reload request is running. + * @retval false If no reload request is running. + */ +__STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register) +{ + return (bool)(((NRF_WDT->REQSTATUS) >> rr_register) & 0x1UL); +} + + +/** + * @brief Function for setting the watchdog reload value. + * + * @param[in] reload_value Watchdog counter initial value. + */ +__STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value) +{ + NRF_WDT->CRV = reload_value; +} + + +/** + * @brief Function for retrieving the watchdog reload value. + * + * @retval Reload value. + */ +__STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void) +{ + return (uint32_t)NRF_WDT->CRV; +} + + +/** + * @brief Function for enabling a specific reload request register. + * + * @param[in] rr_register Reload request register to enable. + */ +__STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register) +{ + NRF_WDT->RREN |= 0x1UL << rr_register; +} + + +/** + * @brief Function for disabling a specific reload request register. + * + * @param[in] rr_register Reload request register to disable. + */ +__STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register) +{ + NRF_WDT->RREN &= ~(0x1UL << rr_register); +} + + +/** + * @brief Function for retrieving the status of a specific reload request register. + * + * @param[in] rr_register Reload request register to check. + * + * @retval true If the reload request register is enabled. + * @retval false If the reload request register is not enabled. + */ +__STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register) +{ + return (bool)(NRF_WDT->RREN & (0x1UL << rr_register)); +} + + +/** + * @brief Function for setting a specific reload request register. + * + * @param[in] rr_register Reload request register to set. + */ +__STATIC_INLINE void nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register) +{ + NRF_WDT->RR[rr_register] = NRF_WDT_RR_VALUE; +} + + +#endif + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage.h new file mode 100644 index 0000000..f7d2f43 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage.h @@ -0,0 +1,381 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup persistent_storage Persistent Storage Interface + * @{ + * @ingroup app_common + * @brief Abstracted flash interface. + * + * @details An abstracted interface is provided by the module to easily port the application and + * SDK modules to an alternate option. This ensures that the SDK and application are moved + * to alternate persistent storage instead of the one provided by default. + */ + +#ifndef PSTORAGE_H__ +#define PSTORAGE_H__ + +#include "pstorage_platform.h" + + +/**@defgroup ps_opcode Persistent Storage Access Operation Codes + * @{ + * @brief Persistent Storage Access Operation Codes. + * + * @details Persistent Storage Access Operation Codes are used by Persistent storage operation + * completion callback @ref pstorage_ntf_cb_t to identify the operation type requested by + * the application. + */ +#define PSTORAGE_STORE_OP_CODE 0x01 /**< Store Operation type. */ +#define PSTORAGE_LOAD_OP_CODE 0x02 /**< Load Operation type. */ +#define PSTORAGE_CLEAR_OP_CODE 0x03 /**< Clear Operation type. */ +#define PSTORAGE_UPDATE_OP_CODE 0x04 /**< Update Operation type. */ + +/**@} */ + +/**@defgroup pstorage_data_types Persistent Memory Interface Data Types + * @{ + * @brief Data Types needed for interfacing with persistent memory. + * + * @details Data Types needed for interfacing with persistent memory. + */ + +/**@brief Persistent storage operation completion callback function type. + * + * @details The persistent storage operation completion callback is used by the interface to report + * success or failure of a flash operation. Since data is not copied for a store operation, + * a callback is an indication that the resident memory can now be reused or freed. + * + * @param[in] handle Identifies the module and block for the callback that is received. + * @param[in] op_code Identifies the operation for the event that is notified. + * @param[in] result Identifies the result of a flash access operation. NRF_SUCCESS implies + * operation succeeded. + * + * @note Unmanaged (abnormal behaviour) error codes from the SoftDevice flash + * access API are forwarded as is and are expected to be handled by the + * application. For details refer to the implementation file and corresponding + * SoftDevice flash API documentation. + * + * @param[in] p_data Identifies the application data pointer. For a store operation, this points + * to the resident source of application memory that the application can now + * free or reuse. When there is a clear operation, this is NULL since no + * application pointer is needed for this operation. + * @param[in] data_len Length data the application provided for the operation. + */ +typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle, + uint8_t op_code, + uint32_t result, + uint8_t * p_data, + uint32_t data_len); + +/**@brief Struct containing module registration context. */ +typedef struct +{ + pstorage_ntf_cb_t cb; /**< Persistent storage operation completion callback function @ref pstorage_ntf_cb_t. */ + pstorage_size_t block_size; /**< Desired block size for persistent memory storage. For example, if a module has a table with 10 entries, and each entry is 64 bytes in size, + * it can request 10 blocks with a block size of 64 bytes. The module can also request one block that is 640 bytes depending + * on how it would like to access or alter the memory in persistent memory. + * The first option is preferred when it is a single entry that needs to be updated often and doesn't impact the other entries. + * The second option is preferred when table entries are not changed individually but have a common point of loading and storing + * data. */ + pstorage_size_t block_count; /** Number of blocks requested by the module; minimum values is 1. */ +} pstorage_module_param_t; + +/**@} */ + +/**@defgroup pstorage_routines Persistent Storage Access Routines + * @{ + * @brief Functions/Interface SDK modules used to persistently store data. + * + * @details Interface for the Application and SDK modules to load/store information persistently. + * Note: While implementation of each of the persistent storage access functions + * depends on the system and is specific to system/solution, the signature of the + * interface routines should not be altered. + */ + +/**@brief Function for initializing the module. + * + * @details Function for initializing the module. This function is called once before any other APIs + * of the module are used. + * + * @retval NRF_SUCCESS Operation success. + */ +uint32_t pstorage_init(void); + +/**@brief Function for registering with persistent storage interface. + * + * @param[in] p_module_param Module registration parameter. + * @param[out] p_block_id Block identifier to identify persistent memory blocks when + * registration succeeds. Application is expected to use the block IDs + * for subsequent operations on requested persistent memory. Maximum + * registrations permitted is determined by the configuration of the + * parameter PSTORAGE_NUM_OF_PAGES. If more than one memory block is + * requested, the identifier provided here is the base identifier for the + * first block and used to identify the subsequent block. The application + * uses \@ref pstorage_block_identifier_get with this base identifier and + * block number. Therefore if 10 blocks of size 64 are requested and the + * application wishes to store memory in the 6th block, it shall use + * \@ref pstorage_block_identifier_get with the base ID and provide a + * block number of 5. This way the application is only expected to + * remember the base block identifier. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed. + * @retval NRF_ERROR_NO_MEM Operation failure. Additional registrations can't be + * supported. + */ +uint32_t pstorage_register(pstorage_module_param_t * p_module_param, + pstorage_handle_t * p_block_id); + +/**@brief Function for getting block ID with reference to base block identifier provided at the time + * of registration. + * + * @details Function to get the block ID with reference to base block identifier provided at the + * time of registration. + * If more than one memory block was requested when registering, the identifier provided + * here is the base identifier for the first block which is used to identify subsequent + * blocks. The application shall use this routine to get the block identifier, providing + * input as base identifier and block number. Therefore, if 10 blocks of size 64 are + * requested and the application wishes to store memory in the 6th block, it shall use + * \@ref pstorage_block_identifier_get with the base ID and provide a block number of 5. + * This way the application is only expected to remember the base block identifier. + * + * @param[in] p_base_id Base block ID received at the time of registration. + * @param[in] block_num Block Number, with first block numbered zero. + * @param[out] p_block_id Block identifier for the block number requested when the API succeeds. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed. + */ +uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id, + pstorage_size_t block_num, + pstorage_handle_t * p_block_id); + +/**@brief Function for persistently storing data of length 'size' contained in the 'p_src' address + * in the storage module at 'p_dest' address. Equivalent to Storage Write. + * + * @param[in] p_dest Destination address where data is to be stored persistently. + * @param[in] p_src Source address containing data to be stored. API assumes this to be resident + * memory and no intermediate copy of data is made by the API. Must be word + * aligned. + * @param[in] size Size of data to be stored expressed in bytes. Must be word aligned and size + + * offset must be <= block size. + * @param[in] offset Offset in bytes to be applied when writing to the block. + * For example, if within a block of 100 bytes, the application wishes to + * write 20 bytes at an offset of 12, then this field should be set to 12. + * Must be word aligned. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed. + * @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned. + * @retval NRF_ERROR_NO_MEM Operation failure. No storage space available. + * + * @warning No copy of the data is made, meaning memory provided for the data source that is to + * be written to flash cannot be freed or reused by the application until this procedure + * is complete. The application is notified when the procedure is finished using the + * notification callback registered by the application. + */ +uint32_t pstorage_store(pstorage_handle_t * p_dest, + uint8_t * p_src, + pstorage_size_t size, + pstorage_size_t offset); + +/**@brief Function for updating persistently stored data of length 'size' contained in the 'p_src' + * address in the storage module at 'p_dest' address. + * + * @param[in] p_dest Destination address where data is to be updated. + * @param[in] p_src Source address containing data to be stored. API assumes this to be resident + * memory and no intermediate copy of data is made by the API. + * @param[in] size Size of data to be stored expressed in bytes. Must be word aligned and size + + * offset must be <= block size. + * @param[in] offset Offset in bytes to be applied when writing to the block. + * For example, if within a block of 100 bytes, the application wishes to + * write 20 bytes at an offset of 12 bytes, then this field should be set to 12. + * Must be word aligned. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed. + * @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned. + * @retval NRF_ERROR_NO_MEM Operation failure. No storage space available. + * + * @warning No copy of the data is made, meaning memory provided for the data source that is to + * be written to flash cannot be freed or reused by the application until this procedure + * is complete. The application is notified when the procedure is finished using the + * notification callback registered by the application. + */ +uint32_t pstorage_update(pstorage_handle_t * p_dest, + uint8_t * p_src, + pstorage_size_t size, + pstorage_size_t offset); + +/**@brief Function for loading persistently stored data of length 'size' from 'p_src' address + * to 'p_dest' address. Equivalent to Storage Read. + * + * @param[in] p_dest Destination address where persistently stored data is to be loaded. + * @param[in] p_src Source where data is loaded from persistent memory. + * @param[in] size Size of data to be loaded from persistent memory expressed in bytes. + * Should be word aligned. + * @param[in] offset Offset in bytes, to be applied when loading from the block. + * For example, if within a block of 100 bytes, the application wishes to + * load 20 bytes from offset of 12 bytes, then this field should be set to 12. + * Should be word aligned. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed. + * @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned. + * @retval NRF_ERROR_NO_MEM Operation failure. No storage space available. + */ +uint32_t pstorage_load(uint8_t * p_dest, + pstorage_handle_t * p_src, + pstorage_size_t size, + pstorage_size_t offset); + +/**@brief Function for clearing data in persistent memory. + * + * @param[in] p_base_id Base block identifier in persistent memory that needs to be cleared; + * equivalent to an Erase Operation. + * @param[in] size Size of data to be cleared from persistent memory expressed in bytes. + * This parameter is to provision for clearing of certain blocks + * of memory, or all memory blocks in a registered module. If the total size + * of the application module is used (blocks * block size) in combination with + * the identifier for the first block in the module, all blocks in the + * module will be erased. Must be multiple of block size. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed. + * @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned. + * @retval NRF_ERROR_NO_MEM Operation failure. No storage space available. + * + * @note Clear operations may take time. This API however, does not block until the clear + * procedure is complete. The application is notified of procedure completion using + * a notification callback registered by the application. The 'result' parameter of the + * callback indicates if the procedure was successful or not. + */ +uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size); + +/**@brief Function for getting the number of pending operations with the module. + * + * @param[out] p_count Number of storage operations pending with the module. If 0, there are no + * outstanding requests. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + */ +uint32_t pstorage_access_status_get(uint32_t * p_count); + +#ifdef PSTORAGE_RAW_MODE_ENABLE + +/**@brief Function for registering with the persistent storage interface. + * + * @param[in] p_module_param Module registration parameter. + * @param[out] p_block_id Block identifier used to identify persistent memory blocks upon + * successful registration. The application is expected to use the block + * IDs for subsequent operations on requested persistent memory. When + * more than one memory block is requested, this identifier is the base + * identifier for the first block and used to identify subsequent blocks. + * The application shall use \@ref pstorage_block_identifier_get with + * this base identifier and block number. Therefore if 10 blocks of size + * 64 are requested and the application wishes to store memory in the 6th + * block, it shall use \@ref pstorage_block_identifier_get with the base + * ID and provide a block number of 5. Therefore, the application is only + * expected to remember the base block identifier. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed. + * @retval NRF_ERROR_NO_MEM Operation failure. No storage space available. + */ +uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param, + pstorage_handle_t * p_block_id); + +/**@brief Function for persistently storing data of length 'size' contained in 'p_src' address in + * storage module at 'p_dest' address. Equivalent to Storage Write. + * + * @param[in] p_dest Destination address where data is to be stored persistently. + * @param[in] p_src Source address containing data to be stored. The API assumes this is resident + * memory and no intermediate copy of data is made by the API. Must be word + * aligned. + * @param[in] size Size of data to be stored expressed in bytes. Must be word aligned. + * @param[in] offset Offset in bytes to be applied when writing to the block. + * For example, if within a block of 100 bytes, the application wishes to + * write 20 bytes at an offset of 12 bytes, this field should be set to 12. + * Must be word aligned. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed. + * @retval NRF_ERROR_INVALID_ADDR Operation failure. Parameter is not aligned. + * @retval NRF_ERROR_NO_MEM Operation failure. No storage space available. + * + * @warning No copy of the data is made, meaning memory provided for data source that is to be + * written to flash cannot be freed or reused by the application until this procedure + * is complete. The application is notified when the procedure is finished using the + * notification callback registered by the application. + */ +uint32_t pstorage_raw_store(pstorage_handle_t * p_dest, + uint8_t * p_src, + pstorage_size_t size, + pstorage_size_t offset); + +/**@brief Function for clearing data in persistent memory in raw mode. + * + * @param[in] p_dest Base block identifier in persistent memory that needs to be cleared. + * Equivalent to an Erase Operation. + * @param[in] size Size of data to be cleared from persistent memory expressed in bytes. + * Not used. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INVALID_STATE Operation failure. API is called without module + * initialization. + * @retval NRF_ERROR_NULL Operation failure. NULL parameter has been passed. + * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed. + * @retval NRF_ERROR_NO_MEM Operation failure. No storage space available. + * + * @note Clear operations may take time. This API, however, does not block until the clear + * procedure is complete. The application is notified of procedure completion using + * a notification callback registered by the application. The 'result' parameter of the + * callback indicates if the procedure was successful or not. + */ +uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size); + +#endif // PSTORAGE_RAW_MODE_ENABLE + +/**@} */ +/**@} */ + +#endif // PSTORAGE_H__ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage_raw.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage_raw.c new file mode 100644 index 0000000..ac12f7c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/pstorage/pstorage_raw.c @@ -0,0 +1,471 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "pstorage.h" +#include +#include +#include "nordic_common.h" +#include "nrf_error.h" +#include "nrf_assert.h" +#include "nrf.h" +#include "nrf_soc.h" +#include "app_util.h" + +/** @file + * + * @defgroup persistent_storage_raw Persistent Storage Interface - Raw Mode Implementation + * @{ + * @ingroup persistent_storage + * @brief Persistent Storage Interface - Raw Mode Implementation. + * + * @details This file contains the source code for raw mode implementation of pstorage. + * It is intended for special use cases where flash size is critical or the application must have + * full control of the flash, such as DFU. The registration function in this implementation only + * allocates a module id for the queue but does not locate any flash pages for the registrant. + * This implementation provides no safety checking of addresses when clearing or storing data into + * flash. The application is responsible for handling flash addresses and care must therefore be + * taken in application not to erase application area. + * This implementation does not support the @ref pstorage_update function. + */ + +#define INVALID_OPCODE 0x00 /**< Invalid op code identifier. */ + +#ifdef NRF51 +#define SOC_MAX_WRITE_SIZE 1024 /**< Maximum write size allowed for a single call to \ref sd_flash_write as specified in the SoC API on the nRF51. */ +#elif NRF52 +#define SOC_MAX_WRITE_SIZE 4096 /**< Maximum write size allowed for a single call to \ref sd_flash_write as specified in the SoC API on the nRF52. */ +#else +#error No target defined +#endif + + +/** + * @brief Application registration information. + * + * @details Define application specific information that application needs to maintain to be able + * to process requests from each one of them. + */ +typedef struct +{ + pstorage_ntf_cb_t cb; /**< Callback registered with the module to be notified of result of flash access. */ +} pstorage_module_table_t; + + +/** + * @brief Defines command queue element. + * + * @details Defines command queue element. Each element encapsulates needed information to process + * a flash access command. + */ +typedef struct +{ + uint8_t op_code; /**< Identifies flash access operation being queued. Element is free is op-code is INVALID_OPCODE */ + pstorage_size_t size; /**< Identifies size in bytes requested for the operation. */ + pstorage_size_t offset; /**< Offset requested by the application for access operation. */ + pstorage_handle_t storage_addr; /**< Address/Identifier for persistent memory. */ + uint8_t * p_data_addr; /**< Address/Identifier for data memory. This is assumed to be resident memory. */ +} cmd_queue_element_t; + + +/** + * @brief Defines command queue, an element is free is op_code field is not invalid. + * + * @details Defines commands enqueued for flash access. At any point of time, this queue has one or + * more flash access operation pending if the count field is not zero. When the queue is + * not empty, the rp (read pointer) field points to the flash access command in progress + * or to requested next. The queue implements a simple first in first out algorithm. + * Data addresses are assumed to be resident. + */ +typedef struct +{ + uint8_t rp; /**< Read pointer, pointing to flash access that is ongoing or to be requested next. */ + uint8_t count; /**< Number of elements in the queue. */ + bool flash_access; /**< Flag to ensure an flash event received is for an request issued by the module. */ + cmd_queue_element_t cmd[PSTORAGE_CMD_QUEUE_SIZE]; /**< Array to maintain flash access operation details */ +}cmd_queue_t; + +static cmd_queue_t m_cmd_queue; /**< Flash operation request queue. */ +static pstorage_module_table_t m_app_table[PSTORAGE_NUM_OF_PAGES]; /**< Registered application information table. */ +static pstorage_size_t m_next_app_instance; /**< Points to the application module instance that can be allocated next */ +static pstorage_size_t m_round_val; /**< Round value for multiple round operations. For erase operations, the round value will contain current round counter which is identical to number of pages erased. For store operations, the round value contains current round of operation * SOC_MAX_WRITE_SIZE to ensure each store to the SoC Flash API is within the SoC limit. */ + +/** + * @brief Function for processing of commands and issuing flash access request to the SoftDevice. + * + * @return The return value received from SoftDevice. + */ +static uint32_t cmd_process(void); + + +/** + * @brief Function for notifying application of any errors. + * + * @param[in] result Result of event being notified. + * @param[in] p_elem Pointer to the element for which a notification should be given. + */ +static void app_notify(uint32_t result, cmd_queue_element_t * p_elem); + + +/** + * @defgroup utility_functions Utility internal functions. + * @{ + * @details Utility functions needed for interfacing with flash through SoC APIs. + * SoC APIs are non blocking and provide the result of flash access through an event. + * + * @note Only one flash access operation is permitted at a time by SoC. Hence a queue is + * maintained by this module. + */ + +/** + * @brief Function for initializing a command queue element. + * + * @param[in] index Index identifying element to be initialized. + */ +static void cmd_queue_element_init(uint32_t index) +{ + // Internal function and checks on range of index can be avoided + m_cmd_queue.cmd[index].op_code = INVALID_OPCODE; + m_cmd_queue.cmd[index].size = 0; + m_cmd_queue.cmd[index].storage_addr.module_id = PSTORAGE_NUM_OF_PAGES; + m_cmd_queue.cmd[index].storage_addr.block_id = 0; + m_cmd_queue.cmd[index].p_data_addr = NULL; + m_cmd_queue.cmd[index].offset = 0; +} + + +/** + * @brief Function for initializing the command queue. + */ +static void cmd_queue_init(void) +{ + uint32_t cmd_index; + + m_round_val = 0; + m_cmd_queue.rp = 0; + m_cmd_queue.count = 0; + m_cmd_queue.flash_access = false; + + for(cmd_index = 0; cmd_index < PSTORAGE_CMD_QUEUE_SIZE; cmd_index++) + { + cmd_queue_element_init(cmd_index); + } +} + + +/** + * @brief Function for enqueueing a flash access operation. + * + * @param[in] opcode Operation code for the command to queue. + * @param[in] p_storage_addr Pointer to the destination address. + * @param[in] p_data_addr Pointer to the source address containing the data. + * @param[in] size Size of data clear or write. + * @param[in] offset Offset to the address identified by the source data address. + * + * @retval NRF_SUCCESS If the enqueueing succeeded. + * @retval NRF_ERROR_NO_MEM In case the queue is full. + * @return Any error returned by the SoftDevice flash API. + */ +static uint32_t cmd_queue_enqueue(uint8_t opcode, + pstorage_handle_t * p_storage_addr, + uint8_t * p_data_addr, + pstorage_size_t size, + pstorage_size_t offset) +{ + uint32_t retval; + + if (m_cmd_queue.count != PSTORAGE_CMD_QUEUE_SIZE) + { + uint8_t write_index = m_cmd_queue.rp + m_cmd_queue.count; + + if (write_index >= PSTORAGE_CMD_QUEUE_SIZE) + { + write_index -= PSTORAGE_CMD_QUEUE_SIZE; + } + + m_cmd_queue.cmd[write_index].op_code = opcode; + m_cmd_queue.cmd[write_index].p_data_addr = p_data_addr; + m_cmd_queue.cmd[write_index].storage_addr = (*p_storage_addr); + m_cmd_queue.cmd[write_index].size = size; + m_cmd_queue.cmd[write_index].offset = offset; + retval = NRF_SUCCESS; + if (m_cmd_queue.flash_access == false) + { + retval = cmd_process(); + if (retval == NRF_ERROR_BUSY) + { + // In case of busy error code, it is possible to attempt to access flash. + retval = NRF_SUCCESS; + } + } + m_cmd_queue.count++; + } + else + { + retval = NRF_ERROR_NO_MEM; + } + + return retval; +} + + +/** + * @brief Function for dequeueing a command element. + * + * @retval NRF_SUCCESS If the dequeueing succeeded and next command was processed. + * @return Any error returned by the SoftDevice flash API. + */ +static uint32_t cmd_queue_dequeue(void) +{ + uint32_t retval = NRF_SUCCESS; + + // If any flash operation is enqueued, schedule + if ((m_cmd_queue.count > 0) && (m_cmd_queue.flash_access == false)) + { + retval = cmd_process(); + if (retval != NRF_SUCCESS) + { + // Flash could be accessed by other modules, hence a busy error is + // acceptable, but any other error needs to be indicated. + if (retval == NRF_ERROR_BUSY) + { + // In case of busy error code, it is possible to attempt to access flash. + retval = NRF_SUCCESS; + } + } + } + else + { + // No flash access request pending. + } + + return retval; +} + + +/** + * @brief Function for notifying application of any errors. + * + * @param[in] result Result of event being notified. + * @param[in] p_elem Pointer to the element for which a notification should be given. + */ +static void app_notify(uint32_t result, cmd_queue_element_t * p_elem) +{ + pstorage_ntf_cb_t ntf_cb; + uint8_t op_code = p_elem->op_code; + + ntf_cb = m_app_table[p_elem->storage_addr.module_id].cb; + + // Indicate result to client. + ntf_cb(&p_elem->storage_addr, + op_code, + result, + p_elem->p_data_addr, + p_elem->size); +} + + +/** + * @brief Function for handling of system events from SoftDevice. + * + * @param[in] sys_evt System event received. + */ +void pstorage_sys_event_handler(uint32_t sys_evt) +{ + uint32_t retval = NRF_SUCCESS; + + // The event shall only be processed if requested by this module. + if (m_cmd_queue.flash_access == true) + { + cmd_queue_element_t * p_cmd; + m_cmd_queue.flash_access = false; + switch (sys_evt) + { + case NRF_EVT_FLASH_OPERATION_SUCCESS: + { + p_cmd = &m_cmd_queue.cmd[m_cmd_queue.rp]; + m_round_val++; + + bool command_finished = ((m_round_val * SOC_MAX_WRITE_SIZE) >= p_cmd->size); + + if (command_finished) + { + uint8_t queue_rp = m_cmd_queue.rp; + + m_round_val = 0; + m_cmd_queue.count--; + m_cmd_queue.rp++; + + if (m_cmd_queue.rp >= PSTORAGE_CMD_QUEUE_SIZE) + { + m_cmd_queue.rp -= PSTORAGE_CMD_QUEUE_SIZE; + } + + app_notify(retval, &m_cmd_queue.cmd[queue_rp]); + + // Initialize/free the element as it is now processed. + cmd_queue_element_init(queue_rp); + } + // Schedule any queued flash access operations. + retval = cmd_queue_dequeue(); + if (retval != NRF_SUCCESS) + { + app_notify(retval, &m_cmd_queue.cmd[m_cmd_queue.rp]); + } + } + break; + + case NRF_EVT_FLASH_OPERATION_ERROR: + app_notify(NRF_ERROR_TIMEOUT, &m_cmd_queue.cmd[m_cmd_queue.rp]); + break; + + default: + // No implementation needed. + break; + } + } +} + + +/** + * @brief Function for processing of commands and issuing flash access request to the SoftDevice. + * + * @return The return value received from SoftDevice. + */ +static uint32_t cmd_process(void) +{ + uint32_t retval; + uint32_t storage_addr; + cmd_queue_element_t * p_cmd; + + retval = NRF_ERROR_FORBIDDEN; + + p_cmd = &m_cmd_queue.cmd[m_cmd_queue.rp]; + + storage_addr = p_cmd->storage_addr.block_id; + + switch (p_cmd->op_code) + { + case PSTORAGE_STORE_OP_CODE: + { + uint32_t size; + uint32_t offset; + uint8_t * p_data_addr = p_cmd->p_data_addr; + + offset = (m_round_val * SOC_MAX_WRITE_SIZE); + size = p_cmd->size - offset; + p_data_addr += offset; + storage_addr += (p_cmd->offset + offset); + + if (size < SOC_MAX_WRITE_SIZE) + { + retval = sd_flash_write(((uint32_t *)storage_addr), + (uint32_t *)p_data_addr, + size / sizeof(uint32_t)); + } + else + { + retval = sd_flash_write(((uint32_t *)storage_addr), + (uint32_t *)p_data_addr, + SOC_MAX_WRITE_SIZE / sizeof(uint32_t)); + } + } + break; + + case PSTORAGE_CLEAR_OP_CODE: + { + uint32_t page_number; + + page_number = ((storage_addr / PSTORAGE_FLASH_PAGE_SIZE) + + m_round_val); + + retval = sd_flash_page_erase(page_number); + } + break; + + default: + // Should never reach here. + break; + } + + if (retval == NRF_SUCCESS) + { + m_cmd_queue.flash_access = true; + } + + return retval; +} +/** @} */ + + +uint32_t pstorage_init(void) +{ + cmd_queue_init(); + + m_next_app_instance = 0; + m_round_val = 0; + + for(unsigned int index = 0; index < PSTORAGE_NUM_OF_PAGES; index++) + { + m_app_table[index].cb = NULL; + } + + return NRF_SUCCESS; +} + + +uint32_t pstorage_register(pstorage_module_param_t * p_module_param, + pstorage_handle_t * p_block_id) +{ + if (m_next_app_instance == PSTORAGE_NUM_OF_PAGES) + { + return NRF_ERROR_NO_MEM; + } + + p_block_id->module_id = m_next_app_instance; + m_app_table[m_next_app_instance++].cb = p_module_param->cb; + + return NRF_SUCCESS; +} + + +uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id, + pstorage_size_t block_num, + pstorage_handle_t * p_block_id) +{ + return NRF_ERROR_NOT_SUPPORTED; +} + + +uint32_t pstorage_store(pstorage_handle_t * p_dest, + uint8_t * p_src, + pstorage_size_t size, + pstorage_size_t offset) +{ + // Verify word alignment. + if ((!is_word_aligned(p_src)) || (!is_word_aligned(p_src+offset))) + { + return NRF_ERROR_INVALID_ADDR; + } + + return cmd_queue_enqueue(PSTORAGE_STORE_OP_CODE, p_dest, p_src, size, offset); +} + + +uint32_t pstorage_clear(pstorage_handle_t * p_dest, pstorage_size_t size) +{ + return cmd_queue_enqueue(PSTORAGE_CLEAR_OP_CODE, p_dest, NULL , size, 0); +} + + +/** + * @} + */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.c new file mode 100644 index 0000000..1cbb846 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.c @@ -0,0 +1,280 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "nrf_drv_timer.h" +#include "nrf_drv_common.h" +#include "app_util_platform.h" + +#if (TIMER_COUNT == 0) + #error "No TIMER instances enabled in the driver configuration file." +#endif + + +/**@brief Timer control block. */ +typedef struct +{ + nrf_timer_event_handler_t handler; + void * context; + nrf_drv_state_t state; +} timer_control_block_t; + +static timer_control_block_t m_cb[TIMER_COUNT]; + +static const nrf_drv_timer_config_t m_default_config[TIMER_COUNT] = { +#if TIMER0_ENABLED + NRF_DRV_TIMER_DEFAULT_CONFIG(0), +#endif +#if TIMER1_ENABLED + NRF_DRV_TIMER_DEFAULT_CONFIG(1), +#endif +#if TIMER2_ENABLED + NRF_DRV_TIMER_DEFAULT_CONFIG(2), +#endif +#if TIMER3_ENABLED + NRF_DRV_TIMER_DEFAULT_CONFIG(3), +#endif +#if TIMER4_ENABLED + NRF_DRV_TIMER_DEFAULT_CONFIG(4), +#endif +}; + + +ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance, + nrf_drv_timer_config_t const * p_config, + nrf_timer_event_handler_t timer_event_handler) +{ + timer_control_block_t * p_cb = &m_cb[p_instance->instance_id]; + +#ifdef SOFTDEVICE_PRESENT + ASSERT(p_instance->p_reg != NRF_TIMER0); +#endif + ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width)); + + if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED) + { + return NRF_ERROR_INVALID_STATE; + } + + if (timer_event_handler == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + + if (p_config == NULL) + { + p_config = &m_default_config[p_instance->instance_id]; + } + + p_cb->handler = timer_event_handler; + p_cb->context = p_config->p_context; + + uint8_t i; + for (i = 0; i < p_instance->cc_channel_count; ++i) + { + nrf_timer_event_clear(p_instance->p_reg, + nrf_timer_compare_event_get(i)); + } + + nrf_drv_common_irq_enable(nrf_drv_get_IRQn(p_instance->p_reg), + p_config->interrupt_priority); + + nrf_timer_mode_set(p_instance->p_reg, p_config->mode); + nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width); + nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency); + + p_cb->state = NRF_DRV_STATE_INITIALIZED; + + return NRF_SUCCESS; +} + +void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance) +{ + nrf_drv_common_irq_disable(nrf_drv_get_IRQn(p_instance->p_reg)); + + #define DISABLE_ALL UINT32_MAX + nrf_timer_shorts_disable(p_instance->p_reg, DISABLE_ALL); + nrf_timer_int_disable(p_instance->p_reg, DISABLE_ALL); + #undef DISABLE_ALL + + nrf_drv_timer_disable(p_instance); + + m_cb[p_instance->instance_id].state = NRF_DRV_STATE_UNINITIALIZED; +} + +void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance) +{ + ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_INITIALIZED); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START); + m_cb[p_instance->instance_id].state = NRF_DRV_STATE_POWERED_ON; +} + +void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance) +{ + ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_SHUTDOWN); + m_cb[p_instance->instance_id].state = NRF_DRV_STATE_INITIALIZED; +} + +void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance) +{ + ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START); +} + +void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance) +{ + ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_STOP); +} + +void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance) +{ + ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_CLEAR); +} + +void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance) +{ + ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON); + ASSERT(nrf_timer_mode_get(p_instance->p_reg) != NRF_TIMER_MODE_TIMER); + + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_COUNT); +} + +uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel) +{ + ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON); + ASSERT(cc_channel < p_instance->cc_channel_count); + + nrf_timer_task_trigger(p_instance->p_reg, + nrf_timer_capture_task_get(cc_channel)); + return nrf_timer_cc_read(p_instance->p_reg, cc_channel); +} + +void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + bool enable_int) +{ + nrf_timer_int_mask_t timer_int = nrf_timer_compare_int_get(cc_channel); + + if (enable_int) + { + nrf_timer_int_enable(p_instance->p_reg, timer_int); + } + else + { + nrf_timer_int_disable(p_instance->p_reg, timer_int); + } + + nrf_timer_cc_write(p_instance->p_reg, cc_channel, cc_value); +} + +void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + nrf_timer_short_mask_t timer_short_mask, + bool enable_int) +{ + nrf_timer_shorts_disable(p_instance->p_reg, + (TIMER_SHORTS_COMPARE0_STOP_Msk << cc_channel) | + (TIMER_SHORTS_COMPARE0_CLEAR_Msk << cc_channel)); + + nrf_timer_shorts_enable(p_instance->p_reg, timer_short_mask); + + (void)nrf_drv_timer_compare(p_instance, + cc_channel, + cc_value, + enable_int); +} + +void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance, + uint32_t channel) +{ + ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED); + ASSERT(channel < p_instance->cc_channel_count); + + nrf_timer_event_clear(p_instance->p_reg, + nrf_timer_compare_event_get(channel)); + nrf_timer_int_enable(p_instance->p_reg, + nrf_timer_compare_int_get(channel)); +} + +void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance, + uint32_t channel) +{ + ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED); + ASSERT(channel < p_instance->cc_channel_count); + + nrf_timer_int_disable(p_instance->p_reg, + nrf_timer_compare_int_get(channel)); +} + +static void irq_handler(NRF_TIMER_Type * p_reg, + timer_control_block_t * p_cb, + uint8_t channel_count) +{ + uint8_t i; + for (i = 0; i < channel_count; ++i) + { + nrf_timer_event_t event = nrf_timer_compare_event_get(i); + nrf_timer_int_mask_t int_mask = nrf_timer_compare_int_get(i); + + if (nrf_timer_event_check(p_reg, event) && + nrf_timer_int_enable_check(p_reg, int_mask)) + { + nrf_timer_event_clear(p_reg, event); + p_cb->handler(event, p_cb->context); + } + } +} + +#if TIMER0_ENABLED +void TIMER0_IRQHandler(void) +{ + irq_handler(NRF_TIMER0, &m_cb[TIMER0_INSTANCE_INDEX], + NRF_TIMER_CC_CHANNEL_COUNT(0)); +} +#endif + +#if TIMER1_ENABLED +void TIMER1_IRQHandler(void) +{ + irq_handler(NRF_TIMER1, &m_cb[TIMER1_INSTANCE_INDEX], + NRF_TIMER_CC_CHANNEL_COUNT(1)); +} +#endif + +#if TIMER2_ENABLED +void TIMER2_IRQHandler(void) +{ + irq_handler(NRF_TIMER2, &m_cb[TIMER2_INSTANCE_INDEX], + NRF_TIMER_CC_CHANNEL_COUNT(2)); +} +#endif + +#if TIMER3_ENABLED +void TIMER3_IRQHandler(void) +{ + irq_handler(NRF_TIMER3, &m_cb[TIMER3_INSTANCE_INDEX], + NRF_TIMER_CC_CHANNEL_COUNT(3)); +} +#endif + +#if TIMER4_ENABLED +void TIMER4_IRQHandler(void) +{ + irq_handler(NRF_TIMER4, &m_cb[TIMER4_INSTANCE_INDEX], + NRF_TIMER_CC_CHANNEL_COUNT(4)); +} +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.h new file mode 100644 index 0000000..6aa10ca --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/timer/nrf_drv_timer.h @@ -0,0 +1,372 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * @addtogroup nrf_timer Timer HAL and driver + * @ingroup nrf_drivers + * @brief Timer APIs. + * @details The timer HAL provides basic APIs for accessing the registers + * of the timer. The timer driver provides APIs on a higher level. + * + * @defgroup lib_driver_timer Timer driver + * @{ + * @ingroup nrf_timer + * @brief Multi-instance timer driver. + */ + +#ifndef NRF_DRV_TIMER_H__ +#define NRF_DRV_TIMER_H__ + +#include "nordic_common.h" +#include "nrf_drv_config.h" +#include "nrf_timer.h" +#include "sdk_errors.h" +#include "nrf_assert.h" + +/** + * @brief Timer driver instance data structure. + */ +typedef struct +{ + NRF_TIMER_Type * p_reg; ///< Pointer to the structure with TIMER peripheral instance registers. + uint8_t instance_id; ///< Driver instance index. + uint8_t cc_channel_count; ///< Number of capture/compare channels. +} nrf_drv_timer_t; + +/** + * @brief Macro for creating a timer driver instance. + */ +#define NRF_DRV_TIMER_INSTANCE(id) \ +{ \ + .p_reg = CONCAT_2(NRF_TIMER, id), \ + .instance_id = CONCAT_3(TIMER, id, _INSTANCE_INDEX), \ + .cc_channel_count = NRF_TIMER_CC_CHANNEL_COUNT(id), \ +} + +/** + * @brief Timer driver instance configuration structure. + */ +typedef struct +{ + nrf_timer_frequency_t frequency; ///< Frequency. + nrf_timer_mode_t mode; ///< Mode of operation. + nrf_timer_bit_width_t bit_width; ///< Bit width. + uint8_t interrupt_priority; ///< Interrupt priority. + void * p_context; ///< Context passed to interrupt handler. +} nrf_drv_timer_config_t; + +#define TIMER_CONFIG_FREQUENCY(id) CONCAT_3(TIMER, id, _CONFIG_FREQUENCY) +#define TIMER_CONFIG_MODE(id) CONCAT_3(TIMER, id, _CONFIG_MODE) +#define TIMER_CONFIG_BIT_WIDTH(id) CONCAT_3(TIMER, id, _CONFIG_BIT_WIDTH) +#define TIMER_CONFIG_IRQ_PRIORITY(id) CONCAT_3(TIMER, id, _CONFIG_IRQ_PRIORITY) + +/** + * @brief Timer driver instance default configuration. + */ +#define NRF_DRV_TIMER_DEFAULT_CONFIG(id) \ +{ \ + .frequency = TIMER_CONFIG_FREQUENCY(id), \ + .mode = (nrf_timer_mode_t)TIMER_CONFIG_MODE(id), \ + .bit_width = (nrf_timer_bit_width_t)TIMER_CONFIG_BIT_WIDTH(id), \ + .interrupt_priority = TIMER_CONFIG_IRQ_PRIORITY(id), \ + .p_context = NULL \ +} + +/** + * @brief Timer driver event handler type. + * + * @param[in] event_type Timer event. + * @param[in] p_context General purpose parameter set during initialization of + * the timer. This parameter can be used to pass + * additional information to the handler function, for + * example, the timer ID. + */ +typedef void (* nrf_timer_event_handler_t)(nrf_timer_event_t event_type, + void * p_context); + +/** + * @brief Function for initializing the timer. + * + * @param[in] p_instance Timer instance. + * @param[in] p_config Initial configuration. + * If NULL, the default configuration is used. + * @param[in] timer_event_handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_INVALID_STATE If the instance is already initialized. + * @retval NRF_ERROR_INVALID_PARAM If no handler was provided. + */ +ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance, + nrf_drv_timer_config_t const * p_config, + nrf_timer_event_handler_t timer_event_handler); + +/** + * @brief Function for uninitializing the timer. + * + * @param[in] p_instance Timer instance. + */ +void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance); + +/** + * @brief Function for turning on the timer. + * + * @param[in] p_instance Timer instance. + */ +void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance); + +/** + * @brief Function for turning off the timer. + * + * Note that the timer will allow to enter the lowest possible SYSTEM_ON state + * only after this function is called. + * + * @param[in] p_instance Timer instance. + */ +void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance); + +/** + * @brief Function for pausing the timer. + * + * @param[in] p_instance Timer instance. + */ +void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance); + +/** + * @brief Function for resuming the timer. + * + * @param[in] p_instance Timer instance. + */ +void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance); + +/** + * @brief Function for clearing the timer. + * + * @param[in] p_instance Timer instance. + */ +void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance); + +/** + * @brief Function for incrementing the timer. + * + * @param[in] p_instance Timer instance. + */ +void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance); + +/** + * @brief Function for returning the address of a specific timer task. + * + * @param[in] p_instance Timer instance. + * @param[in] timer_task Timer task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get( + nrf_drv_timer_t const * const p_instance, + nrf_timer_task_t timer_task); + +/** + * @brief Function for returning the address of a specific timer capture task. + * + * @param[in] p_instance Timer instance. + * @param[in] channel Capture channel number. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get( + nrf_drv_timer_t const * const p_instance, + uint32_t channel); + +/** + * @brief Function for returning the address of a specific timer event. + * + * @param[in] p_instance Timer instance. + * @param[in] timer_event Timer event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get( + nrf_drv_timer_t const * const p_instance, + nrf_timer_event_t timer_event); + +/** + * @brief Function for returning the address of a specific timer compare event. + * + * @param[in] p_instance Timer instance. + * @param[in] channel Compare channel number. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get( + nrf_drv_timer_t const * const p_instance, + uint32_t channel); + +/** + * @brief Function for capturing the timer value. + * + * @param[in] p_instance Timer instance. + * @param[in] cc_channel Capture channel number. + * + * @return Captured value. + */ +uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel); + +/** + * @brief Function for returning the capture value from a specific channel. + * + * Use this function to read channel values when PPI is used for capturing. + * + * @param[in] p_instance Timer instance. + * @param[in] cc_channel Capture channel number. + * + * @return Captured value. + */ +__STATIC_INLINE uint32_t nrf_drv_timer_capture_get( + nrf_drv_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel); + +/** + * @brief Function for setting the timer channel in compare mode. + * + * @param[in] p_instance Timer instance. + * @param[in] cc_channel Compare channel number. + * @param[in] cc_value Compare value. + * @param[in] enable_int Enable or disable the interrupt for the compare channel. + */ +void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + bool enable_int); + +/** + * @brief Function for setting the timer channel in extended compare mode. + * + * @param[in] p_instance Timer instance. + * @param[in] cc_channel Compare channel number. + * @param[in] cc_value Compare value. + * @param[in] timer_short_mask Shortcut between the compare event on the channel + * and the timer task (STOP or CLEAR). + * @param[in] enable_int Enable or disable the interrupt for the compare + * channel. + */ +void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + nrf_timer_short_mask_t timer_short_mask, + bool enable_int); + +/** + * @brief Function for converting time in microseconds to timer ticks. + * + * @param[in] p_instance Timer instance. + * @param[in] time_us Time in microseconds. + * + * @return Number of ticks. + */ +__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks( + nrf_drv_timer_t const * const p_instance, + uint32_t time_us); + +/** + * @brief Function for converting time in milliseconds to timer ticks. + * + * @param[in] p_instance Timer instance. + * @param[in] time_ms Time in milliseconds. + * + * @return Number of ticks. + */ +__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks( + nrf_drv_timer_t const * const p_instance, + uint32_t time_ms); + +/** + * @brief Function for enabling timer compare interrupt. + * + * @param[in] p_instance Timer instance. + * @param[in] channel Compare channel. + */ +void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance, + uint32_t channel); + +/** + * @brief Function for disabling timer compare interrupt. + * + * @param[in] p_instance Timer instance. + * @param[in] channel Compare channel. + */ +void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance, + uint32_t channel); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get( + nrf_drv_timer_t const * const p_instance, + nrf_timer_task_t timer_task) +{ + return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, timer_task); +} + +__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get( + nrf_drv_timer_t const * const p_instance, + uint32_t channel) +{ + ASSERT(channel < p_instance->cc_channel_count); + return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, + nrf_timer_capture_task_get(channel)); +} + +__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get( + nrf_drv_timer_t const * const p_instance, + nrf_timer_event_t timer_event) +{ + return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, timer_event); +} + +__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get( + nrf_drv_timer_t const * const p_instance, + uint32_t channel) +{ + ASSERT(channel < p_instance->cc_channel_count); + return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, + nrf_timer_compare_event_get(channel)); +} + +__STATIC_INLINE uint32_t nrf_drv_timer_capture_get( + nrf_drv_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel) +{ + return nrf_timer_cc_read(p_instance->p_reg, cc_channel); +} + +__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks( + nrf_drv_timer_t const * const p_instance, + uint32_t timer_us) +{ + return nrf_timer_us_to_ticks(timer_us, + nrf_timer_frequency_get(p_instance->p_reg)); +} + +__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks( + nrf_drv_timer_t const * const p_instance, + uint32_t timer_ms) +{ + return nrf_timer_ms_to_ticks(timer_ms, + nrf_timer_frequency_get(p_instance->p_reg)); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRF_DRV_TIMER_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.c new file mode 100644 index 0000000..845b919 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.c @@ -0,0 +1,851 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "nrf_drv_uart.h" +#include "nrf_assert.h" +#include "nordic_common.h" +#include "nrf_drv_common.h" +#include "nrf_gpio.h" +#include "app_util_platform.h" + +// This set of macros makes it possible to exclude parts of code, when one type +// of supported peripherals is not used. +#ifdef NRF51 +#define UART_IN_USE +#elif defined(NRF52) +#if (UART_EASY_DMA_SUPPORT == 1) +#define UARTE_IN_USE +#endif +#if (UART_LEGACY_SUPPORT == 1) +#define UART_IN_USE +#endif +#endif + + +#if (defined(UARTE_IN_USE) && defined(UART_IN_USE)) + // UARTE and UART combined + #define CODE_FOR_UARTE(code) if (m_cb.use_easy_dma) { code } + #define CODE_FOR_UART(code) else { code } +#elif (defined(UARTE_IN_USE) && !defined(UART_IN_USE)) + // UARTE only + #define CODE_FOR_UARTE(code) { code } + #define CODE_FOR_UART(code) +#elif (!defined(UARTE_IN_USE) && defined(UART_IN_USE)) + // UART only + #define CODE_FOR_UARTE(code) + #define CODE_FOR_UART(code) { code } +#else + #error "Wrong configuration." +#endif + +#ifndef IS_EASY_DMA_RAM_ADDRESS + #define IS_EASY_DMA_RAM_ADDRESS(addr) (((uint32_t)addr & 0xFFFF0000) == 0x20000000) +#endif + +#define TX_COUNTER_ABORT_REQ_VALUE 256 + +typedef struct +{ + void * p_context; + nrf_uart_event_handler_t handler; + uint8_t const * p_tx_buffer; + uint8_t * p_rx_buffer; + uint8_t * p_rx_secondary_buffer; + volatile uint16_t tx_counter; + uint8_t tx_buffer_length; + uint8_t rx_buffer_length; + uint8_t rx_secondary_buffer_length; + volatile uint8_t rx_counter; + bool rx_enabled; + nrf_drv_state_t state; +#if (defined(UARTE_IN_USE) && defined(UART_IN_USE)) + bool use_easy_dma; +#endif +} uart_control_block_t; + +static uart_control_block_t m_cb; +static const nrf_drv_uart_config_t m_default_config = NRF_DRV_UART_DEFAULT_CONFIG; + +__STATIC_INLINE void apply_config(nrf_drv_uart_config_t const * p_config) +{ + nrf_gpio_pin_set(p_config->pseltxd); + nrf_gpio_cfg_output(p_config->pseltxd); + nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL); + + CODE_FOR_UARTE + ( + nrf_uarte_baudrate_set(NRF_UARTE0, (nrf_uarte_baudrate_t)p_config->baudrate); + nrf_uarte_configure(NRF_UARTE0, (nrf_uarte_parity_t)p_config->parity, + (nrf_uarte_hwfc_t)p_config->hwfc); + nrf_uarte_txrx_pins_set(NRF_UARTE0, p_config->pseltxd, p_config->pselrxd); + if (p_config->hwfc == NRF_UART_HWFC_ENABLED) + { + nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); + nrf_gpio_pin_set(p_config->pselrts); + nrf_gpio_cfg_output(p_config->pselrts); + nrf_uarte_hwfc_pins_set(NRF_UARTE0, p_config->pselrts, p_config->pselcts); + } + ) + CODE_FOR_UART + ( + nrf_uart_baudrate_set(NRF_UART0, p_config->baudrate); + nrf_uart_configure(NRF_UART0, p_config->parity, p_config->hwfc); + nrf_uart_txrx_pins_set(NRF_UART0, p_config->pseltxd, p_config->pselrxd); + if (p_config->hwfc == NRF_UART_HWFC_ENABLED) + { + nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); + nrf_gpio_pin_set(p_config->pselrts); + nrf_gpio_cfg_output(p_config->pselrts); + nrf_uart_hwfc_pins_set(NRF_UART0, p_config->pselrts, p_config->pselcts); + } + ) +} + +__STATIC_INLINE void interrupts_enable(uint8_t interrupt_priority) +{ + CODE_FOR_UARTE + ( + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX); + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX); + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ERROR); + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_RXTO); + nrf_uarte_int_enable(NRF_UARTE0, NRF_UARTE_INT_ENDRX_MASK | + NRF_UARTE_INT_ENDTX_MASK | + NRF_UARTE_INT_ERROR_MASK | + NRF_UARTE_INT_RXTO_MASK); + ) + CODE_FOR_UART + ( + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY); + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXTO); + nrf_uart_int_enable(NRF_UART0, NRF_UART_INT_MASK_TXDRDY | + NRF_UART_INT_MASK_RXTO); + ) + nrf_drv_common_irq_enable(UART0_IRQn, interrupt_priority); +} + +__STATIC_INLINE void interrupts_disable(void) +{ + CODE_FOR_UARTE + ( + nrf_uarte_int_disable(NRF_UARTE0, NRF_UARTE_INT_ENDRX_MASK | + NRF_UARTE_INT_ENDTX_MASK | + NRF_UARTE_INT_ERROR_MASK | + NRF_UARTE_INT_RXTO_MASK); + ) + CODE_FOR_UART + ( + nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | + NRF_UART_INT_MASK_TXDRDY | + NRF_UART_INT_MASK_ERROR | + NRF_UART_INT_MASK_RXTO); + ) + nrf_drv_common_irq_disable(UART0_IRQn); +} + +__STATIC_INLINE void pins_to_default(void) +{ + /* Reset pins to default states */ + uint32_t txd; + uint32_t rxd; + uint32_t rts; + uint32_t cts; + + CODE_FOR_UARTE + ( + txd = nrf_uarte_tx_pin_get(NRF_UARTE0); + rxd = nrf_uarte_rx_pin_get(NRF_UARTE0); + rts = nrf_uarte_rts_pin_get(NRF_UARTE0); + cts = nrf_uarte_cts_pin_get(NRF_UARTE0); + nrf_uarte_txrx_pins_disconnect(NRF_UARTE0); + nrf_uarte_hwfc_pins_disconnect(NRF_UARTE0); + ) + CODE_FOR_UART + ( + txd = nrf_uart_tx_pin_get(NRF_UART0); + rxd = nrf_uart_rx_pin_get(NRF_UART0); + rts = nrf_uart_rts_pin_get(NRF_UART0); + cts = nrf_uart_cts_pin_get(NRF_UART0); + nrf_uart_txrx_pins_disconnect(NRF_UART0); + nrf_uart_hwfc_pins_disconnect(NRF_UART0); + ) + + nrf_gpio_cfg_default(txd); + nrf_gpio_cfg_default(rxd); + + if (cts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(cts); + } + + if (rts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(rts); + } + +} + +__STATIC_INLINE void uart_enable(void) +{ + CODE_FOR_UARTE(nrf_uarte_enable(NRF_UARTE0);) + CODE_FOR_UART(nrf_uart_enable(NRF_UART0);); +} + +__STATIC_INLINE void uart_disable(void) +{ + CODE_FOR_UARTE(nrf_uarte_disable(NRF_UARTE0);) + CODE_FOR_UART(nrf_uart_disable(NRF_UART0);); +} + +ret_code_t nrf_drv_uart_init(nrf_drv_uart_config_t const * p_config, + nrf_uart_event_handler_t event_handler) +{ + if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED) + { + return NRF_ERROR_INVALID_STATE; + } + + if (p_config == NULL) + { + p_config = &m_default_config; + } +#if (defined(UARTE_IN_USE) && defined(UART_IN_USE)) + m_cb.use_easy_dma = p_config->use_easy_dma; +#endif + apply_config(p_config); + + m_cb.handler = event_handler; + m_cb.p_context = p_config->p_context; + + if (m_cb.handler) + { + interrupts_enable(p_config->interrupt_priority); + } + + uart_enable(); + m_cb.rx_buffer_length = 0; + m_cb.rx_secondary_buffer_length = 0; + m_cb.tx_buffer_length = 0; + m_cb.state = NRF_DRV_STATE_INITIALIZED; + m_cb.rx_enabled = false; + return NRF_SUCCESS; +} + +void nrf_drv_uart_uninit(void) +{ + uart_disable(); + + if (m_cb.handler) + { + interrupts_disable(); + } + + pins_to_default(); + + m_cb.state = NRF_DRV_STATE_UNINITIALIZED; + m_cb.handler = NULL; +} + +#if defined(UART_IN_USE) +__STATIC_INLINE void tx_byte(void) +{ + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY); + uint8_t txd = m_cb.p_tx_buffer[m_cb.tx_counter]; + m_cb.tx_counter++; + nrf_uart_txd_set(NRF_UART0, txd); +} + +__STATIC_INLINE ret_code_t nrf_drv_uart_tx_for_uart() +{ + ret_code_t err_code = NRF_SUCCESS; + + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY); + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTTX); + + tx_byte(); + + if (m_cb.handler == NULL) + { + while (m_cb.tx_counter < (uint16_t) m_cb.tx_buffer_length) + { + while (!nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_TXDRDY) && + m_cb.tx_counter != TX_COUNTER_ABORT_REQ_VALUE) + { + } + if (m_cb.tx_counter != TX_COUNTER_ABORT_REQ_VALUE) + { + tx_byte(); + } + } + + if (m_cb.tx_counter == TX_COUNTER_ABORT_REQ_VALUE) + { + err_code = NRF_ERROR_FORBIDDEN; + } + else + { + while (!nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_TXDRDY)) + { + } + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPTX); + } + m_cb.tx_buffer_length = 0; + } + + return err_code; +} +#endif + +#if defined(UARTE_IN_USE) +__STATIC_INLINE ret_code_t nrf_drv_uart_tx_for_uarte() +{ + ret_code_t err_code = NRF_SUCCESS; + + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX); + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_TXSTOPPED); + nrf_uarte_tx_buffer_set(NRF_UARTE0, m_cb.p_tx_buffer, m_cb.tx_buffer_length); + nrf_uarte_task_trigger(NRF_UARTE0, NRF_UARTE_TASK_STARTTX); + + if (m_cb.handler == NULL) + { + bool endtx; + bool txstopped; + do + { + endtx = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX); + txstopped = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_TXSTOPPED); + } + while ((!endtx) && (!txstopped)); + + if (txstopped) + { + err_code = NRF_ERROR_FORBIDDEN; + } + m_cb.tx_buffer_length = 0; + } + + return err_code; +} +#endif + +ret_code_t nrf_drv_uart_tx(uint8_t const * const p_data, uint8_t length) +{ + ASSERT(m_cb.state == NRF_DRV_STATE_INITIALIZED); + ASSERT(length>0); + ASSERT(p_data); + + CODE_FOR_UARTE + ( + // EasyDMA requires that transfer buffers are placed in DataRAM, + // signal error if the are not. + if (!IS_EASY_DMA_RAM_ADDRESS(p_data)) + { + return NRF_ERROR_INVALID_ADDR; + } + ) + + if (nrf_drv_uart_tx_in_progress()) + { + return NRF_ERROR_BUSY; + } + m_cb.tx_buffer_length = length; + m_cb.p_tx_buffer = p_data; + m_cb.tx_counter = 0; + + CODE_FOR_UARTE + ( + return nrf_drv_uart_tx_for_uarte(); + ) + CODE_FOR_UART + ( + return nrf_drv_uart_tx_for_uart(); + ) +} + +bool nrf_drv_uart_tx_in_progress(void) +{ + return (m_cb.tx_buffer_length != 0); +} + +#if defined(UART_IN_USE) +__STATIC_INLINE void rx_enable(void) +{ + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_ERROR); + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXDRDY); + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTRX); +} + +__STATIC_INLINE void rx_byte(void) +{ + if (!m_cb.rx_buffer_length) + { + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXDRDY); + // Byte received when buffer is not set - data lost. + (void) nrf_uart_rxd_get(NRF_UART0); + return; + } + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXDRDY); + m_cb.p_rx_buffer[m_cb.rx_counter] = nrf_uart_rxd_get(NRF_UART0); + m_cb.rx_counter++; +} + +__STATIC_INLINE ret_code_t nrf_drv_uart_rx_for_uart(uint8_t * p_data, uint8_t length, bool second_buffer) +{ + if ((!m_cb.rx_enabled) && (!second_buffer)) + { + rx_enable(); + } + if (m_cb.handler == NULL) + { + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXTO); + + bool rxrdy; + bool rxto; + bool error; + do + { + do + { + error = nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_ERROR); + rxrdy = nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_RXDRDY); + rxto = nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_RXTO); + } while ((!rxrdy) && (!rxto) && (!error)); + + if (error || rxto) + { + break; + } + rx_byte(); + } while (m_cb.rx_buffer_length > m_cb.rx_counter); + + m_cb.rx_buffer_length = 0; + if (error) + { + return NRF_ERROR_INTERNAL; + } + + if (rxto) + { + return NRF_ERROR_FORBIDDEN; + } + + if (m_cb.rx_enabled) + { + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTRX); + } + else + { + // Skip stopping RX if driver is forced to be enabled. + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX); + } + } + else + { + nrf_uart_int_enable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR); + } + return NRF_SUCCESS; +} +#endif + +#if defined(UARTE_IN_USE) +__STATIC_INLINE ret_code_t nrf_drv_uart_rx_for_uarte(uint8_t * p_data, uint8_t length, bool second_buffer) +{ + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX); + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_RXTO); + nrf_uarte_rx_buffer_set(NRF_UARTE0, p_data, length); + if (!second_buffer) + { + nrf_uarte_task_trigger(NRF_UARTE0, NRF_UARTE_TASK_STARTRX); + } + else + { + nrf_uarte_shorts_enable(NRF_UARTE0, NRF_UARTE_SHORT_ENDRX_STARTRX); + } + + if (m_cb.handler == NULL) + { + bool endrx; + bool rxto; + bool error; + do { + endrx = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX); + rxto = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_RXTO); + error = nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ERROR); + }while ((!endrx) && (!rxto) && (!error)); + + m_cb.rx_buffer_length = 0; + + if (error) + { + return NRF_ERROR_INTERNAL; + } + + if (rxto) + { + return NRF_ERROR_FORBIDDEN; + } + } + else + { + nrf_uarte_int_enable(NRF_UARTE0, NRF_UARTE_INT_ERROR_MASK | NRF_UARTE_INT_ENDRX_MASK); + } + return NRF_SUCCESS; +} +#endif + +ret_code_t nrf_drv_uart_rx(uint8_t * p_data, uint8_t length) +{ + ASSERT(m_cb.state == NRF_DRV_STATE_INITIALIZED); + ASSERT(length>0); + + CODE_FOR_UARTE + ( + // EasyDMA requires that transfer buffers are placed in DataRAM, + // signal error if the are not. + if (!IS_EASY_DMA_RAM_ADDRESS(p_data)) + { + return NRF_ERROR_INVALID_ADDR; + } + ) + + bool second_buffer = false; + + if (m_cb.handler) + { + CODE_FOR_UARTE + ( + nrf_uarte_int_disable(NRF_UARTE0, NRF_UARTE_INT_ERROR_MASK | NRF_UARTE_INT_ENDRX_MASK); + ) + CODE_FOR_UART + ( + nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR); + ) + } + if (m_cb.rx_buffer_length != 0) + { + if (m_cb.rx_secondary_buffer_length != 0) + { + if (m_cb.handler) + { + CODE_FOR_UARTE + ( + nrf_uarte_int_enable(NRF_UARTE0, NRF_UARTE_INT_ERROR_MASK | NRF_UARTE_INT_ENDRX_MASK); + ) + CODE_FOR_UART + ( + nrf_uart_int_enable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR); + ) + } + return NRF_ERROR_BUSY; + } + second_buffer = true; + } + + if (!second_buffer) + { + m_cb.rx_buffer_length = length; + m_cb.p_rx_buffer = p_data; + m_cb.rx_counter = 0; + m_cb.rx_secondary_buffer_length = 0; + } + else + { + m_cb.p_rx_secondary_buffer = p_data; + m_cb.rx_secondary_buffer_length = length; + } + + CODE_FOR_UARTE + ( + return nrf_drv_uart_rx_for_uarte(p_data, length, second_buffer); + ) + CODE_FOR_UART + ( + return nrf_drv_uart_rx_for_uart(p_data, length, second_buffer); + ) +} + +void nrf_drv_uart_rx_enable(void) +{ + //Easy dma mode does not support enabling receiver without setting up buffer. + CODE_FOR_UARTE + ( + ASSERT(false); + ) + CODE_FOR_UART + ( + if (!m_cb.rx_enabled) + { + rx_enable(); + m_cb.rx_enabled = true; + } + ) +} + +void nrf_drv_uart_rx_disable(void) +{ + //Easy dma mode does not support enabling receiver without setting up buffer. + CODE_FOR_UARTE + ( + ASSERT(false); + ) + CODE_FOR_UART + ( + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX); + m_cb.rx_enabled = false; + ) +} + +uint32_t nrf_drv_uart_errorsrc_get(void) +{ + uint32_t errsrc; + CODE_FOR_UARTE + ( + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ERROR); + errsrc = nrf_uarte_errorsrc_get_and_clear(NRF_UARTE0); + ) + CODE_FOR_UART + ( + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_ERROR); + errsrc = nrf_uart_errorsrc_get_and_clear(NRF_UART0); + ) + return errsrc; +} + +__STATIC_INLINE void rx_done_event(uint8_t bytes, uint8_t * p_data) +{ + nrf_drv_uart_event_t event; + + event.type = NRF_DRV_UART_EVT_RX_DONE; + event.data.rxtx.bytes = bytes; + event.data.rxtx.p_data = p_data; + + m_cb.handler(&event,m_cb.p_context); +} + +__STATIC_INLINE void tx_done_event(uint8_t bytes) +{ + nrf_drv_uart_event_t event; + + event.type = NRF_DRV_UART_EVT_TX_DONE; + event.data.rxtx.bytes = bytes; + event.data.rxtx.p_data = (uint8_t *)m_cb.p_tx_buffer; + + m_cb.tx_buffer_length = 0; + + m_cb.handler(&event,m_cb.p_context); +} + +void nrf_drv_uart_tx_abort(void) +{ + CODE_FOR_UARTE + ( + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_TXSTOPPED); + nrf_uarte_task_trigger(NRF_UARTE0, NRF_UARTE_TASK_STOPTX); + if (m_cb.handler == NULL) + { + while(!nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_TXSTOPPED)); + } + ) + CODE_FOR_UART + ( + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPTX); + if (m_cb.handler) + { + tx_done_event(m_cb.tx_counter); + } + else + { + m_cb.tx_counter = TX_COUNTER_ABORT_REQ_VALUE; + } + ) +} + +void nrf_drv_uart_rx_abort(void) +{ + CODE_FOR_UARTE + ( + nrf_uarte_task_trigger(NRF_UARTE0, NRF_UARTE_TASK_STOPRX); + ) + CODE_FOR_UART + ( + nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR); + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX); + ) +} + + +#if defined(UART_IN_USE) +__STATIC_INLINE void uart_irq_handler() +{ + if (nrf_uart_int_enable_check(NRF_UART0, NRF_UART_INT_MASK_ERROR) && + nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_ERROR)) + { + nrf_drv_uart_event_t event; + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_ERROR); + nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR); + if (!m_cb.rx_enabled) + { + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX); + } + event.type = NRF_DRV_UART_EVT_ERROR; + event.data.error.error_mask = nrf_uart_errorsrc_get_and_clear(NRF_UART0); + event.data.error.rxtx.bytes = m_cb.rx_buffer_length; + event.data.error.rxtx.p_data = m_cb.p_rx_buffer; + + //abort transfer + m_cb.rx_buffer_length = 0; + m_cb.rx_secondary_buffer_length = 0; + + m_cb.handler(&event,m_cb.p_context); + } + else if (nrf_uart_int_enable_check(NRF_UART0, NRF_UART_INT_MASK_RXDRDY) && + nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_RXDRDY)) + { + rx_byte(); + if (m_cb.rx_buffer_length == m_cb.rx_counter) + { + if (m_cb.rx_secondary_buffer_length) + { + uint8_t * p_data = m_cb.p_rx_buffer; + uint8_t rx_counter = m_cb.rx_counter; + + //Switch to secondary buffer. + m_cb.rx_buffer_length = m_cb.rx_secondary_buffer_length; + m_cb.p_rx_buffer = m_cb.p_rx_secondary_buffer; + m_cb.rx_secondary_buffer_length = 0; + m_cb.rx_counter = 0; + rx_done_event(rx_counter, p_data); + } + else + { + if (!m_cb.rx_enabled) + { + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STOPRX); + } + nrf_uart_int_disable(NRF_UART0, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR); + m_cb.rx_buffer_length = 0; + rx_done_event(m_cb.rx_counter, m_cb.p_rx_buffer); + } + } + } + + if (nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_TXDRDY)) + { + if (m_cb.tx_counter < (uint16_t) m_cb.tx_buffer_length) + { + tx_byte(); + } + else + { + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY); + if (m_cb.tx_buffer_length) + { + tx_done_event(m_cb.tx_buffer_length); + } + } + } + + if (nrf_uart_event_check(NRF_UART0, NRF_UART_EVENT_RXTO)) + { + nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXTO); + + // RXTO event may be triggered as a result of abort call. In th + if (m_cb.rx_enabled) + { + nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTRX); + } + if (m_cb.rx_buffer_length) + { + m_cb.rx_buffer_length = 0; + rx_done_event(m_cb.rx_counter, m_cb.p_rx_buffer); + } + } +} +#endif + +#if defined(UARTE_IN_USE) +__STATIC_INLINE void uarte_irq_handler() +{ + if (nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ERROR)) + { + nrf_drv_uart_event_t event; + + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ERROR); + + event.type = NRF_DRV_UART_EVT_ERROR; + event.data.error.error_mask = nrf_uarte_errorsrc_get_and_clear(NRF_UARTE0); + event.data.error.rxtx.bytes = nrf_uarte_rx_amount_get(NRF_UARTE0); + event.data.error.rxtx.p_data = m_cb.p_rx_buffer; + + //abort transfer + m_cb.rx_buffer_length = 0; + m_cb.rx_secondary_buffer_length = 0; + + m_cb.handler(&event,m_cb.p_context); + } + else if (nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX)) + { + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDRX); + uint8_t amount = nrf_uarte_rx_amount_get(NRF_UARTE0); + // If the transfer was stopped before completion, amount of transfered bytes + // will not be equal to the buffer length. Interrupted trunsfer is ignored. + if (amount == m_cb.rx_buffer_length) + { + if (m_cb.rx_secondary_buffer_length) + { + uint8_t * p_data = m_cb.p_rx_buffer; + nrf_uarte_shorts_disable(NRF_UARTE0, NRF_UARTE_SHORT_ENDRX_STARTRX); + m_cb.rx_buffer_length = m_cb.rx_secondary_buffer_length; + m_cb.p_rx_buffer = m_cb.p_rx_secondary_buffer; + m_cb.rx_secondary_buffer_length = 0; + rx_done_event(amount, p_data); + } + else + { + m_cb.rx_buffer_length = 0; + rx_done_event(amount, m_cb.p_rx_buffer); + } + } + } + + if (nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_RXTO)) + { + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_RXTO); + if (m_cb.rx_buffer_length) + { + m_cb.rx_buffer_length = 0; + rx_done_event(nrf_uarte_rx_amount_get(NRF_UARTE0), m_cb.p_rx_buffer); + } + } + + if (nrf_uarte_event_check(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX)) + { + nrf_uarte_event_clear(NRF_UARTE0, NRF_UARTE_EVENT_ENDTX); + if (m_cb.tx_buffer_length) + { + tx_done_event(nrf_uarte_tx_amount_get(NRF_UARTE0)); + } + } +} +#endif + +void UART0_IRQHandler(void) +{ + CODE_FOR_UARTE + ( + uarte_irq_handler(); + ) + CODE_FOR_UART + ( + uart_irq_handler(); + ) +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.h new file mode 100644 index 0000000..ed49f14 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/uart/nrf_drv_uart.h @@ -0,0 +1,293 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * @addtogroup nrf_uart UART driver and HAL + * @ingroup nrf_drivers + * @brief UART API. + * @details The UART driver provides APIs for utilizing the UART peripheral. + * + * @defgroup nrf_drv_uart UART driver + * @{ + * @ingroup nrf_uart + * + * @brief UART driver. + */ + +#ifndef NRF_DRV_UART_H +#define NRF_DRV_UART_H + +#include "nrf_uart.h" +#ifdef NRF52 +#include "nrf_uarte.h" +#endif + +#include "sdk_errors.h" +#include "nrf_drv_config.h" + +/** + * @brief Types of UART driver events. + */ +typedef enum +{ + NRF_DRV_UART_EVT_TX_DONE, ///< Requested TX transfer completed. + NRF_DRV_UART_EVT_RX_DONE, ///< Requested RX transfer completed. + NRF_DRV_UART_EVT_ERROR, ///< Error reported by UART peripheral. +} nrf_drv_uart_evt_type_t; + +/**@brief Structure for UART configuration. */ +typedef struct +{ + uint32_t pseltxd; ///< TXD pin number. + uint32_t pselrxd; ///< RXD pin number. + uint32_t pselcts; ///< CTS pin number. + uint32_t pselrts; ///< RTS pin number. + void * p_context; ///< Context passed to interrupt handler. + nrf_uart_hwfc_t hwfc; ///< Flow control configuration. + nrf_uart_parity_t parity; ///< Parity configuration. + nrf_uart_baudrate_t baudrate; ///< Baudrate. + uint8_t interrupt_priority; ///< Interrupt priority. +#ifdef NRF52 + bool use_easy_dma; +#endif +} nrf_drv_uart_config_t; + +/**@brief UART default configuration. */ +#ifdef NRF52 +#if !UART_LEGACY_SUPPORT +#define DEFAULT_CONFIG_USE_EASY_DMA true +#elif !UART_EASY_DMA_SUPPORT +#define DEFAULT_CONFIG_USE_EASY_DMA false +#else +#define DEFAULT_CONFIG_USE_EASY_DMA UART0_CONFIG_USE_EASY_DMA +#endif +#define NRF_DRV_UART_DEFAULT_CONFIG \ + { \ + .pseltxd = UART0_CONFIG_PSEL_TXD, \ + .pselrxd = UART0_CONFIG_PSEL_RXD, \ + .pselcts = UART0_CONFIG_PSEL_CTS, \ + .pselrts = UART0_CONFIG_PSEL_RTS, \ + .p_context = NULL, \ + .hwfc = UART0_CONFIG_HWFC, \ + .parity = UART0_CONFIG_PARITY, \ + .baudrate = UART0_CONFIG_BAUDRATE, \ + .interrupt_priority = UART0_CONFIG_IRQ_PRIORITY, \ + .use_easy_dma = DEFAULT_CONFIG_USE_EASY_DMA \ + } +#else +#define NRF_DRV_UART_DEFAULT_CONFIG \ + { \ + .pseltxd = UART0_CONFIG_PSEL_TXD, \ + .pselrxd = UART0_CONFIG_PSEL_RXD, \ + .pselcts = UART0_CONFIG_PSEL_CTS, \ + .pselrts = UART0_CONFIG_PSEL_RTS, \ + .p_context = NULL, \ + .hwfc = UART0_CONFIG_HWFC, \ + .parity = UART0_CONFIG_PARITY, \ + .baudrate = UART0_CONFIG_BAUDRATE, \ + .interrupt_priority = UART0_CONFIG_IRQ_PRIORITY \ + } +#endif + +/**@brief Structure for UART transfer completion event. */ +typedef struct +{ + uint8_t * p_data; ///< Pointer to memory used for transfer. + uint8_t bytes; ///< Number of bytes transfered. +} nrf_drv_uart_xfer_evt_t; + +/**@brief Structure for UART error event. */ +typedef struct +{ + nrf_drv_uart_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transfered. + uint32_t error_mask;///< Mask of error flags that generated the event. +} nrf_drv_uart_error_evt_t; + +/**@brief Structure for UART event. */ +typedef struct +{ + nrf_drv_uart_evt_type_t type; ///< Event type. + union + { + nrf_drv_uart_xfer_evt_t rxtx; ///< Data provided for transfer completion events. + nrf_drv_uart_error_evt_t error;///< Data provided for error event. + } data; +} nrf_drv_uart_event_t; + +/** + * @brief UART interrupt event handler. + * + * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available + * only within the context of the event handler. + * @param[in] p_context Context passed to interrupt handler, set on initialization. + */ +typedef void (*nrf_uart_event_handler_t)(nrf_drv_uart_event_t * p_event, void * p_context); + +/** + * @brief Function for initializing the UART driver. + * + * This function configures and enables UART. After this function GPIO pins are controlled by UART. + * + * @param[in] p_config Initial configuration. Default configuration used if NULL. + * @param[in] event_handler Event handler provided by the user. If not provided driver works in + * blocking mode. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_INVALID_STATE If driver is already initialized. + */ +ret_code_t nrf_drv_uart_init(nrf_drv_uart_config_t const * p_config, + nrf_uart_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the UART driver. + */ +void nrf_drv_uart_uninit(void); + +/** + * @brief Function for getting the address of a specific UART task. + * + * @param[in] task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_drv_uart_task_address_get(nrf_uart_task_t task); + +/** + * @brief Function for getting the address of a specific UART event. + * + * @param[in] event Event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrf_drv_uart_event_address_get(nrf_uart_event_t event); + +/** + * @brief Function for sending data over UART. + * + * If an event handler was provided in nrf_drv_uart_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt so + * there is no context switching inside the function. + * + * @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers + * are placed in the Data RAM region. If they are not and UARTE instance is + * used, this function will fail with error code NRF_ERROR_INVALID_ADDR. + * + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to send. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_BUSY If driver is already transferring. + * @retval NRF_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only, also see @ref nrf_drv_uart_rx_disable). + * @retval NRF_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only). + */ +ret_code_t nrf_drv_uart_tx(uint8_t const * const p_data, uint8_t length); + +/** + * @brief Function for checking if UART is currently transmitting. + * + * @retval true If UART is transmitting. + * @retval false If UART is not transmitting. + */ +bool nrf_drv_uart_tx_in_progress(void); + +/** + * @brief Function for aborting any ongoing transmission. + * @note @ref NRF_DRV_UART_EVT_TX_DONE event will be generated in non-blocking mode. Event will + * contain number of bytes sent until abort was called. If Easy DMA is not used event will be + * called from the function context. If Easy DMA is used it will be called from UART interrupt + * context. + */ +void nrf_drv_uart_tx_abort(void); + +/** + * @brief Function for receiving data over UART. + * + * If an event handler was provided in the nrf_drv_uart_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt so + * there is no context switching inside the function. + * The receive buffer pointer is double buffered in non-blocking mode. The secondary + * buffer can be set immediately after starting the transfer and will be filled + * when the primary buffer is full. The double buffering feature allows + * receiving data continuously. + * + * @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers + * are placed in the Data RAM region. If they are not and UARTE instance is + * used, this function will fail with error code NRF_ERROR_INVALID_ADDR. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to receive. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_BUSY If the driver is already receiving + * (and the secondary buffer has already been set + * in non-blocking mode). + * @retval NRF_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only, also see @ref nrf_drv_uart_rx_disable). + * @retval NRF_ERROR_INTERNAL If UART peripheral reported an error. + * @retval NRF_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only). + */ +ret_code_t nrf_drv_uart_rx(uint8_t * p_data, uint8_t length); + +/** + * @brief Function for enabling receiver. + * + * UART has 6 byte long RX FIFO and it will be used to store incoming data. If user will not call + * UART receive function before FIFO is filled, overrun error will encounter. Enabling receiver + * without specifying RX buffer is supported only in UART mode (without Easy DMA). Receiver must be + * explicitly closed by the user @sa nrf_drv_uart_rx_disable. Function asserts if mode is wrong. + */ +void nrf_drv_uart_rx_enable(void); + +/** + * @brief Function for disabling receiver. + * + * Function must be called to close the receiver after it has been explicitly enabled by + * @sa nrf_drv_uart_rx_enable. Feature is supported only in UART mode (without Easy DMA). Function + * asserts if mode is wrong. + */ +void nrf_drv_uart_rx_disable(void); + +/** + * @brief Function for aborting any ongoing reception. + * @note @ref NRF_DRV_UART_EVT_RX_DONE event will be generated in non-blocking mode. Event will + * contain number of bytes received until abort was called. If Easy DMA is not used event will be + * called from the function context. If Easy DMA is used it will be called from UART interrupt + * context. + */ +void nrf_drv_uart_rx_abort(void); + +/** + * @brief Function for reading error source mask. Mask contains values from @ref nrf_uart_error_mask_t. + * @note Function should be used in blocking mode only. In case of non-blocking mode error event is + * generated. Function clears error sources after reading. + * + * @retval Mask of reported errors. + */ +uint32_t nrf_drv_uart_errorsrc_get(void); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE uint32_t nrf_drv_uart_task_address_get(nrf_uart_task_t task) +{ + return nrf_uart_task_address_get(NRF_UART0, task); +} + +__STATIC_INLINE uint32_t nrf_drv_uart_event_address_get(nrf_uart_event_t event) +{ + return nrf_uart_event_address_get(NRF_UART0, event); +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION +#endif //NRF_DRV_UART_H +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/wdt/nrf_drv_wdt.c b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/wdt/nrf_drv_wdt.c new file mode 100644 index 0000000..bfd684f --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/wdt/nrf_drv_wdt.c @@ -0,0 +1,118 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "nrf_drv_wdt.h" +#include "nrf_drv_common.h" +#include "nrf_error.h" +#include "nrf_assert.h" +#include "nrf_wdt.h" +#include "app_util_platform.h" +#include +#include + +/**@brief WDT event handler. */ +static nrf_wdt_event_handler_t m_wdt_event_handler; + +/**@brief WDT state. */ +static nrf_drv_state_t m_state; + +/**@brief WDT alloc table. */ +static uint32_t m_alloc_index; + +static const nrf_drv_wdt_config_t m_default_config = NRF_DRV_WDT_DEAFULT_CONFIG; + +/**@brief WDT interrupt handler. */ +void WDT_IRQHandler(void) +{ + if (nrf_wdt_int_enable_check(NRF_WDT_INT_TIMEOUT_MASK) == true) + { + nrf_wdt_event_clear(NRF_WDT_EVENT_TIMEOUT); + m_wdt_event_handler(); + } +} + + +ret_code_t nrf_drv_wdt_init(nrf_drv_wdt_config_t const * p_config, + nrf_wdt_event_handler_t wdt_event_handler) +{ + ASSERT(wdt_event_handler != NULL); + m_wdt_event_handler = wdt_event_handler; + + if (m_state == NRF_DRV_STATE_UNINITIALIZED) + { + m_state = NRF_DRV_STATE_INITIALIZED; + } + else + { + return NRF_ERROR_INVALID_STATE; // WDT already initialized + } + + if (p_config == NULL) + { + p_config = &m_default_config; + } + + nrf_wdt_behaviour_set(p_config->behaviour); + nrf_wdt_reload_value_set((p_config->reload_value * 32768) / 1000); + + nrf_drv_common_irq_enable(WDT_IRQn, p_config->interrupt_priority); + + return NRF_SUCCESS; +} + + +void nrf_drv_wdt_enable(void) +{ + ASSERT(m_alloc_index != 0); + ASSERT(m_state == NRF_DRV_STATE_INITIALIZED); + nrf_wdt_int_enable(NRF_WDT_INT_TIMEOUT_MASK); + nrf_wdt_task_trigger(NRF_WDT_TASK_START); + m_state = NRF_DRV_STATE_POWERED_ON; +} + + +void nrf_drv_wdt_feed(void) +{ + ASSERT(m_state == NRF_DRV_STATE_POWERED_ON); + for(uint32_t i = 0; i < m_alloc_index; i++) + { + nrf_wdt_reload_request_set((nrf_wdt_rr_register_t)(NRF_WDT_RR0 + i)); + } +} + +ret_code_t nrf_drv_wdt_channel_alloc(nrf_drv_wdt_channel_id * p_channel_id) +{ + ret_code_t result; + ASSERT(p_channel_id); + ASSERT(m_state == NRF_DRV_STATE_INITIALIZED); + + CRITICAL_REGION_ENTER(); + if (m_alloc_index < NRF_WDT_CHANNEL_NUMBER) + { + *p_channel_id = (nrf_drv_wdt_channel_id)(NRF_WDT_RR0 + m_alloc_index); + m_alloc_index++; + nrf_wdt_reload_request_enable(*p_channel_id); + result = NRF_SUCCESS; + } + else + { + result = NRF_ERROR_NO_MEM; + } + CRITICAL_REGION_EXIT(); + return result; +} + +void nrf_drv_wdt_channel_feed(nrf_drv_wdt_channel_id channel_id) +{ + ASSERT(m_state == NRF_DRV_STATE_POWERED_ON); + nrf_wdt_reload_request_set(channel_id); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/wdt/nrf_drv_wdt.h b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/wdt/nrf_drv_wdt.h new file mode 100644 index 0000000..338d5bc --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/wdt/nrf_drv_wdt.h @@ -0,0 +1,124 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * @addtogroup nrf_wdt WDT HAL and driver + * @ingroup nrf_drivers + * @brief Watchdog timer (WDT) APIs. + * @details The WDT HAL provides basic APIs for accessing the registers of the watchdog timer. + * The WDT driver provides APIs on a higher level. + * @defgroup lib_driver_wdt WDT driver + * @{ + * @ingroup nrf_wdt + * + * @brief Driver for managing the watchdog timer (WDT). + */ + +#ifndef NRF_DRV_WDT_H__ +#define NRF_DRV_WDT_H__ + +#include +#include +#include "sdk_errors.h" +#include "nrf_wdt.h" +#include "nrf_drv_config.h" + +/**@brief Struct for WDT initialization. */ +typedef struct +{ + nrf_wdt_behaviour_t behaviour; /**< WDT behaviour when CPU in sleep/halt mode. */ + uint32_t reload_value; /**< WDT reload value in ms. */ + uint8_t interrupt_priority; /**< WDT interrupt priority */ +} nrf_drv_wdt_config_t; + +/**@brief WDT event handler function type. */ +typedef void (*nrf_wdt_event_handler_t)(void); + +/**@brief WDT channel id type. */ +typedef nrf_wdt_rr_register_t nrf_drv_wdt_channel_id; + +#define NRF_DRV_WDT_DEAFULT_CONFIG \ + { \ + .behaviour = WDT_CONFIG_BEHAVIOUR, \ + .reload_value = WDT_CONFIG_RELOAD_VALUE, \ + .interrupt_priority = WDT_CONFIG_IRQ_PRIORITY, \ + } +/** + * @brief This function initializes watchdog. + * + * @param[in] p_config Initial configuration. Default configuration used if NULL. + * @param[in] wdt_event_handler specifies event handler provided by user. + * + * @note Function asserts if wdt_event_handler is NULL. + * + * @return NRF_SUCCESS on success, NRF_ERROR_INVALID_STATE if module ws already initialized. + */ +ret_code_t nrf_drv_wdt_init(nrf_drv_wdt_config_t const * p_config, + nrf_wdt_event_handler_t wdt_event_handler); + +/** + * @brief This function allocate watchdog channel. + * + * @note This function can not be called after nrf_drv_wdt_start(void). + * + * @param[out] p_channel_id ID of granted channel. + * + * @return NRF_SUCCESS on success, otherwise an error code. + */ +ret_code_t nrf_drv_wdt_channel_alloc(nrf_drv_wdt_channel_id * p_channel_id); + +/** + * @brief This function starts watchdog. + * + * @note After calling this function the watchdog is started, so the user needs to feed all allocated + * watchdog channels to avoid reset. At least one watchdog channel has to be allocated. + */ +void nrf_drv_wdt_enable(void); + +/** + * @brief This function feeds the watchdog. + * + * @details Function feeds all allocated watchdog channels. + */ +void nrf_drv_wdt_feed(void); + +/** + * @brief This function feeds the invidual watchdog channel. + * + * @param[in] channel_id ID of watchdog channel. + */ +void nrf_drv_wdt_channel_feed(nrf_drv_wdt_channel_id channel_id); + +/**@brief Function for returning a requested task address for the wdt driver module. + * + * @param[in] task One of the peripheral tasks. + * + * @retval Task address. + */ +__STATIC_INLINE uint32_t nrf_drv_wdt_ppi_task_addr(nrf_wdt_task_t task) +{ + return nrf_wdt_task_address_get(task); +} + +/**@brief Function for returning a requested event address for the wdt driver module. + * + * @param[in] event One of the peripheral events. + * + * @retval Event address + */ +__STATIC_INLINE uint32_t nrf_drv_wdt_ppi_event_addr(nrf_wdt_event_t event) +{ + return nrf_wdt_event_address_get(event); +} +#endif + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/ble_transport/hci_mem_pool_internal.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/ble_transport/hci_mem_pool_internal.h new file mode 100644 index 0000000..945365e --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/ble_transport/hci_mem_pool_internal.h @@ -0,0 +1,32 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup memory_pool_internal Memory Pool Internal + * @{ + * @ingroup memory_pool + * + * @brief Memory pool internal definitions + */ + +#ifndef MEM_POOL_INTERNAL_H__ +#define MEM_POOL_INTERNAL_H__ + +#define TX_BUF_SIZE 4u /**< TX buffer size in bytes. */ +#define RX_BUF_SIZE 32u /**< RX buffer size in bytes. */ + +#define RX_BUF_QUEUE_SIZE 8u /**< RX buffer element size. */ + +#endif // MEM_POOL_INTERNAL_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.c new file mode 100644 index 0000000..da4e53c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.c @@ -0,0 +1,457 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "bootloader.h" +#include "bootloader_types.h" +#include "bootloader_util.h" +#include "bootloader_settings.h" +#include "dfu.h" +#include "dfu_transport.h" +#include "nrf.h" +#include "app_error.h" +#include "nrf_sdm.h" +#include "nrf_mbr.h" +#include "nordic_common.h" +#include "crc16.h" +#include "pstorage.h" +#include "app_scheduler.h" +#include "nrf_delay.h" +#include "sdk_common.h" + +#include "app_timer_appsh.h" + +#define APP_TIMER_PRESCALER 0 + +#define IRQ_ENABLED 0x01 /**< Field identifying if an interrupt is enabled. */ + +#ifdef NRF52 +#define MAX_NUMBER_INTERRUPTS 39 +#else +#define MAX_NUMBER_INTERRUPTS 32 /**< Maximum number of interrupts available. */ +#endif + +/**@brief Enumeration for specifying current bootloader status. + */ +typedef enum +{ + BOOTLOADER_UPDATING, /**< Bootloader status for indicating that an update is in progress. */ + BOOTLOADER_SETTINGS_SAVING, /**< Bootloader status for indicating that saving of bootloader settings is in progress. */ + BOOTLOADER_COMPLETE, /**< Bootloader status for indicating that all operations for the update procedure has completed and it is safe to reset the system. */ + BOOTLOADER_TIMEOUT, /**< Bootloader status field for indicating that a timeout has occured and current update process should be aborted. */ + BOOTLOADER_RESET, /**< Bootloader status field for indicating that a reset has been requested and current update process should be aborted. */ +} bootloader_status_t; + +static pstorage_handle_t m_bootsettings_handle; /**< Pstorage handle to use for registration and identifying the bootloader module on subsequent calls to the pstorage module for load and store of bootloader setting in flash. */ +static bootloader_status_t m_update_status; /**< Current update status for the bootloader module to ensure correct behaviour when updating settings and when update completes. */ + +// Adafruit modification for dual transports and forced startup DFU +extern bool is_ota(void); + +APP_TIMER_DEF( _forced_startup_dfu_timer ); +volatile bool forced_startup_dfu_packet_received = false; +volatile static bool _terminate_startup_dfu = false; + +/**@brief Function for handling callbacks from pstorage module. + * + * @details Handles pstorage results for clear and storage operation. For detailed description of + * the parameters provided with the callback, please refer to \ref pstorage_ntf_cb_t. + */ +static void pstorage_callback_handler(pstorage_handle_t * p_handle, + uint8_t op_code, + uint32_t result, + uint8_t * p_data, + uint32_t data_len) +{ + // If we are in BOOTLOADER_SETTINGS_SAVING state and we receive an PSTORAGE_STORE_OP_CODE + // response then settings has been saved and update has completed. + if ((m_update_status == BOOTLOADER_SETTINGS_SAVING) && (op_code == PSTORAGE_STORE_OP_CODE)) + { + m_update_status = BOOTLOADER_COMPLETE; + } + + APP_ERROR_CHECK(result); +} + +// Adafruit modifcation +static void terminate_startup_dfu(void * p_event_data, uint16_t event_size) +{ + (void) p_event_data; + (void) event_size; + + _terminate_startup_dfu = true; +} + +/* Terminate the forced DFU mode on startup if no packets is received + * by put an terminal handler to scheduler + */ +static void forced_startup_dfu_timer_handler(void * p_context) +{ + // No packets are received within timeout, terminal and DFU mode + // forced_startup_dfu_packet_received is set by process_dfu_packet() in dfu_transport_serial.c + if (!forced_startup_dfu_packet_received) + { + app_sched_event_put(NULL, 0, terminate_startup_dfu); + } +} + +/**@brief Function for waiting for events. + * + * @details This function will place the chip in low power mode while waiting for events from + * the SoftDevice or other peripherals. When interrupted by an event, it will call the + * @ref app_sched_execute function to process the received event. This function will return + * when the final state of the firmware update is reached OR when a tear down is in + * progress. + */ +static void wait_for_events(void) +{ + for (;;) + { + // Wait in low power state for any events. + uint32_t err_code = sd_app_evt_wait(); + APP_ERROR_CHECK(err_code); + + // Event received. Process it from the scheduler. + app_sched_execute(); + + if ((m_update_status == BOOTLOADER_COMPLETE) || + (m_update_status == BOOTLOADER_TIMEOUT) || + (m_update_status == BOOTLOADER_RESET)) + { + // When update has completed or a timeout/reset occured we will return. + return; + } + + // Forced startup dfu mode timeout without any received packet + if (_terminate_startup_dfu) + { + return; + } + } +} + + +bool bootloader_app_is_valid(uint32_t app_addr) +{ + const bootloader_settings_t * p_bootloader_settings; + + // There exists an application in CODE region 1. + if (*((uint32_t *)app_addr) == EMPTY_FLASH_MASK) + { + return false; + } + + bool success = false; + + bootloader_util_settings_get(&p_bootloader_settings); + + // The application in CODE region 1 is flagged as valid during update. + if (p_bootloader_settings->bank_0 == BANK_VALID_APP) + { + uint16_t image_crc = 0; + + // A stored crc value of 0 indicates that CRC checking is not used. + if (p_bootloader_settings->bank_0_crc != 0) + { + image_crc = crc16_compute((uint8_t *)DFU_BANK_0_REGION_START, + p_bootloader_settings->bank_0_size, + NULL); + } + + success = (image_crc == p_bootloader_settings->bank_0_crc); + } + + return success; +} + + +static void bootloader_settings_save(bootloader_settings_t * p_settings) +{ + uint32_t err_code = pstorage_clear(&m_bootsettings_handle, sizeof(bootloader_settings_t)); + APP_ERROR_CHECK(err_code); + + err_code = pstorage_store(&m_bootsettings_handle, + (uint8_t *)p_settings, + sizeof(bootloader_settings_t), + 0); + APP_ERROR_CHECK(err_code); +} + + +void bootloader_dfu_update_process(dfu_update_status_t update_status) +{ + static bootloader_settings_t settings; + const bootloader_settings_t * p_bootloader_settings; + + bootloader_util_settings_get(&p_bootloader_settings); + + if (update_status.status_code == DFU_UPDATE_APP_COMPLETE) + { + settings.bank_0_crc = update_status.app_crc; + settings.bank_0_size = update_status.app_size; + settings.bank_0 = BANK_VALID_APP; + settings.bank_1 = BANK_INVALID_APP; + + m_update_status = BOOTLOADER_SETTINGS_SAVING; + bootloader_settings_save(&settings); + } + else if (update_status.status_code == DFU_UPDATE_SD_COMPLETE) + { + settings.bank_0_crc = update_status.app_crc; + settings.bank_0_size = update_status.sd_size + + update_status.bl_size + + update_status.app_size; + settings.bank_0 = BANK_VALID_SD; + settings.bank_1 = BANK_INVALID_APP; + settings.sd_image_size = update_status.sd_size; + settings.bl_image_size = update_status.bl_size; + settings.app_image_size = update_status.app_size; + settings.sd_image_start = update_status.sd_image_start; + + m_update_status = BOOTLOADER_SETTINGS_SAVING; + bootloader_settings_save(&settings); + } + else if (update_status.status_code == DFU_UPDATE_BOOT_COMPLETE) + { + settings.bank_0 = p_bootloader_settings->bank_0; + settings.bank_0_crc = p_bootloader_settings->bank_0_crc; + settings.bank_0_size = p_bootloader_settings->bank_0_size; + settings.bank_1 = BANK_VALID_BOOT; + settings.sd_image_size = update_status.sd_size; + settings.bl_image_size = update_status.bl_size; + settings.app_image_size = update_status.app_size; + + m_update_status = BOOTLOADER_SETTINGS_SAVING; + bootloader_settings_save(&settings); + } + else if (update_status.status_code == DFU_UPDATE_SD_SWAPPED) + { + if (p_bootloader_settings->bank_0 == BANK_VALID_SD) + { + settings.bank_0_crc = 0; + settings.bank_0_size = 0; + settings.bank_0 = BANK_INVALID_APP; + } + // This handles cases where SoftDevice was not updated, hence bank0 keeps its settings. + else + { + settings.bank_0 = p_bootloader_settings->bank_0; + settings.bank_0_crc = p_bootloader_settings->bank_0_crc; + settings.bank_0_size = p_bootloader_settings->bank_0_size; + } + + settings.bank_1 = BANK_INVALID_APP; + settings.sd_image_size = 0; + settings.bl_image_size = 0; + settings.app_image_size = 0; + + m_update_status = BOOTLOADER_SETTINGS_SAVING; + bootloader_settings_save(&settings); + } + else if (update_status.status_code == DFU_TIMEOUT) + { + // Timeout has occurred. Close the connection with the DFU Controller. + uint32_t err_code; + if ( is_ota() ) + { + err_code = dfu_transport_ble_close(); + }else + { + err_code = dfu_transport_serial_close(); + } + APP_ERROR_CHECK(err_code); + + m_update_status = BOOTLOADER_TIMEOUT; + } + else if (update_status.status_code == DFU_BANK_0_ERASED) + { + settings.bank_0_crc = 0; + settings.bank_0_size = 0; + settings.bank_0 = BANK_INVALID_APP; + settings.bank_1 = p_bootloader_settings->bank_1; + + bootloader_settings_save(&settings); + } + else if (update_status.status_code == DFU_RESET) + { + m_update_status = BOOTLOADER_RESET; + } + else + { + // No implementation needed. + } +} + + +uint32_t bootloader_init(void) +{ + uint32_t err_code; + pstorage_module_param_t storage_params = {.cb = pstorage_callback_handler}; + + err_code = pstorage_init(); + VERIFY_SUCCESS(err_code); + + m_bootsettings_handle.block_id = BOOTLOADER_SETTINGS_ADDRESS; + err_code = pstorage_register(&storage_params, &m_bootsettings_handle); + + return err_code; +} + + +uint32_t bootloader_dfu_start(bool ota, uint32_t timeout_ms) +{ + uint32_t err_code; + + // Clear swap if banked update is used. + err_code = dfu_init(); + VERIFY_SUCCESS(err_code); + + if ( ota ) + { + err_code = dfu_transport_ble_update_start(); + }else + { + // timeout_ms > 0 is forced startup DFU + if ( timeout_ms ) + { + forced_startup_dfu_packet_received = false; + _terminate_startup_dfu = false; + + (void) app_timer_create(&_forced_startup_dfu_timer, APP_TIMER_MODE_SINGLE_SHOT, forced_startup_dfu_timer_handler); + app_timer_start(_forced_startup_dfu_timer, APP_TIMER_TICKS(timeout_ms, APP_TIMER_PRESCALER), NULL); + } + + err_code = dfu_transport_serial_update_start(); + } + + wait_for_events(); + + // Close Serial transport after done + if ( !ota ) dfu_transport_serial_close(); + + return err_code; +} + + +/**@brief Function for disabling all interrupts before jumping from bootloader to application. + */ +static void interrupts_disable(void) +{ + uint32_t interrupt_setting_mask; + uint32_t irq = 0; // We start from first interrupt, i.e. interrupt 0. + + // Fetch the current interrupt settings. + interrupt_setting_mask = NVIC->ISER[0]; + + for (; irq < MAX_NUMBER_INTERRUPTS; irq++) + { + if (interrupt_setting_mask & (IRQ_ENABLED << irq)) + { + // The interrupt was enabled, and hence disable it. + NVIC_DisableIRQ((IRQn_Type)irq); + } + } +} + + +void bootloader_app_start(uint32_t app_addr) +{ + // If the applications CRC has been checked and passed, the magic number will be written and we + // can start the application safely. + uint32_t err_code = sd_softdevice_disable(); + APP_ERROR_CHECK(err_code); + + interrupts_disable(); + + // Disable RTC1 + NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; + NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk; + NRF_RTC1->TASKS_STOP = 1; + NRF_RTC1->TASKS_CLEAR = 1; + + err_code = sd_softdevice_vector_table_base_set(CODE_REGION_1_START); + APP_ERROR_CHECK(err_code); + + bootloader_util_app_start(CODE_REGION_1_START); +} + + +bool bootloader_dfu_sd_in_progress(void) +{ + const bootloader_settings_t * p_bootloader_settings; + + bootloader_util_settings_get(&p_bootloader_settings); + + if (p_bootloader_settings->bank_0 == BANK_VALID_SD || + p_bootloader_settings->bank_1 == BANK_VALID_BOOT) + { + return true; + } + + return false; +} + + +uint32_t bootloader_dfu_sd_update_continue(void) +{ + uint32_t err_code; + + if ((dfu_sd_image_validate() == NRF_SUCCESS) && + (dfu_bl_image_validate() == NRF_SUCCESS)) + { + return NRF_SUCCESS; + } + + // Ensure that flash operations are not executed within the first 100 ms seconds to allow + // a debugger to be attached. + nrf_delay_ms(100); + + err_code = dfu_sd_image_swap(); + APP_ERROR_CHECK(err_code); + + err_code = dfu_sd_image_validate(); + APP_ERROR_CHECK(err_code); + + err_code = dfu_bl_image_swap(); + APP_ERROR_CHECK(err_code); + + return err_code; +} + + +uint32_t bootloader_dfu_sd_update_finalize(void) +{ + dfu_update_status_t update_status = {DFU_UPDATE_SD_SWAPPED, }; + + bootloader_dfu_update_process(update_status); + + wait_for_events(); + + return NRF_SUCCESS; +} + + +void bootloader_settings_get(bootloader_settings_t * const p_settings) +{ + const bootloader_settings_t * p_bootloader_settings; + + bootloader_util_settings_get(&p_bootloader_settings); + + p_settings->bank_0 = p_bootloader_settings->bank_0; + p_settings->bank_0_crc = p_bootloader_settings->bank_0_crc; + p_settings->bank_0_size = p_bootloader_settings->bank_0_size; + p_settings->bank_1 = p_bootloader_settings->bank_1; + p_settings->sd_image_size = p_bootloader_settings->sd_image_size; + p_settings->bl_image_size = p_bootloader_settings->bl_image_size; + p_settings->app_image_size = p_bootloader_settings->app_image_size; + p_settings->sd_image_start = p_bootloader_settings->sd_image_start; +} + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.h new file mode 100644 index 0000000..3a5fa42 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader.h @@ -0,0 +1,97 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup nrf_bootloader Bootloader API. + * @{ + * + * @brief Bootloader module interface. + */ + +#ifndef BOOTLOADER_H__ +#define BOOTLOADER_H__ + +#include +#include +#include "bootloader_types.h" +#include + +/**@brief Function for initializing the Bootloader. + * + * @retval NRF_SUCCESS If bootloader was succesfully initialized. + */ +uint32_t bootloader_init(void); + +/**@brief Function for validating application region in flash. + * + * @param[in] app_addr Address to the region in flash where the application is stored. + * + * @retval true If Application region is valid. + * @retval false If Application region is not valid. + */ +bool bootloader_app_is_valid(uint32_t app_addr); + +/**@brief Function for starting the Device Firmware Update. + * + * @retval NRF_SUCCESS If new application image was successfully transferred. + */ +uint32_t bootloader_dfu_start(bool ota, uint32_t timeout_ms); + +/**@brief Function for exiting bootloader and booting into application. + * + * @details This function will disable SoftDevice and all interrupts before jumping to application. + * The SoftDevice vector table base for interrupt forwarding will be set the application + * address. + * + * @param[in] app_addr Address to the region where the application is stored. + */ +void bootloader_app_start(uint32_t app_addr); + +/**@brief Function for retrieving the bootloader settings. + * + * @param[out] p_settings A copy of the current bootloader settings is returned in the structure + * provided. + */ +void bootloader_settings_get(bootloader_settings_t * const p_settings); + +/**@brief Function for processing DFU status update. + * + * @param[in] update_status DFU update status. + */ +void bootloader_dfu_update_process(dfu_update_status_t update_status); + +/**@brief Function getting state of SoftDevice update in progress. + * After a successfull SoftDevice transfer the system restarts in orderto disable SoftDevice + * and complete the update. + * + * @retval true A SoftDevice update is in progress. This indicates that second stage + * of a SoftDevice update procedure can be initiated. + * @retval false No SoftDevice update is in progress. + */ +bool bootloader_dfu_sd_in_progress(void); + +/**@brief Function for continuing the Device Firmware Update of a SoftDevice. + * + * @retval NRF_SUCCESS If the final stage of SoftDevice update was successful. + */ +uint32_t bootloader_dfu_sd_update_continue(void); + +/**@brief Function for finalizing the Device Firmware Update of a SoftDevice. + * + * @retval NRF_SUCCESS If the final stage of SoftDevice update was successful. + */ +uint32_t bootloader_dfu_sd_update_finalize(void); + +#endif // BOOTLOADER_H__ + +/**@} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.c new file mode 100644 index 0000000..bdb20ce --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.c @@ -0,0 +1,63 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "bootloader_settings.h" +#include +#include + +#if defined ( __CC_ARM ) + +uint8_t m_boot_settings[CODE_PAGE_SIZE] __attribute__((at(BOOTLOADER_SETTINGS_ADDRESS))) __attribute__((used)); /**< This variable reserves a codepage for bootloader specific settings, to ensure the compiler doesn't locate any code or variables at his location. */ +uint32_t m_uicr_bootloader_start_address __attribute__((at(NRF_UICR_BOOT_START_ADDRESS))) = BOOTLOADER_REGION_START; /**< This variable makes the linker script write the bootloader start address to the UICR register. This value will be written in the HEX file and thus written to UICR when the bootloader is flashed into the chip. */ + +#elif defined ( __GNUC__ ) + +uint8_t m_boot_settings[CODE_PAGE_SIZE] __attribute__ ((section(".bootloaderSettings"))); /**< This variable reserves a codepage for bootloader specific settings, to ensure the compiler doesn't locate any code or variables at his location. */ +volatile uint32_t m_uicr_bootloader_start_address __attribute__ ((section(".uicrBootStartAddress"))) = BOOTLOADER_REGION_START; /**< This variable ensures that the linker script will write the bootloader start address to the UICR register. This value will be written in the HEX file and thus written to UICR when the bootloader is flashed into the chip. */ + +#elif defined ( __ICCARM__ ) + +__no_init uint8_t m_boot_settings[CODE_PAGE_SIZE] @ BOOTLOADER_SETTINGS_ADDRESS; /**< This variable reserves a codepage for bootloader specific settings, to ensure the compiler doesn't locate any code or variables at his location. */ +__root const uint32_t m_uicr_bootloader_start_address @ NRF_UICR_BOOT_START_ADDRESS = BOOTLOADER_REGION_START; /**< This variable ensures that the linker script will write the bootloader start address to the UICR register. This value will be written in the HEX file and thus written to UICR when the bootloader is flashed into the chip. */ + +#endif + +#if defined ( NRF52 ) +#if defined ( __CC_ARM ) + +uint8_t m_mbr_params_page[CODE_PAGE_SIZE] __attribute__((at(BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS))) __attribute__((used)); /**< This variable reserves a codepage for mbr parameters, to ensure the compiler doesn't locate any code or variables at his location. */ +uint32_t m_uicr_mbr_params_page_address __attribute__((at(NRF_UICR_MBR_PARAMS_PAGE_ADDRESS))) + = BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS; /**< This variable makes the linker script write the mbr parameters page address to the UICR register. This value will be written in the HEX file and thus written to the UICR when the bootloader is flashed into the chip */ + +#elif defined (__GNUC__ ) + +uint8_t m_mbr_params_page[CODE_PAGE_SIZE] __attribute__ ((section(".mbrParamsPage"))); /**< This variable reserves a codepage for mbr parameters, to ensure the compiler doesn't locate any code or variables at his location. */ +volatile uint32_t m_uicr_mbr_params_page_address __attribute__ ((section(".uicrMbrParamsPageAddress"))) + = BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS; /**< This variable makes the linker script write the mbr parameters page address to the UICR register. This value will be written in the HEX file and thus written to the UICR when the bootloader is flashed into the chip */ + +#elif defined (__ICCARM__ ) + +__no_init uint8_t m_mbr_params_page[CODE_PAGE_SIZE] @ BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS; /**< This variable reserves a codepage for bootloader specific settings, to ensure the compiler doesn't locate any code or variables at his location. */ +__root const uint32_t m_uicr_mbr_params_page_address @ NRF_UICR_MBR_PARAMS_PAGE_ADDRESS = BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS; /**< This variable ensures that the linker script will write the bootloader start address to the UICR register. This value will be written in the HEX file and thus written to UICR when the bootloader is flashed into the chip. */ + +#endif +#endif //defined ( NRF52 ) + + +void bootloader_util_settings_get(const bootloader_settings_t ** pp_bootloader_settings) +{ + // Read only pointer to bootloader settings in flash. + bootloader_settings_t const * const p_bootloader_settings = + (bootloader_settings_t *)&m_boot_settings[0]; + + *pp_bootloader_settings = p_bootloader_settings; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.h new file mode 100644 index 0000000..27e05d3 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_settings.h @@ -0,0 +1,35 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + + /**@file + * + * @defgroup nrf_bootloader_settings Bootloader settings API. + * @{ + * + * @brief Bootloader settings module interface. + */ + +#ifndef BOOTLOADER_SETTINGS_H__ +#define BOOTLOADER_SETTINGS_H__ + +#include +#include "bootloader_types.h" + +/**@brief Function for getting the bootloader settings. + * + * @param[out] pp_bootloader_settings Bootloader settings. + */ +void bootloader_util_settings_get(const bootloader_settings_t ** pp_bootloader_settings); + +#endif // BOOTLOADER_SETTINGS_H__ + +/**@} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_types.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_types.h new file mode 100644 index 0000000..a6ce32d --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_types.h @@ -0,0 +1,59 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup nrf_bootloader_types Types and definitions. + * @{ + * + * @ingroup nrf_bootloader + * + * @brief Bootloader module type and definitions. + */ + +#ifndef BOOTLOADER_TYPES_H__ +#define BOOTLOADER_TYPES_H__ + +#include + +#define BOOTLOADER_DFU_START 0xB1 + +#define BOOTLOADER_SVC_APP_DATA_PTR_GET 0x02 + +/**@brief DFU Bank state code, which indicates wether the bank contains: A valid image, invalid image, or an erased flash. + */ +typedef enum +{ + BANK_VALID_APP = 0x01, + BANK_VALID_SD = 0xA5, + BANK_VALID_BOOT = 0xAA, + BANK_ERASED = 0xFE, + BANK_INVALID_APP = 0xFF, +} bootloader_bank_code_t; + +/**@brief Structure holding bootloader settings for application and bank data. + */ +typedef struct +{ + bootloader_bank_code_t bank_0; /**< Variable to store if bank 0 contains a valid application. */ + uint16_t bank_0_crc; /**< If bank is valid, this field will contain a valid CRC of the total image. */ + bootloader_bank_code_t bank_1; /**< Variable to store if bank 1 has been erased/prepared for new image. Bank 1 is only used in Banked Update scenario. */ + uint32_t bank_0_size; /**< Size of active image in bank0 if present, otherwise 0. */ + uint32_t sd_image_size; /**< Size of SoftDevice image in bank0 if bank_0 code is BANK_VALID_SD. */ + uint32_t bl_image_size; /**< Size of Bootloader image in bank0 if bank_0 code is BANK_VALID_SD. */ + uint32_t app_image_size; /**< Size of Application image in bank0 if bank_0 code is BANK_VALID_SD. */ + uint32_t sd_image_start; /**< Location in flash where SoftDevice image is stored for SoftDevice update. */ +} bootloader_settings_t; + +#endif // BOOTLOADER_TYPES_H__ + +/**@} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.c new file mode 100644 index 0000000..0a8a213 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.c @@ -0,0 +1,152 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "bootloader_util.h" +#include +#include + + +/** + * @brief Function for aborting current application/bootloader jump to to other app/bootloader. + * + * @details This functions will use the address provide to swap the stack pointer and then load + * the address of the reset handler to be executed. It will check current system mode + * (thread/handler) and if in thread mode it will reset into other application. + * If in handler mode \ref isr_abort will be executed to ensure correct exit of handler + * mode and jump into reset handler of other application. + * + * @param[in] start_addr Start address of other application. This address must point to the + initial stack pointer of the application. + * + * @note This function will never return but issue a reset into provided application. + */ +#if defined ( __CC_ARM ) +__asm static void bootloader_util_reset(uint32_t start_addr) +{ + LDR R5, [R0] ; Get App initial MSP for bootloader. + MSR MSP, R5 ; Set the main stack pointer to the applications MSP. + LDR R0, [R0, #0x04] ; Load Reset handler into R0. This will be first argument to branch instruction (BX). + + MOVS R4, #0xFF ; Load ones to R4. + SXTB R4, R4 ; Sign extend R4 to obtain 0xFFFFFFFF instead of 0xFF. + MRS R5, IPSR ; Load IPSR to R5 to check for handler or thread mode. + CMP R5, #0x00 ; Compare, if 0 then we are in thread mode and can continue to reset handler of bootloader. + BNE isr_abort ; If not zero we need to exit current ISR and jump to reset handler of bootloader. + + MOV LR, R4 ; Clear the link register and set to ones to ensure no return, R4 = 0xFFFFFFFF. + BX R0 ; Branch to reset handler of bootloader. + +isr_abort + ; R4 contains ones from line above. Will be popped as R12 when exiting ISR (Cleaning up the registers). + MOV R5, R4 ; Fill with ones before jumping to reset handling. We be popped as LR when exiting ISR. Ensures no return to application. + MOV R6, R0 ; Move address of reset handler to R6. Will be popped as PC when exiting ISR. Ensures the reset handler will be executed when exist ISR. + MOVS r7, #0x21 ; Move MSB reset value of xPSR to R7. Will be popped as xPSR when exiting ISR. xPSR is 0x21000000 thus MSB is 0x21. + REV r7, r7 ; Reverse byte order to put 0x21 as MSB. + PUSH {r4-r7} ; Push everything to new stack to allow interrupt handler to fetch it on exiting the ISR. + + MOVS R4, #0x00 ; Fill with zeros before jumping to reset handling. We be popped as R0 when exiting ISR (Cleaning up of the registers). + MOVS R5, #0x00 ; Fill with zeros before jumping to reset handling. We be popped as R1 when exiting ISR (Cleaning up of the registers). + MOVS R6, #0x00 ; Fill with zeros before jumping to reset handling. We be popped as R2 when exiting ISR (Cleaning up of the registers). + MOVS R7, #0x00 ; Fill with zeros before jumping to reset handling. We be popped as R3 when exiting ISR (Cleaning up of the registers). + PUSH {r4-r7} ; Push zeros (R4-R7) to stack to prepare for exiting the interrupt routine. + + MOVS R0, #0xF9 ; Move the execution return command into register, 0xFFFFFFF9. + SXTB R0, R0 ; Sign extend R0 to obtain 0xFFFFFFF9 instead of 0xF9. + BX R0 ; No return - Handler mode will be exited. Stack will be popped and execution will continue in reset handler initializing other application. + ALIGN +} +#elif defined ( __GNUC__ ) +static inline void bootloader_util_reset(uint32_t start_addr) +{ + __asm volatile( + "ldr r0, [%0]\t\n" // Get App initial MSP for bootloader. + "msr msp, r0\t\n" // Set the main stack pointer to the applications MSP. + "ldr r0, [%0, #0x04]\t\n" // Load Reset handler into R0. + + "movs r4, #0xFF\t\n" // Move ones to R4. + "sxtb r4, r4\t\n" // Sign extend R4 to obtain 0xFFFFFFFF instead of 0xFF. + + "mrs r5, IPSR\t\n" // Load IPSR to R5 to check for handler or thread mode. + "cmp r5, #0x00\t\n" // Compare, if 0 then we are in thread mode and can continue to reset handler of bootloader. + "bne isr_abort\t\n" // If not zero we need to exit current ISR and jump to reset handler of bootloader. + + "mov lr, r4\t\n" // Clear the link register and set to ones to ensure no return. + "bx r0\t\n" // Branch to reset handler of bootloader. + + "isr_abort: \t\n" + + "mov r5, r4\t\n" // Fill with ones before jumping to reset handling. Will be popped as LR when exiting ISR. Ensures no return to application. + "mov r6, r0\t\n" // Move address of reset handler to R6. Will be popped as PC when exiting ISR. Ensures the reset handler will be executed when exist ISR. + "movs r7, #0x21\t\n" // Move MSB reset value of xPSR to R7. Will be popped as xPSR when exiting ISR. xPSR is 0x21000000 thus MSB is 0x21. + "rev r7, r7\t\n" // Reverse byte order to put 0x21 as MSB. + "push {r4-r7}\t\n" // Push everything to new stack to allow interrupt handler to fetch it on exiting the ISR. + + "movs r4, #0x00\t\n" // Fill with zeros before jumping to reset handling. We be popped as R0 when exiting ISR (Cleaning up of the registers). + "movs r5, #0x00\t\n" // Fill with zeros before jumping to reset handling. We be popped as R1 when exiting ISR (Cleaning up of the registers). + "movs r6, #0x00\t\n" // Fill with zeros before jumping to reset handling. We be popped as R2 when exiting ISR (Cleaning up of the registers). + "movs r7, #0x00\t\n" // Fill with zeros before jumping to reset handling. We be popped as R3 when exiting ISR (Cleaning up of the registers). + "push {r4-r7}\t\n" // Push zeros (R4-R7) to stack to prepare for exiting the interrupt routine. + + "movs r0, #0xF9\t\n" // Move the execution return command into register, 0xFFFFFFF9. + "sxtb r0, r0\t\n" // Sign extend R0 to obtain 0xFFFFFFF9 instead of 0xF9. + "bx r0\t\n" // No return - Handler mode will be exited. Stack will be popped and execution will continue in reset handler initializing other application. + ".align\t\n" + :: "r" (start_addr) // Argument list for the gcc assembly. start_addr is %0. + : "r0", "r4", "r5", "r6", "r7" // List of register maintained manually. + ); +} +#elif defined ( __ICCARM__ ) +static inline void bootloader_util_reset(uint32_t start_addr) +{ + asm("ldr r5, [%0]\n" // Get App initial MSP for bootloader. + "msr msp, r5\n" // Set the main stack pointer to the applications MSP. + "ldr r0, [%0, #0x04]\n" // Load Reset handler into R0. + + "movs r4, #0x00\n" // Load zero into R4. + "mvns r4, r4\n" // Invert R4 to ensure it contain ones. + + "mrs r5, IPSR\n" // Load IPSR to R5 to check for handler or thread mode + "cmp r5, #0x00\n" // Compare, if 0 then we are in thread mode and can continue to reset handler of bootloader. + "bne.n isr_abort\n" // If not zero we need to exit current ISR and jump to reset handler of bootloader. + + "mov lr, r4\n" // Clear the link register and set to ones to ensure no return. + "bx r0\n" // Branch to reset handler of bootloader. + + "isr_abort: \n" + // R4 contains ones from line above. We be popped as R12 when exiting ISR (Cleaning up the registers). + "mov r5, r4\n" // Fill with ones before jumping to reset handling. Will be popped as LR when exiting ISR. Ensures no return to application. + "mov r6, r0\n" // Move address of reset handler to R6. Will be popped as PC when exiting ISR. Ensures the reset handler will be executed when exist ISR. + "movs r7, #0x21\n" // Move MSB reset value of xPSR to R7. Will be popped as xPSR when exiting ISR. xPSR is 0x21000000 thus MSB is 0x21. + "rev r7, r7\n" // Reverse byte order to put 0x21 as MSB. + "push {r4-r7}\n" // Push everything to new stack to allow interrupt handler to fetch it on exiting the ISR. + + "movs r4, #0x00\n" // Fill with zeros before jumping to reset handling. We be popped as R0 when exiting ISR (Cleaning up of the registers). + "movs r5, #0x00\n" // Fill with zeros before jumping to reset handling. We be popped as R1 when exiting ISR (Cleaning up of the registers). + "movs r6, #0x00\n" // Fill with zeros before jumping to reset handling. We be popped as R2 when exiting ISR (Cleaning up of the registers). + "movs r7, #0x00\n" // Fill with zeros before jumping to reset handling. We be popped as R3 when exiting ISR (Cleaning up of the registers). + "push {r4-r7}\n" // Push zeros (R4-R7) to stack to prepare for exiting the interrupt routine. + + "movs r0, #0x06\n" // Load 0x06 into R6 to prepare for exec return command. + "mvns r0, r0\n" // Invert 0x06 to obtain EXEC_RETURN, 0xFFFFFFF9. + "bx r0\n" // No return - Handler mode will be exited. Stack will be popped and execution will continue in reset handler initializing other application. + :: "r" (start_addr) // Argument list for the IAR assembly. start_addr is %0. + : "r0", "r4", "r5", "r6", "r7"); // List of register maintained manually. +} +#else +#error Compiler not supported. +#endif + + +void bootloader_util_app_start(uint32_t start_addr) +{ + bootloader_util_reset(start_addr); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.h new file mode 100644 index 0000000..aefd764 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/bootloader_util.h @@ -0,0 +1,38 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + + /**@file + * + * @defgroup nrf_bootloader_util Bootloader util API. + * @{ + * + * @brief Bootloader util module interface. + */ + +#ifndef BOOTLOADER_UTIL_H__ +#define BOOTLOADER_UTIL_H__ + +#include +#include "bootloader_types.h" + +/**@brief Function for starting the application (or bootloader) at the provided address. + * + * @param[in] start_addr Start address. + * + * @note This function will never retrun. Instead it will reset into the application of the + * provided address. + */ +void bootloader_util_app_start(uint32_t start_addr); + +#endif // BOOTLOADER_UTIL_H__ + +/**@} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu.h new file mode 100644 index 0000000..8916b7a --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu.h @@ -0,0 +1,134 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup nrf_dfu Device Firmware Update API. + * @{ + * + * @brief Device Firmware Update module interface. + */ + +#ifndef DFU_H__ +#define DFU_H__ + +#include +#include +#include + + +/**@brief DFU event callback for asynchronous calls. + * + * @param[in] packet Packet type for which this callback is related. START_PACKET, DATA_PACKET. + * @param[in] result Operation result code. NRF_SUCCESS when a queued operation was successful. + * @param[in] p_data Pointer to the data to which the operation is related. + */ +typedef void (*dfu_callback_t)(uint32_t packet, uint32_t result, uint8_t * p_data); + +/**@brief Function for initializing the Device Firmware Update module. + * + * @return NRF_SUCCESS on success, an error_code otherwise. + */ +uint32_t dfu_init(void); + +/**@brief Function for registering a callback listener for \ref dfu_data_pkt_handle callbacks. + * + * @param[in] callback_handler Callback handler for receiving DFU events on completed operations + * of DFU packets. + */ +void dfu_register_callback(dfu_callback_t callback_handler); + +/**@brief Function for setting the DFU image size. + * + * @details Function sets the DFU image size. This function must be called when an update is started + * in order to notify the DFU of the new image size. If multiple images are to be + * transferred within the same update context then this function must be called with size + * information for each image being transfered. + * If an image type is not being transfered, e.g. SoftDevice but no Application , then the + * image size for application must be zero. + * + * @param[in] p_packet Pointer to the DFU packet containing information on DFU update process to + * be started. + * + * @return NRF_SUCCESS on success, an error_code otherwise. + */ +uint32_t dfu_start_pkt_handle(dfu_update_packet_t * p_packet); + +/**@brief Function for handling DFU data packets. + * + * @param[in] p_packet Pointer to the DFU packet. + * + * @return NRF_SUCCESS on success, an error_code otherwise. + */ +uint32_t dfu_data_pkt_handle(dfu_update_packet_t * p_packet); + +/**@brief Function for handling DFU init packets. + * + * @return NRF_SUCCESS on success, an error_code otherwise. + */ +uint32_t dfu_init_pkt_handle(dfu_update_packet_t * p_packet); + +/**@brief Function for validating a transferred image after the transfer has completed. + * + * @return NRF_SUCCESS on success, an error_code otherwise. + */ +uint32_t dfu_image_validate(void); + +/**@brief Function for activating the transfered image after validation has successfully completed. + * + * @return NRF_SUCCESS on success, an error_code otherwise. + */ +uint32_t dfu_image_activate(void); + +/**@brief Function for reseting the current update procedure and return to initial state. + * + * @details This function call will result in a system reset to ensure correct system behavior. + * The reset will might be scheduled to execute at a later point in time to ensure pending + * flash operations has completed. + */ +void dfu_reset(void); + +/**@brief Function for validating that new bootloader has been correctly installed. + * + * @return NRF_SUCCESS if install was successful. NRF_ERROR_NULL if the images differs. + */ +uint32_t dfu_bl_image_validate(void); + +/**@brief Function for validating that new SoftDevicehas been correctly installed. + * + * @return NRF_SUCCESS if install was successful. NRF_ERROR_NULL if the images differs. + */ +uint32_t dfu_sd_image_validate(void); + +/**@brief Function for swapping existing bootloader with newly received. + * + * @return NRF_SUCCESS on succesfull swapping. For error code please refer to + * \ref sd_mbr_command_copy_bl_t. + */ +uint32_t dfu_bl_image_swap(void); + +/**@brief Function for swapping existing SoftDevice with newly received. + * + * @return NRF_SUCCESS on succesfull swapping. For error code please refer to + * \ref sd_mbr_command_copy_sd_t. + */ +uint32_t dfu_sd_image_swap(void); + +/**@brief Function for handling DFU init packet complete. + * + * @return NRF_SUCCESS on success, an error_code otherwise. + */ +uint32_t dfu_init_pkt_complete(void); + +#endif // DFU_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_app_handler.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_app_handler.c new file mode 100644 index 0000000..6180c40 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_app_handler.c @@ -0,0 +1,192 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "dfu_app_handler.h" +#include +#include "bootloader_util.h" +#include "nrf.h" +#include "nrf_sdm.h" +#include "ble_gatt.h" +#include "ble_gatts.h" +#include "app_error.h" +#include "dfu_ble_svc.h" +#include "device_manager.h" +#include "nrf_delay.h" + +#define IRQ_ENABLED 0x01 /**< Field that identifies if an interrupt is enabled. */ +#define MAX_NUMBER_INTERRUPTS 32 /**< Maximum number of interrupts available. */ + +static void dfu_app_reset_prepare(void); /**< Forward declaration of default reset handler. */ +static dfu_app_reset_prepare_t m_reset_prepare = dfu_app_reset_prepare; /**< Callback function to application to prepare for system reset. Allows application to clean up service and memory before reset. */ +static dfu_ble_peer_data_t m_peer_data; /**< Peer data to be used for data exchange when resetting into DFU mode. */ +static dm_handle_t m_dm_handle; /**< Device Manager handle with instance IDs of current BLE connection. */ + + +/**@brief Function for reset_prepare handler if the application has not registered a handler. + */ +static void dfu_app_reset_prepare(void) +{ + // Reset prepare should be handled by application. + // This function can be extended to include default handling if application does not implement + // own handler. +} + + +/**@brief Function for disabling all interrupts before jumping from bootloader to application. + */ +static void interrupts_disable(void) +{ + uint32_t interrupt_setting_mask; + uint32_t irq; + + // Fetch the current interrupt settings. + interrupt_setting_mask = NVIC->ISER[0]; + + // Loop from interrupt 0 for disabling of all interrupts. + for (irq = 0; irq < MAX_NUMBER_INTERRUPTS; irq++) + { + if (interrupt_setting_mask & (IRQ_ENABLED << irq)) + { + // The interrupt was enabled, hence disable it. + NVIC_DisableIRQ((IRQn_Type)irq); + } + } +} + + +/**@brief Function for providing peer information to DFU for re-establishing a bonded connection in + * DFU mode. + * + * @param[in] conn_handle Connection handle for the connection requesting DFU mode. + */ +static void dfu_app_peer_data_set(uint16_t conn_handle) +{ + uint32_t err_code; + dm_sec_keyset_t key_set; + uint32_t app_context_data = 0; + dm_application_context_t app_context; + + +/** [DFU bond sharing] */ + err_code = dm_handle_get(conn_handle, &m_dm_handle); + if (err_code == NRF_SUCCESS) + { + err_code = dm_distributed_keys_get(&m_dm_handle, &key_set); + if (err_code == NRF_SUCCESS) + { + APP_ERROR_CHECK(err_code); + + m_peer_data.addr = key_set.keys_central.p_id_key->id_addr_info; + m_peer_data.irk = key_set.keys_central.p_id_key->id_info; + m_peer_data.enc_key.enc_info = key_set.keys_periph.enc_key.p_enc_key->enc_info; + m_peer_data.enc_key.master_id = key_set.keys_periph.enc_key.p_enc_key->master_id; + + err_code = dfu_ble_svc_peer_data_set(&m_peer_data); + APP_ERROR_CHECK(err_code); + + app_context_data = (DFU_APP_ATT_TABLE_CHANGED << DFU_APP_ATT_TABLE_POS); + app_context.len = sizeof(app_context_data); + app_context.p_data = (uint8_t *)&app_context_data; + app_context.flags = 0; + + err_code = dm_application_context_set(&m_dm_handle, &app_context); + APP_ERROR_CHECK(err_code); + } + else + { + // Keys were not available, thus we have a non-encrypted connection. + err_code = dm_peer_addr_get(&m_dm_handle, &m_peer_data.addr); + APP_ERROR_CHECK(err_code); + + err_code = dfu_ble_svc_peer_data_set(&m_peer_data); + APP_ERROR_CHECK(err_code); + } + } +/** [DFU bond sharing] */ +} + + +/**@brief Function for preparing the reset, disabling SoftDevice, and jumping to the bootloader. + * + * @param[in] conn_handle Connection handle for peer requesting to enter DFU mode. + */ +static void bootloader_start(uint16_t conn_handle) +{ + uint32_t err_code; + uint16_t sys_serv_attr_len = sizeof(m_peer_data.sys_serv_attr); + + err_code = sd_ble_gatts_sys_attr_get(conn_handle, + m_peer_data.sys_serv_attr, + &sys_serv_attr_len, + BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS); + if (err_code != NRF_SUCCESS) + { + // Any error at this stage means the system service attributes could not be fetched. + // This means the service changed indication cannot be sent in DFU mode, but connection + // is still possible to establish. + } + + m_reset_prepare(); + + err_code = sd_power_gpregret_set(BOOTLOADER_DFU_START); + APP_ERROR_CHECK(err_code); + + err_code = sd_softdevice_disable(); + APP_ERROR_CHECK(err_code); + + err_code = sd_softdevice_vector_table_base_set(NRF_UICR->NRFFW[0]); + APP_ERROR_CHECK(err_code); + + dfu_app_peer_data_set(conn_handle); + + NVIC_ClearPendingIRQ(SWI2_IRQn); + interrupts_disable(); + bootloader_util_app_start(NRF_UICR->NRFFW[0]); +} + + +void dfu_app_on_dfu_evt(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt) +{ + switch (p_evt->ble_dfu_evt_type) + { + case BLE_DFU_START: + // Starting the bootloader - will cause reset. + bootloader_start(p_dfu->conn_handle); + break; + + default: + { + // Unsupported event received from DFU Service. + // Send back BLE_DFU_RESP_VAL_NOT_SUPPORTED message to peer. + uint32_t err_code = ble_dfu_response_send(p_dfu, + BLE_DFU_START_PROCEDURE, + BLE_DFU_RESP_VAL_NOT_SUPPORTED); + APP_ERROR_CHECK(err_code); + } + break; + } +} + + +void dfu_app_reset_prepare_set(dfu_app_reset_prepare_t reset_prepare_func) +{ + m_reset_prepare = reset_prepare_func; +} + + +void dfu_app_dm_appl_instance_set(dm_application_instance_t app_instance) +{ + uint32_t err_code; + + err_code = dm_application_instance_set(&app_instance, &m_dm_handle); + APP_ERROR_CHECK(err_code); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_app_handler.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_app_handler.h new file mode 100644 index 0000000..b93bd26 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_app_handler.h @@ -0,0 +1,86 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup nrf_dfu_app_handler DFU BLE packet handling in application + * @{ + * + * @brief Handling of DFU BLE packets in the application. + * + * @details This module implements the handling of DFU packets for switching + * from an application to the bootloader and start DFU mode. The DFU + * packets are transmitted over BLE. + * This module handles only the StartDFU packet, which allows a BLE + * application to expose support for the DFU Service. + * The actual DFU Service runs in a dedicated environment after a BLE + * disconnect and reset of the \nRFXX device. + * The host must reconnect and continue the update procedure with + * access to the full DFU Service. + * + * @note The application must propagate DFU events to this module by calling + * @ref dfu_app_on_dfu_evt from the @ref ble_dfu_evt_handler_t callback. + */ + +#ifndef DFU_APP_HANDLER_H__ +#define DFU_APP_HANDLER_H__ + +#include "ble_dfu.h" +#include "nrf_svc.h" +#include "bootloader_types.h" +#include "device_manager.h" + +#define DFU_APP_ATT_TABLE_POS 0 /**< Position for the ATT table changed setting. */ +#define DFU_APP_ATT_TABLE_CHANGED 1 /**< Value indicating that the ATT table might have changed. This value will be set in the application-specific context in Device Manager when entering DFU mode. */ + +/**@brief DFU application reset_prepare function. This function is a callback that allows the + * application to prepare for an upcoming application reset. + */ +typedef void (*dfu_app_reset_prepare_t)(void); + +/**@brief Function for handling events from the DFU Service. + * + * @details The application must inject this function into the DFU Service or propagate DFU events + * to the dfu_app_handler module by calling this function in the application-specific DFU event + * handler. + * + * @param[in] p_dfu Pointer to the DFU Service structure to which the include event relates. + * @param[in] p_evt Pointer to the DFU event. + */ +void dfu_app_on_dfu_evt(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt); + +/**@brief Function for registering a function to prepare a reset. + * + * @details The provided function is executed before resetting the system into bootloader/DFU + * mode. By registering this function, the caller is notified before the reset and can + * thus prepare the application for reset. For example, the application can gracefully + * disconnect any peers on BLE, turn of LEDS, ensure that all pending flash operations + * have completed, and so on. + * + * @param[in] reset_prepare_func Function to be executed before a reset. + */ +void dfu_app_reset_prepare_set(dfu_app_reset_prepare_t reset_prepare_func); + +/**@brief Function for setting the Device Manager application instance. + * + * @details This function allows to set the @ref dm_application_instance_t value that is returned by the + * Device Manager when the application registers using @ref dm_register. + * If this function is not called, it is not be possible to share bonding information + * from the application to the bootloader/DFU when entering DFU mode. + * + * @param[in] app_instance Value for the application instance in use. + */ +void dfu_app_dm_appl_instance_set(dm_application_instance_t app_instance); + +#endif // DFU_APP_HANDLER_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_bank_internal.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_bank_internal.h new file mode 100644 index 0000000..b939622 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_bank_internal.h @@ -0,0 +1,87 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup dfu_bank_internal Device Firmware Update internal header for bank handling in DFU. + * @{ + * + * @brief Device Firmware Update Bank handling module interface. + * + * @details This header is intended for shared definition and functions between single and dual bank + * implementations used for DFU support. It is not supposed to be used for external access + * to the DFU module. + * + */ +#ifndef DFU_BANK_INTERNAL_H__ +#define DFU_BANK_INTERNAL_H__ + +#include + +/**@brief States of the DFU state machine. */ +typedef enum +{ + DFU_STATE_INIT_ERROR, /**< State for: dfu_init(...) error. */ + DFU_STATE_IDLE, /**< State for: idle. */ + DFU_STATE_PREPARING, /**< State for: preparing, indicates that the flash is being erased and no data packets can be processed. */ + DFU_STATE_RDY, /**< State for: ready. */ + DFU_STATE_RX_INIT_PKT, /**< State for: receiving initialization packet. */ + DFU_STATE_RX_DATA_PKT, /**< State for: receiving data packet. */ + DFU_STATE_VALIDATE, /**< State for: validate. */ + DFU_STATE_WAIT_4_ACTIVATE /**< State for: waiting for dfu_image_activate(). */ +} dfu_state_t; + +#define APP_TIMER_PRESCALER 0 /**< Value of the RTC1 PRESCALER register. */ +#define DFU_TIMEOUT_INTERVAL APP_TIMER_TICKS(300000, APP_TIMER_PRESCALER) /**< DFU timeout interval in units of timer ticks. */ + +#define IS_UPDATING_SD(START_PKT) ((START_PKT).dfu_update_mode & DFU_UPDATE_SD) /**< Macro for determining if a SoftDevice update is ongoing. */ +#define IS_UPDATING_BL(START_PKT) ((START_PKT).dfu_update_mode & DFU_UPDATE_BL) /**< Macro for determining if a Bootloader update is ongoing. */ +#define IS_UPDATING_APP(START_PKT) ((START_PKT).dfu_update_mode & DFU_UPDATE_APP) /**< Macro for determining if a Application update is ongoing. */ +#define IMAGE_WRITE_IN_PROGRESS() (m_data_received > 0) /**< Macro for determining if an image write is in progress. */ +#define IS_WORD_SIZED(SIZE) ((SIZE & (sizeof(uint32_t) - 1)) == 0) /**< Macro for checking that the provided is word sized. */ + +/**@cond NO_DOXYGEN */ +static uint32_t m_data_received; /**< Amount of received data. */ +/**@endcond */ + +/**@brief Type definition of function used for preparing of the bank before receiving of a + * software image. + * + * @param[in] image_size Size of software image being received. + */ +typedef void (*dfu_bank_prepare_t)(uint32_t image_size); + +/**@brief Type definition of function used for handling clear complete of the bank before + * receiving of a software image. + */ +typedef void (*dfu_bank_cleared_t)(void); + +/**@brief Type definition of function used for activating of the software image received. + * + * @return NRF_SUCCESS If the image has been successfully activated any other NRF_ERROR code in + * case of a failure. + */ +typedef uint32_t (*dfu_bank_activate_t)(void); + +/**@brief Structure for holding of function pointers for needed prepare and activate procedure for + * the requested update procedure. + */ +typedef struct +{ + dfu_bank_prepare_t prepare; /**< Function pointer to the prepare function called on start of update procedure. */ + dfu_bank_cleared_t cleared; /**< Function pointer to the cleared function called after prepare function completes. */ + dfu_bank_activate_t activate; /**< Function pointer to the activate function called on finalizing the update procedure. */ +} dfu_bank_func_t; + +#endif // DFU_BANK_INTERNAL_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc.h new file mode 100644 index 0000000..5e5ae4b --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc.h @@ -0,0 +1,80 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup nrf_dfu_ble_svc DFU BLE SVC + * @{ + * + * @brief DFU BLE SVC in bootloader. The DFU BLE SuperVisor Calls allow an application to execute + * functions in the installed bootloader. + * + * @details This module implements handling of SuperVisor Calls in the bootloader. + * SuperVisor Calls allow for an application to execute calls into the bootloader. + * Currently, it is possible to exchange bonding information (like keys) from the + * application to a bootloader supporting DFU OTA using BLE, so the update process can be + * done through an already existing bond. + * + * @note The application must make sure that all SuperVisor Calls (SVC) are forwarded to the + * bootloader to ensure correct behavior. Forwarding of SVCs to the bootloader is + * done using the SoftDevice SVC @ref sd_softdevice_vector_table_base_set with the value + * present in @c NRF_UICR->NRFFW[0]. + */ + +#ifndef DFU_BLE_SVC_H__ +#define DFU_BLE_SVC_H__ + +#include "nrf_svc.h" +#include +#include "ble_gap.h" +#include "nrf.h" +#include "nrf_soc.h" +#include "nrf_error_sdm.h" + +#define BOOTLOADER_SVC_BASE 0x0 /**< The number of the lowest SVC number reserved for the bootloader. */ +#define SYSTEM_SERVICE_ATT_SIZE 8 /**< Size of the system service attribute length including CRC-16 at the end. */ + +/**@brief The SVC numbers used by the SVC functions in the SoC library. */ +enum BOOTLOADER_SVCS +{ + DFU_BLE_SVC_PEER_DATA_SET = BOOTLOADER_SVC_BASE, /**< SVC number for the setting of peer data call. */ + BOOTLOADER_SVC_LAST +}; + +/**@brief DFU Peer data structure. + * + * @details This structure contains peer data needed for connection to a bonded device during DFU. + * The peer data must be provided by the application to the bootloader during buttonless + * update. See @ref dfu_ble_svc_peer_data_set. It contains bond information about the + * desired DFU peer. + */ +typedef struct +{ + ble_gap_addr_t addr; /**< BLE GAP address of the device that initiated the DFU process. */ + ble_gap_irk_t irk; /**< IRK of the device that initiated the DFU process if this device uses Private Resolvable Addresses. */ + ble_gap_enc_key_t enc_key; /**< Encryption key structure containing encrypted diversifier and LTK for re-establishing the bond. */ + uint8_t sys_serv_attr[SYSTEM_SERVICE_ATT_SIZE]; /**< System service attributes for restoring of Service Changed Indication setting in DFU mode. */ +} dfu_ble_peer_data_t; + +/**@brief SVC Function for setting peer data containing address, IRK, and LTK to establish bonded + * connection in DFU mode. + * + * @param[in] p_peer_data Pointer to the peer data containing keys for the connection. + * + * @retval NRF_ERROR_NULL If a NULL pointer was provided as argument. + * @retval NRF_SUCCESS If the function completed successfully. + */ +SVCALL(DFU_BLE_SVC_PEER_DATA_SET, uint32_t, dfu_ble_svc_peer_data_set(dfu_ble_peer_data_t * p_peer_data)); + +#endif // DFU_BLE_SVC_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc_internal.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc_internal.h new file mode 100644 index 0000000..0b6e5d4 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_ble_svc_internal.h @@ -0,0 +1,43 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup nrf_dfu_ble_svc_internal DFU BLE SVC internal + * @{ + * + * @brief DFU BLE SVC internal functions in bootloader. The DFU BLE SuperVisor Calls allow an + * application to execute functions in the installed bootloader. This interface provides + * internal Bootloader DFU functions for retrieving data exchanged through SuperVisor Calls. + * + */ + +#ifndef DFU_BLE_SVC_INTERNAL_H__ +#define DFU_BLE_SVC_INTERNAL_H__ + +#include +#include "dfu_ble_svc.h" +#include "ble_gap.h" + +/**@brief Internal bootloader/DFU function for retrieving peer data provided from application. + * + * @param[out] p_peer_data Peer data set by application to be used for DFU connection. + * + * @retval NRF_SUCCESS If peer data is valid and can be used for connection. + * @retval NRF_ERROR_NULL If p_peer_data is a NULL pointer. + * @retval NRF_ERROR_INVALID_DATA If peer data is not available or invalid. + */ +uint32_t dfu_ble_peer_data_get(dfu_ble_peer_data_t * p_peer_data); + +#endif // DFU_BLE_SVC_INTERNAL_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_dual_bank.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_dual_bank.c new file mode 100644 index 0000000..99f3d45 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_dual_bank.c @@ -0,0 +1,840 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include +#include "dfu.h" +#include +#include "dfu_bank_internal.h" +#include "nrf.h" +#include "nrf_sdm.h" +#include "app_error.h" +#include "app_timer.h" +#include "bootloader.h" +#include "bootloader_types.h" +#include "pstorage.h" +#include "nrf_mbr.h" +#include "dfu_init.h" +#include "sdk_common.h" + +static dfu_state_t m_dfu_state; /**< Current DFU state. */ +static uint32_t m_image_size; /**< Size of the image that will be transmitted. */ + +static dfu_start_packet_t m_start_packet; /**< Start packet received for this update procedure. Contains update mode and image sizes information to be used for image transfer. */ +static uint8_t m_init_packet[128]; /**< Init packet, can hold CRC, Hash, Signed Hash and similar, for image validation, integrety check and authorization checking. */ +static uint8_t m_init_packet_length; /**< Length of init packet received. */ +static uint16_t m_image_crc; /**< Calculated CRC of the image received. */ + +APP_TIMER_DEF(m_dfu_timer_id); /**< Application timer id. */ +static bool m_dfu_timed_out = false; /**< Boolean flag value for tracking DFU timer timeout state. */ + +static pstorage_handle_t m_storage_handle_swap; /**< Pstorage handle for the swap area (bank 1). Bank used when updating an application or bootloader without SoftDevice. */ +static pstorage_handle_t m_storage_handle_app; /**< Pstorage handle for the application area (bank 0). Bank used when updating a SoftDevice w/wo bootloader. Handle also used when swapping received application from bank 1 to bank 0. */ +static pstorage_handle_t * mp_storage_handle_active; /**< Pointer to the pstorage handle for the active bank for receiving of data packets. */ + +static dfu_callback_t m_data_pkt_cb; /**< Callback from DFU Bank module for notification of asynchronous operation such as flash prepare. */ +static dfu_bank_func_t m_functions; /**< Structure holding operations for the selected update process. */ + + +/**@brief Function for handling callbacks from pstorage module. + * + * @details Handles pstorage results for clear and storage operation. For detailed description of + * the parameters provided with the callback, please refer to \ref pstorage_ntf_cb_t. + */ +static void pstorage_callback_handler(pstorage_handle_t * p_handle, + uint8_t op_code, + uint32_t result, + uint8_t * p_data, + uint32_t data_len) +{ + switch (op_code) + { + case PSTORAGE_STORE_OP_CODE: + if ((m_dfu_state == DFU_STATE_RX_DATA_PKT) && (m_data_pkt_cb != NULL)) + { + m_data_pkt_cb(DATA_PACKET, result, p_data); + } + break; + + case PSTORAGE_CLEAR_OP_CODE: + if (m_dfu_state == DFU_STATE_PREPARING) + { + m_functions.cleared(); + m_dfu_state = DFU_STATE_RDY; + if (m_data_pkt_cb != NULL) + { + m_data_pkt_cb(START_PACKET, result, p_data); + } + } + break; + + default: + break; + } + APP_ERROR_CHECK(result); +} + + +/**@brief Function for handling the DFU timeout. + * + * @param[in] p_context The timeout context. + */ +static void dfu_timeout_handler(void * p_context) +{ + UNUSED_PARAMETER(p_context); + dfu_update_status_t update_status; + + m_dfu_timed_out = true; + update_status.status_code = DFU_TIMEOUT; + + bootloader_dfu_update_process(update_status); +} + + +/**@brief Function for restarting the DFU Timer. + * + * @details This function will stop and restart the DFU timer. This function will be called by the + * functions handling any DFU packet received from the peer that is transferring a firmware + * image. + */ +static uint32_t dfu_timer_restart(void) +{ + if (m_dfu_timed_out) + { + // The DFU timer had already timed out. + return NRF_ERROR_INVALID_STATE; + } + + uint32_t err_code = app_timer_stop(m_dfu_timer_id); + APP_ERROR_CHECK(err_code); + + err_code = app_timer_start(m_dfu_timer_id, DFU_TIMEOUT_INTERVAL, NULL); + APP_ERROR_CHECK(err_code); + + return err_code; +} + + +/**@brief Function for preparing of flash before receiving SoftDevice image. + * + * @details This function will erase current application area to ensure sufficient amount of + * storage for the SoftDevice image. Upon erase complete a callback will be done. + * See \ref dfu_bank_prepare_t for further details. + */ +static void dfu_prepare_func_app_erase(uint32_t image_size) +{ + uint32_t err_code; + + mp_storage_handle_active = &m_storage_handle_app; + + // Doing a SoftDevice update thus current application must be cleared to ensure enough space + // for new SoftDevice. + m_dfu_state = DFU_STATE_PREPARING; + err_code = pstorage_clear(&m_storage_handle_app, m_image_size); + APP_ERROR_CHECK(err_code); +} + + +/**@brief Function for preparing swap before receiving application or bootloader image. + * + * @details This function will erase current swap area to ensure flash is ready for storage of the + * Application or Bootloader image. Upon erase complete a callback will be done. + * See \ref dfu_bank_prepare_t for further details. + */ +static void dfu_prepare_func_swap_erase(uint32_t image_size) +{ + uint32_t err_code; + + mp_storage_handle_active = &m_storage_handle_swap; + + m_dfu_state = DFU_STATE_PREPARING; +// err_code = pstorage_clear(&m_storage_handle_swap, DFU_IMAGE_MAX_SIZE_BANKED); + err_code = pstorage_clear(&m_storage_handle_swap, image_size); + APP_ERROR_CHECK(err_code); +} + + +/**@brief Function for handling behaviour when clear operation has completed. + */ +static void dfu_cleared_func_swap(void) +{ + // Do nothing. +} + + +/**@brief Function for handling behaviour when clear operation has completed. + */ +static void dfu_cleared_func_app(void) +{ + dfu_update_status_t update_status = {DFU_BANK_0_ERASED, }; + bootloader_dfu_update_process(update_status); +} + + +/**@brief Function for calculating storage offset for receiving SoftDevice image. + * + * @details When a new SoftDevice is received it will be temporary stored in flash before moved to + * address 0x0. In order to succesfully validate transfer and relocation it is important + * that temporary image and final installed image does not ovwerlap hence an offset must + * be calculated in case new image is larger than currently installed SoftDevice. + */ +uint32_t offset_calculate(uint32_t sd_image_size) +{ + uint32_t offset = 0; + + if (m_start_packet.sd_image_size > DFU_BANK_0_REGION_START) + { + uint32_t page_mask = (CODE_PAGE_SIZE - 1); + uint32_t diff = m_start_packet.sd_image_size - DFU_BANK_0_REGION_START; + + offset = diff & ~page_mask; + + // Align offset to next page if image size is not page sized. + if ((diff & page_mask) > 0) + { + offset += CODE_PAGE_SIZE; + } + } + + return offset; +} + + +/**@brief Function for activating received SoftDevice image. + * + * @note This function will not move the SoftDevice image. + * The bootloader settings will be marked as SoftDevice update complete and the swapping of + * current SoftDevice will occur after system reset. + * + * @return NRF_SUCCESS on success. + */ +static uint32_t dfu_activate_sd(void) +{ + dfu_update_status_t update_status; + + update_status.status_code = DFU_UPDATE_SD_COMPLETE; + update_status.app_crc = m_image_crc; + update_status.sd_image_start = DFU_BANK_0_REGION_START; + update_status.sd_size = m_start_packet.sd_image_size; + update_status.bl_size = m_start_packet.bl_image_size; + update_status.app_size = m_start_packet.app_image_size; + + bootloader_dfu_update_process(update_status); + + return NRF_SUCCESS; +} + + +/**@brief Function for activating received Application image. + * + * @details This function will move the received application image fram swap (bank 1) to + * application area (bank 0). + * + * @return NRF_SUCCESS on success. Error code otherwise. + */ +static uint32_t dfu_activate_app(void) +{ + uint32_t err_code; + + // Erase BANK 0. + err_code = pstorage_clear(&m_storage_handle_app, m_start_packet.app_image_size); + APP_ERROR_CHECK(err_code); + + err_code = pstorage_store(&m_storage_handle_app, + (uint8_t *)m_storage_handle_swap.block_id, + m_start_packet.app_image_size, + 0); + + if (err_code == NRF_SUCCESS) + { + dfu_update_status_t update_status; + + memset(&update_status, 0, sizeof(dfu_update_status_t )); + update_status.status_code = DFU_UPDATE_APP_COMPLETE; + update_status.app_crc = m_image_crc; + update_status.app_size = m_start_packet.app_image_size; + + bootloader_dfu_update_process(update_status); + } + + return err_code; +} + + +/**@brief Function for activating received Bootloader image. + * + * @note This function will not move the bootloader image. + * The bootloader settings will be marked as Bootloader update complete and the swapping of + * current bootloader will occur after system reset. + * + * @return NRF_SUCCESS on success. + */ +static uint32_t dfu_activate_bl(void) +{ + dfu_update_status_t update_status; + + update_status.status_code = DFU_UPDATE_BOOT_COMPLETE; + update_status.app_crc = m_image_crc; + update_status.sd_size = m_start_packet.sd_image_size; + update_status.bl_size = m_start_packet.bl_image_size; + update_status.app_size = m_start_packet.app_image_size; + + bootloader_dfu_update_process(update_status); + + return NRF_SUCCESS; +} + + +uint32_t dfu_init(void) +{ + uint32_t err_code; + pstorage_module_param_t storage_module_param = {.cb = pstorage_callback_handler}; + + m_init_packet_length = 0; + m_image_crc = 0; + + err_code = pstorage_register(&storage_module_param, &m_storage_handle_app); + if (err_code != NRF_SUCCESS) + { + m_dfu_state = DFU_STATE_INIT_ERROR; + return err_code; + } + + m_storage_handle_app.block_id = DFU_BANK_0_REGION_START; + m_storage_handle_swap = m_storage_handle_app; + m_storage_handle_swap.block_id = DFU_BANK_1_REGION_START; + + // Create the timer to monitor the activity by the peer doing the firmware update. + err_code = app_timer_create(&m_dfu_timer_id, + APP_TIMER_MODE_SINGLE_SHOT, + dfu_timeout_handler); + APP_ERROR_CHECK(err_code); + + // Start the DFU timer. + err_code = app_timer_start(m_dfu_timer_id, DFU_TIMEOUT_INTERVAL, NULL); + APP_ERROR_CHECK(err_code); + + m_data_received = 0; + m_dfu_state = DFU_STATE_IDLE; + + return NRF_SUCCESS; +} + + +void dfu_register_callback(dfu_callback_t callback_handler) +{ + m_data_pkt_cb = callback_handler; +} + + +uint32_t dfu_start_pkt_handle(dfu_update_packet_t * p_packet) +{ + uint32_t err_code; + + m_start_packet = *(p_packet->params.start_packet); + + // Check that the requested update procedure is supported. + // Currently the following combinations are allowed: + // - Application + // - SoftDevice + // - Bootloader + // - SoftDevice with Bootloader + if (IS_UPDATING_APP(m_start_packet) && + (IS_UPDATING_SD(m_start_packet) || IS_UPDATING_BL(m_start_packet))) + { + // App update is only supported independently. + return NRF_ERROR_NOT_SUPPORTED; + } + + if (!(IS_WORD_SIZED(m_start_packet.sd_image_size) && + IS_WORD_SIZED(m_start_packet.bl_image_size) && + IS_WORD_SIZED(m_start_packet.app_image_size))) + { + // Image_sizes are not a multiple of 4 (word size). + return NRF_ERROR_NOT_SUPPORTED; + } + + m_image_size = m_start_packet.sd_image_size + m_start_packet.bl_image_size + + m_start_packet.app_image_size; + + if (m_start_packet.bl_image_size > DFU_BL_IMAGE_MAX_SIZE) + { + return NRF_ERROR_DATA_SIZE; + } + + if (IS_UPDATING_SD(m_start_packet)) + { + if (m_image_size > (DFU_IMAGE_MAX_SIZE_FULL)) + { + return NRF_ERROR_DATA_SIZE; + } + m_functions.prepare = dfu_prepare_func_app_erase; + m_functions.cleared = dfu_cleared_func_app; + m_functions.activate = dfu_activate_sd; + } + else + { + if (m_image_size > DFU_IMAGE_MAX_SIZE_BANKED) + { + return NRF_ERROR_DATA_SIZE; + } + + m_functions.prepare = dfu_prepare_func_swap_erase; + m_functions.cleared = dfu_cleared_func_swap; + if (IS_UPDATING_BL(m_start_packet)) + { + m_functions.activate = dfu_activate_bl; + } + else + { + m_functions.activate = dfu_activate_app; + } + } + + switch (m_dfu_state) + { + case DFU_STATE_IDLE: + // Valid peer activity detected. Hence restart the DFU timer. + err_code = dfu_timer_restart(); + VERIFY_SUCCESS(err_code); + m_functions.prepare(m_image_size); + + break; + + default: + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +uint32_t dfu_data_pkt_handle(dfu_update_packet_t * p_packet) +{ + uint32_t data_length; + uint32_t err_code; + uint32_t * p_data; + + VERIFY_PARAM_NOT_NULL(p_packet); + + // Check pointer alignment. + if (!is_word_aligned(p_packet->params.data_packet.p_data_packet)) + { + // The p_data_packet is not word aligned address. + return NRF_ERROR_INVALID_ADDR; + } + + switch (m_dfu_state) + { + case DFU_STATE_RDY: + case DFU_STATE_RX_INIT_PKT: + return NRF_ERROR_INVALID_STATE; + + case DFU_STATE_RX_DATA_PKT: + data_length = p_packet->params.data_packet.packet_length * sizeof(uint32_t); + + if ((m_data_received + data_length) > m_image_size) + { + // The caller is trying to write more bytes into the flash than the size provided to + // the dfu_image_size_set function. This is treated as a serious error condition and + // an unrecoverable one. Hence point the variable mp_app_write_address to the top of + // the flash area. This will ensure that all future application data packet writes + // will be blocked because of the above check. + m_data_received = 0xFFFFFFFF; + + return NRF_ERROR_DATA_SIZE; + } + + // Valid peer activity detected. Hence restart the DFU timer. + err_code = dfu_timer_restart(); + VERIFY_SUCCESS(err_code); + + p_data = (uint32_t *)p_packet->params.data_packet.p_data_packet; + + err_code = pstorage_store(mp_storage_handle_active, + (uint8_t *)p_data, + data_length, + m_data_received); + VERIFY_SUCCESS(err_code); + + m_data_received += data_length; + + if (m_data_received != m_image_size) + { + // The entire image is not received yet. More data is expected. + err_code = NRF_ERROR_INVALID_LENGTH; + } + else + { + // The entire image has been received. Return NRF_SUCCESS. + err_code = NRF_SUCCESS; + } + break; + + default: + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +uint32_t dfu_init_pkt_complete(void) +{ + uint32_t err_code = NRF_ERROR_INVALID_STATE; + + // DFU initialization has been done and a start packet has been received. + if (IMAGE_WRITE_IN_PROGRESS()) + { + // Image write is already in progress. Cannot handle an init packet now. + return NRF_ERROR_INVALID_STATE; + } + + if (m_dfu_state == DFU_STATE_RX_INIT_PKT) + { + err_code = dfu_init_prevalidate(m_init_packet, m_init_packet_length, m_start_packet.dfu_update_mode); + if (err_code == NRF_SUCCESS) + { + m_dfu_state = DFU_STATE_RX_DATA_PKT; + } + else + { + m_init_packet_length = 0; + } + } + return err_code; +} + + +uint32_t dfu_init_pkt_handle(dfu_update_packet_t * p_packet) +{ + uint32_t err_code = NRF_SUCCESS; + uint32_t length; + + switch (m_dfu_state) + { + case DFU_STATE_RDY: + m_dfu_state = DFU_STATE_RX_INIT_PKT; + // When receiving init packet in state ready just update and fall through this case. + + case DFU_STATE_RX_INIT_PKT: + // DFU initialization has been done and a start packet has been received. + if (IMAGE_WRITE_IN_PROGRESS()) + { + // Image write is already in progress. Cannot handle an init packet now. + return NRF_ERROR_INVALID_STATE; + } + + // Valid peer activity detected. Hence restart the DFU timer. + err_code = dfu_timer_restart(); + VERIFY_SUCCESS(err_code); + + length = p_packet->params.data_packet.packet_length * sizeof(uint32_t); + if ((m_init_packet_length + length) > sizeof(m_init_packet)) + { + return NRF_ERROR_INVALID_LENGTH; + } + + memcpy(&m_init_packet[m_init_packet_length], + &p_packet->params.data_packet.p_data_packet[0], + length); + m_init_packet_length += length; + break; + + default: + // Either the start packet was not received or dfu_init function was not called before. + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +uint32_t dfu_image_validate() +{ + uint32_t err_code; + + switch (m_dfu_state) + { + case DFU_STATE_RX_DATA_PKT: + // Check if the application image write has finished. + if (m_data_received != m_image_size) + { + // Image not yet fully transfered by the peer or the peer has attempted to write + // too much data. Hence the validation should fail. + err_code = NRF_ERROR_INVALID_STATE; + } + else + { + m_dfu_state = DFU_STATE_VALIDATE; + + // Valid peer activity detected. Hence restart the DFU timer. + err_code = dfu_timer_restart(); + if (err_code == NRF_SUCCESS) + { + err_code = dfu_init_postvalidate((uint8_t *)mp_storage_handle_active->block_id, + m_image_size); + VERIFY_SUCCESS(err_code); + + m_dfu_state = DFU_STATE_WAIT_4_ACTIVATE; + } + } + break; + + default: + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +uint32_t dfu_image_activate() +{ + uint32_t err_code; + + switch (m_dfu_state) + { + case DFU_STATE_WAIT_4_ACTIVATE: + + // Stop the DFU Timer because the peer activity need not be monitored any longer. + err_code = app_timer_stop(m_dfu_timer_id); + APP_ERROR_CHECK(err_code); + + err_code = m_functions.activate(); + break; + + default: + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +void dfu_reset(void) +{ + dfu_update_status_t update_status; + + update_status.status_code = DFU_RESET; + + bootloader_dfu_update_process(update_status); +} + + +static uint32_t dfu_compare_block(uint32_t * ptr1, uint32_t * ptr2, uint32_t len) +{ + sd_mbr_command_t sd_mbr_cmd; + + sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE; + sd_mbr_cmd.params.compare.ptr1 = ptr1; + sd_mbr_cmd.params.compare.ptr2 = ptr2; + sd_mbr_cmd.params.compare.len = len / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); +} + + +static uint32_t dfu_copy_sd(uint32_t * src, uint32_t * dst, uint32_t len) +{ + sd_mbr_command_t sd_mbr_cmd; + + sd_mbr_cmd.command = SD_MBR_COMMAND_COPY_SD; + sd_mbr_cmd.params.copy_sd.src = src; + sd_mbr_cmd.params.copy_sd.dst = dst; + sd_mbr_cmd.params.copy_sd.len = len / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); +} + + +static uint32_t dfu_sd_img_block_swap(uint32_t * src, + uint32_t * dst, + uint32_t len, + uint32_t block_size) +{ + // It is neccesarry to swap the new SoftDevice in 3 rounds to ensure correct copy of data + // and verifucation of data in case power reset occurs during write to flash. + // To ensure the robustness of swapping the images are compared backwards till start of + // image swap. If the back is identical everything is swapped. + uint32_t err_code = dfu_compare_block(src, dst, len); + if (err_code == NRF_SUCCESS) + { + return err_code; + } + + if ((uint32_t)dst > SOFTDEVICE_REGION_START) + { + err_code = dfu_sd_img_block_swap((uint32_t *)((uint32_t)src - block_size), + (uint32_t *)((uint32_t)dst - block_size), + block_size, + block_size); + VERIFY_SUCCESS(err_code); + } + + err_code = dfu_copy_sd(src, dst, len); + VERIFY_SUCCESS(err_code); + + return dfu_compare_block(src, dst, len); +} + + +uint32_t dfu_sd_image_swap(void) +{ + bootloader_settings_t boot_settings; + + bootloader_settings_get(&boot_settings); + + if (boot_settings.sd_image_size == 0) + { + return NRF_SUCCESS; + } + + if ((SOFTDEVICE_REGION_START + boot_settings.sd_image_size) > boot_settings.sd_image_start) + { + uint32_t err_code; + uint32_t sd_start = SOFTDEVICE_REGION_START; + uint32_t block_size = (boot_settings.sd_image_start - sd_start) / 2; + + /* ##### FIX START ##### */ + block_size &= ~(uint32_t)(CODE_PAGE_SIZE - 1); + /* ##### FIX END ##### */ + + uint32_t image_end = boot_settings.sd_image_start + boot_settings.sd_image_size; + + uint32_t img_block_start = boot_settings.sd_image_start + 2 * block_size; + uint32_t sd_block_start = sd_start + 2 * block_size; + + if (SD_SIZE_GET(MBR_SIZE) < boot_settings.sd_image_size) + { + // This will clear a page thus ensuring the old image is invalidated before swapping. + err_code = dfu_copy_sd((uint32_t *)(sd_start + block_size), + (uint32_t *)(sd_start + block_size), + sizeof(uint32_t)); + VERIFY_SUCCESS(err_code); + + err_code = dfu_copy_sd((uint32_t *)sd_start, (uint32_t *)sd_start, sizeof(uint32_t)); + VERIFY_SUCCESS(err_code); + } + + return dfu_sd_img_block_swap((uint32_t *)img_block_start, + (uint32_t *)sd_block_start, + image_end - img_block_start, + block_size); + } + else + { + if (boot_settings.sd_image_size != 0) + { + return dfu_copy_sd((uint32_t *)boot_settings.sd_image_start, + (uint32_t *)SOFTDEVICE_REGION_START, + boot_settings.sd_image_size); + } + } + + return NRF_SUCCESS; +} + + +uint32_t dfu_bl_image_swap(void) +{ + bootloader_settings_t bootloader_settings; + sd_mbr_command_t sd_mbr_cmd; + + bootloader_settings_get(&bootloader_settings); + + if (bootloader_settings.bl_image_size != 0) + { + uint32_t bl_image_start = (bootloader_settings.sd_image_size == 0) ? + DFU_BANK_1_REGION_START : + bootloader_settings.sd_image_start + + bootloader_settings.sd_image_size; + + sd_mbr_cmd.command = SD_MBR_COMMAND_COPY_BL; + sd_mbr_cmd.params.copy_bl.bl_src = (uint32_t *)(bl_image_start); + sd_mbr_cmd.params.copy_bl.bl_len = bootloader_settings.bl_image_size / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); + } + return NRF_SUCCESS; +} + + +uint32_t dfu_bl_image_validate(void) +{ + bootloader_settings_t bootloader_settings; + sd_mbr_command_t sd_mbr_cmd; + + bootloader_settings_get(&bootloader_settings); + + if (bootloader_settings.bl_image_size != 0) + { + uint32_t bl_image_start = (bootloader_settings.sd_image_size == 0) ? + DFU_BANK_1_REGION_START : + bootloader_settings.sd_image_start + + bootloader_settings.sd_image_size; + + sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE; + sd_mbr_cmd.params.compare.ptr1 = (uint32_t *)BOOTLOADER_REGION_START; + sd_mbr_cmd.params.compare.ptr2 = (uint32_t *)(bl_image_start); + sd_mbr_cmd.params.compare.len = bootloader_settings.bl_image_size / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); + } + return NRF_SUCCESS; +} + + +uint32_t dfu_sd_image_validate(void) +{ + bootloader_settings_t bootloader_settings; + sd_mbr_command_t sd_mbr_cmd; + + bootloader_settings_get(&bootloader_settings); + + if (bootloader_settings.sd_image_size == 0) + { + return NRF_SUCCESS; + } + + if ((SOFTDEVICE_REGION_START + bootloader_settings.sd_image_size) > bootloader_settings.sd_image_start) + { + uint32_t sd_start = SOFTDEVICE_REGION_START; + uint32_t block_size = (bootloader_settings.sd_image_start - sd_start) / 2; + uint32_t image_end = bootloader_settings.sd_image_start + + bootloader_settings.sd_image_size; + + uint32_t img_block_start = bootloader_settings.sd_image_start + 2 * block_size; + uint32_t sd_block_start = sd_start + 2 * block_size; + + if (SD_SIZE_GET(MBR_SIZE) < bootloader_settings.sd_image_size) + { + return NRF_ERROR_NULL; + } + + return dfu_sd_img_block_swap((uint32_t *)img_block_start, + (uint32_t *)sd_block_start, + image_end - img_block_start, + block_size); + } + + sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE; + sd_mbr_cmd.params.compare.ptr1 = (uint32_t *)SOFTDEVICE_REGION_START; + sd_mbr_cmd.params.compare.ptr2 = (uint32_t *)bootloader_settings.sd_image_start; + sd_mbr_cmd.params.compare.len = bootloader_settings.sd_image_size / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init.h new file mode 100644 index 0000000..8b4807a --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init.h @@ -0,0 +1,134 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup nrf_dfu_init Init packet handling in DFU + * @{ + * + * @brief Device Firmware Update module type and function declaration for init packet handling. + * + * @details This header contains basic functionality for performing safety checks on software + * updates for \nRFXX based devices. It provides a skeleton for pre-checking an init packet + * to ensure the following image is compatible with this device. A safety check should + * always be performed to prevent accidental flashing of unsupported applications or a + * wrong combination of application and SoftDevice. + * The device information contains information such as: + * - Device type (2 bytes), for example Heart Rate. The device type is a number defined by + * the customer. It can be located in UICR or FICR. + * - Device revision (2 bytes), for example major revision 1, minor revision 0. The device + * revision is a number defined by the customer. It can be located in UICR or FICR. + * - List of SoftDevices supported by this application, for example + * 0x0049 = S110v6_0_0 + * 0xFFFE = S110 development (any SoftDevice accepted), + * - CRC or hash of firmware image + * + * @note This module does not support security features such as image signing, but the corresponding + * implementation allows for such extensions. + * If the init packet is signed by a trusted source, it must be decrypted before it can be + * processed. + */ + +#ifndef DFU_INIT_H__ +#define DFU_INIT_H__ + +#include +#include "nrf.h" + +/**@brief Structure contained in an init packet. Contains information on device type, revision, and + * supported SoftDevices. + */ +typedef struct +{ + uint16_t device_type; /**< Device type (2 bytes), for example Heart Rate. This number must be defined by the customer before production. It can be located in UICR or FICR. */ + uint16_t device_rev; /**< Device revision (2 bytes), for example major revision 1, minor revision 0. This number must be defined by the customer before production. It can be located in UICR or FICR. */ + uint32_t app_version; /**< Application version for the image software. This field allows for additional checking, for example ensuring that a downgrade is not allowed. */ + uint16_t softdevice_len; /**< Number of different SoftDevice revisions compatible with this application. The list of SoftDevice firmware IDs is defined in @ref softdevice. */ + uint16_t softdevice[1]; /**< Variable length array of SoftDevices compatible with this application. The length of the array is specified in the length field. SoftDevice firmware id 0xFFFE indicates any SoftDevice. */ +} dfu_init_packet_t; + +/**@brief Structure holding basic device information settings. + */ +typedef struct +{ + uint16_t device_type; /**< Device type (2 bytes), for example Heart Rate. This number must be defined by the customer before production. It can be located in UICR or FICR. */ + uint16_t device_rev; /**< Device revision (2 bytes), for example major revision 1, minor revision 0. This number must be defined by the customer before production. It can be located in UICR or FICR. */ +} dfu_device_info_t; + +/** The device info offset can be modified to place the device info settings at a different location. + * If the customer reserved UICR location is used for other application specific data, the offset + * must be updated to avoid collision with that data. + */ +/** [DFU UICR DEV offset] */ +#define UICR_CUSTOMER_DEVICE_INFO_OFFSET 0x0 /**< Device info offset inside the customer UICR reserved area. Customers may change this value to place the device information in a user-preferred location. */ +/** [DFU UICR DEV offset] */ + +#define UICR_CUSTOMER_RESERVED_OFFSET 0x80 /**< Customer reserved area in the UICR. The area from UICR + 0x80 is reserved for customer usage. */ +#define DFU_DEVICE_INFO_BASE (NRF_UICR_BASE + \ + UICR_CUSTOMER_RESERVED_OFFSET + \ + UICR_CUSTOMER_DEVICE_INFO_OFFSET) /**< The device information base address inside of UICR. */ +#define DFU_DEVICE_INFO ((dfu_device_info_t *)DFU_DEVICE_INFO_BASE) /**< The memory mapped structure for device information data. */ + +#define DFU_DEVICE_TYPE_EMPTY ((uint16_t)0xFFFF) /**< Mask indicating no device type is present in UICR. 0xFFFF is default flash pattern when not written with data. */ +#define DFU_DEVICE_REVISION_EMPTY ((uint16_t)0xFFFF) /**< Mask indicating no device revision is present in UICR. 0xFFFF is default flash pattern when not written with data. */ +#define DFU_SOFTDEVICE_ANY ((uint16_t)0xFFFE) /**< Mask indicating that any SoftDevice is allowed for updating this application. Allows for easy development. Not to be used in production images. */ + + +/**@brief DFU prevalidate call for pre-checking the received init packet. + * + * @details Pre-validation will safety check the firmware image to be transfered in second stage. + * The function currently checks the device type, device revision, application firmware + * version, and supported SoftDevices. More checks should be added according to + * customer-specific requirements. + * + * @param[in] p_init_data Pointer to the init packet. If the init packet is encrypted or signed, + * it must first be decrypted before being checked. + * @param[in] init_data_len Length of the init data. + * + * @retval NRF_SUCCESS If the pre-validation succeeded, that means the image is + * supported by the device and it is considered to come from a + * trusted source (signing). + * @retval NRF_ERROR_INVALID_DATA If the pre-validation failed, that means the image is not + * supported by the device or comes from an un-trusted source + * (signing). + * @retval NRF_ERROR_INVALID_LENGTH If the size of the init packet is not within the limits of + * the init packet handler. + */ +uint32_t dfu_init_prevalidate(uint8_t * p_init_data, uint32_t init_data_len, uint8_t image_type); + +/**@brief DFU postvalidate call for post-checking the received image using the init packet. + * + * @details Post-validation can verify the integrity check the firmware image received before + * activating the image. + * Checks performed can be: + * - A simple CRC as shown in the corresponding implementation of this API in the file + * dfu_init_template.c + * - A hash for better verification of the image. + * - A signature to ensure the image originates from a trusted source. + * Checks are intended to be expanded for customer-specific requirements. + * + * @param[in] p_image Pointer to the received image. The init data provided in the call + * \ref dfu_init_prevalidate will be used for validating the image. + * @param[in] image_len Length of the image data. + * + * @retval NRF_SUCCESS If the post-validation succeeded, that meant the integrity of the + * image has been verified and the image originates from a trusted + * source (signing). + * @retval NRF_ERROR_INVALID_DATA If the post-validation failed, that meant the post check of the + * image failed such as the CRC is not matching the image transfered + * or the verification of the image fails (signing). + */ +uint32_t dfu_init_postvalidate(uint8_t * p_image, uint32_t image_len); + +#endif // DFU_INIT_H__ + +/**@} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init_template.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init_template.c new file mode 100644 index 0000000..450853e --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_init_template.c @@ -0,0 +1,172 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup nrf_dfu_init_template Template file with an DFU init packet handling example. + * @{ + * + * @ingroup nrf_dfu + * + * @brief This file contains a template on how to implement DFU init packet handling. + * + * @details The template shows how device type and revision can be used for a safety check of the + * received image. It shows how validation can be performed in two stages: + * - Stage 1: Pre-check of firmware image before transfer to ensure the firmware matches: + * - Device Type. + * - Device Revision. + * Installed SoftDevice. + * This template can be extended with additional checks according to needs. + * For example, such a check could be the origin of the image (trusted source) + * based on a signature scheme. + * - Stage 2: Post-check of the image after image transfer but before installing firmware. + * For example, such a check could be an integrity check in form of hashing or + * verification of a signature. + * In this template, a simple CRC check is carried out. + * The CRC check can be replaced with other mechanisms, like signing. + * + * @note This module does not support security features such as image signing, but the + * implementation allows for such extension. + * If the init packet is signed by a trusted source, it must be decrypted before it can be + * processed. + */ + +#include "dfu_init.h" +#include +#include +#include +#include "nrf_error.h" +#include "crc16.h" + +// ADAFRUIT +// All firmware init data must has Device Type ADAFRUIT_DEVICE_TYPE +// SD + Bootloader upgrade must have ADAFRUIT_SD_UNLOCK_CODE in Device Revision +#define ADAFRUIT_DEVICE_TYPE 0x0052 // for nrf52 +#define ADAFRUIT_SD_UNLOCK_CODE 0xADAF + +#define DFU_INIT_PACKET_EXT_LENGTH_MIN 2 //< Minimum length of the extended init packet. The extended init packet may contain a CRC, a HASH, or other data. This value must be changed according to the requirements of the system. The template uses a minimum value of two in order to hold a CRC. */ +#define DFU_INIT_PACKET_EXT_LENGTH_MAX 10 //< Maximum length of the extended init packet. The extended init packet may contain a CRC, a HASH, or other data. This value must be changed according to the requirements of the system. The template uses a maximum value of 10 in order to hold a CRC and any padded data on transport layer without overflow. */ + +static uint8_t m_extended_packet[DFU_INIT_PACKET_EXT_LENGTH_MAX]; //< Data array for storage of the extended data received. The extended data follows the normal init data of type \ref dfu_init_packet_t. Extended data can be used for a CRC, hash, signature, or other data. */ +static uint8_t m_extended_packet_length; //< Length of the extended data received with init packet. */ + + +uint32_t dfu_init_prevalidate(uint8_t * p_init_data, uint32_t init_data_len, uint8_t image_type) +{ + uint32_t i = 0; + + // In order to support signing or encryption then any init packet decryption function / library + // should be called from here or implemented at this location. + + // Length check to ensure valid data are parsed. + if (init_data_len < sizeof(dfu_init_packet_t)) + { + return NRF_ERROR_INVALID_LENGTH; + } + + // Current template uses clear text data so they can be casted for pre-check. + dfu_init_packet_t * p_init_packet = (dfu_init_packet_t *)p_init_data; + + m_extended_packet_length = ((uint32_t)p_init_data + init_data_len) - + (uint32_t)&p_init_packet->softdevice[p_init_packet->softdevice_len]; + if (m_extended_packet_length < DFU_INIT_PACKET_EXT_LENGTH_MIN) + { + return NRF_ERROR_INVALID_LENGTH; + } + + if (((uint32_t)p_init_data + init_data_len) < + (uint32_t)&p_init_packet->softdevice[p_init_packet->softdevice_len]) + { + return NRF_ERROR_INVALID_LENGTH; + } + + memcpy(m_extended_packet, + &p_init_packet->softdevice[p_init_packet->softdevice_len], + m_extended_packet_length); + + /** [DFU init application version] */ + // To support application versioning, this check should be updated. + // This template allows for any application to be installed. However, + // customers can place a revision number at the bottom of the application + // to be verified by the bootloader. This can be done at a location + // relative to the application, for example the application start + // address + 0x0100. + /** [DFU init application version] */ + + // First check to verify the image to be transfered matches the device type. + // If no Device type is present in DFU_DEVICE_INFO then any image will be accepted. +// if ((DFU_DEVICE_INFO->device_type != DFU_DEVICE_TYPE_EMPTY) && +// (p_init_packet->device_type != DFU_DEVICE_INFO->device_type)) +// { +// return NRF_ERROR_INVALID_DATA; +// } + + // Second check to verify the image to be transfered matches the device revision. + // If no Device revision is present in DFU_DEVICE_INFO then any image will be accepted. + // if ((DFU_DEVICE_INFO->device_rev != DFU_DEVICE_REVISION_EMPTY) && + // (p_init_packet->device_rev != DFU_DEVICE_INFO->device_rev)) + + if ( p_init_packet->device_type != ADAFRUIT_DEVICE_TYPE ) + { + return NRF_ERROR_FORBIDDEN; + } + + // Adafruit unlock code must match to upgrade SoftDevice and/or Bootloader + if ( image_type & (DFU_UPDATE_SD | DFU_UPDATE_BL) ) + { + if (p_init_packet->device_rev != ADAFRUIT_SD_UNLOCK_CODE) + { + return NRF_ERROR_FORBIDDEN; + } + } + + // Third check: Check the array of supported SoftDevices by this application. + // If the installed SoftDevice does not match any SoftDevice in the list then an + // error is returned. + while (i < p_init_packet->softdevice_len) + { + if (p_init_packet->softdevice[i] == DFU_SOFTDEVICE_ANY || + p_init_packet->softdevice[i++] == SD_FWID_GET(MBR_SIZE)) + { + return NRF_SUCCESS; + } + } + + // No matching SoftDevice found - Return NRF_ERROR_INVALID_DATA. + return NRF_ERROR_INVALID_DATA; +} + + +uint32_t dfu_init_postvalidate(uint8_t * p_image, uint32_t image_len) +{ + uint16_t image_crc; + uint16_t received_crc; + + // In order to support hashing (and signing) then the (decrypted) hash should be fetched and + // the corresponding hash should be calculated over the image at this location. + // If hashing (or signing) is added to the system then the CRC validation should be removed. + + // calculate CRC from active block. + image_crc = crc16_compute(p_image, image_len, NULL); + + // Decode the received CRC from extended data. + received_crc = uint16_decode((uint8_t *)&m_extended_packet[0]); + + // Compare the received and calculated CRC. + if (image_crc != received_crc) + { + return NRF_ERROR_INVALID_DATA; + } + + return NRF_SUCCESS; +} + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_single_bank.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_single_bank.c new file mode 100644 index 0000000..c230a8b --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_single_bank.c @@ -0,0 +1,788 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include +#include "dfu.h" +#include +#include "dfu_bank_internal.h" +#include "nrf.h" +#include "nrf_sdm.h" +#include "app_error.h" +#include "app_timer.h" +#include "bootloader.h" +#include "bootloader_types.h" +#include "pstorage.h" +#include "nrf_mbr.h" +#include "dfu_init.h" +#include "sdk_common.h" + +static dfu_state_t m_dfu_state; /**< Current DFU state. */ +static uint32_t m_image_size; /**< Size of the image that will be transmitted. */ + +static dfu_start_packet_t m_start_packet; /**< Start packet received for this update procedure. Contains update mode and image sizes information to be used for image transfer. */ +static uint8_t m_init_packet[64]; /**< Init packet, can hold CRC, Hash, Signed Hash and similar, for image validation, integrety check and authorization checking. */ +static uint8_t m_init_packet_length; /**< Length of init packet received. */ +static uint16_t m_image_crc; /**< Calculated CRC of the image received. */ + +APP_TIMER_DEF(m_dfu_timer_id); /**< Application timer id. */ +static bool m_dfu_timed_out = false; /**< Boolean flag value for tracking DFU timer timeout state. */ + +static pstorage_handle_t m_storage_handle_app; /**< Pstorage handle for the application area (bank 0). Bank used when updating a SoftDevice w/wo bootloader. Handle also used when swapping received application from bank 1 to bank 0. */ +static pstorage_handle_t * mp_storage_handle_active; /**< Pointer to the pstorage handle for the active bank for receiving of data packets. */ + +static dfu_callback_t m_data_pkt_cb; /**< Callback from DFU Bank module for notification of asynchronous operation such as flash prepare. */ +static dfu_bank_func_t m_functions; /**< Structure holding operations for the selected update process. */ + + +/**@brief Function for handling callbacks from pstorage module. + * + * @details Handles pstorage results for clear and storage operation. For detailed description of + * the parameters provided with the callback, please refer to \ref pstorage_ntf_cb_t. + */ +static void pstorage_callback_handler(pstorage_handle_t * p_handle, + uint8_t op_code, + uint32_t result, + uint8_t * p_data, + uint32_t data_len) +{ + switch (op_code) + { + case PSTORAGE_STORE_OP_CODE: + if ((m_dfu_state == DFU_STATE_RX_DATA_PKT) && (m_data_pkt_cb != NULL)) + { + m_data_pkt_cb(DATA_PACKET, result, p_data); + } + break; + + case PSTORAGE_CLEAR_OP_CODE: + if (m_dfu_state == DFU_STATE_PREPARING) + { + m_functions.cleared(); + m_dfu_state = DFU_STATE_RDY; + if (m_data_pkt_cb != NULL) + { + m_data_pkt_cb(START_PACKET, result, p_data); + } + } + break; + + default: + break; + } + APP_ERROR_CHECK(result); +} + + +/**@brief Function for handling the DFU timeout. + * + * @param[in] p_context The timeout context. + */ +static void dfu_timeout_handler(void * p_context) +{ + UNUSED_PARAMETER(p_context); + dfu_update_status_t update_status; + + m_dfu_timed_out = true; + update_status.status_code = DFU_TIMEOUT; + + bootloader_dfu_update_process(update_status); +} + + +/**@brief Function for restarting the DFU Timer. + * + * @details This function will stop and restart the DFU timer. This function will be called by the + * functions handling any DFU packet received from the peer that is transferring a firmware + * image. + */ +static uint32_t dfu_timer_restart(void) +{ + if (m_dfu_timed_out) + { + // The DFU timer had already timed out. + return NRF_ERROR_INVALID_STATE; + } + + uint32_t err_code = app_timer_stop(m_dfu_timer_id); + APP_ERROR_CHECK(err_code); + + err_code = app_timer_start(m_dfu_timer_id, DFU_TIMEOUT_INTERVAL, NULL); + APP_ERROR_CHECK(err_code); + + return err_code; +} + + +/**@brief Function for preparing of flash before receiving SoftDevice image. + * + * @details This function will erase current application area to ensure sufficient amount of + * storage for the SoftDevice image. Upon erase complete a callback will be done. + * See \ref dfu_bank_prepare_t for further details. + */ +static void dfu_prepare_func_app_erase(uint32_t image_size) +{ + uint32_t err_code; + + mp_storage_handle_active = &m_storage_handle_app; + + // Doing a SoftDevice update thus current application must be cleared to ensure enough space + // for new SoftDevice. + m_dfu_state = DFU_STATE_PREPARING; + err_code = pstorage_clear(&m_storage_handle_app, m_image_size); + APP_ERROR_CHECK(err_code); +} + + +/**@brief Function for handling behaviour when clear operation has completed. + */ +static void dfu_cleared_func_app(void) +{ + dfu_update_status_t update_status = {DFU_BANK_0_ERASED, }; + bootloader_dfu_update_process(update_status); +} + + +/**@brief Function for calculating storage offset for receiving SoftDevice image. + * + * @details When a new SoftDevice is received it will be temporary stored in flash before moved to + * address 0x0. In order to succesfully validate transfer and relocation it is important + * that temporary image and final installed image does not ovwerlap hence an offset must + * be calculated in case new image is larger than currently installed SoftDevice. + */ +uint32_t offset_calculate(uint32_t sd_image_size) +{ + uint32_t offset = 0; + + if (m_start_packet.sd_image_size > DFU_BANK_0_REGION_START) + { + uint32_t page_mask = (CODE_PAGE_SIZE - 1); + uint32_t diff = m_start_packet.sd_image_size - DFU_BANK_0_REGION_START; + + offset = diff & ~page_mask; + + // Align offset to next page if image size is not page sized. + if ((diff & page_mask) > 0) + { + offset += CODE_PAGE_SIZE; + } + } + + return offset; +} + + +/**@brief Function for activating received SoftDevice image. + * + * @note This function will not move the SoftDevice image. + * The bootloader settings will be marked as SoftDevice update complete and the swapping of + * current SoftDevice will occur after system reset. + * + * @return NRF_SUCCESS on success. + */ +static uint32_t dfu_activate_sd(void) +{ + dfu_update_status_t update_status; + + update_status.status_code = DFU_UPDATE_SD_COMPLETE; + update_status.app_crc = m_image_crc; + update_status.sd_image_start = DFU_BANK_0_REGION_START; + update_status.sd_size = m_start_packet.sd_image_size; + update_status.bl_size = m_start_packet.bl_image_size; + update_status.app_size = m_start_packet.app_image_size; + + bootloader_dfu_update_process(update_status); + + return NRF_SUCCESS; +} + + +/**@brief Function for activating received Application image. + * + * @details This function will move the received application image fram swap (bank 1) to + * application area (bank 0). + * + * @return NRF_SUCCESS on success. Error code otherwise. + */ +static uint32_t dfu_activate_app(void) +{ + uint32_t err_code = NRF_SUCCESS; + dfu_update_status_t update_status; + + memset(&update_status, 0, sizeof(dfu_update_status_t )); + update_status.status_code = DFU_UPDATE_APP_COMPLETE; + update_status.app_crc = m_image_crc; + update_status.app_size = m_start_packet.app_image_size; + + bootloader_dfu_update_process(update_status); + + return err_code; +} + + +/**@brief Function for activating received Bootloader image. + * + * @note This function will not move the bootloader image. + * The bootloader settings will be marked as Bootloader update complete and the swapping of + * current bootloader will occur after system reset. + * + * @return NRF_SUCCESS on success. + */ +static uint32_t dfu_activate_bl(void) +{ + dfu_update_status_t update_status; + + update_status.status_code = DFU_UPDATE_BOOT_COMPLETE; + update_status.app_crc = m_image_crc; + update_status.sd_size = m_start_packet.sd_image_size; + update_status.bl_size = m_start_packet.bl_image_size; + update_status.app_size = m_start_packet.app_image_size; + + bootloader_dfu_update_process(update_status); + + return NRF_SUCCESS; +} + + +uint32_t dfu_init(void) +{ + uint32_t err_code; + pstorage_module_param_t storage_module_param = {.cb = pstorage_callback_handler}; + + m_init_packet_length = 0; + m_image_crc = 0; + + err_code = pstorage_register(&storage_module_param, &m_storage_handle_app); + if (err_code != NRF_SUCCESS) + { + m_dfu_state = DFU_STATE_INIT_ERROR; + return err_code; + } + + m_storage_handle_app.block_id = DFU_BANK_0_REGION_START; + + // Create the timer to monitor the activity by the peer doing the firmware update. + err_code = app_timer_create(&m_dfu_timer_id, + APP_TIMER_MODE_SINGLE_SHOT, + dfu_timeout_handler); + APP_ERROR_CHECK(err_code); + + // Start the DFU timer. + err_code = app_timer_start(m_dfu_timer_id, DFU_TIMEOUT_INTERVAL, NULL); + APP_ERROR_CHECK(err_code); + + m_data_received = 0; + m_dfu_state = DFU_STATE_IDLE; + + return NRF_SUCCESS; +} + + +void dfu_register_callback(dfu_callback_t callback_handler) +{ + m_data_pkt_cb = callback_handler; +} + + +uint32_t dfu_start_pkt_handle(dfu_update_packet_t * p_packet) +{ + uint32_t err_code; + + m_start_packet = *(p_packet->params.start_packet); + + // Check that the requested update procedure is supported. + // Currently the following combinations are allowed: + // - Application + // - SoftDevice + // - Bootloader + // - SoftDevice with Bootloader + if (IS_UPDATING_APP(m_start_packet) && + (IS_UPDATING_SD(m_start_packet) || IS_UPDATING_BL(m_start_packet))) + { + // App update is only supported independently. + return NRF_ERROR_NOT_SUPPORTED; + } + + if (!(IS_WORD_SIZED(m_start_packet.sd_image_size) && + IS_WORD_SIZED(m_start_packet.bl_image_size) && + IS_WORD_SIZED(m_start_packet.app_image_size))) + { + // Image_sizes are not a multiple of 4 (word size). + return NRF_ERROR_NOT_SUPPORTED; + } + + m_image_size = m_start_packet.sd_image_size + m_start_packet.bl_image_size + + m_start_packet.app_image_size; + + if (m_start_packet.bl_image_size > DFU_BL_IMAGE_MAX_SIZE) + { + return NRF_ERROR_DATA_SIZE; + } + + if (m_image_size > (DFU_IMAGE_MAX_SIZE_FULL)) + { + return NRF_ERROR_DATA_SIZE; + } + m_functions.prepare = dfu_prepare_func_app_erase; + m_functions.cleared = dfu_cleared_func_app; + + if (IS_UPDATING_SD(m_start_packet)) + { + m_functions.activate = dfu_activate_sd; + } + else if (IS_UPDATING_BL(m_start_packet)) + { + m_functions.activate = dfu_activate_bl; + } + else + { + m_functions.activate = dfu_activate_app; + } + + switch (m_dfu_state) + { + case DFU_STATE_IDLE: + // Valid peer activity detected. Hence restart the DFU timer. + err_code = dfu_timer_restart(); + VERIFY_SUCCESS(err_code); + m_functions.prepare(m_image_size); + + break; + + default: + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +uint32_t dfu_data_pkt_handle(dfu_update_packet_t * p_packet) +{ + uint32_t data_length; + uint32_t err_code; + uint32_t * p_data; + + VERIFY_PARAM_NOT_NULL(p_packet); + + // Check pointer alignment. + if (!is_word_aligned(p_packet->params.data_packet.p_data_packet)) + { + // The p_data_packet is not word aligned address. + return NRF_ERROR_INVALID_ADDR; + } + + switch (m_dfu_state) + { + case DFU_STATE_RDY: + case DFU_STATE_RX_INIT_PKT: + return NRF_ERROR_INVALID_STATE; + + case DFU_STATE_RX_DATA_PKT: + data_length = p_packet->params.data_packet.packet_length * sizeof(uint32_t); + + if ((m_data_received + data_length) > m_image_size) + { + // The caller is trying to write more bytes into the flash than the size provided to + // the dfu_image_size_set function. This is treated as a serious error condition and + // an unrecoverable one. Hence point the variable mp_app_write_address to the top of + // the flash area. This will ensure that all future application data packet writes + // will be blocked because of the above check. + m_data_received = 0xFFFFFFFF; + + return NRF_ERROR_DATA_SIZE; + } + + // Valid peer activity detected. Hence restart the DFU timer. + err_code = dfu_timer_restart(); + VERIFY_SUCCESS(err_code); + + p_data = (uint32_t *)p_packet->params.data_packet.p_data_packet; + + err_code = pstorage_store(mp_storage_handle_active, + (uint8_t *)p_data, + data_length, + m_data_received); + VERIFY_SUCCESS(err_code); + + m_data_received += data_length; + + if (m_data_received != m_image_size) + { + // The entire image is not received yet. More data is expected. + err_code = NRF_ERROR_INVALID_LENGTH; + } + else + { + // The entire image has been received. Return NRF_SUCCESS. + err_code = NRF_SUCCESS; + } + break; + + default: + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +uint32_t dfu_init_pkt_complete(void) +{ + uint32_t err_code = NRF_ERROR_INVALID_STATE; + + // DFU initialization has been done and a start packet has been received. + if (IMAGE_WRITE_IN_PROGRESS()) + { + // Image write is already in progress. Cannot handle an init packet now. + return NRF_ERROR_INVALID_STATE; + } + + if (m_dfu_state == DFU_STATE_RX_INIT_PKT) + { + err_code = dfu_init_prevalidate(m_init_packet, m_init_packet_length, m_start_packet.dfu_update_mode); + if (err_code == NRF_SUCCESS) + { + m_dfu_state = DFU_STATE_RX_DATA_PKT; + } + else + { + m_init_packet_length = 0; + } + } + return err_code; +} + + +uint32_t dfu_init_pkt_handle(dfu_update_packet_t * p_packet) +{ + uint32_t err_code = NRF_SUCCESS; + uint32_t length; + + switch (m_dfu_state) + { + case DFU_STATE_RDY: + m_dfu_state = DFU_STATE_RX_INIT_PKT; + // When receiving init packet in state ready just update and fall through this case. + + case DFU_STATE_RX_INIT_PKT: + // DFU initialization has been done and a start packet has been received. + if (IMAGE_WRITE_IN_PROGRESS()) + { + // Image write is already in progress. Cannot handle an init packet now. + return NRF_ERROR_INVALID_STATE; + } + + // Valid peer activity detected. Hence restart the DFU timer. + err_code = dfu_timer_restart(); + VERIFY_SUCCESS(err_code); + + length = p_packet->params.data_packet.packet_length * sizeof(uint32_t); + if ((m_init_packet_length + length) > sizeof(m_init_packet)) + { + return NRF_ERROR_INVALID_LENGTH; + } + + memcpy(&m_init_packet[m_init_packet_length], + &p_packet->params.data_packet.p_data_packet[0], + length); + m_init_packet_length += length; + break; + + default: + // Either the start packet was not received or dfu_init function was not called before. + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +uint32_t dfu_image_validate() +{ + uint32_t err_code; + + switch (m_dfu_state) + { + case DFU_STATE_RX_DATA_PKT: + // Check if the application image write has finished. + if (m_data_received != m_image_size) + { + // Image not yet fully transfered by the peer or the peer has attempted to write + // too much data. Hence the validation should fail. + err_code = NRF_ERROR_INVALID_STATE; + } + else + { + m_dfu_state = DFU_STATE_VALIDATE; + + // Valid peer activity detected. Hence restart the DFU timer. + err_code = dfu_timer_restart(); + if (err_code == NRF_SUCCESS) + { + err_code = dfu_init_postvalidate((uint8_t *)mp_storage_handle_active->block_id, + m_image_size); + VERIFY_SUCCESS(err_code); + + m_dfu_state = DFU_STATE_WAIT_4_ACTIVATE; + } + } + break; + + default: + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +uint32_t dfu_image_activate() +{ + uint32_t err_code; + + switch (m_dfu_state) + { + case DFU_STATE_WAIT_4_ACTIVATE: + + // Stop the DFU Timer because the peer activity need not be monitored any longer. + err_code = app_timer_stop(m_dfu_timer_id); + APP_ERROR_CHECK(err_code); + + err_code = m_functions.activate(); + break; + + default: + err_code = NRF_ERROR_INVALID_STATE; + break; + } + + return err_code; +} + + +void dfu_reset(void) +{ + dfu_update_status_t update_status; + + update_status.status_code = DFU_RESET; + + bootloader_dfu_update_process(update_status); +} + + +static uint32_t dfu_compare_block(uint32_t * ptr1, uint32_t * ptr2, uint32_t len) +{ + sd_mbr_command_t sd_mbr_cmd; + + sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE; + sd_mbr_cmd.params.compare.ptr1 = ptr1; + sd_mbr_cmd.params.compare.ptr2 = ptr2; + sd_mbr_cmd.params.compare.len = len / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); +} + + +static uint32_t dfu_copy_sd(uint32_t * src, uint32_t * dst, uint32_t len) +{ + sd_mbr_command_t sd_mbr_cmd; + + sd_mbr_cmd.command = SD_MBR_COMMAND_COPY_SD; + sd_mbr_cmd.params.copy_sd.src = src; + sd_mbr_cmd.params.copy_sd.dst = dst; + sd_mbr_cmd.params.copy_sd.len = len / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); +} + + +static uint32_t dfu_sd_img_block_swap(uint32_t * src, + uint32_t * dst, + uint32_t len, + uint32_t block_size) +{ + // It is neccesarry to swap the new SoftDevice in 3 rounds to ensure correct copy of data + // and verifucation of data in case power reset occurs during write to flash. + // To ensure the robustness of swapping the images are compared backwards till start of + // image swap. If the back is identical everything is swapped. + uint32_t err_code = dfu_compare_block(src, dst, len); + if (err_code == NRF_SUCCESS) + { + return err_code; + } + + if ((uint32_t)dst > SOFTDEVICE_REGION_START) + { + err_code = dfu_sd_img_block_swap((uint32_t *)((uint32_t)src - block_size), + (uint32_t *)((uint32_t)dst - block_size), + block_size, + block_size); + VERIFY_SUCCESS(err_code); + } + + err_code = dfu_copy_sd(src, dst, len); + VERIFY_SUCCESS(err_code); + + return dfu_compare_block(src, dst, len); +} + + +uint32_t dfu_sd_image_swap(void) +{ + bootloader_settings_t boot_settings; + + bootloader_settings_get(&boot_settings); + + if (boot_settings.sd_image_size == 0) + { + return NRF_SUCCESS; + } + + if ((SOFTDEVICE_REGION_START + boot_settings.sd_image_size) > boot_settings.sd_image_start) + { + uint32_t err_code; + uint32_t sd_start = SOFTDEVICE_REGION_START; + uint32_t block_size = (boot_settings.sd_image_start - sd_start) / 2; + + /* ##### FIX START ##### */ + block_size &= ~(uint32_t)(CODE_PAGE_SIZE - 1); + /* ##### FIX END ##### */ + + uint32_t image_end = boot_settings.sd_image_start + boot_settings.sd_image_size; + + uint32_t img_block_start = boot_settings.sd_image_start + 2 * block_size; + uint32_t sd_block_start = sd_start + 2 * block_size; + + if (SD_SIZE_GET(MBR_SIZE) < boot_settings.sd_image_size) + { + // This will clear a page thus ensuring the old image is invalidated before swapping. + err_code = dfu_copy_sd((uint32_t *)(sd_start + block_size), + (uint32_t *)(sd_start + block_size), + sizeof(uint32_t)); + VERIFY_SUCCESS(err_code); + + err_code = dfu_copy_sd((uint32_t *)sd_start, (uint32_t *)sd_start, sizeof(uint32_t)); + VERIFY_SUCCESS(err_code); + } + + return dfu_sd_img_block_swap((uint32_t *)img_block_start, + (uint32_t *)sd_block_start, + image_end - img_block_start, + block_size); + } + else + { + if (boot_settings.sd_image_size != 0) + { + return dfu_copy_sd((uint32_t *)boot_settings.sd_image_start, + (uint32_t *)SOFTDEVICE_REGION_START, + boot_settings.sd_image_size); + } + } + + return NRF_SUCCESS; +} + + +uint32_t dfu_bl_image_swap(void) +{ + bootloader_settings_t bootloader_settings; + sd_mbr_command_t sd_mbr_cmd; + + bootloader_settings_get(&bootloader_settings); + + if (bootloader_settings.bl_image_size != 0) + { + uint32_t bl_image_start = (bootloader_settings.sd_image_size == 0) ? + DFU_BANK_0_REGION_START : + bootloader_settings.sd_image_start + + bootloader_settings.sd_image_size; + + sd_mbr_cmd.command = SD_MBR_COMMAND_COPY_BL; + sd_mbr_cmd.params.copy_bl.bl_src = (uint32_t *)(bl_image_start); + sd_mbr_cmd.params.copy_bl.bl_len = bootloader_settings.bl_image_size / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); + } + return NRF_SUCCESS; +} + + +uint32_t dfu_bl_image_validate(void) +{ + bootloader_settings_t bootloader_settings; + sd_mbr_command_t sd_mbr_cmd; + + bootloader_settings_get(&bootloader_settings); + + if (bootloader_settings.bl_image_size != 0) + { + uint32_t bl_image_start = (bootloader_settings.sd_image_size == 0) ? + DFU_BANK_0_REGION_START : + bootloader_settings.sd_image_start + + bootloader_settings.sd_image_size; + + sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE; + sd_mbr_cmd.params.compare.ptr1 = (uint32_t *)BOOTLOADER_REGION_START; + sd_mbr_cmd.params.compare.ptr2 = (uint32_t *)(bl_image_start); + sd_mbr_cmd.params.compare.len = bootloader_settings.bl_image_size / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); + } + return NRF_SUCCESS; +} + + +uint32_t dfu_sd_image_validate(void) +{ + bootloader_settings_t bootloader_settings; + sd_mbr_command_t sd_mbr_cmd; + + bootloader_settings_get(&bootloader_settings); + + if (bootloader_settings.sd_image_size == 0) + { + return NRF_SUCCESS; + } + + if ((SOFTDEVICE_REGION_START + bootloader_settings.sd_image_size) > bootloader_settings.sd_image_start) + { + uint32_t sd_start = SOFTDEVICE_REGION_START; + uint32_t block_size = (bootloader_settings.sd_image_start - sd_start) / 2; + uint32_t image_end = bootloader_settings.sd_image_start + + bootloader_settings.sd_image_size; + + uint32_t img_block_start = bootloader_settings.sd_image_start + 2 * block_size; + uint32_t sd_block_start = sd_start + 2 * block_size; + + if (SD_SIZE_GET(MBR_SIZE) < bootloader_settings.sd_image_size) + { + return NRF_ERROR_NULL; + } + + return dfu_sd_img_block_swap((uint32_t *)img_block_start, + (uint32_t *)sd_block_start, + image_end - img_block_start, + block_size); + } + + sd_mbr_cmd.command = SD_MBR_COMMAND_COMPARE; + sd_mbr_cmd.params.compare.ptr1 = (uint32_t *)SOFTDEVICE_REGION_START; + sd_mbr_cmd.params.compare.ptr2 = (uint32_t *)bootloader_settings.sd_image_start; + sd_mbr_cmd.params.compare.len = bootloader_settings.sd_image_size / sizeof(uint32_t); + + return sd_mbr_command(&sd_mbr_cmd); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport.h new file mode 100644 index 0000000..864ff87 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport.h @@ -0,0 +1,44 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup nrf_dfu_transport DFU transport API. + * @{ + * + * @brief DFU transport module interface. + */ + +#ifndef DFU_TRANSPORT_H__ +#define DFU_TRANSPORT_H__ + +#include + +/**@brief Function for starting the update of Device Firmware. + * + * @retval NRF_SUCCESS Operation success. + */ +uint32_t dfu_transport_serial_update_start(void); + +/**@brief Function for closing the transport layer. + * + * @retval NRF_SUCCESS Operation success. + */ +uint32_t dfu_transport_serial_close(void); + + +uint32_t dfu_transport_ble_update_start(void); +uint32_t dfu_transport_ble_close(); + +#endif // DFU_TRANSPORT_H__ + +/**@} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_ble.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_ble.c new file mode 100644 index 0000000..b386a94 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_ble.c @@ -0,0 +1,1155 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "dfu_transport.h" +#include "dfu.h" +#include +#include +#include "boards.h" +#include "nrf.h" +#include "nrf_sdm.h" +#include "nrf_gpio.h" +#include "app_util.h" +#include "app_error.h" +#include "softdevice_handler.h" +#include "ble_stack_handler_types.h" +#include "ble_advdata.h" +#include "ble_l2cap.h" +#include "ble_gap.h" +#include "ble_gatt.h" +#include "ble_hci.h" +#include "ble_dfu.h" +#include "ble_dis.h" +#include "app_timer.h" +#include "ble_conn_params.h" +#include "hci_mem_pool.h" +#include "bootloader.h" +#include "dfu_ble_svc_internal.h" +#include "nrf_delay.h" +#include "sdk_common.h" + + +#define BLEGAP_EVENT_LENGTH 6 +#define BLEGATT_ATT_MTU_MAX 247 +enum { BLE_CONN_CFG_HIGH_BANDWIDTH = 1 }; + +#define DFU_REV_MAJOR 0x00 /** DFU Major revision number to be exposed. */ +#define DFU_REV_MINOR 0x08 /** DFU Minor revision number to be exposed. */ +#define DFU_REVISION ((DFU_REV_MAJOR << 8) | DFU_REV_MINOR) /** DFU Revision number to be exposed. Combined of major and minor versions. */ +//#define ADVERTISING_LED_PIN_NO 17 /**< Is on when device is advertising. */ +//#define CONNECTED_LED_PIN_NO 19 /**< Is on when device has connected. */ +#define DFU_SERVICE_HANDLE 0x000C /**< Handle of DFU service when DFU service is first service initialized. */ +#define BLE_HANDLE_MAX 0xFFFF /**< Max handle value is BLE. */ + +#define DEVICE_NAME "AdaDFU" // limit of 8 chars /**< Name of device. Will be included in the advertising data. */ +#define DIS_MANUFACTURER "Adafruit Industries" +// DIS_MODEL is defined in boards.h + +// TODO Update when upgrade bootloader +#define DIS_FIRMWARE "S132 5.1.0, 5.1.0" + + +#define MIN_CONN_INTERVAL (uint16_t)(MSEC_TO_UNITS(10, UNIT_1_25_MS)) /**< Minimum acceptable connection interval (11.25 milliseconds). */ +#define MAX_CONN_INTERVAL (uint16_t)(MSEC_TO_UNITS(30, UNIT_1_25_MS)) /**< Maximum acceptable connection interval (15 milliseconds). */ +#define SLAVE_LATENCY 0 /**< Slave latency. */ +#define CONN_SUP_TIMEOUT (4 * 100) /**< Connection supervisory timeout (4 seconds). */ + +#define APP_TIMER_PRESCALER 0 /**< Value of the RTC1 PRESCALER register. */ + +#define FIRST_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(100, APP_TIMER_PRESCALER) /**< Time from the Connected event to first time sd_ble_gap_conn_param_update is called (100 milliseconds). */ +#define NEXT_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(500, APP_TIMER_PRESCALER) /**< Time between each call to sd_ble_gap_conn_param_update after the first call (500 milliseconds). */ +#define MAX_CONN_PARAMS_UPDATE_COUNT 3 /**< Number of attempts before giving up the connection parameter negotiation. */ + +#define APP_ADV_INTERVAL MSEC_TO_UNITS(25, UNIT_0_625_MS) /**< The advertising interval (25 ms.). */ +#define APP_ADV_TIMEOUT_IN_SECONDS BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED /**< The advertising timeout in units of seconds. This is set to @ref BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED so that the advertisement is done as long as there there is a call to @ref dfu_transport_close function.*/ +#define APP_DIRECTED_ADV_TIMEOUT 50 /**< number of direct advertisement (each lasting 1.28seconds). */ +#define PEER_ADDRESS_TYPE_INVALID 0xFF /**< Value indicating that no valid peer address exists. This will be the case when a private resolvable address is used in which case there is no address available but instead an IRK is present. */ +#define PEER_ADDRESS_TYPE_INVALID 0xFF /**< Value indicating that no valid peer address exists. This will be the case when a private resolvable address is used in which case there is no address available but instead an IRK is present. */ + +#define SEC_PARAM_TIMEOUT 30 /**< Timeout for Pairing Request or Security Request (in seconds). */ +#define SEC_PARAM_BOND 0 /**< Perform bonding. */ +#define SEC_PARAM_MITM 0 /**< Man In The Middle protection not required. */ +#define SEC_PARAM_LESC 0 /**< LE Secure Connections not enabled. */ +#define SEC_PARAM_KEYPRESS 0 /**< Keypress notifications not enabled. */ +#define SEC_PARAM_IO_CAPABILITIES BLE_GAP_IO_CAPS_NONE /**< No I/O capabilities. */ +#define SEC_PARAM_OOB 0 /**< Out Of Band data not available. */ +#define SEC_PARAM_MIN_KEY_SIZE 7 /**< Minimum encryption key size. */ +#define SEC_PARAM_MAX_KEY_SIZE 16 /**< Maximum encryption key size. */ + +#define MAX_SIZE_OF_BLE_STACK_EVT (sizeof(ble_evt_t) + BLE_L2CAP_MTU_DEF) /**< Maximum size (in bytes) of the event received from S110 SoftDevice.*/ +#define NUM_WORDS_RESERVED_FOR_BLE_EVENTS CEIL_DIV(MAX_SIZE_OF_BLE_STACK_EVT, sizeof(uint32_t)) /**< Size of the memory (in words) reserved for receiving S110 SoftDevice events. */ + +#define IS_CONNECTED() (m_conn_handle != BLE_CONN_HANDLE_INVALID) /**< Macro to determine if the device is in connected state. */ + +#define APP_FEATURE_NOT_SUPPORTED BLE_GATT_STATUS_ATTERR_APP_BEGIN + 2 /**< Reply when unsupported features are requested. */ +#define SD_IMAGE_SIZE_OFFSET 0 /**< Offset in start packet for the size information for SoftDevice. */ +#define BL_IMAGE_SIZE_OFFSET 4 /**< Offset in start packet for the size information for bootloader. */ +#define APP_IMAGE_SIZE_OFFSET 8 /**< Offset in start packet for the size information for application. */ + +/**@brief Packet type enumeration. + */ +typedef enum +{ + PKT_TYPE_INVALID, /**< Invalid packet type. Used for initialization purpose.*/ + PKT_TYPE_START, /**< Start packet.*/ + PKT_TYPE_INIT, /**< Init packet.*/ + PKT_TYPE_FIRMWARE_DATA /**< Firmware data packet.*/ +} pkt_type_t; + +static ble_gap_sec_params_t m_sec_params; /**< Security requirements for this application. */ +static ble_gap_adv_params_t m_adv_params; /**< Parameters to be passed to the stack when starting advertising. */ +static ble_dfu_t m_dfu; /**< Structure used to identify the Device Firmware Update service. */ +static pkt_type_t m_pkt_type; /**< Type of packet to be expected from the DFU Controller. */ +static uint8_t m_update_mode; /**< Type of update mode specified by the DFU Controller. */ +static uint32_t m_num_of_firmware_bytes_rcvd; /**< Cumulative number of bytes of firmware data received. */ +static uint16_t m_pkt_notif_target; /**< Number of packets of firmware data to be received before transmitting the next Packet Receipt Notification to the DFU Controller. */ +static uint16_t m_pkt_notif_target_cnt; /**< Number of packets of firmware data received after sending last Packet Receipt Notification or since the receipt of a @ref BLE_DFU_PKT_RCPT_NOTIF_ENABLED event from the DFU service, which ever occurs later.*/ +static uint8_t * mp_rx_buffer; /**< Pointer to a RX buffer.*/ +static bool m_tear_down_in_progress = false; /**< Variable to indicate whether a tear down is in progress. A tear down could be because the application has initiated it or the peer has disconnected. */ +static bool m_pkt_rcpt_notif_enabled = false; /**< Variable to denote whether packet receipt notification has been enabled by the DFU controller.*/ +static uint16_t m_conn_handle = BLE_CONN_HANDLE_INVALID; /**< Handle of the current connection. */ +static bool m_is_advertising = false; /**< Variable to indicate if advertising is ongoing.*/ +static dfu_ble_peer_data_t m_ble_peer_data; /**< BLE Peer data exchanged from application on buttonless update mode. */ +static bool m_ble_peer_data_valid = false; /**< True if BLE Peer data has been exchanged from application. */ +static uint32_t m_direct_adv_cnt = APP_DIRECTED_ADV_TIMEOUT; /**< Counter of direct advertisements. */ +static uint8_t * mp_final_packet; /**< Pointer to final data packet received. When callback for succesful packet handling is received from dfu bank handling a transfer complete response can be sent to peer. */ + + +static ble_gap_addr_t const * m_whitelist[1]; /**< List of peers in whitelist (only one) */ +static ble_gap_id_key_t const * m_gap_ids[1]; + +// Adafruit +extern void blinky_fast_set(bool isFast); +extern void blinky_ota_connected(void); +extern void blinky_ota_disconneted(void); + +/**@brief Function updating Service Changed CCCD and indicate a service change to peer. + * + * @details This function will verify the CCCD setting provided with \ref m_ble_peer_data and + * update the system attributes accordingly. If Service Change CCCD is set to indicate + * then a service change indication will be send to the peer. + * + * @retval NRF_INVALID_STATE if no connection has been established to a central. + * @return Any error code returned by SoftDevice function calls. + */ +static uint32_t service_change_indicate() +{ + uint32_t err_code; + + if (m_conn_handle == BLE_CONN_HANDLE_INVALID) + { + return NRF_ERROR_INVALID_STATE; + } + + if (m_ble_peer_data_valid) + { + err_code = sd_ble_gatts_sys_attr_set(m_conn_handle, + m_ble_peer_data.sys_serv_attr, + sizeof(m_ble_peer_data.sys_serv_attr), + BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS); + VERIFY_SUCCESS(err_code); + + err_code = sd_ble_gatts_sys_attr_set(m_conn_handle, + NULL, + 0, + BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS); + VERIFY_SUCCESS(err_code); + + err_code = sd_ble_gatts_service_changed(m_conn_handle, DFU_SERVICE_HANDLE, BLE_HANDLE_MAX); + if ((err_code == BLE_ERROR_INVALID_CONN_HANDLE) || + (err_code == NRF_ERROR_INVALID_STATE) || + (err_code == NRF_ERROR_BUSY)) + { + // Those errors can be expected when sending trying to send Service Changed Indication + // if the CCCD is not set to indicate. Thus set the returning error code to success. + err_code = NRF_SUCCESS; + } + } + else + { + err_code = sd_ble_gatts_sys_attr_set(m_conn_handle, NULL, 0, 0); + } + + return err_code; +} + + +/**@brief Function to convert an nRF51 error code to a DFU Response Value. + * + * @details This function will convert a given nRF51 error code to a DFU Response Value. The + * result of this function depends on the current DFU procedure in progress, given as + * input in current_dfu_proc parameter. + * + * @param[in] err_code The nRF51 error code to be converted. + * @param[in] current_dfu_proc Current DFU procedure in progress. + * + * @return Converted Response Value. + */ +static ble_dfu_resp_val_t nrf_err_code_translate(uint32_t err_code, + const ble_dfu_procedure_t current_dfu_proc) +{ + switch (err_code) + { + case NRF_SUCCESS: + return BLE_DFU_RESP_VAL_SUCCESS; + + case NRF_ERROR_INVALID_STATE: + return BLE_DFU_RESP_VAL_INVALID_STATE; + + case NRF_ERROR_NOT_SUPPORTED: + return BLE_DFU_RESP_VAL_NOT_SUPPORTED; + + case NRF_ERROR_DATA_SIZE: + return BLE_DFU_RESP_VAL_DATA_SIZE; + + case NRF_ERROR_INVALID_DATA: + if (current_dfu_proc == BLE_DFU_VALIDATE_PROCEDURE) + { + // When this error is received in Validation phase, then it maps to a CRC Error. + // Refer dfu_image_validate function for more information. + return BLE_DFU_RESP_VAL_CRC_ERROR; + } + return BLE_DFU_RESP_VAL_OPER_FAILED; + + default: + return BLE_DFU_RESP_VAL_OPER_FAILED; + } +} + + +/**@brief Function for handling the callback events from the dfu module. + * Callbacks are expected when \ref dfu_data_pkt_handle has been executed. + * + * @param[in] packet Packet type for which this callback is related. + * @param[in] result Operation result code. NRF_SUCCESS when a queued operation was successful. + * @param[in] p_data Pointer to the data to which the operation is related. + */ +static void dfu_cb_handler(uint32_t packet, uint32_t result, uint8_t * p_data) +{ + switch (packet) + { + ble_dfu_resp_val_t resp_val; + uint32_t err_code; + + case DATA_PACKET: + if (result != NRF_SUCCESS) + { + // Disconnect from peer. + if (IS_CONNECTED()) + { + err_code = sd_ble_gap_disconnect(m_conn_handle, + BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION); + APP_ERROR_CHECK(err_code); + } + } + else + { + err_code = hci_mem_pool_rx_consume(p_data); + APP_ERROR_CHECK(err_code); + + // If the callback matches final data packet received then the peer is notified. + if (mp_final_packet == p_data) + { + // Notify the DFU Controller about the success of the procedure. + err_code = ble_dfu_response_send(&m_dfu, + BLE_DFU_RECEIVE_APP_PROCEDURE, + BLE_DFU_RESP_VAL_SUCCESS); + APP_ERROR_CHECK(err_code); + } + } + break; + + case START_PACKET: + // Translate the err_code returned by the above function to DFU Response Value. + resp_val = nrf_err_code_translate(result, BLE_DFU_START_PROCEDURE); + + err_code = ble_dfu_response_send(&m_dfu, + BLE_DFU_START_PROCEDURE, + resp_val); + APP_ERROR_CHECK(err_code); + break; + + default: + // ignore. + break; + } +} + + +/**@brief Function for notifying a DFU Controller about error conditions in the DFU module. + * This function also ensures that an error is translated from nrf_errors to DFU Response + * Value. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] err_code Nrf error code that should be translated and send to the DFU Controller. + */ +static void dfu_error_notify(ble_dfu_t * p_dfu, uint32_t err_code) +{ + // An error has occurred. Notify the DFU Controller about this error condition. + // Translate the err_code returned to DFU Response Value. + ble_dfu_resp_val_t resp_val; + + resp_val = nrf_err_code_translate(err_code, BLE_DFU_RECEIVE_APP_PROCEDURE); + + err_code = ble_dfu_response_send(p_dfu, BLE_DFU_RECEIVE_APP_PROCEDURE, resp_val); + APP_ERROR_CHECK(err_code); +} + + +/**@brief Function for processing start data written by the peer to the DFU Packet + * Characteristic. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] p_evt Pointer to the event received from the S110 SoftDevice. + */ +static void start_data_process(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt) +{ + uint32_t err_code; + + dfu_start_packet_t start_packet = {.dfu_update_mode = m_update_mode}; + dfu_update_packet_t update_packet = + { + .packet_type = START_PACKET, + .params.start_packet = &start_packet + }; + + uint32_t length = p_evt->evt.ble_dfu_pkt_write.len; + + // Verify that the data is exactly three * four bytes (three words) long. + if (length != (3 * sizeof(uint32_t))) + { + err_code = ble_dfu_response_send(p_dfu, + BLE_DFU_START_PROCEDURE, + BLE_DFU_RESP_VAL_NOT_SUPPORTED); + APP_ERROR_CHECK(err_code); + } + else + { + // Extract the size of from the DFU Packet Characteristic. + uint8_t * p_length_data = p_evt->evt.ble_dfu_pkt_write.p_data; + + start_packet.sd_image_size = uint32_decode(p_length_data + SD_IMAGE_SIZE_OFFSET); + start_packet.bl_image_size = uint32_decode(p_length_data + BL_IMAGE_SIZE_OFFSET); + start_packet.app_image_size = uint32_decode(p_length_data + APP_IMAGE_SIZE_OFFSET); + + err_code = dfu_start_pkt_handle(&update_packet); + if (err_code != NRF_SUCCESS) + { + // Translate the err_code returned by the above function to DFU Response Value. + ble_dfu_resp_val_t resp_val; + + resp_val = nrf_err_code_translate(err_code, BLE_DFU_START_PROCEDURE); + err_code = ble_dfu_response_send(p_dfu, BLE_DFU_START_PROCEDURE, resp_val); + } + + APP_ERROR_CHECK(err_code); + } +} + + +/**@brief Function for processing initialization data written by the peer to the DFU Packet + * Characteristic. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] p_evt Pointer to the event received from the S110 SoftDevice. + */ +static void init_data_process(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt) +{ + uint32_t err_code; + dfu_update_packet_t dfu_pkt; + + // The DFU module accepts the dfu_pkt.packet_length to be in 'number of words'. And so if the + // received data does not have a size which is a multiple of four, it should be padded with + // zeros and the packet_length should be incremented accordingly before calling + // dfu_init_pkt_handle. + if ((p_evt->evt.ble_dfu_pkt_write.len & (sizeof(uint32_t) - 1)) != 0) + { + uint32_t padding; + uint32_t i; + uint8_t pkt_length = p_evt->evt.ble_dfu_pkt_write.len; + + // Find out the number of bytes to be padded. + padding = sizeof(uint32_t) - (pkt_length & (sizeof(uint32_t) - 1)); + + for (i = 0; i < padding; i++) + { + p_evt->evt.ble_dfu_pkt_write.p_data[pkt_length++] = 0; + } + + p_evt->evt.ble_dfu_pkt_write.len = pkt_length; + } + + dfu_pkt.packet_type = INIT_PACKET; + + dfu_pkt.params.data_packet.p_data_packet = (uint32_t *)p_evt->evt.ble_dfu_pkt_write.p_data; + dfu_pkt.params.data_packet.packet_length = p_evt->evt.ble_dfu_pkt_write.len / sizeof(uint32_t); + + err_code = dfu_init_pkt_handle(&dfu_pkt); + + // Translate the err_code returned by the above function to DFU Response Value. + if (err_code != NRF_SUCCESS) + { + ble_dfu_resp_val_t resp_val = nrf_err_code_translate(err_code, BLE_DFU_INIT_PROCEDURE); + + err_code = ble_dfu_response_send(p_dfu, BLE_DFU_INIT_PROCEDURE, resp_val); + APP_ERROR_CHECK(err_code); + } +} + + +/**@brief Function for processing application data written by the peer to the DFU Packet + * Characteristic. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] p_evt Pointer to the event received from the S110 SoftDevice. + */ +static void app_data_process(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt) +{ + uint32_t err_code; + + if ((p_evt->evt.ble_dfu_pkt_write.len & (sizeof(uint32_t) - 1)) != 0) + { + // Data length is not a multiple of 4 (word size). + err_code = ble_dfu_response_send(p_dfu, + BLE_DFU_RECEIVE_APP_PROCEDURE, + BLE_DFU_RESP_VAL_NOT_SUPPORTED); + APP_ERROR_CHECK(err_code); + return; + } + + uint32_t length = p_evt->evt.ble_dfu_pkt_write.len; + + err_code = hci_mem_pool_rx_produce(length, (void **) &mp_rx_buffer); + if (err_code != NRF_SUCCESS) + { + dfu_error_notify(p_dfu, err_code); + return; + } + + uint8_t * p_data_packet = p_evt->evt.ble_dfu_pkt_write.p_data; + + memcpy(mp_rx_buffer, p_data_packet, length); + + err_code = hci_mem_pool_rx_data_size_set(length); + if (err_code != NRF_SUCCESS) + { + dfu_error_notify(p_dfu, err_code); + return; + } + + err_code = hci_mem_pool_rx_extract(&mp_rx_buffer, &length); + if (err_code != NRF_SUCCESS) + { + dfu_error_notify(p_dfu, err_code); + return; + } + + dfu_update_packet_t dfu_pkt; + + dfu_pkt.packet_type = DATA_PACKET; + dfu_pkt.params.data_packet.packet_length = length / sizeof(uint32_t); + dfu_pkt.params.data_packet.p_data_packet = (uint32_t *)mp_rx_buffer; + + err_code = dfu_data_pkt_handle(&dfu_pkt); + + if (err_code == NRF_SUCCESS) + { + m_num_of_firmware_bytes_rcvd += p_evt->evt.ble_dfu_pkt_write.len; + + // All the expected firmware data has been received and processed successfully. + // Response will be sent when flash operation for final packet is completed. + mp_final_packet = mp_rx_buffer; + } + else if (err_code == NRF_ERROR_INVALID_LENGTH) + { + // Firmware data packet was handled successfully. And more firmware data is expected. + m_num_of_firmware_bytes_rcvd += p_evt->evt.ble_dfu_pkt_write.len; + + // Check if a packet receipt notification is needed to be sent. + if (m_pkt_rcpt_notif_enabled) + { + // Decrement the counter for the number firmware packets needed for sending the + // next packet receipt notification. + m_pkt_notif_target_cnt--; + + if (m_pkt_notif_target_cnt == 0) + { + err_code = ble_dfu_pkts_rcpt_notify(p_dfu, m_num_of_firmware_bytes_rcvd); + APP_ERROR_CHECK(err_code); + + // Reset the counter for the number of firmware packets. + m_pkt_notif_target_cnt = m_pkt_notif_target; + } + } + } + else + { + uint32_t hci_error = hci_mem_pool_rx_consume(mp_rx_buffer); + if (hci_error != NRF_SUCCESS) + { + dfu_error_notify(p_dfu, hci_error); + } + + dfu_error_notify(p_dfu, err_code); + } +} + + +/**@brief Function for processing data written by the peer to the DFU Packet Characteristic. + * + * @param[in] p_dfu DFU Service Structure. + * @param[in] p_evt Pointer to the event received from the S110 SoftDevice. + */ +static void on_dfu_pkt_write(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt) +{ + // The peer has written to the DFU Packet characteristic. Depending on the value of + // the current value of the DFU Control Point, the appropriate action is taken. + switch (m_pkt_type) + { + case PKT_TYPE_START: + // The peer has written a start packet to the DFU Packet characteristic. + start_data_process(p_dfu, p_evt); + break; + + case PKT_TYPE_INIT: + // The peer has written an init packet to the DFU Packet characteristic. + init_data_process(p_dfu, p_evt); + break; + + case PKT_TYPE_FIRMWARE_DATA: + app_data_process(p_dfu, p_evt); + break; + + default: + // It is not possible to find out what packet it is. Ignore. There is no + // mechanism to notify the DFU Controller about this error condition. + break; + } +} + + +/**@brief Function for handling a Connection Parameters error. + * + * @param[in] nrf_error Error code. + */ +static void conn_params_error_handler(uint32_t nrf_error) +{ + APP_ERROR_HANDLER(nrf_error); +} + + +/**@brief Function for initializing the Connection Parameters module. + */ +static void conn_params_init(void) +{ + uint32_t err_code; + ble_conn_params_init_t cp_init; + + memset(&cp_init, 0, sizeof(cp_init)); + + cp_init.p_conn_params = NULL; + cp_init.first_conn_params_update_delay = FIRST_CONN_PARAMS_UPDATE_DELAY; + cp_init.next_conn_params_update_delay = NEXT_CONN_PARAMS_UPDATE_DELAY; + cp_init.max_conn_params_update_count = MAX_CONN_PARAMS_UPDATE_COUNT; + cp_init.start_on_notify_cccd_handle = BLE_GATT_HANDLE_INVALID; + cp_init.disconnect_on_fail = false; + cp_init.evt_handler = NULL; + cp_init.error_handler = conn_params_error_handler; + + err_code = ble_conn_params_init(&cp_init); + APP_ERROR_CHECK(err_code); +} + + +/**@brief Function for the Device Firmware Update Service event handler. + * + * @details This function will be called for all Device Firmware Update Service events which + * are passed to the application. + * + * @param[in] p_dfu Device Firmware Update Service structure. + * @param[in] p_evt Event received from the Device Firmware Update Service. + */ +static void on_dfu_evt(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt) +{ + uint32_t err_code; + ble_dfu_resp_val_t resp_val; + + switch (p_evt->ble_dfu_evt_type) + { + case BLE_DFU_VALIDATE: + err_code = dfu_image_validate(); + + // Translate the err_code returned by the above function to DFU Response Value. + resp_val = nrf_err_code_translate(err_code, BLE_DFU_VALIDATE_PROCEDURE); + + err_code = ble_dfu_response_send(p_dfu, BLE_DFU_VALIDATE_PROCEDURE, resp_val); + APP_ERROR_CHECK(err_code); + break; + + case BLE_DFU_ACTIVATE_N_RESET: + err_code = dfu_transport_ble_close(); + APP_ERROR_CHECK(err_code); + + // With the S110 Flash API it is safe to initiate the activate before connection is + // fully closed. + err_code = dfu_image_activate(); + if (err_code != NRF_SUCCESS) + { + dfu_reset(); + } + break; + + case BLE_DFU_SYS_RESET: + err_code = dfu_transport_ble_close(); + APP_ERROR_CHECK(err_code); + + dfu_reset(); + break; + + case BLE_DFU_START: + m_pkt_type = PKT_TYPE_START; + m_update_mode = (uint8_t)p_evt->evt.ble_dfu_pkt_write.p_data[0]; + break; + + case BLE_DFU_RECEIVE_INIT_DATA: + m_pkt_type = PKT_TYPE_INIT; + if ((uint8_t)p_evt->evt.ble_dfu_pkt_write.p_data[0] == DFU_INIT_COMPLETE) + { + err_code = dfu_init_pkt_complete(); + + // Translate the err_code returned by the above function to DFU Response Value. + resp_val = nrf_err_code_translate(err_code, BLE_DFU_INIT_PROCEDURE); + + err_code = ble_dfu_response_send(p_dfu, BLE_DFU_INIT_PROCEDURE, resp_val); + APP_ERROR_CHECK(err_code); + } + break; + + case BLE_DFU_RECEIVE_APP_DATA: + m_pkt_type = PKT_TYPE_FIRMWARE_DATA; + break; + + case BLE_DFU_PACKET_WRITE: + blinky_fast_set(true); + on_dfu_pkt_write(p_dfu, p_evt); + break; + + case BLE_DFU_PKT_RCPT_NOTIF_ENABLED: + m_pkt_rcpt_notif_enabled = true; + m_pkt_notif_target = p_evt->evt.pkt_rcpt_notif_req.num_of_pkts; + m_pkt_notif_target_cnt = p_evt->evt.pkt_rcpt_notif_req.num_of_pkts; + break; + + case BLE_DFU_PKT_RCPT_NOTIF_DISABLED: + m_pkt_rcpt_notif_enabled = false; + m_pkt_notif_target = 0; + break; + + case BLE_DFU_BYTES_RECEIVED_SEND: + err_code = ble_dfu_bytes_rcvd_report(p_dfu, m_num_of_firmware_bytes_rcvd); + APP_ERROR_CHECK(err_code); + break; + + default: + // Unsupported event received from DFU Service. Ignore. + break; + } +} + + +/**@brief Function for the Advertising functionality initialization. + * + * @details Encodes the required advertising data and passes it to the stack. + * Also builds a structure to be passed to the stack when starting advertising. + */ +static void advertising_init(uint8_t adv_flags) +{ + uint32_t err_code; + ble_advdata_t advdata; + ble_uuid_t service_uuid; + + service_uuid.type = m_dfu.uuid_type; + service_uuid.uuid = BLE_DFU_SERVICE_UUID; + + // Build and set advertising data. + memset(&advdata, 0, sizeof(advdata)); + + advdata.name_type = BLE_ADVDATA_FULL_NAME; + advdata.include_appearance = false; + advdata.flags = adv_flags; + advdata.uuids_more_available.uuid_cnt = 1; + advdata.uuids_more_available.p_uuids = &service_uuid; + + err_code = ble_advdata_set(&advdata, NULL); + APP_ERROR_CHECK(err_code); +} + + +/**@brief Function for starting advertising. + */ +static void advertising_start(void) +{ + if (!m_is_advertising) + { + uint32_t err_code; + + // Initialize advertising parameters (used when starting advertising). + memset(&m_adv_params, 0, sizeof(m_adv_params)); + + if (m_ble_peer_data_valid) + { + ble_gap_irk_t empty_irk = {{0}}; + + if (memcmp(m_ble_peer_data.irk.irk, empty_irk.irk, sizeof(empty_irk.irk)) == 0) + { + advertising_init(BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE); + m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_DIRECT_IND; + m_adv_params.p_peer_addr = &m_ble_peer_data.addr; + m_adv_params.fp = BLE_GAP_ADV_FP_ANY; + m_adv_params.interval = 0; + m_adv_params.timeout = 0; + } + else + { + m_whitelist[0] = &m_ble_peer_data.addr; + err_code = sd_ble_gap_whitelist_set(m_whitelist, 1); + APP_ERROR_CHECK(err_code); + + ble_gap_id_key_t id_key = { + .id_info = m_ble_peer_data.irk, + .id_addr_info = m_ble_peer_data.addr + }; + + m_gap_ids[0] = &id_key; + err_code = sd_ble_gap_device_identities_set(m_gap_ids, NULL, 1); + APP_ERROR_CHECK(err_code); + + advertising_init(BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED); + m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND; + m_adv_params.fp = BLE_GAP_ADV_FP_FILTER_CONNREQ; + m_adv_params.interval = APP_ADV_INTERVAL; + m_adv_params.timeout = APP_ADV_TIMEOUT_IN_SECONDS; + + } + } + else + { + advertising_init(BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE); + m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND; + m_adv_params.p_peer_addr = NULL; + m_adv_params.fp = BLE_GAP_ADV_FP_ANY; + m_adv_params.interval = APP_ADV_INTERVAL; + m_adv_params.timeout = APP_ADV_TIMEOUT_IN_SECONDS; + } + + err_code = sd_ble_gap_adv_start(&m_adv_params, BLE_CONN_CFG_HIGH_BANDWIDTH); + APP_ERROR_CHECK(err_code); + +// led_on(ADVERTISING_LED_PIN_NO); + + m_is_advertising = true; + } +} + + +/**@brief Function for stopping advertising. + */ +static void advertising_stop(void) +{ + if (m_is_advertising) + { + uint32_t err_code; + + err_code = sd_ble_gap_adv_stop(); + APP_ERROR_CHECK(err_code); + +// led_off(ADVERTISING_LED_PIN_NO); + + m_is_advertising = false; + } +} + + +/**@brief Function for the Application's S110 SoftDevice event handler. + * + * @param[in] p_ble_evt S110 SoftDevice event. + */ +static void on_ble_evt(ble_evt_t * p_ble_evt) +{ + uint32_t err_code; + ble_gatts_rw_authorize_reply_params_t auth_reply; + + switch (p_ble_evt->header.evt_id) + { + case BLE_GAP_EVT_CONNECTED: + blinky_ota_connected(); + led_on(LED_BLUE); +// led_off(ADVERTISING_LED_PIN_NO); + + m_conn_handle = p_ble_evt->evt.gap_evt.conn_handle; + m_is_advertising = false; + break; + + case BLE_GAP_EVT_DISCONNECTED: + { + uint8_t sys_attr[128]; + uint16_t sys_attr_len = 128; + + m_direct_adv_cnt = APP_DIRECTED_ADV_TIMEOUT; + blinky_ota_disconneted(); + blinky_fast_set(false); + + led_off(LED_BLUE); + + err_code = sd_ble_gatts_sys_attr_get(m_conn_handle, + sys_attr, + &sys_attr_len, + BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS); + APP_ERROR_CHECK(err_code); + + } + if (!m_tear_down_in_progress) + { + // The Disconnected event is because of an external event. (Link loss or + // disconnect triggered by the DFU Controller before the firmware update was + // complete). + // Restart advertising so that the DFU Controller can reconnect if possible. + advertising_start(); + } + + m_conn_handle = BLE_CONN_HANDLE_INVALID; + + break; + + case BLE_GAP_EVT_SEC_PARAMS_REQUEST: + { + ble_gap_sec_keyset_t keys; + ble_gap_enc_key_t enc_key; + ble_gap_id_key_t id_key; + + id_key.id_addr_info = m_ble_peer_data.addr; + id_key.id_info = m_ble_peer_data.irk; + enc_key = m_ble_peer_data.enc_key; + + keys.keys_peer.p_id_key = &id_key; + keys.keys_peer.p_enc_key = &enc_key; + + err_code = sd_ble_gap_sec_params_reply(m_conn_handle, + BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP, + &m_sec_params, + &keys); + APP_ERROR_CHECK(err_code); + } + break; + + case BLE_GATTS_EVT_TIMEOUT: + if (p_ble_evt->evt.gatts_evt.params.timeout.src == BLE_GATT_TIMEOUT_SRC_PROTOCOL) + { + err_code = sd_ble_gap_disconnect(m_conn_handle, + BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION); + APP_ERROR_CHECK(err_code); + } + break; + + case BLE_GAP_EVT_TIMEOUT: + if (p_ble_evt->evt.gap_evt.params.timeout.src == BLE_GAP_TIMEOUT_SRC_ADVERTISING) + { + m_is_advertising = false; + m_direct_adv_cnt--; + if (m_direct_adv_cnt == 0) + { + dfu_update_status_t update_status = {.status_code = DFU_TIMEOUT}; + bootloader_dfu_update_process(update_status); + } + else + { + advertising_start(); + } + } + break; + + case BLE_EVT_USER_MEM_REQUEST: + err_code = sd_ble_user_mem_reply(m_conn_handle, NULL); + APP_ERROR_CHECK(err_code); + break; + + case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST: + if (p_ble_evt->evt.gatts_evt.params.authorize_request.type + != BLE_GATTS_AUTHORIZE_TYPE_INVALID) + { + if ((p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op + == BLE_GATTS_OP_PREP_WRITE_REQ) + || (p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op + == BLE_GATTS_OP_EXEC_WRITE_REQ_NOW) + || (p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op + == BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL)) + { + if (p_ble_evt->evt.gatts_evt.params.authorize_request.type + == BLE_GATTS_AUTHORIZE_TYPE_WRITE) + { + auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE; + } + else + { + auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_READ; + } + auth_reply.params.write.gatt_status = APP_FEATURE_NOT_SUPPORTED; + + err_code = sd_ble_gatts_rw_authorize_reply(m_conn_handle,&auth_reply); + APP_ERROR_CHECK(err_code); + } + } + break; + + case BLE_GAP_EVT_SEC_INFO_REQUEST: + { + ble_gap_enc_info_t * p_enc_info = NULL; + + // If there is a match in diversifier then set the correct keys. + if (p_ble_evt->evt.gap_evt.params.sec_info_request.master_id.ediv == + m_ble_peer_data.enc_key.master_id.ediv) + { + p_enc_info = &m_ble_peer_data.enc_key.enc_info; + } + + err_code = sd_ble_gap_sec_info_reply(p_ble_evt->evt.gap_evt.conn_handle, + p_enc_info, + &m_ble_peer_data.irk, + NULL); + APP_ERROR_CHECK(err_code); + } + break; + + case BLE_GATTS_EVT_SYS_ATTR_MISSING: + case BLE_GAP_EVT_CONN_SEC_UPDATE: + err_code = service_change_indicate(); + APP_ERROR_CHECK(err_code); + break; + + case BLE_GAP_EVT_AUTH_STATUS: + // No implementation needed. + break; + + case BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST: + // Let Softdevice decide the data length + // ble_gap_data_length_params_t* param = &evt->evt.gap_evt.params.data_length_update_request.peer_params + APP_ERROR_CHECK( sd_ble_gap_data_length_update(m_conn_handle, NULL, NULL) ); + break; + + case BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST: + { + uint16_t att_mtu = MIN(p_ble_evt->evt.gatts_evt.params.exchange_mtu_request.client_rx_mtu, BLEGATT_ATT_MTU_MAX); + APP_ERROR_CHECK( sd_ble_gatts_exchange_mtu_reply(m_conn_handle, att_mtu) ); + } + break; + + default: + // No implementation needed. + break; + } +} + + +/**@brief Function for dispatching a S110 SoftDevice event to all modules with a S110 + * SoftDevice event handler. + * + * @details This function is called from the S110 SoftDevice event interrupt handler after a + * S110 SoftDevice event has been received. + * + * @param[in] p_ble_evt S110 SoftDevice event. + */ +static void ble_evt_dispatch(ble_evt_t * p_ble_evt) +{ + ble_conn_params_on_ble_evt(p_ble_evt); + ble_dfu_on_ble_evt(&m_dfu, p_ble_evt); + on_ble_evt(p_ble_evt); +} + + +/**@brief Function for the LEDs initialization. + * + * @details Initializes all LEDs used by this application. + */ +static void leds_init(void) +{ + // Adafruit: already done in bootloader's main +// nrf_gpio_cfg_output(ADVERTISING_LED_PIN_NO); +// nrf_gpio_cfg_output(CONNECTED_LED_PIN_NO); +// led_off(ADVERTISING_LED_PIN_NO); +// led_off(CONNECTED_LED_PIN_NO); +} + + +/**@brief Function for the GAP initialization. + * + * @details This function will setup all the necessary GAP (Generic Access Profile) parameters of + * the device. It also sets the permissions and appearance. + */ +static void gap_params_init(void) +{ + uint32_t err_code; + ble_gap_conn_params_t gap_conn_params; + ble_gap_conn_sec_mode_t sec_mode; + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); + + err_code = sd_ble_gap_device_name_set(&sec_mode, + (const uint8_t *)DEVICE_NAME, + strlen(DEVICE_NAME)); + APP_ERROR_CHECK(err_code); + + memset(&gap_conn_params, 0, sizeof(gap_conn_params)); + + gap_conn_params.min_conn_interval = MIN_CONN_INTERVAL; + gap_conn_params.max_conn_interval = MAX_CONN_INTERVAL; + gap_conn_params.slave_latency = SLAVE_LATENCY; + gap_conn_params.conn_sup_timeout = CONN_SUP_TIMEOUT; + + err_code = sd_ble_gap_ppcp_set(&gap_conn_params); + APP_ERROR_CHECK(err_code); +} + + +/**@brief Function for handling Service errors. + * + * @details A pointer to this function will be passed to the DFU service which may need to inform + * the application about an error. + * + * @param[in] nrf_error Error code containing information about what went wrong. + */ +static void service_error_handler(uint32_t nrf_error) +{ + APP_ERROR_HANDLER(nrf_error); +} + + +/**@brief Function for initializing services that will be used by the application. + */ +static void services_init(void) +{ + uint32_t err_code; + ble_dfu_init_t dfu_init_obj; + + // Initialize the Device Firmware Update Service. + memset(&dfu_init_obj, 0, sizeof(dfu_init_obj)); + + dfu_init_obj.revision = DFU_REVISION; + dfu_init_obj.evt_handler = on_dfu_evt; + dfu_init_obj.error_handler = service_error_handler; + + err_code = ble_dfu_init(&m_dfu, &dfu_init_obj); + APP_ERROR_CHECK(err_code); + + // Adafruit DIS + ble_dis_init_t dis_init; + memset(&dis_init, 0, sizeof(dis_init)); + + ble_srv_ascii_to_utf8(&dis_init.manufact_name_str, DIS_MANUFACTURER); + ble_srv_ascii_to_utf8(&dis_init.model_num_str, DIS_MODEL); + ble_srv_ascii_to_utf8(&dis_init.fw_rev_str, DIS_FIRMWARE); + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&dis_init.dis_attr_md.read_perm); + BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&dis_init.dis_attr_md.write_perm); + + (void) ble_dis_init(&dis_init); +} + + +/**@brief Function for initializing security parameters. + */ +static void sec_params_init(void) +{ + m_sec_params.bond = SEC_PARAM_BOND; + m_sec_params.mitm = SEC_PARAM_MITM; + m_sec_params.lesc = SEC_PARAM_LESC; + m_sec_params.keypress = SEC_PARAM_KEYPRESS; + m_sec_params.io_caps = SEC_PARAM_IO_CAPABILITIES; + m_sec_params.oob = SEC_PARAM_OOB; + m_sec_params.min_key_size = SEC_PARAM_MIN_KEY_SIZE; + m_sec_params.max_key_size = SEC_PARAM_MAX_KEY_SIZE; +} + + +uint32_t dfu_transport_ble_update_start(void) +{ + uint32_t err_code; + + m_tear_down_in_progress = false; + m_pkt_type = PKT_TYPE_INVALID; + + leds_init(); + + err_code = softdevice_ble_evt_handler_set(ble_evt_dispatch); + VERIFY_SUCCESS(err_code); + + dfu_register_callback(dfu_cb_handler); + + err_code = hci_mem_pool_open(); + VERIFY_SUCCESS(err_code); + + err_code = dfu_ble_peer_data_get(&m_ble_peer_data); + if (err_code == NRF_SUCCESS) + { + m_ble_peer_data_valid = true; + } + else + { + ble_gap_addr_t addr; + + err_code = sd_ble_gap_addr_get(&addr); + APP_ERROR_CHECK(err_code); + + // Increase the BLE address by one when advertising openly. + addr.addr[0] += 1; + + err_code = sd_ble_gap_addr_set(&addr); + APP_ERROR_CHECK(err_code); + +// ble_gap_privacy_params_t privacy = { .privacy_mode = BLE_GAP_PRIVACY_MODE_OFF }; +// sd_ble_gap_privacy_set(&privacy); + } + + gap_params_init(); + services_init(); + conn_params_init(); + sec_params_init(); + + sd_ble_gap_tx_power_set(4); // maximum power + advertising_start(); + + return NRF_SUCCESS; +} + + +uint32_t dfu_transport_ble_close() +{ + uint32_t err_code; + + m_tear_down_in_progress = true; + + if (IS_CONNECTED()) + { + // Disconnect from peer. + err_code = sd_ble_gap_disconnect(m_conn_handle, BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION); + APP_ERROR_CHECK(err_code); + } + else + { + // If not connected, then the device will be advertising. Hence stop the advertising. + advertising_stop(); + } + + err_code = ble_conn_params_stop(); + APP_ERROR_CHECK(err_code); + + return NRF_SUCCESS; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_serial.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_serial.c new file mode 100644 index 0000000..db227e6 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_transport_serial.c @@ -0,0 +1,314 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "dfu_transport.h" +#include +#include "dfu.h" +#include +#include "app_error.h" +#include "app_util.h" +#include "hci_transport.h" +#include "app_timer.h" +#include "app_scheduler.h" + +#define MAX_BUFFERS 4u /**< Maximum number of buffers that can be received queued without being consumed. */ + +/** + * defgroup Data Packet Queue Access Operation Macros + * @{ + */ + +/** Provides status showing if the queue is full or not. */ +#define DATA_QUEUE_FULL() \ + (((MAX_BUFFERS -1) == m_data_queue.count) ? true : false) + +/** Provides status showing if the queue is empty or not */ +#define DATA_QUEUE_EMPTY() \ + ((0 == m_data_queue.count) ? true : false) + +/** Initializes an element of the data queue. */ +#define DATA_QUEUE_ELEMENT_INIT(i) \ + m_data_queue.data_packet[(i)].packet_type = INVALID_PACKET + +/** Sets the packet type of an element of the data queue. */ +#define DATA_QUEUE_ELEMENT_SET_PTYPE(i, t) \ + m_data_queue.data_packet[(i)].packet_type = (t) + +/** Copies a data packet pointer of an element of the data queue. */ +#define DATA_QUEUE_ELEMENT_COPY_PDATA(i, dp) \ + m_data_queue.data_packet[(i)].params.data_packet.p_data_packet = (uint32_t *)(dp) + +/** Sets the packet length of an element in the data queue. */ +#define DATA_QUEUE_ELEMENT_SET_PLEN(i, l) \ + m_data_queue.data_packet[(i)].params.data_packet.packet_length = (l) + +/** Gets a data packet pointer of an element in the data queue. */ +#define DATA_QUEUE_ELEMENT_GET_PDATA(i) \ + (m_data_queue.data_packet[(i)].params.data_packet.p_data_packet) + +/** Gets the packet type of an element in the data queue. */ +#define DATA_QUEUE_ELEMENT_GET_PTYPE(i) \ + m_data_queue.data_packet[(i)].packet_type + +/* @} */ + +/** Abstracts data packet queue */ +typedef struct +{ + dfu_update_packet_t data_packet[MAX_BUFFERS]; /**< Bootloader data packets used when processing data from the UART. */ + volatile uint8_t count; /**< Counter to maintain number of elements in the queue. */ +} dfu_data_queue_t; + +static dfu_data_queue_t m_data_queue; /**< Received-data packet queue. */ + +/**@brief Initializes an element of the data buffer queue. + * + * @param[in] element_index index of the element. + */ +static void data_queue_element_init (uint8_t element_index) +{ + DATA_QUEUE_ELEMENT_INIT(element_index); + DATA_QUEUE_ELEMENT_SET_PTYPE(element_index, INVALID_PACKET); + DATA_QUEUE_ELEMENT_COPY_PDATA(element_index, NULL); + DATA_QUEUE_ELEMENT_SET_PLEN(element_index, 0); +} + +/** Initializes data buffer queue */ +static void data_queue_init(void) +{ + uint32_t index; + + m_data_queue.count = 0; + + for (index = 0; index < MAX_BUFFERS; index++) + { + data_queue_element_init(index); + } +} + +/**@brief Function for freeing an element. + * + * @param[in] element_index index of the element. + */ +static uint32_t data_queue_element_free(uint8_t element_index) +{ + uint8_t * p_data; + uint32_t retval; + + retval = NRF_ERROR_INVALID_PARAM; + + if (MAX_BUFFERS > element_index) + { + p_data = (uint8_t *)DATA_QUEUE_ELEMENT_GET_PDATA(element_index); + if (INVALID_PACKET != DATA_QUEUE_ELEMENT_GET_PTYPE(element_index)) + { + m_data_queue.count--; + data_queue_element_init (element_index); + retval = hci_transport_rx_pkt_consume((p_data - 4)); + APP_ERROR_CHECK(retval); + } + } + else + { + return NRF_ERROR_INVALID_PARAM; + } + + return NRF_SUCCESS; +} + +/**@brief Function for Allocating element. + * + * @param[in] packet_type packet type. + * @param[out] p_element_index index of the element. + */ +static uint32_t data_queue_element_alloc(uint8_t * p_element_index, uint8_t packet_type) +{ + uint32_t retval; + uint32_t index; + + retval = NRF_ERROR_NO_MEM; + + if (INVALID_PACKET == packet_type) + { + retval = NRF_ERROR_INVALID_PARAM; + } + else if (true == DATA_QUEUE_FULL()) + { + retval = NRF_ERROR_NO_MEM; + } + else + { + for (index = 0; index < MAX_BUFFERS; index++) + { + if (INVALID_PACKET == DATA_QUEUE_ELEMENT_GET_PTYPE(index)) + { + // Found a free element: allocate, and end search. + *p_element_index = index; + DATA_QUEUE_ELEMENT_SET_PTYPE(index, packet_type); + retval = NRF_SUCCESS; + m_data_queue.count++; + break; + } + } + } + + return retval; +} + +// Flush everything on disconnect or stop. +static void data_queue_flush(void) +{ + uint32_t index; + + for (index = 0; index < MAX_BUFFERS; index++) + { + // In this case it does not matter if free succeeded or not as data packets are being flushed because DFU Trnsport was closed + (void)data_queue_element_free(index); + } +} + + +/**@brief Function for handling the callback events from the dfu module. + * Callbacks are expected when \ref dfu_data_pkt_handle has been executed. + * + * @param[in] packet Packet type for which this callback is related. START_PACKET, DATA_PACKET. + * @param[in] result Operation result code. NRF_SUCCESS when a queued operation was successful. + * @param[in] p_data Pointer to the data to which the operation is related. + */ +static void dfu_cb_handler(uint32_t packet, uint32_t result, uint8_t * p_data) +{ + APP_ERROR_CHECK(result); +} + + +static void process_dfu_packet(void * p_event_data, uint16_t event_size) +{ + uint32_t retval; + uint32_t index; + dfu_update_packet_t * packet; + + // Adafruit modification for startup dfu + extern bool forced_startup_dfu_packet_received; + forced_startup_dfu_packet_received = true; + + while (false == DATA_QUEUE_EMPTY()) + { + // Fetch the element to be processed. + for (index = 0; index < MAX_BUFFERS ; index++) + { + packet = &m_data_queue.data_packet[index]; + if (INVALID_PACKET != packet->packet_type) + { + extern void blinky_fast_set(bool isFast); + switch (DATA_QUEUE_ELEMENT_GET_PTYPE(index)) + { + case DATA_PACKET: + (void)dfu_data_pkt_handle(packet); + break; + + case START_PACKET: + packet->params.start_packet = + (dfu_start_packet_t*)packet->params.data_packet.p_data_packet; + retval = dfu_start_pkt_handle(packet); + APP_ERROR_CHECK(retval); + break; + + case INIT_PACKET: + (void)dfu_init_pkt_handle(packet); + retval = dfu_init_pkt_complete(); + APP_ERROR_CHECK(retval); + + blinky_fast_set(true); + break; + + case STOP_DATA_PACKET: + (void)dfu_image_validate(); + (void)dfu_image_activate(); + + blinky_fast_set(false); + + // Break the loop by returning. + return; + + default: + // No implementation needed. + break; + } + + // Free the processed element. + retval = data_queue_element_free(index); + APP_ERROR_CHECK(retval); + } + } + } +} + + +void rpc_transport_event_handler(hci_transport_evt_t event) +{ + uint32_t retval; + uint16_t rpc_cmd_length_read = 0; + uint8_t * p_rpc_cmd_buffer = NULL; + uint8_t element_index; + + retval = hci_transport_rx_pkt_extract(&p_rpc_cmd_buffer, &rpc_cmd_length_read); + if (NRF_SUCCESS == retval) + { + // Verify if the data queue can buffer the packet. + retval = data_queue_element_alloc(&element_index, p_rpc_cmd_buffer[0]); + if (NRF_SUCCESS == retval) + { + //subtract 1 since we are interested in payload length and not the type field. + DATA_QUEUE_ELEMENT_SET_PLEN(element_index,(rpc_cmd_length_read / sizeof(uint32_t)) - 1); + DATA_QUEUE_ELEMENT_COPY_PDATA(element_index, &p_rpc_cmd_buffer[4]); + retval = app_sched_event_put(NULL, 0, process_dfu_packet); + } + } + + if (p_rpc_cmd_buffer != NULL && NRF_SUCCESS != retval) + { + // Free the packet that could not be processed. + retval = hci_transport_rx_pkt_consume(p_rpc_cmd_buffer); + APP_ERROR_CHECK(retval); + } +} + + +uint32_t dfu_transport_serial_update_start(void) +{ + uint32_t err_code; + + // Initialize data buffer queue. + data_queue_init(); + + dfu_register_callback(dfu_cb_handler); + + // Open transport layer. + err_code = hci_transport_open(); + APP_ERROR_CHECK(err_code); + + // Register callback to be run when commands have been received by the transport layer. + err_code = hci_transport_evt_handler_reg(rpc_transport_event_handler); + APP_ERROR_CHECK(err_code); + + return NRF_SUCCESS; +} + + +uint32_t dfu_transport_serial_close(void) +{ + // Remove all buffered packets. + data_queue_flush(); + + return hci_transport_close(); +} + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_types.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_types.h new file mode 100644 index 0000000..07483f0 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/dfu_types.h @@ -0,0 +1,168 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup nrf_dfu_types Types and definitions. + * @{ + * + * @ingroup nrf_dfu + * + * @brief Device Firmware Update module type and definitions. + */ + +#ifndef DFU_TYPES_H__ +#define DFU_TYPES_H__ + +#include +#include "nrf_sdm.h" +#include "nrf_mbr.h" +#include "nrf.h" +#include "app_util.h" + +#define NRF_UICR_BOOT_START_ADDRESS (NRF_UICR_BASE + 0x14) /**< Register where the bootloader start address is stored in the UICR register. */ + +#if defined(NRF52) +#define NRF_UICR_MBR_PARAMS_PAGE_ADDRESS (NRF_UICR_BASE + 0x18) /**< Register where the mbr params page is stored in the UICR register. (Only in use in nRF52 MBR).*/ +#endif + +#define CODE_REGION_1_START SD_SIZE_GET(MBR_SIZE) /**< This field should correspond to the size of Code Region 0, (which is identical to Start of Code Region 1), found in UICR.CLEN0 register. This value is used for compile safety, as the linker will fail if application expands into bootloader. Runtime, the bootloader will use the value found in UICR.CLEN0. */ +#define SOFTDEVICE_REGION_START MBR_SIZE /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */ + +#ifdef NRF51 + +#define CODE_PAGE_SIZE 0x0400 /**< Size of a flash codepage. Used for size of the reserved flash space in the bootloader region. Will be runtime checked against NRF_UICR->CODEPAGESIZE to ensure the region is correct. */ + +#ifdef SIGNING + +#define BOOTLOADER_REGION_START 0x00039C00 /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */ +#define BOOTLOADER_SETTINGS_ADDRESS 0x0003D800 /**< The field specifies the page location of the bootloader settings address. */ + +#else + +#define BOOTLOADER_REGION_START 0x0003C000 /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */ +#define BOOTLOADER_SETTINGS_ADDRESS 0x0003FC00 /**< The field specifies the page location of the bootloader settings address. */ + +#endif + + + +#elif defined(NRF52) + +#define BOOTLOADER_REGION_START 0x00074000 /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */ +#define BOOTLOADER_SETTINGS_ADDRESS 0x0007F000 /**< The field specifies the page location of the bootloader settings address. */ +#define BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS 0x0007E000 /**< The field specifies the page location of the mbr params page address. */ + +#define CODE_PAGE_SIZE 0x1000 /**< Size of a flash codepage. Used for size of the reserved flash space in the bootloader region. Will be runtime checked against NRF_UICR->CODEPAGESIZE to ensure the region is correct. */ + +#else + +#error No target defined + +#endif + +#define DFU_REGION_TOTAL_SIZE (BOOTLOADER_REGION_START - CODE_REGION_1_START) /**< Total size of the region between SD and Bootloader. */ + +#ifndef DFU_APP_DATA_RESERVED +#define DFU_APP_DATA_RESERVED CODE_PAGE_SIZE * 7 /**< Size of Application Data that must be preserved between application updates. This value must be a multiple of page size. Page size is 0x400 (1024d) bytes, thus this value must be 0x0000, 0x0400, 0x0800, 0x0C00, 0x1000, etc. */ +#endif + +#define DFU_IMAGE_MAX_SIZE_FULL (DFU_REGION_TOTAL_SIZE - DFU_APP_DATA_RESERVED) /**< Maximum size of an application, excluding save data from the application. */ + +#define DFU_IMAGE_MAX_SIZE_BANKED (((DFU_IMAGE_MAX_SIZE_FULL) - \ + (DFU_IMAGE_MAX_SIZE_FULL % (2 * CODE_PAGE_SIZE)))/2) /**< Maximum size of an application, excluding save data from the application. */ + +#define DFU_BL_IMAGE_MAX_SIZE (BOOTLOADER_SETTINGS_ADDRESS - BOOTLOADER_REGION_START) /**< Maximum size of a bootloader, excluding save data from the current bootloader. */ + +#define DFU_BANK_0_REGION_START CODE_REGION_1_START /**< Bank 0 region start. */ +#define DFU_BANK_1_REGION_START (DFU_BANK_0_REGION_START + DFU_IMAGE_MAX_SIZE_BANKED) /**< Bank 1 region start. */ + +#define EMPTY_FLASH_MASK 0xFFFFFFFF /**< Bit mask that defines an empty address in flash. */ + +#define INVALID_PACKET 0x00 /**< Invalid packet identifies. */ +#define INIT_PACKET 0x01 /**< Packet identifies for initialization packet. */ +#define STOP_INIT_PACKET 0x02 /**< Packet identifies for stop initialization packet. Used when complete init packet has been received so that the init packet can be used for pre validaiton. */ +#define START_PACKET 0x03 /**< Packet identifies for the Data Start Packet. */ +#define DATA_PACKET 0x04 /**< Packet identifies for a Data Packet. */ +#define STOP_DATA_PACKET 0x05 /**< Packet identifies for the Data Stop Packet. */ + +#define DFU_UPDATE_SD 0x01 /**< Bit field indicating update of SoftDevice is ongoing. */ +#define DFU_UPDATE_BL 0x02 /**< Bit field indicating update of bootloader is ongoing. */ +#define DFU_UPDATE_APP 0x04 /**< Bit field indicating update of application is ongoing. */ + +#define DFU_INIT_RX 0x00 /**< Op Code identifies for receiving init packet. */ +#define DFU_INIT_COMPLETE 0x01 /**< Op Code identifies for transmission complete of init packet. */ + +// Safe guard to ensure during compile time that the DFU_APP_DATA_RESERVED is a multiple of page size. +STATIC_ASSERT((((DFU_APP_DATA_RESERVED) & (CODE_PAGE_SIZE - 1)) == 0x00)); + +/**@brief Structure holding a start packet containing update mode and image sizes. + */ +typedef struct +{ + uint8_t dfu_update_mode; /**< Packet type, used to identify the content of the received packet referenced by data packet. */ + uint32_t sd_image_size; /**< Size of the SoftDevice image to be transferred. Zero if no SoftDevice image will be transfered. */ + uint32_t bl_image_size; /**< Size of the Bootloader image to be transferred. Zero if no Bootloader image will be transfered. */ + uint32_t app_image_size; /**< Size of the application image to be transmitted. Zero if no Bootloader image will be transfered. */ +} dfu_start_packet_t; + +/**@brief Structure holding a bootloader init/data packet received. + */ +typedef struct +{ + uint32_t packet_length; /**< Packet length of the data packet. Each data is word size, meaning length of 4 is 4 words, not bytes. */ + uint32_t * p_data_packet; /**< Data Packet received. Each data is a word size entry. */ +} dfu_data_packet_t; + +/**@brief Structure for holding dfu update packet. Packet type indicate the type of packet. + */ +typedef struct +{ + uint32_t packet_type; /**< Packet type, used to identify the content of the received packet referenced by data packet. */ + union + { + dfu_data_packet_t data_packet; /**< Used when packet type is INIT_PACKET or DATA_PACKET. Packet contains data received for init or data. */ + dfu_start_packet_t * start_packet; /**< Used when packet type is START_DATA_PACKET. Will contain information on software to be updtaed, i.e. SoftDevice, Bootloader and/or Application along with image sizes. */ + } params; +} dfu_update_packet_t; + +/**@brief DFU status error codes. +*/ +typedef enum +{ + DFU_UPDATE_APP_COMPLETE, /**< Status update of application complete.*/ + DFU_UPDATE_SD_COMPLETE, /**< Status update of SoftDevice update complete. Note that this solely indicates that a new SoftDevice has been received and stored in bank 0 and 1. */ + DFU_UPDATE_SD_SWAPPED, /**< Status update of SoftDevice update complete. Note that this solely indicates that a new SoftDevice has been received and stored in bank 0 and 1. */ + DFU_UPDATE_BOOT_COMPLETE, /**< Status update complete.*/ + DFU_BANK_0_ERASED, /**< Status bank 0 erased.*/ + DFU_TIMEOUT, /**< Status timeout.*/ + DFU_RESET /**< Status Reset to indicate current update procedure has been aborted and system should reset. */ +} dfu_update_status_code_t; + +/**@brief Structure holding DFU complete event. +*/ +typedef struct +{ + dfu_update_status_code_t status_code; /**< Device Firmware Update status. */ + uint16_t app_crc; /**< CRC of the recieved application. */ + uint32_t sd_size; /**< Size of the recieved SoftDevice. */ + uint32_t bl_size; /**< Size of the recieved BootLoader. */ + uint32_t app_size; /**< Size of the recieved Application. */ + uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */ +} dfu_update_status_t; + +/**@brief Update complete handler type. */ +typedef void (*dfu_complete_handler_t)(dfu_update_status_t dfu_update_status); + +#endif // DFU_TYPES_H__ + +/**@} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h new file mode 100644 index 0000000..fdfd3fe --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h @@ -0,0 +1,32 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup memory_pool_internal Memory Pool Internal + * @{ + * @ingroup memory_pool + * + * @brief Memory pool internal definitions + */ + +#ifndef MEM_POOL_INTERNAL_H__ +#define MEM_POOL_INTERNAL_H__ + +#define TX_BUF_SIZE 32u /**< TX buffer size in bytes. */ +#define RX_BUF_SIZE 600u /**< RX buffer size in bytes. */ + +#define RX_BUF_QUEUE_SIZE 2u /**< RX buffer element size. */ + +#endif // MEM_POOL_INTERNAL_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_transport_config.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_transport_config.h new file mode 100644 index 0000000..9dc1866 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/bootloader_dfu/hci_transport/hci_transport_config.h @@ -0,0 +1,45 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup ble_sdk_bootloader_hci_congfig HCI Transport Layer Configuration + * @{ + * @ingroup dfu_bootloader_api + * @brief Definition of HCI Transport Layer configurable parameters + */ + +#ifndef HCI_TRANSPORT_CONFIG_H__ +#define HCI_TRANSPORT_CONFIG_H__ + +#include "boards.h" /**< Default include for boards.h which means that default pin numbers will be used for RX, TX, CTS, and RTS on the UART. Other pin number can be used if desired. */ + +/** This section covers configurable parameters for the HCI Transport SLIP layer. */ +#define HCI_SLIP_UART_RX_PIN_NUMBER RX_PIN_NUMBER /**< Defines the UART RX pin number. The default pin for the board is chosen, but can be overwritten. */ + +#define HCI_SLIP_UART_TX_PIN_NUMBER TX_PIN_NUMBER /**< Defines the UART TX pin number. The default pin for the board is chosen, but can be overwritten. */ + +#define HCI_SLIP_UART_RTS_PIN_NUMBER RTS_PIN_NUMBER /**< Defines the UART RTS pin number. The default pin for the board is chosen, but can be overwritten. */ + +#define HCI_SLIP_UART_CTS_PIN_NUMBER CTS_PIN_NUMBER /**< Defines the UART CTS pin number. The default pin for the board is chosen, but can be overwritten. */ + +#define HCI_SLIP_UART_MODE APP_UART_FLOW_CONTROL_DISABLED /**< Defines the UART mode to be used. Use UART Low Power with Flow Control - Valid values are defined in \ref app_uart_flow_control_t. For further information on the UART Low Power mode, please refer to: \ref app_uart . */ + +#define HCI_SLIP_UART_BAUDRATE UART_BAUDRATE_BAUDRATE_Baud115200 // UART_BAUDRATE_BAUDRATE_Baud38400 /**< Defines the UART Baud rate. Default is 38400 baud. */ + +/** This section covers configurable parameters for the HCI Transport layer that are used for calculating correct value for the retransmission timer timeout. */ +#define MAX_PACKET_SIZE_IN_BITS 8000u /**< Maximum size of a single application packet in bits. */ +#define USED_BAUD_RATE 115200u /**< The used uart baudrate. */ + +#endif // HCI_TRANSPORT_CONFIG_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.c new file mode 100644 index 0000000..aa289af --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.c @@ -0,0 +1,31 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "crc16.h" + +#include + +uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc) +{ + uint16_t crc = (p_crc == NULL) ? 0xFFFF : *p_crc; + + for (uint32_t i = 0; i < size; i++) + { + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= p_data[i]; + crc ^= (uint8_t)(crc & 0xFF) >> 4; + crc ^= (crc << 8) << 4; + crc ^= ((crc & 0xFF) << 4) << 1; + } + + return crc; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.h new file mode 100644 index 0000000..63defad --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/crc16/crc16.h @@ -0,0 +1,44 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup crc_compute CRC compute + * @{ + * @ingroup hci_transport + * + * @brief This module implements CRC-16-CCITT (polynomial 0x1021) with 0xFFFF initial value. + * The data can be passed in multiple blocks. + */ + +#ifndef CRC16_H__ +#define CRC16_H__ + +#include + +/**@brief Function for calculating CRC-16 in blocks. + * + * Feed each consecutive data block into this function, along with the current value of p_crc as + * returned by the previous call of this function. The first call of this function should pass NULL + * as the initial value of the crc in p_crc. + * + * @param[in] p_data The input data block for computation. + * @param[in] size The size of the input data block in bytes. + * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call. + * + * @return The updated CRC-16 value, based on the input supplied. + */ +uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc); + +#endif // CRC16_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.c new file mode 100644 index 0000000..e0cfe9e --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.c @@ -0,0 +1,186 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_fifo.h" +#include "sdk_common.h" +#include "nordic_common.h" + +static __INLINE uint32_t fifo_length(app_fifo_t * p_fifo) +{ + uint32_t tmp = p_fifo->read_pos; + return p_fifo->write_pos - tmp; +} + + +#define FIFO_LENGTH fifo_length(p_fifo) /**< Macro for calculating the FIFO length. */ + + +/**@brief Put one byte to the FIFO. */ +static __INLINE void fifo_put(app_fifo_t * p_fifo, uint8_t byte) +{ + p_fifo->p_buf[p_fifo->write_pos & p_fifo->buf_size_mask] = byte; + p_fifo->write_pos++; +} + + +/**@brief Look at one byte in the FIFO. */ +static __INLINE void fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte) +{ + *p_byte = p_fifo->p_buf[(p_fifo->read_pos + index) & p_fifo->buf_size_mask]; +} + + +/**@brief Get one byte from the FIFO. */ +static __INLINE void fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte) +{ + fifo_peek(p_fifo, 0, p_byte); + p_fifo->read_pos++; +} + + +uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size) +{ + // Check buffer for null pointer. + if (p_buf == NULL) + { + return NRF_ERROR_NULL; + } + + // Check that the buffer size is a power of two. + if (!IS_POWER_OF_TWO(buf_size)) + { + return NRF_ERROR_INVALID_LENGTH; + } + + p_fifo->p_buf = p_buf; + p_fifo->buf_size_mask = buf_size - 1; + p_fifo->read_pos = 0; + p_fifo->write_pos = 0; + + return NRF_SUCCESS; +} + + +uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte) +{ + if (FIFO_LENGTH <= p_fifo->buf_size_mask) + { + fifo_put(p_fifo, byte); + return NRF_SUCCESS; + } + + return NRF_ERROR_NO_MEM; +} + + +uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte) +{ + if (FIFO_LENGTH != 0) + { + fifo_get(p_fifo, p_byte); + return NRF_SUCCESS; + } + + return NRF_ERROR_NOT_FOUND; + +} + + +uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte) +{ + if (FIFO_LENGTH > index) + { + fifo_peek(p_fifo, index, p_byte); + return NRF_SUCCESS; + } + + return NRF_ERROR_NOT_FOUND; +} + + +uint32_t app_fifo_flush(app_fifo_t * p_fifo) +{ + p_fifo->read_pos = p_fifo->write_pos; + return NRF_SUCCESS; +} + + +uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size) +{ + VERIFY_PARAM_NOT_NULL(p_fifo); + VERIFY_PARAM_NOT_NULL(p_size); + + const uint32_t byte_count = fifo_length(p_fifo); + const uint32_t requested_len = (*p_size); + uint32_t index = 0; + uint32_t read_size = MIN(requested_len, byte_count); + + (*p_size) = byte_count; + + // Check if the FIFO is empty. + if (byte_count == 0) + { + return NRF_ERROR_NOT_FOUND; + } + + // Check if application has requested only the size. + if (p_byte_array == NULL) + { + return NRF_SUCCESS; + } + + // Fetch bytes from the FIFO. + while (index < read_size) + { + fifo_get(p_fifo, &p_byte_array[index++]); + } + + (*p_size) = read_size; + + return NRF_SUCCESS; +} + + +uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size) +{ + VERIFY_PARAM_NOT_NULL(p_fifo); + VERIFY_PARAM_NOT_NULL(p_size); + + const uint32_t available_count = p_fifo->buf_size_mask - fifo_length(p_fifo) + 1; + const uint32_t requested_len = (*p_size); + uint32_t index = 0; + uint32_t write_size = MIN(requested_len, available_count); + + (*p_size) = available_count; + + // Check if the FIFO is FULL. + if (available_count == 0) + { + return NRF_ERROR_NO_MEM; + } + + // Check if application has requested only the size. + if (p_byte_array == NULL) + { + return NRF_SUCCESS; + } + + //Fetch bytes from the FIFO. + while (index < write_size) + { + fifo_put(p_fifo, p_byte_array[index++]); + } + + (*p_size) = write_size; + + return NRF_SUCCESS; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.h new file mode 100644 index 0000000..300adca --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/fifo/app_fifo.h @@ -0,0 +1,145 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup app_fifo FIFO implementation + * @{ + * @ingroup app_common + * + * @brief FIFO implementation. + */ + +#ifndef APP_FIFO_H__ +#define APP_FIFO_H__ + +#include +#include + +/**@brief A FIFO instance structure. + * @details Keeps track of which bytes to read and write next. + * Also, it keeps the information about which memory is allocated for the buffer + * and its size. This structure must be initialized by app_fifo_init() before use. + */ +typedef struct +{ + uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */ + uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */ + volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */ + volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */ +} app_fifo_t; + +/**@brief Function for initializing the FIFO. + * + * @param[out] p_fifo FIFO object. + * @param[in] p_buf FIFO buffer for storing data. The buffer size must be a power of two. + * @param[in] buf_size Size of the FIFO buffer provided. This size must be a power of two. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer. + * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two. + */ +uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size); + +/**@brief Function for adding an element to the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. + * @param[in] byte Data byte to add to the FIFO. + * + * @retval NRF_SUCCESS If an element has been successfully added to the FIFO. + * @retval NRF_ERROR_NO_MEM If the FIFO is full. + */ +uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte); + +/**@brief Function for getting the next element from the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. + * @param[out] p_byte Byte fetched from the FIFO. + * + * @retval NRF_SUCCESS If an element was returned. + * @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue. + */ +uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte); + +/**@brief Function for looking at an element in the FIFO, without consuming it. + * + * @param[in] p_fifo Pointer to the FIFO. + * @param[in] index Which element to look at. The lower the index, the earlier it was put. + * @param[out] p_byte Byte fetched from the FIFO. + * + * @retval NRF_SUCCESS If an element was returned. + * @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue, or the index was + * too large. + */ +uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte); + +/**@brief Function for flushing the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. + * + * @retval NRF_SUCCESS If the FIFO was flushed successfully. + */ +uint32_t app_fifo_flush(app_fifo_t * p_fifo); + +/**@brief Function for reading bytes from the FIFO. + * + * This function can also be used to get the number of bytes in the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. Must not be NULL. + * @param[out] p_byte_array Memory pointer where the read bytes are fetched from the FIFO. + * Can be NULL. If NULL, the number of bytes that can be read in the FIFO + * are returned in the p_size parameter. + * @param[inout] p_size Address to memory indicating the maximum number of bytes to be read. + * The provided memory is overwritten with the actual number of bytes + * read if the procedure was successful. This field must not be NULL. + * If p_byte_array is set to NULL by the application, this parameter + * returns the number of bytes in the FIFO. + * + * @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes read might + * be less than the requested maximum, depending on how many elements exist + * in the FIFO. Even if less bytes are returned, the procedure is considered + * successful. + * @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not + * be NULL. + * @retval NRF_ERROR_NOT_FOUND If the FIFO is empty. + */ +uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size); + +/**@brief Function for writing bytes to the FIFO. + * + * This function can also be used to get the available size on the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. Must not be NULL. + * @param[in] p_byte_array Memory pointer containing the bytes to be written to the FIFO. + * Can be NULL. If NULL, this function returns the number of bytes + * that can be written to the FIFO. + * @param[inout] p_size Address to memory indicating the maximum number of bytes to be written. + * The provided memory is overwritten with the number of bytes that were actually + * written if the procedure is successful. This field must not be NULL. + * If p_byte_array is set to NULL by the application, this parameter + * returns the number of bytes available in the FIFO. + * + * @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes written might + * be less than the requested maximum, depending on how much room there is in + * the FIFO. Even if less bytes are written, the procedure is considered + * successful. If the write was partial, the application should use + * subsequent calls to attempt writing the data again. + * @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not + * be NULL. + * @retval NRF_ERROR_NO_MEM If the FIFO is full. + * + */ +uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size); + +#endif // APP_FIFO_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault.h new file mode 100644 index 0000000..3cb099a --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault.h @@ -0,0 +1,60 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#ifndef HARFAULT_H__ +#define HARFAULT_H__ +#include +#include +/** + * @defgroup hardfault_default HardFault exception + * @{ + * @brief Default HardFault exception implementation. + * @ingroup app_common + */ + +/** + * @brief Contents of the stack. + * + * This structure is used to re-create the stack layout after a HardFault exception was raised. + */ +typedef struct HardFault_stack +{ + uint32_t r0; ///< R0 register. + uint32_t r1; ///< R1 register. + uint32_t r2; ///< R2 register. + uint32_t r3; ///< R3 register. + uint32_t r12; ///< R12 register. + uint32_t lr; ///< Link register. + uint32_t pc; ///< Program counter. + uint32_t psr; ///< Program status register. +}HardFault_stack_t; + +/** + * @brief Function for processing HardFault exceptions. + * + * An application that needs to process HardFault exceptions should provide an implementation of this function. + * It will be called from the HardFault handler. + * If no implementation is provided, the library uses a default one, which just restarts the MCU. + * + * @note If the DEBUG_NRF macro is defined, the software breakpoint is set just before the call + * to this function. + * + * @param p_stack Pointer to the stack bottom. + * This pointer might be NULL if the HardFault was called when the main stack was + * the active stack and a stack overrun is detected. + * In such a situation, the stack pointer is reinitialized to the default position, + * and the stack content is lost. + */ +void HardFault_process(HardFault_stack_t *p_stack); + +/** @} */ +#endif /* HARFAULT_H__ */ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault_implementation.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault_implementation.c new file mode 100644 index 0000000..0a5fee8 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault_implementation.c @@ -0,0 +1,47 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#include "hardfault.h" +#include "nrf.h" +#include "compiler_abstraction.h" +#include "nordic_common.h" +#ifdef SOFTDEVICE_PRESENT +#include "nrf_soc.h" +#endif + +#if defined(DEBUG_NRF) +/** + * @brief Pointer to the last received stack pointer. + * + * This pointer is set in the debug version of the HardFault handler. + * It helps to debug HardFault reasons. + */ +volatile HardFault_stack_t *HardFault_p_stack; +#endif + +/*lint -save -e14 */ +__WEAK void HardFault_process(HardFault_stack_t *p_stack) +{ + // Restart the system by default + NVIC_SystemReset(); +} +/*lint -restore */ + +void HardFault_c_handler( uint32_t *p_stack_address ) +{ +#if defined(DEBUG_NRF) + HardFault_p_stack = (HardFault_stack_t*)p_stack_address; + /* Generate breakpoint if debugger is connected */ + __BKPT(0); +#endif + + HardFault_process((HardFault_stack_t*)p_stack_address); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_gcc.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_gcc.c new file mode 100644 index 0000000..e29b6c0 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_gcc.c @@ -0,0 +1,52 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#include + +void HardFault_Handler(void) __attribute__(( naked )); + +void HardFault_Handler(void) +{ + __asm volatile( + " .syntax unified \n" + + " ldr r0, =0xFFFFFFFD \n" + " cmp r0, lr \n" + " bne HardFault_Handler_ChooseMSP \n" + /* Reading PSP into R0 */ + " mrs r0, PSP \n" + " b HardFault_Handler_Continue \n" + "HardFault_Handler_ChooseMSP: \n" + /* Reading MSP into R0 */ + " mrs r0, MSP \n" + /* ----------------------------------------------------------------- + * If we have selected MSP check if we may use stack safetly. + * If not - reset the stack to the initial value. */ + " ldr r1, =__StackTop \n" + " ldr r2, =__StackLimit \n" + + /* MSP is in the range of <__StackTop, __StackLimit) */ + " cmp r0, r1 \n" + " bhi HardFault_MoveSP \n" + " cmp r0, r2 \n" + " bhi HardFault_Handler_Continue \n" + /* ----------------------------------------------------------------- */ + "HardFault_MoveSP: \n" + " mov SP, r1 \n" + " movs r0, #0 \n" + + "HardFault_Handler_Continue: \n" + " ldr r3, =HardFault_c_handler \n" + " bx r3 \n" + + " .align \n" + ); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_iar.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_iar.c new file mode 100644 index 0000000..cfd341b --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_iar.c @@ -0,0 +1,65 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#include + +#pragma section = "CSTACK" +extern void HardFault_c_handler( uint32_t * ); + +__stackless void HardFault_Handler(void); + +__stackless void HardFault_Handler(void) +{ + __asm volatile( + " ldr r0, 100f \n" + " cmp r0, lr \n" + " bne 1f \n" + /* Reading PSP into R0 */ + " mrs r0, PSP \n" + " b 3f \n" + "1: \n" + /* Reading MSP into R0 */ + " mrs r0, MSP \n" + /* ----------------------------------------------------------------- + * If we have selected MSP check if we may use stack safetly. + * If not - reset the stack to the initial value. */ + " ldr r1, 101f \n" + " ldr r2, 102f \n" + + /* MSP is in the range of <__StackTop, __StackLimit) */ + " cmp r0, r1 \n" + " bhi 2f \n" + " cmp r0, r2 \n" + " bhi 3f \n" + /* ----------------------------------------------------------------- */ + "2: \n" + " mov SP, r1 \n" + " movs r0, #0 \n" + + "3: \n" + " ldr r3, 103f \n" + " bx r3 \n" + + "100: \n" + " DC32 0xFFFFFFFD \n" + "101: \n" + " DC32 %c0 \n" + "102: \n" + " DC32 %c1 \n" + "103: \n" + " DC32 %c2 \n" + : /* Outputs */ + : /* Inputs */ + "i"(__section_end("CSTACK")), + "i"(__section_begin("CSTACK")), + "i"(&HardFault_c_handler) + ); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_keil.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_keil.c new file mode 100644 index 0000000..2b88df9 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_keil.c @@ -0,0 +1,61 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#include + +//lint -save -e27 -e10 -e19 -e40 +extern char STACK$$Base; + +/* This variable should be static but then it cannot be used in assembly code below. + * The problem here is that the address of the section can be archived by $$ operator + * that is not allowed in assembly code. */ +char const * HardFault_Handler_stack_bottom = &STACK$$Base; +//lint -restore + +__asm void HardFault_Handler(void) +{ + PRESERVE8 + EXTERN HardFault_c_handler + EXTERN __initial_sp + EXTERN HardFault_Handler_stack_bottom + + ldr r0, =0xFFFFFFFD + cmp r0, lr + bne HardFault_Handler_ChooseMSP + /* Reading PSP into R0 */ + mrs r0, PSP + b HardFault_Handler_Continue +HardFault_Handler_ChooseMSP + /* Reading MSP into R0 */ + mrs r0, MSP + /* ----------------------------------------------------------------- + * If we have selected MSP, check if we may use stack safely. + * If not - reset the stack to the initial value. */ + ldr r1, =__initial_sp + ldr r2, =HardFault_Handler_stack_bottom + ldr r2, [r2] + + /* MSP is in the range of <__StackTop, __StackLimit) */ + cmp r0, r1 + bhi HardFault_MoveSP + cmp r0, r2 + bhi HardFault_Handler_Continue + /* ----------------------------------------------------------------- */ +HardFault_MoveSP + mov SP, r1 + movs r0, #0 + +HardFault_Handler_Continue + ldr r3, =HardFault_c_handler + bx r3 + + ALIGN +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_gcc.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_gcc.c new file mode 100644 index 0000000..8d2bb99 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_gcc.c @@ -0,0 +1,49 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#include + +void HardFault_Handler(void) __attribute__(( naked )); + +void HardFault_Handler(void) +{ + __asm volatile( + " ldr r3, =HardFault_c_handler \n" + " tst lr, #4 \n" + + /* PSP is quite simple and does not require additional handler */ + " itt ne \n" + " mrsne r0, psp \n" + /* Jump to the handler, do not store LR - returning from handler just exits exception */ + " bxne r3 \n" + + /* Processing MSP requires stack checking */ + " mrs r0, msp \n" + + " ldr r1, =__StackTop \n" + " ldr r2, =__StackLimit \n" + + /* MSP is in the range of <__StackTop, __StackLimit) */ + " cmp r0, r1 \n" + " bhi HardFault_MoveSP \n" + " cmp r0, r2 \n" + " bhi HardFault_Handler_Continue \n" + + "HardFault_MoveSP: \n" + " mov sp, r1 \n" + " mov r0, #0 \n" + + "HardFault_Handler_Continue: \n" + " bx r3 \n" + + " .align \n" + ); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_iar.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_iar.c new file mode 100644 index 0000000..d390c4a --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_iar.c @@ -0,0 +1,64 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#include + +#pragma section = "CSTACK" +extern void HardFault_c_handler( uint32_t * ); + +__stackless void HardFault_Handler(void); + +__stackless void HardFault_Handler(void) +{ + __asm volatile( + " ldr.n r3, 103f \n" + " tst lr, #4 \n" + + /* PSP is quite simple and does not require additional handler */ + " itt ne \n" + " mrsne r0, psp \n" + /* Jump to the handler, do not store LR - returning from handler just exits exception */ + " bxne r3 \n" + + /* Processing MSP requires stack checking */ + " mrs r0, msp \n" + + " ldr.n r1, 101f \n" + " ldr.n r2, 102f \n" + + /* MSP is in the range of <__StackTop, __StackLimit) */ + " cmp r0, r1 \n" + " bhi.n 1f \n" + " cmp r0, r2 \n" + " bhi.n 2f \n" + + "1: \n" + " mov sp, r1 \n" + " mov r0, #0 \n" + + "2: \n" + " bx r3 \n" + /* Data alignment if required */ + " nop \n" + + "101: \n" + " DC32 %c0 \n" + "102: \n" + " DC32 %c1 \n" + "103: \n" + " DC32 %c2 \n" + : /* Outputs */ + : /* Inputs */ + "i"(__section_end("CSTACK")), + "i"(__section_begin("CSTACK")), + "i"(&HardFault_c_handler) + ); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_keil.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_keil.c new file mode 100644 index 0000000..ad9642c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_keil.c @@ -0,0 +1,60 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#include + +//lint -save -e27 -e10 -e19 -e40 +extern char STACK$$Base; + +/* This variable should be static but then it cannot be used in assembly code below. + * The problem here is that the address of the section can be archived by $$ operator + * that is not allowed in assembly code. */ +char const * HardFault_Handler_stack_bottom = &STACK$$Base; +//lint -restore + +__asm void HardFault_Handler(void) +{ + PRESERVE8 + EXTERN HardFault_c_handler + EXTERN __initial_sp + EXTERN HardFault_Handler_stack_bottom + + ldr r3, =HardFault_c_handler + tst lr, #4 + + /* PSP is quite simple and does not require additional handler */ + itt ne + mrsne r0, psp + /* Jump to the handler, do not store LR - returning from handler just exits exception */ + bxne r3 + + /* Processing MSP requires stack checking */ + mrs r0, msp + + ldr r1, =__initial_sp + ldr r2, =HardFault_Handler_stack_bottom + ldr r2, [r2] + + /* MSP is in the range of <__StackTop, __StackLimit) */ + cmp r0, r1 + bhi HardFault_MoveSP + cmp r0, r2 + bhi HardFault_Handler_Continue + +HardFault_MoveSP + mov sp, r1 + mov r0, #0 + +HardFault_Handler_Continue + bx r3 + + ALIGN +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.c new file mode 100644 index 0000000..e898e95 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.c @@ -0,0 +1,253 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "hci_mem_pool.h" +//#include "hci_mem_pool_internal.h" +#include "nordic_common.h" +#include +#include + + +// Adafruit for dual transport serial + ble +#define BLE_TX_BUF_SIZE 4u /**< TX buffer size in bytes. */ +#define BLE_RX_BUF_SIZE 32u /**< RX buffer size in bytes. */ +#define BLE_RX_BUF_QUEUE_SIZE 8u /**< RX buffer element size. */ + +#define SERIAL_TX_BUF_SIZE 32u /**< TX buffer size in bytes. */ +#define SERIAL_RX_BUF_SIZE 600u /**< RX buffer size in bytes. */ +#define SERIAL_RX_BUF_QUEUE_SIZE 2u /**< RX buffer element size. */ + +extern bool is_ota(void); + +#define RX_BUF_SIZE (is_ota() ? BLE_RX_BUF_SIZE : SERIAL_RX_BUF_SIZE) +#define TX_BUF_SIZE (is_ota() ? BLE_TX_BUF_SIZE : SERIAL_TX_BUF_SIZE) +#define RX_BUF_QUEUE_SIZE (is_ota() ? BLE_RX_BUF_QUEUE_SIZE : SERIAL_RX_BUF_QUEUE_SIZE) + +/**@brief RX buffer element instance structure. + */ +typedef struct +{ +// uint8_t rx_buffer[RX_BUF_SIZE]; /**< RX buffer memory array. */ + uint8_t rx_buffer[MAX(BLE_RX_BUF_SIZE, SERIAL_RX_BUF_SIZE)]; + uint32_t length; /**< Length of the RX buffer memory array. */ +} rx_buffer_elem_t; + +/**@brief RX buffer queue element instance structure. + */ +typedef struct +{ + rx_buffer_elem_t * p_buffer; /**< Pointer to RX buffer element. */ + uint32_t free_window_count; /**< Free space element count. */ + uint32_t free_available_count; /**< Free area element count. */ + uint32_t read_available_count; /**< Read area element count. */ + uint32_t write_index; /**< Write position index. */ + uint32_t read_index; /**< Read position index. */ + uint32_t free_index; /**< Free position index. */ +} rx_buffer_queue_t; + +static bool m_is_tx_allocated; /**< Boolean value to determine if the TX buffer is allocated. */ +static rx_buffer_elem_t m_rx_buffer_elem_queue[MAX(BLE_RX_BUF_QUEUE_SIZE, SERIAL_RX_BUF_QUEUE_SIZE)]; /**< RX buffer element instances. */ +static rx_buffer_queue_t m_rx_buffer_queue; /**< RX buffer queue element instance. */ + + +uint32_t hci_mem_pool_open(void) +{ + m_is_tx_allocated = false; + m_rx_buffer_queue.p_buffer = m_rx_buffer_elem_queue; + m_rx_buffer_queue.free_window_count = RX_BUF_QUEUE_SIZE; + m_rx_buffer_queue.free_available_count = 0; + m_rx_buffer_queue.read_available_count = 0; + m_rx_buffer_queue.write_index = 0; + m_rx_buffer_queue.read_index = 0; + m_rx_buffer_queue.free_index = 0; + + return NRF_SUCCESS; +} + + +uint32_t hci_mem_pool_close(void) +{ + return NRF_SUCCESS; +} + + +uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer) +{ + static uint8_t tx_buffer[MAX(BLE_TX_BUF_SIZE, SERIAL_TX_BUF_SIZE)]; + + uint32_t err_code; + + if (pp_buffer == NULL) + { + return NRF_ERROR_NULL; + } + + if (!m_is_tx_allocated) + { + m_is_tx_allocated = true; + *pp_buffer = tx_buffer; + err_code = NRF_SUCCESS; + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + + return err_code; +} + + +uint32_t hci_mem_pool_tx_free(void) +{ + m_is_tx_allocated = false; + + return NRF_SUCCESS; +} + + +uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer) +{ + uint32_t err_code; + + if (pp_buffer == NULL) + { + return NRF_ERROR_NULL; + } + *pp_buffer = NULL; + + if (m_rx_buffer_queue.free_window_count != 0) + { + if (length <= RX_BUF_SIZE) + { + --(m_rx_buffer_queue.free_window_count); + ++(m_rx_buffer_queue.read_available_count); + + *pp_buffer = + m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.write_index].rx_buffer; + + m_rx_buffer_queue.free_index |= (1u << m_rx_buffer_queue.write_index); + + // @note: Adjust the write_index making use of the fact that the buffer size is of + // power of two and two's complement arithmetic. For details refer example to book + // "Making embedded systems: Elicia White". + m_rx_buffer_queue.write_index = + (m_rx_buffer_queue.write_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u); + + err_code = NRF_SUCCESS; + } + else + { + err_code = NRF_ERROR_DATA_SIZE; + } + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + + return err_code; +} + + +uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer) +{ + uint32_t err_code; + uint32_t consume_index; + uint32_t start_index; + + if (m_rx_buffer_queue.free_available_count != 0) + { + // Find the buffer that has been freed - + // Start at read_index minus free_available_count and then increment until read index. + err_code = NRF_ERROR_INVALID_ADDR; + consume_index = (m_rx_buffer_queue.read_index - m_rx_buffer_queue.free_available_count) & + (RX_BUF_QUEUE_SIZE - 1u); + start_index = consume_index; + + do + { + if (m_rx_buffer_queue.p_buffer[consume_index].rx_buffer == p_buffer) + { + m_rx_buffer_queue.free_index ^= (1u << consume_index); + err_code = NRF_SUCCESS; + break; + } + else + { + consume_index = (consume_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u); + } + } + while (consume_index != m_rx_buffer_queue.read_index); + + while (!(m_rx_buffer_queue.free_index & (1 << start_index)) && + (m_rx_buffer_queue.free_available_count != 0)) + { + --(m_rx_buffer_queue.free_available_count); + ++(m_rx_buffer_queue.free_window_count); + start_index = (consume_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u); + } + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + + return err_code; +} + + +uint32_t hci_mem_pool_rx_data_size_set(uint32_t length) +{ + // @note: Adjust the write_index making use of the fact that the buffer size is of power + // of two and two's complement arithmetic. For details refer example to book + // "Making embedded systems: Elicia White". + const uint32_t index = (m_rx_buffer_queue.write_index - 1u) & (RX_BUF_QUEUE_SIZE - 1u); + m_rx_buffer_queue.p_buffer[index].length = length; + + return NRF_SUCCESS; +} + + +uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length) +{ + uint32_t err_code; + + if ((pp_buffer == NULL) || (p_length == NULL)) + { + return NRF_ERROR_NULL; + } + + if (m_rx_buffer_queue.read_available_count != 0) + { + --(m_rx_buffer_queue.read_available_count); + ++(m_rx_buffer_queue.free_available_count); + + *pp_buffer = + m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].rx_buffer; + *p_length = + m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].length; + + // @note: Adjust the write_index making use of the fact that the buffer size is of power + // of two and two's complement arithmetic. For details refer example to book + // "Making embedded systems: Elicia White". + m_rx_buffer_queue.read_index = + (m_rx_buffer_queue.read_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u); + + err_code = NRF_SUCCESS; + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + + return err_code; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.h new file mode 100644 index 0000000..502265e --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.h @@ -0,0 +1,132 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup memory_pool Memory pool + * @{ + * @ingroup app_common + * + * @brief Memory pool implementation + * + * Memory pool implementation, based on circular buffer data structure, which supports asynchronous + * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers. + * The memory managed by the pool is allocated from static storage instead of heap. The internal + * design of the circular buffer implementing the RX memory layout is illustrated in the picture + * below. + * + * @image html memory_pool.png "Circular buffer design" + * + * The expected call order for the RX APIs is as follows: + * - hci_mem_pool_rx_produce + * - hci_mem_pool_rx_data_size_set + * - hci_mem_pool_rx_extract + * - hci_mem_pool_rx_consume + * + * @warning If the above mentioned expected call order is violated the end result can be undefined. + * + * \par Component specific configuration options + * + * The following compile time configuration options are available to suit various implementations: + * - TX_BUF_SIZE TX buffer size in bytes. + * - RX_BUF_SIZE RX buffer size in bytes. + * - RX_BUF_QUEUE_SIZE RX buffer element size. + */ + +#ifndef HCI_MEM_POOL_H__ +#define HCI_MEM_POOL_H__ + +#include +#include "nrf_error.h" + +/**@brief Function for opening the module. + * + * @retval NRF_SUCCESS Operation success. + */ +uint32_t hci_mem_pool_open(void); + +/**@brief Function for closing the module. + * + * @retval NRF_SUCCESS Operation success. + */ +uint32_t hci_mem_pool_close(void); + +/**@brief Function for allocating requested amount of TX memory. + * + * @param[out] pp_buffer Pointer to the allocated memory. + * + * @retval NRF_SUCCESS Operation success. Memory was allocated. + * @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation. + * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. + */ +uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer); + +/**@brief Function for freeing previously allocated TX memory. + * + * @note Memory management follows the FIFO principle meaning that free() order must match the + * alloc(...) order, which is the reason for omitting exact memory block identifier as an + * input parameter. + * + * @retval NRF_SUCCESS Operation success. Memory was freed. + */ +uint32_t hci_mem_pool_tx_free(void); + +/**@brief Function for producing a free RX memory block for usage. + * + * @note Upon produce request amount being 0, NRF_SUCCESS is returned. + * + * @param[in] length Amount, in bytes, of free memory to be produced. + * @param[out] pp_buffer Pointer to the allocated memory. + * + * @retval NRF_SUCCESS Operation success. Free RX memory block produced. + * @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation. + * @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit. + * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. + */ +uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer); + +/**@brief Function for setting the length of the last produced RX memory block. + * + * @warning If call to this API is omitted the end result is that the following call to + * mem_pool_rx_extract will return incorrect data in the p_length output parameter. + * + * @param[in] length Amount, in bytes, of actual memory used. + * + * @retval NRF_SUCCESS Operation success. Length was set. + */ +uint32_t hci_mem_pool_rx_data_size_set(uint32_t length); + +/**@brief Function for extracting a packet, which has been filled with read data, for further + * processing. + * + * @param[out] pp_buffer Pointer to the packet data. + * @param[out] p_length Length of packet data in bytes. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. + * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. + */ +uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length); + +/**@brief Function for freeing previously extracted packet, which has been filled with read data. + * + * @param[in] p_buffer Pointer to consumed buffer. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free. + * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. + */ +uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer); + +#endif // HCI_MEM_POOL_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.c new file mode 100644 index 0000000..4c40808 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.c @@ -0,0 +1,428 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "hci_slip.h" +#include +#include "hci_transport_config.h" +#include "app_uart.h" +#include "nrf_error.h" + +#define APP_SLIP_END 0xC0 /**< SLIP code for identifying the beginning and end of a packet frame.. */ +#define APP_SLIP_ESC 0xDB /**< SLIP escape code. This code is used to specify that the following character is specially encoded. */ +#define APP_SLIP_ESC_END 0xDC /**< SLIP special code. When this code follows 0xDB, this character is interpreted as payload data 0xC0.. */ +#define APP_SLIP_ESC_ESC 0xDD /**< SLIP special code. When this code follows 0xDB, this character is interpreted as payload data 0xDB. */ + +/** @brief States for the SLIP state machine. */ +typedef enum +{ + SLIP_OFF, /**< SLIP state OFF. */ + SLIP_READY, /**< SLIP state ON. */ + SLIP_TRANSMITTING, /**< SLIP state is transmitting indicating write() has been called but data transmission has not completed. */ +} slip_states_t; + +static slip_states_t m_current_state = SLIP_OFF; /** Current state for the SLIP TX state machine. */ + +static hci_slip_event_handler_t m_slip_event_handler; /** Event callback function for handling of SLIP events, @ref hci_slip_evt_type_t . */ + +static const uint8_t * mp_tx_buffer; /** Pointer to the current TX buffer that is in transmission. */ +static uint32_t m_tx_buffer_length; /** Length of the current TX buffer that is in transmission. */ +static volatile uint32_t m_tx_buffer_index; /** Current index for next byte to transmit in the mp_tx_buffer. */ + +static uint8_t * mp_rx_buffer; /** Pointer to the current RX buffer where the next SLIP decoded packet will be stored. */ +static uint32_t m_rx_buffer_length; /** Length of the current RX buffer. */ +static uint32_t m_rx_received_count; /** Number of SLIP decoded bytes received and stored in mp_rx_buffer. */ + + +/**@brief Function for parsing bytes received on the UART until a SLIP escape byte is received. + * + * @param[in] byte Byte received in UART module. + */ +static void handle_rx_byte_default(uint8_t byte); + +/**@brief Function for parsing bytes received on the UART until SLIP end byte is received. + * + * @param[in] byte Byte received in UART module. + */ +static void handle_rx_byte_wait_start(uint8_t byte); + +/**@brief Function for decoding a received SLIP escape byte. + * It will ensure correct decoding of the byte following the SLIP escape byte. + * + * @param[in] byte Byte received in UART module. + */ +static void handle_rx_byte_esc(uint8_t byte); + +/**@brief Function pointer for parsing and decoding SLIP bytes from the UART module. + * + * @param[in] byte Byte received in UART module. + */ +static void (*handle_rx_byte) (uint8_t byte) = handle_rx_byte_wait_start; + +/**@brief Function pointer for sending a byte through the UART module. + */ +static uint32_t send_tx_byte_default(void); + +/**@brief Function for transferring a SLIP escape byte (0xDB) when special bytes are transferred, + * that is 0xC0 and 0xDB. + */ +static uint32_t send_tx_byte_esc(void); + +/**@brief Function for transferring a byte when it collides with SLIP commands and follows the SLIP + * escape byte, that is 0xC0 => 0xDC and 0xDB => 0xDD. + */ +static uint32_t send_tx_byte_encoded(void); + +/**@brief Function for transferring the SLIP end frame byte, 0xC0. + */ +static uint32_t send_tx_byte_end(void); + +/**@brief Function pointer for sending a byte through the UART module. + */ +uint32_t (*send_tx_byte) (void) = send_tx_byte_default; + + +static uint32_t send_tx_byte_end(void) +{ + uint32_t err_code = app_uart_put(APP_SLIP_END); + + if ((err_code == NRF_SUCCESS) && (m_tx_buffer_index == 0)) + { + // Packet transmission started. + send_tx_byte = send_tx_byte_default; + } + + return err_code; +} + + +static uint32_t send_tx_byte_default(void) +{ + uint32_t err_code = app_uart_put(mp_tx_buffer[m_tx_buffer_index]); + + if (err_code == NRF_SUCCESS) + { + m_tx_buffer_index++; + } + + return err_code; +} + + +static uint32_t send_tx_byte_encoded(void) +{ + uint32_t err_code; + + switch(mp_tx_buffer[m_tx_buffer_index]) + { + case APP_SLIP_END: + err_code = app_uart_put(APP_SLIP_ESC_END); + break; + + case APP_SLIP_ESC: + err_code = app_uart_put(APP_SLIP_ESC_ESC); + break; + + default: + err_code = NRF_ERROR_NO_MEM; + break; + } + + if (err_code == NRF_SUCCESS) + { + m_tx_buffer_index++; + send_tx_byte = send_tx_byte_default; + } + + return err_code; +} + + +static uint32_t send_tx_byte_esc(void) +{ + uint32_t err_code = app_uart_put(APP_SLIP_ESC); + + if (err_code == NRF_SUCCESS) + { + send_tx_byte = send_tx_byte_encoded; + } + + return err_code; +} + + +/** @brief Function for transferring the content of the mp_tx_buffer to the UART. + * It continues to transfer bytes until the UART buffer is full or the complete buffer is + * transferred. + */ +static void transmit_buffer(void) +{ + uint32_t err_code = NRF_SUCCESS; + + while (m_tx_buffer_index < m_tx_buffer_length) + { + if ((mp_tx_buffer[m_tx_buffer_index] == APP_SLIP_END || + mp_tx_buffer[m_tx_buffer_index] == APP_SLIP_ESC) && + send_tx_byte == send_tx_byte_default) + { + send_tx_byte = send_tx_byte_esc; + } + + err_code = send_tx_byte(); + + if (err_code == NRF_ERROR_NO_MEM || err_code == NRF_ERROR_BUSY) + { + // No memory left in UART TX buffer. Abort and wait for APP_UART_TX_EMPTY to continue. + return; + } + } + + send_tx_byte = send_tx_byte_end; + + err_code = send_tx_byte(); + + if (err_code == NRF_SUCCESS) + { + // Packet transmission ended. Notify higher level. + m_current_state = SLIP_READY; + + if (m_slip_event_handler != NULL) + { + hci_slip_evt_t event = {HCI_SLIP_TX_DONE, mp_tx_buffer, m_tx_buffer_index}; + + m_slip_event_handler(event); + } + } +} + + +/** @brief Function for handling the reception of a SLIP end byte. + * If the number of bytes received is greater than zero it will call m_slip_event_handler + * with number of bytes received and invalidate the mp_rx_buffer to protect against data + * corruption. + * No new bytes can be received until a new RX buffer is supplied. + */ +static void handle_slip_end(void) +{ + if (m_rx_received_count > 0) + { + // Full packet received, push it up. + if (m_slip_event_handler != NULL) + { + hci_slip_evt_t event = {HCI_SLIP_RX_RDY, mp_rx_buffer, m_rx_received_count}; + + m_rx_received_count = 0; + mp_rx_buffer = NULL; + + m_slip_event_handler(event); + } + } +} + + +static void handle_rx_byte_esc(uint8_t byte) +{ + switch (byte) + { + case APP_SLIP_END: + handle_slip_end(); + break; + + case APP_SLIP_ESC_END: + mp_rx_buffer[m_rx_received_count++] = APP_SLIP_END; + break; + + case APP_SLIP_ESC_ESC: + mp_rx_buffer[m_rx_received_count++] = APP_SLIP_ESC; + break; + + default: + mp_rx_buffer[m_rx_received_count++] = byte; + break; + } + + handle_rx_byte = handle_rx_byte_default; +} + + +static void handle_rx_byte_default(uint8_t byte) +{ + switch (byte) + { + case APP_SLIP_END: + handle_slip_end(); + break; + + case APP_SLIP_ESC: + handle_rx_byte = handle_rx_byte_esc; + break; + + default: + mp_rx_buffer[m_rx_received_count++] = byte; + break; + } +} + + +static void handle_rx_byte_wait_start(uint8_t byte) +{ + if (byte == APP_SLIP_END) + { + handle_rx_byte = handle_rx_byte_default; + } +} + + +/** @brief Function for checking the current index and length of the RX buffer to determine if the + * buffer is full. If an event handler has been registered, the callback function will + * be executed.. + * + * @retval true If RX buffer has overflowed. + * @retval false otherwise. + * + */ +static bool rx_buffer_overflowed(void) +{ + if (mp_rx_buffer == NULL || m_rx_received_count >= m_rx_buffer_length) + { + if (m_slip_event_handler != NULL) + { + hci_slip_evt_t event = {HCI_SLIP_RX_OVERFLOW, mp_rx_buffer, m_rx_received_count}; + m_slip_event_handler(event); + } + + return true; + } + + return false; +} + + +/** @brief Function for handling the UART module event. It parses events from the UART when + * bytes are received/transmitted. + * + * @param[in] uart_event Event received from app_uart module. + */ +static void slip_uart_eventhandler(app_uart_evt_t * uart_event) +{ + if (uart_event->evt_type == APP_UART_TX_EMPTY && m_current_state == SLIP_TRANSMITTING) + { + transmit_buffer(); + } + + if ((uart_event->evt_type == APP_UART_DATA) && (!rx_buffer_overflowed())) + { + handle_rx_byte(uart_event->data.value); + } +} + + +/** @brief Function for enabling the UART module when the SLIP layer is opened. + */ +static uint32_t slip_uart_open(void) +{ + uint32_t err_code; + + app_uart_comm_params_t comm_params = + { + HCI_SLIP_UART_RX_PIN_NUMBER, + HCI_SLIP_UART_TX_PIN_NUMBER, + HCI_SLIP_UART_RTS_PIN_NUMBER, + HCI_SLIP_UART_CTS_PIN_NUMBER, + HCI_SLIP_UART_MODE, + false, + HCI_SLIP_UART_BAUDRATE + }; + + err_code = app_uart_init(&comm_params, + NULL, + slip_uart_eventhandler, + APP_IRQ_PRIORITY_LOW); + + if (err_code == NRF_SUCCESS) + { + m_current_state = SLIP_READY; + } + + return err_code; +} + + +uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler) +{ + m_slip_event_handler = event_handler; + + return NRF_SUCCESS; +} + + +uint32_t hci_slip_open() +{ + switch (m_current_state) + { + case SLIP_OFF: + return slip_uart_open(); + + default: + // Do nothing. + break; + } + + return NRF_SUCCESS; +} + + +uint32_t hci_slip_close() +{ + m_current_state = SLIP_OFF; + uint32_t err_code = app_uart_close(); + + return err_code; +} + + +uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length) +{ + if (p_buffer == NULL) + { + return NRF_ERROR_INVALID_ADDR; + } + + switch (m_current_state) + { + case SLIP_READY: + m_tx_buffer_index = 0; + m_tx_buffer_length = length; + mp_tx_buffer = p_buffer; + m_current_state = SLIP_TRANSMITTING; + send_tx_byte = send_tx_byte_end; + + transmit_buffer(); + return NRF_SUCCESS; + + case SLIP_TRANSMITTING: + return NRF_ERROR_NO_MEM; + + case SLIP_OFF: + default: + return NRF_ERROR_INVALID_STATE; + } +} + + +uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length) +{ + mp_rx_buffer = p_buffer; + m_rx_buffer_length = length; + m_rx_received_count = 0; + handle_rx_byte = handle_rx_byte_wait_start; + return NRF_SUCCESS; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.h new file mode 100644 index 0000000..cc3b415 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_slip.h @@ -0,0 +1,129 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup hci_slip SLIP module + * @{ + * @ingroup app_common + * + * @brief SLIP layer for supporting packet framing in HCI transport. + * + * @details This module implements SLIP packet framing as described in the Bluetooth Core + * Specification 4.0, Volume 4, Part D, Chapter 3 SLIP Layer. + * + * SLIP framing ensures that all packets sent on the UART are framed as: + * <0xC0> SLIP packet 1 <0xC0> <0xC0> SLIP packet 2 <0xC0>. + * + * The SLIP layer uses events to notify the upper layer when data transmission is complete + * and when a SLIP packet is received. + */ + +#ifndef HCI_SLIP_H__ +#define HCI_SLIP_H__ + +#include + +/**@brief Event types from the SLIP Layer. */ +typedef enum +{ + HCI_SLIP_RX_RDY, /**< An event indicating that an RX packet is ready to be read. */ + HCI_SLIP_TX_DONE, /**< An event indicating write completion of the TX packet provided in the function call \ref hci_slip_write . */ + HCI_SLIP_RX_OVERFLOW, /**< An event indicating that RX data has been discarded due to lack of free RX memory. */ + HCI_SLIP_ERROR, /**< An event indicating that an unrecoverable error has occurred. */ + HCI_SLIP_EVT_TYPE_MAX /**< Enumeration upper bound. */ +} hci_slip_evt_type_t; + +/**@brief Structure containing an event from the SLIP layer. + */ +typedef struct +{ + hci_slip_evt_type_t evt_type; /**< Type of event. */ + const uint8_t * packet; /**< This field contains a pointer to the packet for which the event relates, i.e. SLIP_TX_DONE: the packet transmitted, SLIP_RX_RDY: the packet received, SLIP_RX_OVERFLOW: The packet which overflow/or NULL if no receive buffer is available. */ + uint32_t packet_length; /**< Packet length, i.e. SLIP_TX_DONE: Bytes transmitted, SLIP_RX_RDY: Bytes received, SLIP_RX_OVERFLOW: index at which the packet overflowed. */ +} hci_slip_evt_t; + +/**@brief Function for the SLIP layer event callback. + */ +typedef void (*hci_slip_event_handler_t)(hci_slip_evt_t event); + +/**@brief Function for registering the event handler provided as parameter and this event handler + * will be used by SLIP layer to send events described in \ref hci_slip_evt_type_t. + * + * @note Multiple registration requests will overwrite any existing registration. + * + * @param[in] event_handler This function is called by the SLIP layer upon an event. + * + * @retval NRF_SUCCESS Operation success. + */ +uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler); + +/**@brief Function for opening the SLIP layer. This function must be called before + * \ref hci_slip_write and before any data can be received. + * + * @note Can be called multiple times. + * + * @retval NRF_SUCCESS Operation success. + * + * The SLIP layer module will propagate errors from underlying sub-modules. + * This implementation is using UART module as a physical transmission layer, and hci_slip_open + * executes \ref app_uart_init . For an extended error list, please refer to \ref app_uart_init . + */ +uint32_t hci_slip_open(void); + +/**@brief Function for closing the SLIP layer. After this function is called no data can be + * transmitted or received in this layer. + * + * @note This function can be called multiple times and also for an unopened channel. + * + * @retval NRF_SUCCESS Operation success. + */ +uint32_t hci_slip_close(void); + +/**@brief Function for writing a packet with SLIP encoding. Packet transmission is confirmed when + * the HCI_SLIP_TX_DONE event is received by the function caller. + * + * @param[in] p_buffer Pointer to the packet to transmit. + * @param[in] length Packet length, in bytes. + * + * @retval NRF_SUCCESS Operation success. Packet was encoded and added to the + * transmission queue and an event will be sent upon transmission + * completion. + * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not + * added to the transmission queue. Application shall wait for + * the \ref HCI_SLIP_TX_DONE event. After HCI_SLIP_TX_DONE this + * function can be executed for transmission of next packet. + * @retval NRF_ERROR_INVALID_ADDR If a NULL pointer is provided. + * @retval NRF_ERROR_INVALID_STATE Operation failure. Module is not open. + */ +uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length); + +/**@brief Function for registering a receive buffer. The receive buffer will be used for storage of + * received and SLIP decoded data. + * No data can be received by the SLIP layer until a receive buffer has been registered. + * + * @note The lifetime of the buffer must be valid during complete reception of data. A static + * buffer is recommended. + * + * @warning Multiple registration requests will overwrite any existing registration. + * + * @param[in] p_buffer Pointer to receive buffer. The received and SLIP decoded packet + * will be placed in this buffer. + * @param[in] length Buffer length, in bytes. + * + * @retval NRF_SUCCESS Operation success. + */ +uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length); + +#endif // HCI_SLIP_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.c new file mode 100644 index 0000000..fe45f24 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.c @@ -0,0 +1,779 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "hci_transport_config.h" +#include "hci_transport.h" +#include "hci_slip.h" +#include "crc16.h" +#include "hci_mem_pool.h" +#include "hci_mem_pool_internal.h" +#include "app_timer.h" +#include "app_error.h" +#include +#include "sdk_common.h" + +#define PKT_HDR_SIZE 4u /**< Packet header size in number of bytes. */ +#define PKT_CRC_SIZE 2u /**< Packet CRC size in number of bytes. */ +#define PKT_TYPE_VENDOR_SPECIFIC 14u /**< Packet type vendor specific. */ +#define PKT_TYPE_ACK 0 /**< Packet type acknowledgement. */ +#define DATA_INTEGRITY_MASK (1u << 6u) /**< Mask for data integrity bit in the packet header. */ +#define RELIABLE_PKT_MASK (1u << 7u) /**< Mask for reliable packet bit in the packet header. */ +#define INITIAL_ACK_NUMBER_EXPECTED 1u /**< Initial acknowledge number expected. */ +#define INITIAL_ACK_NUMBER_TX INITIAL_ACK_NUMBER_EXPECTED /**< Initial acknowledge number transmitted. */ +#define INVALID_PKT_TYPE 0xFFFFFFFFu /**< Internal invalid packet type value. */ +#define MAX_TRANSMISSION_TIME (ROUNDED_DIV((MAX_PACKET_SIZE_IN_BITS * 1000u), USED_BAUD_RATE)) /**< Max transmission time of a single application packet over UART in units of mseconds. */ +#define RETRANSMISSION_TIMEOUT_IN_MS (3u * MAX_TRANSMISSION_TIME) /**< Retransmission timeout for application packet in units of mseconds. */ +#define APP_TIMER_PRESCALER 0 /**< Value of the RTC1 PRESCALER register. */ +#define RETRANSMISSION_TIMEOUT_IN_TICKS APP_TIMER_TICKS(RETRANSMISSION_TIMEOUT_IN_MS, APP_TIMER_PRESCALER) /**< Retransmission timeout for application packet in units of timer ticks. */ +#define MAX_RETRY_COUNT 5u /**< Max retransmission retry count for application packets. */ +#define ACK_BUF_SIZE 5u /**< Length of module internal RX buffer which is big enough to hold an acknowledgement packet. */ + +/**@brief States of the TX state machine. */ +typedef enum +{ + TX_STATE_IDLE, /**< State for: no application transmission packet processing in progress. */ + TX_STATE_PENDING, /**< State for: TX in progress in slip layer and TX-done event is waited for to signal the end of transmission. */ + TX_STATE_ACTIVE /**< State for: application packet has been delivered to slip for transmission and peer transport entity acknowledgement packet is waited for. */ +} tx_state_t; + +/**@brief TX state machine events. */ +typedef enum +{ + TX_EVENT_STATE_ENTRY, /**< Event for: state entry use case. */ + TX_EVENT_SLIP_TX_DONE, /**< Event for: HCI_SLIP_TX_DONE event use case. */ + TX_EVENT_TIMEOUT, /**< Event for: retransmission timeout use case. */ + TX_EVENT_VALID_RX_ACK /**< Event for: valid acknowledgement received for TX packet use case. */ +} tx_event_t; + +static void tx_sm_state_change(tx_state_t new_state); + +static tx_state_t m_tx_state; /**< Current TX state. */ +static hci_transport_tx_done_handler_t m_transport_tx_done_handle; /**< TX done event callback function. */ +static hci_transport_event_handler_t m_transport_event_handle; /**< Event handler callback function. */ +static uint8_t * mp_slip_used_rx_buffer; /**< Reference to RX buffer used by the slip layer. */ +static uint32_t m_packet_expected_seq_number; /**< Sequence number counter of the packet expected to be received . */ +static uint32_t m_packet_transmit_seq_number; /**< Sequence number counter of the transmitted packet for which acknowledgement packet is waited for. */ +static uint8_t * mp_tx_buffer; /**< Pointer to TX application buffer to be transmitted. */ +static uint32_t m_tx_buffer_length; /**< Length of application TX packet data to be transmitted in bytes. */ +static bool m_is_slip_decode_ready; /**< Boolean to determine has slip decode been completed or not. */ +APP_TIMER_DEF(m_app_timer_id); /**< Application timer id. */ +static uint32_t m_tx_retry_counter; /**< Application packet retransmission counter. */ +static hci_transport_tx_done_result_t m_tx_done_result_code; /**< TX done event callback function result code. */ +static uint8_t m_rx_ack_buffer[ACK_BUF_SIZE];/**< RX buffer big enough to hold an acknowledgement packet and which is taken in use upon receiving HCI_SLIP_RX_OVERFLOW event. */ + + +/**@brief Function for validating a received packet. + * + * @param[in] p_buffer Pointer to the packet data. + * @param[in] length Length of packet data in bytes. + * + * @return true if received packet is valid, false in other case. + */ +static bool is_rx_pkt_valid(const uint8_t * p_buffer, uint32_t length) +{ + // Executed packet filtering algorithm order: + // - verify packet overall length + // - verify data integrity bit set + // - verify reliable packet bit set + // - verify supported packet type + // - verify header checksum + // - verify payload length field + // - verify CRC + if (length <= PKT_HDR_SIZE) + { + return false; + } + + if (!(p_buffer[0] & DATA_INTEGRITY_MASK)) + { + return false; + } + + if (!(p_buffer[0] & RELIABLE_PKT_MASK)) + { + return false; + } + + if ((p_buffer[1] & 0x0Fu) != PKT_TYPE_VENDOR_SPECIFIC) + { + return false; + } + + const uint32_t expected_checksum = + ((p_buffer[0] + p_buffer[1] + p_buffer[2] + p_buffer[3])) & 0xFFu; + if (expected_checksum != 0) + { + return false; + } + + const uint16_t crc_calculated = crc16_compute(p_buffer, (length - PKT_CRC_SIZE), NULL); + const uint16_t crc_received = uint16_decode(&p_buffer[length - PKT_CRC_SIZE]); + if (crc_calculated != crc_received) + { + return false; + } + + return true; +} + + +/**@brief Function for getting the sequence number of the next reliable packet expected. + * + * @return sequence number of the next reliable packet expected. + */ +static __INLINE uint8_t packet_number_expected_get(void) +{ + return (uint8_t) m_packet_expected_seq_number; +} + + +/**@brief Function for calculating a packet header checksum. + * + * @param[in] p_hdr Pointer to the packet header. + * + * @return Calculated checksum. + */ +static uint8_t header_checksum_calculate(const uint8_t * p_hdr) +{ + // @note: no pointer validation check needed as already checked by calling function. + uint32_t checksum; + + checksum = p_hdr[0]; + checksum += p_hdr[1]; + checksum += p_hdr[2]; + checksum &= 0xFFu; + checksum = (~checksum + 1u); + + return (uint8_t)checksum; +} + + +/**@brief Function for writing an acknowledgment packet for transmission. + */ +static void ack_transmit(void) +{ + static uint8_t ack_packet[PKT_HDR_SIZE]; + + // TX ACK packet format: + // - Unreliable Packet type + // - Payload Length set to 0 + // - Sequence Number set to 0 + // - Header checksum calculated + // - Acknowledge Number set correctly + ack_packet[0] = (packet_number_expected_get() << 3u); + ack_packet[1] = 0; + ack_packet[2] = 0; + ack_packet[3] = header_checksum_calculate(ack_packet); + + // @note: no return value check needed for hci_slip_write(...) call as acknowledgement packets + // are considered to be from system design point of view unreliable packets.Use case where + // underlying slip layer does not accept a packet for transmission is managed either by: + // - acknowledged by possible future application packet as acknowledgement number header field + // is included + // - protocol peer entity will retransmit the packet + UNUSED_VARIABLE(hci_slip_write(ack_packet, sizeof(ack_packet))); +} + + +/**@brief Function for validating a received packet. + * + * @param[in] p_buffer Pointer to the packet data. + * + * @return sequence number field of the packet header with unrelated data masked out. + */ +static __INLINE uint8_t packet_seq_nmbr_extract(const uint8_t * p_buffer) +{ + return (p_buffer[0] & 0x07u); +} + + +/**@brief Function for incrementing the sequence number counter for next reliable packet expected. + */ +static __INLINE void packet_number_expected_inc(void) +{ + ++m_packet_expected_seq_number; + m_packet_expected_seq_number &= 0x07u; +} + + +/**@brief Function for decoding a packet type field. + * + * @param[in] p_buffer Pointer to the packet data. + * @param[in] length Length of packet data in bytes. + * + * @return Packet type field or INVALID_PKT_TYPE in case of decode error. + */ +static __INLINE uint32_t packet_type_decode(const uint8_t * p_buffer, uint32_t length) +{ + // @note: no pointer validation check needed as allready checked by calling function. + uint32_t return_value; + + if (length >= PKT_HDR_SIZE) + { + return_value = (p_buffer[1] & 0x0Fu); + } + else + { + return_value = INVALID_PKT_TYPE; + } + + return return_value; +} + + +/**@brief Function for processing a received vendor specific packet. + * + * @param[in] p_buffer Pointer to the packet data. + * @param[in] length Length of packet data in bytes. + */ +static void rx_vendor_specific_pkt_type_handle(const uint8_t * p_buffer, uint32_t length) +{ + // @note: no pointer validation check needed as allready checked by calling function. + uint32_t err_code; + + if (is_rx_pkt_valid(p_buffer, length)) + { + // RX packet is valid: validate sequence number. + const uint8_t rx_seq_number = packet_seq_nmbr_extract(p_buffer); + if (packet_number_expected_get() == rx_seq_number) + { + // Sequence number is valid: transmit acknowledgement. + packet_number_expected_inc(); + ack_transmit(); + + m_is_slip_decode_ready = true; + + err_code = hci_mem_pool_rx_data_size_set(length); + APP_ERROR_CHECK(err_code); + + err_code = hci_mem_pool_rx_produce(RX_BUF_SIZE, (void **)&mp_slip_used_rx_buffer); + APP_ERROR_CHECK_BOOL((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NO_MEM)); + + // If memory pool RX buffer produce succeeded we register that buffer to slip layer + // otherwise we register the internal acknowledgement buffer. + err_code = hci_slip_rx_buffer_register( + (err_code == NRF_SUCCESS) ? mp_slip_used_rx_buffer : m_rx_ack_buffer, + (err_code == NRF_SUCCESS) ? RX_BUF_SIZE : ACK_BUF_SIZE); + + APP_ERROR_CHECK(err_code); + + if (m_transport_event_handle != NULL) + { + // Send application event of RX packet reception. + const hci_transport_evt_t evt = {HCI_TRANSPORT_RX_RDY}; + m_transport_event_handle(evt); + } + } + else + { + // RX packet discarded: sequence number not valid, set the same buffer to slip layer in + // order to avoid buffer overrun. + err_code = hci_slip_rx_buffer_register(mp_slip_used_rx_buffer, RX_BUF_SIZE); + APP_ERROR_CHECK(err_code); + + // As packet did not have expected sequence number: send acknowledgement with the + // current expected sequence number. + ack_transmit(); + } + } + else + { + // RX packet discarded: reset the same buffer to slip layer in order to avoid buffer + // overrun. + err_code = hci_slip_rx_buffer_register(mp_slip_used_rx_buffer, RX_BUF_SIZE); + APP_ERROR_CHECK(err_code); + } +} + + +/**@brief Function for getting the sequence number of a reliable TX packet for which peer protocol + * entity acknowledgment is pending. + * + * @return sequence number of a reliable TX packet for which peer protocol entity acknowledgement + * is pending. + */ +static __INLINE uint8_t packet_number_to_transmit_get(void) +{ + return m_packet_transmit_seq_number; +} + + +/**@brief Function for getting the expected acknowledgement number. + * + * @return expected acknowledgement number. + */ +static __INLINE uint8_t expected_ack_number_get(void) +{ + uint8_t seq_nmbr = packet_number_to_transmit_get(); + ++seq_nmbr; + seq_nmbr &= 0x07u; + + return seq_nmbr; +} + + +/**@brief Function for processing a received acknowledgement packet. + * + * Verifies does the received acknowledgement packet has the expected acknowledgement number and + * that the header checksum is correct. + * + * @param[in] p_buffer Pointer to the packet data. + * + * @return true if valid acknowledgement packet received. + */ +static __INLINE bool rx_ack_pkt_type_handle(const uint8_t * p_buffer) +{ + // @note: no pointer validation check needed as allready checked by calling function. + + // Verify header checksum. + const uint32_t expected_checksum = + ((p_buffer[0] + p_buffer[1] + p_buffer[2] + p_buffer[3])) & 0xFFu; + if (expected_checksum != 0) + { + return false; + } + + const uint8_t ack_number = (p_buffer[0] >> 3u) & 0x07u; + + // Verify expected acknowledgment number. + return (ack_number == expected_ack_number_get()); +} + + +/**@brief Function for incrementing the sequence number counter of the TX packet. + */ +static __INLINE void packet_number_tx_inc(void) +{ + ++m_packet_transmit_seq_number; + m_packet_transmit_seq_number &= 0x07u; +} + + +/**@brief Function for TX state machine event processing in a state centric manner. + * + * @param[in] event Type of event occurred. + */ +static void tx_sm_event_handle(tx_event_t event) +{ + uint32_t err_code; + + switch (m_tx_state) + { + case TX_STATE_IDLE: + if (event == TX_EVENT_STATE_ENTRY) + { + err_code = app_timer_stop(m_app_timer_id); + APP_ERROR_CHECK(err_code); + + // Send TX-done event if registered handler exists. + if (m_transport_tx_done_handle != NULL) + { + m_transport_tx_done_handle(m_tx_done_result_code); + } + } + break; + + case TX_STATE_PENDING: + if (event == TX_EVENT_SLIP_TX_DONE) + { + // @note: this call should always succeed as called from HCI_SLIP_TX_DONE context + // and error cases are managed by dedicated error event from the slip layer. + err_code = hci_slip_write(mp_tx_buffer, + (m_tx_buffer_length + PKT_HDR_SIZE + PKT_CRC_SIZE)); + APP_ERROR_CHECK(err_code); + tx_sm_state_change(TX_STATE_ACTIVE); + } + break; + + case TX_STATE_ACTIVE: + switch (event) + { + case TX_EVENT_VALID_RX_ACK: + // Tx sequence number counter incremented as packet transmission + // acknowledged by peer transport entity. + packet_number_tx_inc(); + tx_sm_state_change(TX_STATE_IDLE); + break; + + case TX_EVENT_STATE_ENTRY: + m_tx_retry_counter = 0; + err_code = app_timer_start(m_app_timer_id, + RETRANSMISSION_TIMEOUT_IN_TICKS, + NULL); + APP_ERROR_CHECK(err_code); + break; + + case TX_EVENT_TIMEOUT: + if (m_tx_retry_counter != MAX_RETRY_COUNT) + { + ++m_tx_retry_counter; + // @note: no return value check done for hci_slip_write(...) call as current + // system design allows use case where retransmission is not accepted by the + // slip layer due to existing acknowledgement packet transmission in the + // slip layer. + UNUSED_VARIABLE(hci_slip_write(mp_tx_buffer, + (m_tx_buffer_length + + PKT_HDR_SIZE + + PKT_CRC_SIZE))); + } + else + { + // Application packet retransmission count reached: + // - set correct TX done event callback function result code + // - execute state change + // @note: m_tx_retry_counter is reset in TX_STATE_ACTIVE state entry. + m_tx_done_result_code = HCI_TRANSPORT_TX_DONE_FAILURE; + tx_sm_state_change(TX_STATE_IDLE); + } + break; + + default: + // No implementation needed. + break; + } + break; + + default: + // No implementation needed. + break; + } +} + + +/**@brief Function for changing the state of the TX state machine. + * + * @param[in] new_state State TX state machine transits to. + */ +static void tx_sm_state_change(tx_state_t new_state) +{ + m_tx_state = new_state; + tx_sm_event_handle(TX_EVENT_STATE_ENTRY); +} + + +/**@brief Function for handling slip events. + * + * @param[in] event The event structure. + */ +void slip_event_handle(hci_slip_evt_t event) +{ + uint32_t return_code; + uint32_t err_code; + + switch (event.evt_type) + { + case HCI_SLIP_TX_DONE: + tx_sm_event_handle(TX_EVENT_SLIP_TX_DONE); + break; + + case HCI_SLIP_RX_RDY: + return_code = packet_type_decode(event.packet, event.packet_length); + + switch (return_code) + { + case PKT_TYPE_VENDOR_SPECIFIC: + rx_vendor_specific_pkt_type_handle(event.packet, event.packet_length); + break; + + case PKT_TYPE_ACK: + if (rx_ack_pkt_type_handle(event.packet)) + { + // Valid expected acknowledgement packet received: set correct TX done event + // callback function result code and execute state change. + m_tx_done_result_code = HCI_TRANSPORT_TX_DONE_SUCCESS; + tx_sm_event_handle(TX_EVENT_VALID_RX_ACK); + } + + /* fall-through */ + default: + // RX packet dropped: reset memory buffer to slip in order to avoid RX buffer + // overflow. + // If existing mem pool produced RX buffer exists reuse that one. If existing + // mem pool produced RX buffer does not exist try to produce new one. If + // producing fails use the internal acknowledgement buffer. + if (mp_slip_used_rx_buffer != NULL) + { + err_code = hci_slip_rx_buffer_register(mp_slip_used_rx_buffer, RX_BUF_SIZE); + APP_ERROR_CHECK(err_code); + } + else + { + err_code = hci_mem_pool_rx_produce(RX_BUF_SIZE, + (void **)&mp_slip_used_rx_buffer); + APP_ERROR_CHECK_BOOL((err_code == NRF_SUCCESS) || + (err_code == NRF_ERROR_NO_MEM)); + + err_code = hci_slip_rx_buffer_register( + (err_code == NRF_SUCCESS) ? mp_slip_used_rx_buffer : m_rx_ack_buffer, + (err_code == NRF_SUCCESS) ? RX_BUF_SIZE : ACK_BUF_SIZE); + APP_ERROR_CHECK(err_code); + } + break; + } + break; + + case HCI_SLIP_RX_OVERFLOW: + err_code = hci_slip_rx_buffer_register(m_rx_ack_buffer, ACK_BUF_SIZE); + APP_ERROR_CHECK(err_code); + break; + + case HCI_SLIP_ERROR: + APP_ERROR_HANDLER(event.evt_type); + break; + + default: + APP_ERROR_HANDLER(event.evt_type); + break; + } +} + + +uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler) +{ + uint32_t err_code; + + m_transport_event_handle = event_handler; + err_code = hci_slip_evt_handler_register(slip_event_handle); + APP_ERROR_CHECK(err_code); + + return (event_handler != NULL) ? NRF_SUCCESS : NRF_ERROR_NULL; +} + + +uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler) +{ + uint32_t err_code; + + m_transport_tx_done_handle = event_handler; + err_code = hci_slip_evt_handler_register(slip_event_handle); + APP_ERROR_CHECK(err_code); + + return (event_handler != NULL) ? NRF_SUCCESS : NRF_ERROR_NULL; +} + + +/**@brief Function for handling the application packet retransmission timeout. + * + * This function is registered in the @ref app_timer module when a timer is created on + * @ref hci_transport_open. + * + * @note This function must be executed in APP-LO context otherwise retransmission behaviour is + * undefined, see @ref nrf51_system_integration_serialization. + * + * @param[in] p_context The timeout context. + */ +void hci_transport_timeout_handle(void * p_context) +{ + tx_sm_event_handle(TX_EVENT_TIMEOUT); +} + + +uint32_t hci_transport_open(void) +{ + mp_tx_buffer = NULL; + m_tx_buffer_length = 0; + m_tx_retry_counter = 0; + m_is_slip_decode_ready = false; + m_tx_state = TX_STATE_IDLE; + m_packet_expected_seq_number = INITIAL_ACK_NUMBER_EXPECTED; + m_packet_transmit_seq_number = INITIAL_ACK_NUMBER_TX; + m_tx_done_result_code = HCI_TRANSPORT_TX_DONE_FAILURE; + + uint32_t err_code = app_timer_create(&m_app_timer_id, + APP_TIMER_MODE_REPEATED, + hci_transport_timeout_handle); + if (err_code != NRF_SUCCESS) + { + // @note: conduct required interface adjustment. + return NRF_ERROR_INTERNAL; + } + + err_code = hci_mem_pool_open(); + VERIFY_SUCCESS(err_code); + + err_code = hci_slip_open(); + VERIFY_SUCCESS(err_code); + + err_code = hci_mem_pool_rx_produce(RX_BUF_SIZE, (void **)&mp_slip_used_rx_buffer); + if (err_code != NRF_SUCCESS) + { + // @note: conduct required interface adjustment. + return NRF_ERROR_INTERNAL; + } + + err_code = hci_slip_rx_buffer_register(mp_slip_used_rx_buffer, RX_BUF_SIZE); + + return err_code; +} + + +uint32_t hci_transport_close(void) +{ + uint32_t err_code; + + m_transport_tx_done_handle = NULL; + m_transport_event_handle = NULL; + + err_code = hci_mem_pool_close(); + APP_ERROR_CHECK(err_code); + err_code = hci_slip_close(); + APP_ERROR_CHECK(err_code); + + // @note: NRF_ERROR_NO_MEM is the only return value which should never be returned. + err_code = app_timer_stop(m_app_timer_id); + APP_ERROR_CHECK_BOOL(err_code != NRF_ERROR_NO_MEM); + + return NRF_SUCCESS; +} + + +uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory) +{ + const uint32_t err_code = hci_mem_pool_tx_alloc((void **)pp_memory); + if (err_code == NRF_SUCCESS) + { + // @note: no need to validate pp_memory against null as validation has already been done + // by hci_mem_pool_tx_alloc(...) and visible to us from the method return code. + //lint -e(413) "Likely use of null pointer" + *pp_memory += PKT_HDR_SIZE; + } + + return err_code; +} + + +uint32_t hci_transport_tx_free(void) +{ + return hci_mem_pool_tx_free(); +} + + +/**@brief Function for constructing 1st byte of the packet header of the packet to be transmitted. + * + * @return 1st byte of the packet header of the packet to be transmitted + */ +static __INLINE uint8_t tx_packet_byte_zero_construct(void) +{ + const uint32_t value = DATA_INTEGRITY_MASK | + RELIABLE_PKT_MASK | + (packet_number_expected_get() << 3u) | + packet_number_to_transmit_get(); + + return (uint8_t) value; +} + + +/**@brief Function for handling the application packet write request in tx-idle state. + */ +static uint32_t pkt_write_handle(void) +{ + uint32_t err_code; + + // Set packet header fields. + + mp_tx_buffer -= PKT_HDR_SIZE; + mp_tx_buffer[0] = tx_packet_byte_zero_construct(); + + const uint16_t type_and_length_fields = ((m_tx_buffer_length << 4u) | PKT_TYPE_VENDOR_SPECIFIC); + // @note: no use case for uint16_encode(...) return value. + UNUSED_VARIABLE(uint16_encode(type_and_length_fields, &(mp_tx_buffer[1]))); + mp_tx_buffer[3] = header_checksum_calculate(mp_tx_buffer); + + // Calculate, append CRC to the packet and write it. + + const uint16_t crc = crc16_compute(mp_tx_buffer, (PKT_HDR_SIZE + m_tx_buffer_length), NULL); + // @note: no use case for uint16_encode(...) return value. + UNUSED_VARIABLE(uint16_encode(crc, &(mp_tx_buffer[PKT_HDR_SIZE + m_tx_buffer_length]))); + err_code = hci_slip_write(mp_tx_buffer, (m_tx_buffer_length + PKT_HDR_SIZE + PKT_CRC_SIZE)); + switch (err_code) + { + case NRF_SUCCESS: + tx_sm_state_change(TX_STATE_ACTIVE); + break; + + case NRF_ERROR_NO_MEM: + tx_sm_state_change(TX_STATE_PENDING); + err_code = NRF_SUCCESS; + break; + + default: + // No implementation needed. + break; + } + + return err_code; +} + + +uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length) +{ + uint32_t err_code; + + if (p_buffer) + { + switch (m_tx_state) + { + case TX_STATE_IDLE: + mp_tx_buffer = (uint8_t *)p_buffer; + m_tx_buffer_length = length; + err_code = pkt_write_handle(); + break; + + default: + err_code = NRF_ERROR_NO_MEM; + break; + } + } + else + { + err_code = NRF_ERROR_NULL; + } + + return err_code; +} + + +uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length) +{ + uint32_t err_code; + + if (pp_buffer != NULL && p_length != NULL) + { + uint32_t length = 0; + + if (m_is_slip_decode_ready) + { + m_is_slip_decode_ready = false; + err_code = hci_mem_pool_rx_extract(pp_buffer, &length); + length -= (PKT_HDR_SIZE + PKT_CRC_SIZE); + + *p_length = (uint16_t)length; + *pp_buffer += PKT_HDR_SIZE; + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + } + else + { + err_code = NRF_ERROR_NULL; + } + + return err_code; +} + + +uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer) +{ + return (hci_mem_pool_rx_consume(p_buffer - PKT_HDR_SIZE)); +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.h new file mode 100644 index 0000000..85a4d6a --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_transport.h @@ -0,0 +1,220 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup hci_transport HCI Transport + * @{ + * @ingroup app_common + * + * @brief HCI transport module implementation. + * + * This module implements certain specific features from the three-wire UART transport layer, + * defined by the Bluetooth specification version 4.0 [Vol 4] part D. + * + * \par Features supported + * - Transmission and reception of Vendor Specific HCI packet type application packets. + * - Transmission and reception of reliable packets: defined by chapter 6 of the specification. + * + * \par Features not supported + * - Link establishment procedure: defined by chapter 8 of the specification. + * - Low power: defined by chapter 9 of the specification. + * + * \par Implementation specific behaviour + * - As Link establishment procedure is not supported following static link configuration parameters + * are used: + * + TX window size is 1. + * + 16 bit CCITT-CRC must be used. + * + Out of frame software flow control not supported. + * + Parameters specific for resending reliable packets are compile time configurable (clarifed + * later in this document). + * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for + * transmission within same context which the corresponding application packet was received. + * + * \par Implementation specific limitations + * Current implementation has the following limitations which will have impact to system wide + * behaviour: + * - Delayed acknowledgement scheduling not implemented: + * There exists a possibility that acknowledgement TX packet and application TX packet will collide + * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX + * pipeline which will trigger the retransmission algorithm within the peer protocol entity. + * - Delayed retransmission scheduling not implemented: + * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet + * will collide in the TX pipeline having the end result that retransmitted application TX packet + * will be excluded from the TX pipeline. + * - Processing of the acknowledgement number from RX application packets: + * Acknowledgement number is not processed from the RX application packets having the end result + * that unnecessary application packet retransmissions can occur. + * + * The application TX packet processing flow is illustrated by the statemachine below. + * + * @image html hci_transport_tx_sm.png "TX - application packet statemachine" + * + * \par Component specific configuration options + * + * The following compile time configuration options are available, and used to configure the + * application TX packet retransmission interval, in order to suite various application specific + * implementations: + * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits. + * - USED_BAUD_RATE Used uart baudrate. + * + * The following compile time configuration option is available to configure module specific + * behaviour: + * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets. + */ + +#ifndef HCI_TRANSPORT_H__ +#define HCI_TRANSPORT_H__ + +#include +#include "nrf_error.h" + +/**@brief Generic event callback function events. */ +typedef enum +{ + HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */ + HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */ +} hci_transport_evt_type_t; + +/**@brief Struct containing events from the Transport layer. + */ +typedef struct +{ + hci_transport_evt_type_t evt_type; /**< Type of event. */ +} hci_transport_evt_t; + +/**@brief Transport layer generic event callback function type. + * + * @param[in] event Transport layer event. + */ +typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event); + +/**@brief TX done event callback function result codes. */ +typedef enum +{ + HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */ + HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */ +} hci_transport_tx_done_result_t; + +/**@brief Transport layer TX done event callback function type. + * + * @param[in] result TX done event result code. + */ +typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result); + +/**@brief Function for registering a generic event handler. + * + * @note Multiple registration requests will overwrite any possible existing registration. + * + * @param[in] event_handler The function to be called by the transport layer upon an event. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. + */ +uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler); + +/**@brief Function for registering a handler for TX done event. + * + * @note Multiple registration requests will overwrite any possible existing registration. + * + * @param[in] event_handler The function to be called by the transport layer upon TX done + * event. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. + */ +uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler); + +/**@brief Function for opening the transport channel and initializing the transport layer. + * + * @warning Must not be called for a channel which has been allready opened. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred. + */ +uint32_t hci_transport_open(void); + +/**@brief Function for closing the transport channel. + * + * @note Can be called multiple times and also for not opened channel. + * + * @retval NRF_SUCCESS Operation success. + */ +uint32_t hci_transport_close(void); + +/**@brief Function for allocating tx packet memory. + * + * @param[out] pp_memory Pointer to the packet data. + * + * @retval NRF_SUCCESS Operation success. Memory was allocated. + * @retval NRF_ERROR_NO_MEM Operation failure. No memory available. + * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. + */ +uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory); + +/**@brief Function for freeing tx packet memory. + * + * @note Memory management works in FIFO principle meaning that free order must match the alloc + * order. + * + * @retval NRF_SUCCESS Operation success. Memory was freed. + */ +uint32_t hci_transport_tx_free(void); + +/**@brief Function for writing a packet. + * + * @note Completion of this method does not guarantee that actual peripheral transmission would + * have completed. + * + * @note In case of 0 byte packet length write request, message will consist of only transport + * module specific headers. + * + * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue + * and an event will be send upon transmission completion. + * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not + * added to the transmission queue. User should wait for + * a appropriate event prior issuing this operation again. + * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit. + * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. + * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open. + */ +uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length); + +/**@brief Function for extracting received packet. + * + * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to + * hci_transport_rx_pkt_consume(). + * + * @param[out] pp_buffer Pointer to the packet data. + * @param[out] p_length Length of packet data in bytes. + * + * @retval NRF_SUCCESS Operation success. Packet was extracted. + * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. + * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. + */ +uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length); + +/**@brief Function for consuming extracted packet described by p_buffer. + * + * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer. + * + * @param[in] p_buffer Pointer to the buffer that has been consumed. + * + * @retval NRF_SUCCESS Operation success. + * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume. + * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. + */ +uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer); + +#endif // HCI_TRANSPORT_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.c new file mode 100644 index 0000000..829d7f9 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.c @@ -0,0 +1,227 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_scheduler.h" +#include +#include +#include +#include "nrf_soc.h" +#include "nrf_assert.h" +#include "app_util.h" +#include "app_util_platform.h" + +/**@brief Structure for holding a scheduled event header. */ +typedef struct +{ + app_sched_event_handler_t handler; /**< Pointer to event handler to receive the event. */ + uint16_t event_data_size; /**< Size of event data. */ +} event_header_t; + +STATIC_ASSERT(sizeof(event_header_t) <= APP_SCHED_EVENT_HEADER_SIZE); + +static event_header_t * m_queue_event_headers; /**< Array for holding the queue event headers. */ +static uint8_t * m_queue_event_data; /**< Array for holding the queue event data. */ +static volatile uint8_t m_queue_start_index; /**< Index of queue entry at the start of the queue. */ +static volatile uint8_t m_queue_end_index; /**< Index of queue entry at the end of the queue. */ +static uint16_t m_queue_event_size; /**< Maximum event size in queue. */ +static uint16_t m_queue_size; /**< Number of queue entries. */ + +#ifdef APP_SCHEDULER_WITH_PROFILER +static uint16_t m_max_queue_utilization; /**< Maximum observed queue utilization. */ +#endif + +/**@brief Function for incrementing a queue index, and handle wrap-around. + * + * @param[in] index Old index. + * + * @return New (incremented) index. + */ +static __INLINE uint8_t next_index(uint8_t index) +{ + return (index < m_queue_size) ? (index + 1) : 0; +} + + +static __INLINE uint8_t app_sched_queue_full() +{ + uint8_t tmp = m_queue_start_index; + return next_index(m_queue_end_index) == tmp; +} + +/**@brief Macro for checking if a queue is full. */ +#define APP_SCHED_QUEUE_FULL() app_sched_queue_full() + + +static __INLINE uint8_t app_sched_queue_empty() +{ + uint8_t tmp = m_queue_start_index; + return m_queue_end_index == tmp; +} + +/**@brief Macro for checking if a queue is empty. */ +#define APP_SCHED_QUEUE_EMPTY() app_sched_queue_empty() + + +uint32_t app_sched_init(uint16_t event_size, uint16_t queue_size, void * p_event_buffer) +{ + uint16_t data_start_index = (queue_size + 1) * sizeof(event_header_t); + + // Check that buffer is correctly aligned + if (!is_word_aligned(p_event_buffer)) + { + return NRF_ERROR_INVALID_PARAM; + } + + // Initialize event scheduler + m_queue_event_headers = p_event_buffer; + m_queue_event_data = &((uint8_t *)p_event_buffer)[data_start_index]; + m_queue_end_index = 0; + m_queue_start_index = 0; + m_queue_event_size = event_size; + m_queue_size = queue_size; + +#ifdef APP_SCHEDULER_WITH_PROFILER + m_max_queue_utilization = 0; +#endif + + return NRF_SUCCESS; +} + + +#ifdef APP_SCHEDULER_WITH_PROFILER +static void queue_utilization_check(void) +{ + uint16_t start = m_queue_start_index; + uint16_t end = m_queue_end_index; + uint16_t queue_utilization = (end >= start) ? (end - start) : + (m_queue_size + 1 - start + end); + + if (queue_utilization > m_max_queue_utilization) + { + m_max_queue_utilization = queue_utilization; + } +} + +uint16_t app_sched_queue_utilization_get(void) +{ + return m_max_queue_utilization; +} +#endif + + +uint32_t app_sched_event_put(void * p_event_data, + uint16_t event_data_size, + app_sched_event_handler_t handler) +{ + uint32_t err_code; + + if (event_data_size <= m_queue_event_size) + { + uint16_t event_index = 0xFFFF; + + CRITICAL_REGION_ENTER(); + + if (!APP_SCHED_QUEUE_FULL()) + { + event_index = m_queue_end_index; + m_queue_end_index = next_index(m_queue_end_index); + + #ifdef APP_SCHEDULER_WITH_PROFILER + // This function call must be protected with critical region because + // it modifies 'm_max_queue_utilization'. + queue_utilization_check(); + #endif + } + + CRITICAL_REGION_EXIT(); + + if (event_index != 0xFFFF) + { + // NOTE: This can be done outside the critical region since the event consumer will + // always be called from the main loop, and will thus never interrupt this code. + m_queue_event_headers[event_index].handler = handler; + if ((p_event_data != NULL) && (event_data_size > 0)) + { + memcpy(&m_queue_event_data[event_index * m_queue_event_size], + p_event_data, + event_data_size); + m_queue_event_headers[event_index].event_data_size = event_data_size; + } + else + { + m_queue_event_headers[event_index].event_data_size = 0; + } + + err_code = NRF_SUCCESS; + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + } + else + { + err_code = NRF_ERROR_INVALID_LENGTH; + } + + return err_code; +} + + +/**@brief Function for reading the next event from specified event queue. + * + * @param[out] pp_event_data Pointer to pointer to event data. + * @param[out] p_event_data_size Pointer to size of event data. + * @param[out] p_event_handler Pointer to event handler function pointer. + * + * @return NRF_SUCCESS if new event, NRF_ERROR_NOT_FOUND if event queue is empty. + */ +static uint32_t app_sched_event_get(void ** pp_event_data, + uint16_t * p_event_data_size, + app_sched_event_handler_t * p_event_handler) +{ + uint32_t err_code = NRF_ERROR_NOT_FOUND; + + if (!APP_SCHED_QUEUE_EMPTY()) + { + uint16_t event_index; + + // NOTE: There is no need for a critical region here, as this function will only be called + // from app_sched_execute() from inside the main loop, so it will never interrupt + // app_sched_event_put(). Also, updating of (i.e. writing to) the start index will be + // an atomic operation. + event_index = m_queue_start_index; + m_queue_start_index = next_index(m_queue_start_index); + + *pp_event_data = &m_queue_event_data[event_index * m_queue_event_size]; + *p_event_data_size = m_queue_event_headers[event_index].event_data_size; + *p_event_handler = m_queue_event_headers[event_index].handler; + + err_code = NRF_SUCCESS; + } + + return err_code; +} + + +void app_sched_execute(void) +{ + void * p_event_data; + uint16_t event_data_size; + app_sched_event_handler_t event_handler; + + // Get next event (if any), and execute handler + while ((app_sched_event_get(&p_event_data, &event_data_size, &event_handler) == NRF_SUCCESS)) + { + event_handler(p_event_data, event_data_size); + } +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.h new file mode 100644 index 0000000..f52e616 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup app_scheduler Scheduler + * @{ + * @ingroup app_common + * + * @brief The scheduler is used for transferring execution from the interrupt context to the main + * context. + * + * @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events + * when using the Scheduler. + * + * @section app_scheduler_req Requirements: + * + * @subsection main_context_logic Logic in main context: + * + * - Define an event handler for each type of event expected. + * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the + * application main loop. + * - Call app_sched_execute() from the main loop each time the application wakes up because of an + * event (typically when sd_app_evt_wait() returns). + * + * @subsection int_context_logic Logic in interrupt context: + * + * - In the interrupt handler, call app_sched_event_put() + * with the appropriate data and event handler. This will insert an event into the + * scheduler's queue. The app_sched_execute() function will pull this event and call its + * handler in the main context. + * + * @if (PERIPHERAL) + * For an example usage of the scheduler, see the implementations of + * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard. + * @endif + * + * @image html scheduler_working.jpg The high level design of the scheduler + */ + +#ifndef APP_SCHEDULER_H__ +#define APP_SCHEDULER_H__ + +#include +#include "app_error.h" +#include "app_util.h" + +#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */ + +/**@brief Compute number of bytes required to hold the scheduler buffer. + * + * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. + * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events + * that can be scheduled for execution). + * + * @return Required scheduler buffer size (in bytes). + */ +#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \ + (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1)) + +/**@brief Scheduler event handler type. */ +typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size); + +/**@brief Macro for initializing the event scheduler. + * + * @details It will also handle dimensioning and allocation of the memory buffer required by the + * scheduler, making sure the buffer is correctly aligned. + * + * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. + * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events + * that can be scheduled for execution). + * + * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it + * several times as long as it is from the same location, e.g. to do a reinitialization). + */ +#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \ + do \ + { \ + static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \ + sizeof(uint32_t))]; \ + uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \ + APP_ERROR_CHECK(ERR_CODE); \ + } while (0) + +/**@brief Function for initializing the Scheduler. + * + * @details It must be called before entering the main loop. + * + * @param[in] max_event_size Maximum size of events to be passed through the scheduler. + * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of + * events that can be scheduled for execution). + * @param[in] p_evt_buffer Pointer to memory buffer for holding the scheduler queue. It must + * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer + * must be aligned to a 4 byte boundary. + * + * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both + * allocate the scheduler buffer, and also align the buffer correctly. + * + * @retval NRF_SUCCESS Successful initialization. + * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte + * boundary). + */ +uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer); + +/**@brief Function for executing all scheduled events. + * + * @details This function must be called from within the main loop. It will execute all events + * scheduled since the last time it was called. + */ +void app_sched_execute(void); + +/**@brief Function for scheduling an event. + * + * @details Puts an event into the event queue. + * + * @param[in] p_event_data Pointer to event data to be scheduled. + * @param[in] event_size Size of event data to be scheduled. + * @param[in] handler Event handler to receive the event. + * + * @return NRF_SUCCESS on success, otherwise an error code. + */ +uint32_t app_sched_event_put(void * p_event_data, + uint16_t event_size, + app_sched_event_handler_t handler); + +#ifdef APP_SCHEDULER_WITH_PROFILER +/**@brief Function for getting the maximum observed queue utilization. + * + * Function for tuning the module and determining QUEUE_SIZE value and thus module RAM usage. + * + * @return Maximum number of events in queue observed so far. + */ +uint16_t app_sched_queue_utilization_get(void); +#endif + +#ifdef APP_SCHEDULER_WITH_PAUSE +/**@brief A function to pause the scheduler. + * + * @details When the scheduler is paused events are not pulled from the scheduler queue for + * processing. The function can be called multiple times. To unblock the scheduler the + * function @ref app_sched_resume has to be called the same number of times. + */ +void app_sched_pause(void); + +/**@brief A function to resume a scheduler. + * + * @details To unblock the scheduler this function has to be called the same number of times as + * @ref app_sched_pause function. + */ +void app_sched_resume(void); +#endif +#endif // APP_SCHEDULER_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler_serconn.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler_serconn.c new file mode 100644 index 0000000..f411eff --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/scheduler/app_scheduler_serconn.c @@ -0,0 +1,262 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_scheduler.h" +#include +#include +#include +#include "nrf_soc.h" +#include "nrf_assert.h" +#include "app_util.h" +#include "app_util_platform.h" + +/**@brief Structure for holding a scheduled event header. */ +typedef struct +{ + app_sched_event_handler_t handler; /**< Pointer to event handler to receive the event. */ + uint16_t event_data_size; /**< Size of event data. */ +} event_header_t; + +STATIC_ASSERT(sizeof (event_header_t) <= APP_SCHED_EVENT_HEADER_SIZE); + +static event_header_t * m_queue_event_headers; /**< Array for holding the queue event headers. */ +static uint8_t * m_queue_event_data; /**< Array for holding the queue event data. */ +static volatile uint8_t m_queue_start_index; /**< Index of queue entry at the start of the queue. */ +static volatile uint8_t m_queue_end_index; /**< Index of queue entry at the end of the queue. */ +static uint16_t m_queue_event_size; /**< Maximum event size in queue. */ +static uint16_t m_queue_size; /**< Number of queue entries. */ + +#ifdef APP_SCHEDULER_WITH_PROFILER +static uint16_t m_max_queue_utilization; /**< Maximum observed queue utilization. */ +#endif + +static uint32_t m_scheduler_paused_counter = 0; /**< Counter storing the difference between pausing + and resuming the scheduler. */ + +/**@brief Function for incrementing a queue index, and handle wrap-around. + * + * @param[in] index Old index. + * + * @return New (incremented) index. + */ +static __INLINE uint8_t next_index(uint8_t index) +{ + return (index < m_queue_size) ? (index + 1) : 0; +} + +static __INLINE uint8_t app_sched_queue_full(void) +{ + uint8_t tmp = m_queue_start_index; + return next_index(m_queue_end_index) == tmp; +} + +/**@brief Macro for checking if a queue is full. */ +#define APP_SCHED_QUEUE_FULL() app_sched_queue_full() + +static __INLINE uint8_t app_sched_queue_empty(void) +{ + uint8_t tmp = m_queue_start_index; + return m_queue_end_index == tmp; +} + +/**@brief Macro for checking if a queue is empty. */ +#define APP_SCHED_QUEUE_EMPTY() app_sched_queue_empty() + + +uint32_t app_sched_init(uint16_t event_size, uint16_t queue_size, void * p_event_buffer) +{ + uint16_t data_start_index = (queue_size + 1) * sizeof (event_header_t); + + //Check that buffer is correctly aligned + if (!is_word_aligned(p_event_buffer)) + { + return NRF_ERROR_INVALID_PARAM; + } + + //Initialize event scheduler + m_queue_event_headers = p_event_buffer; + m_queue_event_data = &((uint8_t *)p_event_buffer)[data_start_index]; + m_queue_end_index = 0; + m_queue_start_index = 0; + m_queue_event_size = event_size; + m_queue_size = queue_size; + +#ifdef APP_SCHEDULER_WITH_PROFILER + m_max_queue_utilization = 0; +#endif + + return NRF_SUCCESS; +} + + +#ifdef APP_SCHEDULER_WITH_PROFILER +static void check_queue_utilization(void) +{ + uint16_t start = m_queue_start_index; + uint16_t end = m_queue_end_index; + uint16_t queue_utilization = (end >= start) ? (end - start) : + (m_queue_size + 1 - start + end); + + if (queue_utilization > m_max_queue_utilization) + { + m_max_queue_utilization = queue_utilization; + } +} + +uint16_t app_sched_queue_utilization_get(void) +{ + return m_max_queue_utilization; +} +#endif + + +uint32_t app_sched_event_put(void * p_event_data, + uint16_t event_data_size, + app_sched_event_handler_t handler) +{ + uint32_t err_code; + + if (event_data_size <= m_queue_event_size) + { + uint16_t event_index = 0xFFFF; + + CRITICAL_REGION_ENTER(); + + if (!APP_SCHED_QUEUE_FULL()) + { + event_index = m_queue_end_index; + m_queue_end_index = next_index(m_queue_end_index); + } + + CRITICAL_REGION_EXIT(); + + if (event_index != 0xFFFF) + { + //NOTE: This can be done outside the critical region since the event consumer will + //always be called from the main loop, and will thus never interrupt this code. + m_queue_event_headers[event_index].handler = handler; + + if ((p_event_data != NULL) && (event_data_size > 0)) + { + memcpy(&m_queue_event_data[event_index * m_queue_event_size], + p_event_data, + event_data_size); + m_queue_event_headers[event_index].event_data_size = event_data_size; + } + else + { + m_queue_event_headers[event_index].event_data_size = 0; + } + + #ifdef APP_SCHEDULER_WITH_PROFILER + check_queue_utilization(); + #endif + + err_code = NRF_SUCCESS; + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + } + else + { + err_code = NRF_ERROR_INVALID_LENGTH; + } + + return err_code; +} + + +/**@brief Function for reading the next event from specified event queue. + * + * @param[out] pp_event_data Pointer to pointer to event data. + * @param[out] p_event_data_size Pointer to size of event data. + * @param[out] p_event_handler Pointer to event handler function pointer. + * + * @return NRF_SUCCESS if new event, NRF_ERROR_NOT_FOUND if event queue is empty. + */ +static uint32_t app_sched_event_get(void * * pp_event_data, + uint16_t * p_event_data_size, + app_sched_event_handler_t * p_event_handler) +{ + uint32_t err_code = NRF_ERROR_NOT_FOUND; + + if (!APP_SCHED_QUEUE_EMPTY()) + { + uint16_t event_index; + + //NOTE: There is no need for a critical region here, as this function will only be called + //from app_sched_execute() from inside the main loop, so it will never interrupt + //app_sched_event_put(). Also, updating of (i.e. writing to) the start index will be + //an atomic operation. + event_index = m_queue_start_index; + m_queue_start_index = next_index(m_queue_start_index); + + *pp_event_data = &m_queue_event_data[event_index * m_queue_event_size]; + *p_event_data_size = m_queue_event_headers[event_index].event_data_size; + *p_event_handler = m_queue_event_headers[event_index].handler; + + err_code = NRF_SUCCESS; + } + + return err_code; +} + + +void app_sched_pause(void) +{ + CRITICAL_REGION_ENTER(); + + if (m_scheduler_paused_counter < UINT32_MAX) + { + m_scheduler_paused_counter++; + } + CRITICAL_REGION_EXIT(); +} + + +void app_sched_resume(void) +{ + CRITICAL_REGION_ENTER(); + + if (m_scheduler_paused_counter > 0) + { + m_scheduler_paused_counter--; + } + CRITICAL_REGION_EXIT(); +} + +/**@brief Function for checking if scheduler is paused which means that should break processing + * events. + * + * @return Boolean value - true if scheduler is paused, false otherwise. + */ +static __INLINE bool is_app_sched_paused(void) +{ + return (m_scheduler_paused_counter > 0); +} + + +void app_sched_execute(void) +{ + void * p_event_data; + uint16_t event_data_size; + app_sched_event_handler_t event_handler; + + //Get next event (if any), and execute handler + while ((!is_app_sched_paused()) && + (app_sched_event_get(&p_event_data, &event_data_size, &event_handler) == NRF_SUCCESS)) + { + event_handler(p_event_data, event_data_size); + } +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/simple_timer/app_simple_timer.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/simple_timer/app_simple_timer.c new file mode 100644 index 0000000..eef38ec --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/simple_timer/app_simple_timer.c @@ -0,0 +1,187 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_simple_timer.h" +#include "nrf.h" +#include "app_util_platform.h" +#include "app_error.h" +#include "nrf_timer.h" +#include "nrf_drv_timer.h" +#include "sdk_common.h" + +/**@brief States of simple timer state machine. + */ +typedef enum +{ + SIMPLE_TIMER_STATE_IDLE = 0, + SIMPLE_TIMER_STATE_INITIALIZED, + SIMPLE_TIMER_STATE_STOPPED, + SIMPLE_TIMER_STATE_STARTED +}simple_timer_states_t; + +static app_simple_timer_mode_t m_mode; /**< Registered timer mode. */ +static app_simple_timer_timeout_handler_t m_timeout_handler = NULL; /**< Registered time-out handler. */ +static void * mp_timeout_handler_context = NULL; /**< Registered time-out handler context. */ +static simple_timer_states_t m_simple_timer_state = SIMPLE_TIMER_STATE_IDLE; /**< State machine state. */ + +#define APP_SIMPLE_TIMER_INSTANCE 1 + +#if (APP_SIMPLE_TIMER_INSTANCE == 0) + #if (TIMER_CONFIG_MODE(0) != TIMER_MODE_MODE_Timer) + #error "Unsupported timer mode." + #endif + #if (TIMER_CONFIG_BIT_WIDTH(0) != TIMER_BITMODE_BITMODE_16Bit) + #error "Unsupported timer bit width." + #endif + const nrf_drv_timer_t SIMPLE_TIMER = NRF_DRV_TIMER_INSTANCE(0); +#elif (APP_SIMPLE_TIMER_INSTANCE == 1) + #if (TIMER_CONFIG_MODE(1) != TIMER_MODE_MODE_Timer) + #error "Unsupported timer mode." + #endif + #if (TIMER_CONFIG_BIT_WIDTH(1) != TIMER_BITMODE_BITMODE_16Bit) + #error "Unsupported timer bit width." + #endif + const nrf_drv_timer_t SIMPLE_TIMER = NRF_DRV_TIMER_INSTANCE(1); +#elif (APP_SIMPLE_TIMER_INSTANCE == 2) + #if (TIMER_CONFIG_MODE(2) != TIMER_MODE_MODE_Timer) + #error "Unsupported timer mode." + #endif + #if (TIMER_CONFIG_BIT_WIDTH(2) != TIMER_BITMODE_BITMODE_16Bit) + #error "Unsupported timer bit width." + #endif + const nrf_drv_timer_t SIMPLE_TIMER = NRF_DRV_TIMER_INSTANCE(2); +#else + #error "Wrong timer instance id." +#endif + +/** + * @brief Handler for timer events. + */ +static void app_simple_timer_event_handler(nrf_timer_event_t event_type, void * p_context) +{ + switch(event_type) + { + case NRF_TIMER_EVENT_COMPARE0: + if (m_mode == APP_SIMPLE_TIMER_MODE_SINGLE_SHOT) + { + m_simple_timer_state = SIMPLE_TIMER_STATE_STOPPED; + } + + //@note: No NULL check required as performed in timer_start(...). + m_timeout_handler(mp_timeout_handler_context); + break; + + default: + //Do nothing. + break; + } +} + +uint32_t app_simple_timer_init(void) +{ + uint32_t err_code = NRF_SUCCESS; + + err_code = nrf_drv_timer_init(&SIMPLE_TIMER, NULL, app_simple_timer_event_handler); + + if(NRF_SUCCESS == err_code) + { + m_simple_timer_state = SIMPLE_TIMER_STATE_INITIALIZED; + } + + return err_code; +} + +uint32_t app_simple_timer_start(app_simple_timer_mode_t mode, + app_simple_timer_timeout_handler_t timeout_handler, + uint16_t timeout_ticks, + void * p_context) +{ + uint32_t err_code = NRF_SUCCESS; + nrf_timer_short_mask_t timer_short; + + VERIFY_PARAM_NOT_NULL(timeout_handler); + + if (APP_SIMPLE_TIMER_MODE_REPEATED == mode) + { + timer_short = NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK; + } + else if(APP_SIMPLE_TIMER_MODE_SINGLE_SHOT == mode) + { + timer_short = NRF_TIMER_SHORT_COMPARE0_STOP_MASK; + } + else + { + return NRF_ERROR_INVALID_PARAM; + } + + if(SIMPLE_TIMER_STATE_IDLE == m_simple_timer_state) + { + return NRF_ERROR_INVALID_STATE; + } + + if(SIMPLE_TIMER_STATE_STARTED == m_simple_timer_state) + { + err_code = app_simple_timer_stop(); + APP_ERROR_CHECK(err_code); + } + + if(SIMPLE_TIMER_STATE_STOPPED == m_simple_timer_state) + { + nrf_drv_timer_clear(&SIMPLE_TIMER); + } + + m_mode = mode; + m_timeout_handler = timeout_handler; + mp_timeout_handler_context = p_context; + + nrf_drv_timer_extended_compare( + &SIMPLE_TIMER, NRF_TIMER_CC_CHANNEL0, (uint32_t)timeout_ticks, timer_short, true); + + if (m_simple_timer_state == SIMPLE_TIMER_STATE_STOPPED) + { + nrf_drv_timer_resume(&SIMPLE_TIMER); + } + else + { + nrf_drv_timer_enable(&SIMPLE_TIMER); + } + + + m_simple_timer_state = SIMPLE_TIMER_STATE_STARTED; + + return NRF_SUCCESS; +} + +uint32_t app_simple_timer_stop(void) +{ + if(SIMPLE_TIMER_STATE_STARTED == m_simple_timer_state) + { + nrf_drv_timer_pause(&SIMPLE_TIMER); + + m_simple_timer_state = SIMPLE_TIMER_STATE_STOPPED; + } + + return NRF_SUCCESS; +} + +uint32_t app_simple_timer_uninit(void) +{ + uint32_t err_code = NRF_SUCCESS; + + if(SIMPLE_TIMER_STATE_IDLE != m_simple_timer_state) + { + nrf_drv_timer_uninit(&SIMPLE_TIMER); + m_simple_timer_state = SIMPLE_TIMER_STATE_IDLE; + } + + return err_code; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/simple_timer/app_simple_timer.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/simple_timer/app_simple_timer.h new file mode 100644 index 0000000..f72d7ca --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/simple_timer/app_simple_timer.h @@ -0,0 +1,98 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup lib_driver_simple_timer Simple Timer + * @{ + * @ingroup app_common + * + * @brief Simple timer module. + * + * Supported features and limitations: + * - Two modes: single shot mode and repeated mode. + * - No more than one timer can run simultaneously. + * - The timer is hard-coded to use the TIMER1 peripheral and compare channel 0. + */ + +#ifndef TIMER_H__ +#define TIMER_H__ + +#include + +/**@brief Timer time-out handler type. */ +typedef void (*app_simple_timer_timeout_handler_t)(void * p_context); + +/**@brief Timer modes. */ +typedef enum +{ + APP_SIMPLE_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */ + APP_SIMPLE_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */ +} app_simple_timer_mode_t; + +/**@brief Function for configuring and setting up the timer hardware. + * + * @note Configuration parameters should be set in nrf_drv_config.h file. + * The TIMER1_CONFIG_MODE has to be set to NRF_TIMER_MODE_TIMER value. + * The TIMER1_CONFIG_BIT_WIDTH has to be set to NRF_TIMER_BIT_WIDTH_16 value. + * + * @retval NRF_SUCCESS If the operation is successful. + * @retval NRF_ERROR_INVALID_STATE If the operation fails because the timer is already initialized. + * @retval NRF_ERROR_INVALID_PARAM If the operation fails because some configuration parameter is + * not valid. + */ +uint32_t app_simple_timer_init(void); + +/**@brief Function for starting a timer. + * + * @note If this function is called for a timer that is already running, the currently running + * timer is stopped before starting the new one. + * + * @param[in] mode Timer mode (see @ref app_simple_timer_mode_t). + * @param[in] timeout_handler Function to be executed when the timer expires + * (see @ref app_simple_timer_timeout_handler_t). + * @param[in] timeout_ticks Number of timer ticks to time-out event. + * @param[in] p_context General purpose pointer. Will be passed to the time-out handler + * when the timer expires. + * + * @retval NRF_SUCCESS If the operation is successful. + * @retval NRF_ERROR_INVALID_STATE If the operation fails because @ref app_simple_timer_init has not + * been called and the operation is not allowed in this state. + * @retval NRF_ERROR_NULL If the operation fails because timeout_handler is NULL. + * @retval NRF_ERROR_INVALID_PARAM If the operation fails because "mode" parameter is not valid. + */ + +uint32_t app_simple_timer_start(app_simple_timer_mode_t mode, + app_simple_timer_timeout_handler_t timeout_handler, + uint16_t timeout_ticks, + void * p_context); + +/**@brief Function for stopping the timer. + * + * @retval NRF_SUCCESS If the operation is successful. + */ +uint32_t app_simple_timer_stop(void); + +/**@brief Function for uninitializing the timer. Should be called also when the timer is not used + * anymore to reach lowest power consumption in system. + * + * @note The function switches off the internal core of the timer to reach lowest power consumption + * in system. The startup time from this state may be longer compared to starting the timer + * from the stopped state. + * + * @retval NRF_SUCCESS If the operation is successful. + */ +uint32_t app_simple_timer_uninit(void); + +#endif // TIMER_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/slip/slip.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/slip/slip.c new file mode 100644 index 0000000..8e5bad8 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/slip/slip.c @@ -0,0 +1,112 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "slip.h" +#include "nrf_error.h" + +#define SLIP_END 0300 /* indicates end of packet */ +#define SLIP_ESC 0333 /* indicates byte stuffing */ +#define SLIP_ESC_END 0334 /* ESC ESC_END means END data byte */ +#define SLIP_ESC_ESC 0335 /* ESC ESC_ESC means ESC data byte */ + + +uint32_t slip_encode(uint8_t * p_output, uint8_t * p_input, uint32_t input_length, uint32_t output_buffer_length) +{ + uint32_t input_index; + uint32_t output_index; + + for (input_index = 0, output_index = 0; input_index < input_length && output_index < output_buffer_length; input_index++) + { + switch (p_input[input_index]) + { + case SLIP_END: + p_output[output_index++] = SLIP_END; + p_output[output_index++] = SLIP_ESC_END; + break; + + case SLIP_ESC: + p_output[output_index++] = SLIP_ESC; + p_output[output_index++] = SLIP_ESC_ESC; + break; + + default: + p_output[output_index++] = p_input[input_index]; + } + } + p_output[output_index++] = (uint8_t)SLIP_END; + p_output[output_index++] = (uint8_t)SLIP_END; // clarify that the packet has ended. + + return output_index; +} + + +uint32_t slip_decoding_add_char(uint8_t c, buffer_t * p_buf, slip_state_t * current_state) +{ + switch (*current_state) + { + case SLIP_DECODING: + if (c == SLIP_END) + { + *current_state = SLIP_END_RECEIVED; + } + else if (c == SLIP_ESC) + { + *current_state = SLIP_END_RECEIVED; + } + else + { + p_buf->p_buffer[p_buf->current_index++] = c; + p_buf->current_length++; + } + break; + + case SLIP_ESC_RECEIVED: + if (c == SLIP_ESC_ESC) + { + p_buf->p_buffer[p_buf->current_index++] = SLIP_ESC; + p_buf->current_length++; + *current_state = SLIP_DECODING; + } + else + { + // violation of protocol + *current_state = SLIP_CLEARING_INVALID_PACKET; + return NRF_ERROR_INVALID_DATA; + } + break; + + case SLIP_END_RECEIVED: + if (c == SLIP_ESC_END) + { + p_buf->p_buffer[p_buf->current_index++] = SLIP_END; + p_buf->current_length++; + *current_state = SLIP_DECODING; + } + else + { + // packet is finished + *current_state = SLIP_DECODING; + return NRF_SUCCESS; + } + break; + + case SLIP_CLEARING_INVALID_PACKET: + if (c == SLIP_END) + { + *current_state = SLIP_DECODING; + p_buf->current_index = 0; + p_buf->current_length = 0; + } + break; + } + return NRF_ERROR_BUSY; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/slip/slip.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/slip/slip.h new file mode 100644 index 0000000..7c63b81 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/slip/slip.h @@ -0,0 +1,66 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef SLIP_H__ +#define SLIP_H__ + +#include +#include "app_fifo.h" + +/** @file + * + * @defgroup slip SLIP encoding decoding + * @{ + * @ingroup app_common + * + * @brief This module encodes and decodes slip packages (RFC1055). + * + * @details The standard is described in https://tools.ietf.org/html/rfc1055 + */ + +typedef enum { + SLIP_DECODING, + SLIP_END_RECEIVED, + SLIP_ESC_RECEIVED, + SLIP_CLEARING_INVALID_PACKET, +} slip_state_t; + +typedef struct { + uint8_t * p_buffer; + uint32_t current_index; + uint32_t current_length; + uint32_t len; +} buffer_t; + +/**@brief Encodes a slip packet. + * + * @details Note that the encoded output data will be longer than the input data. + * + * @retval The length of the encoded packet. If it is smaller than the input length, an error has occurred. + */ +uint32_t slip_encode(uint8_t * p_output, uint8_t * p_input, uint32_t input_length, uint32_t output_buffer_length); + +/**@brief Decodes a slip packet. + * + * @details When decoding a slip packet, a state must be preserved. Initial state must be set to SLIP_DECODING. + * + * @retval NRF_SUCCESS when a packet is parsed. The length of the packet can be read out from p_buf->current_index + * @retval NRF_ERROR_BUSY when packet is not finished parsing + * @retval NRF_ERROR_INVALID_DATA when packet is encoded wrong. + This moves the decoding to SLIP_CLEARING_INVALID_PACKET, and will stay in this state until SLIP_END is encountered. + */ +uint32_t slip_decoding_add_char(uint8_t c, buffer_t * p_buf, slip_state_t * current_state); + + +#endif // SLIP_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.c new file mode 100644 index 0000000..d19f009 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.c @@ -0,0 +1,1152 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_timer.h" +#include +#include "nrf.h" +#include "nrf_soc.h" +#include "app_error.h" +#include "nrf_delay.h" +#include "app_util_platform.h" +#include "sdk_common.h" + +#define RTC1_IRQ_PRI APP_IRQ_PRIORITY_LOW /**< Priority of the RTC1 interrupt (used for checking for timeouts and executing timeout handlers). */ +#define SWI_IRQ_PRI APP_IRQ_PRIORITY_LOW /**< Priority of the SWI interrupt (used for updating the timer list). */ + +// The current design assumes that both interrupt handlers run at the same interrupt level. +// If this is to be changed, protection must be added to prevent them from interrupting each other +// (e.g. by using guard/trigger flags). +STATIC_ASSERT(RTC1_IRQ_PRI == SWI_IRQ_PRI); + +#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */ + +#define APP_HIGH_USER_ID 0 /**< User Id for the Application High "user". */ +#define APP_LOW_USER_ID 1 /**< User Id for the Application Low "user". */ +#define THREAD_MODE_USER_ID 2 /**< User Id for the Thread Mode "user". */ + +#define RTC_COMPARE_OFFSET_MIN 3 /**< Minimum offset between the current RTC counter value and the Capture Compare register. Although the nRF51 Series User Specification recommends this value to be 2, we use 3 to be safer.*/ + +#define MAX_RTC_TASKS_DELAY 47 /**< Maximum delay until an RTC task is executed. */ + +#ifdef NRF51 +#define SWI_IRQn SWI0_IRQn +#define SWI_IRQHandler SWI0_IRQHandler +#elif defined NRF52 +#define SWI_IRQn SWI0_EGU0_IRQn +#define SWI_IRQHandler SWI0_EGU0_IRQHandler +#endif + +/**@brief Timer node type. The nodes will be used form a linked list of running timers. */ +typedef struct +{ + uint32_t ticks_to_expire; /**< Number of ticks from previous timer interrupt to timer expiry. */ + uint32_t ticks_at_start; /**< Current RTC counter value when the timer was started. */ + uint32_t ticks_first_interval; /**< Number of ticks in the first timer interval. */ + uint32_t ticks_periodic_interval; /**< Timer period (for repeating timers). */ + bool is_running; /**< True if timer is running, False otherwise. */ + app_timer_mode_t mode; /**< Timer mode. */ + app_timer_timeout_handler_t p_timeout_handler; /**< Pointer to function to be executed when the timer expires. */ + void * p_context; /**< General purpose pointer. Will be passed to the timeout handler when the timer expires. */ + void * next; /**< Pointer to the next node. */ +} timer_node_t; + +STATIC_ASSERT(sizeof(timer_node_t) == APP_TIMER_NODE_SIZE); + +/**@brief Set of available timer operation types. */ +typedef enum +{ + TIMER_USER_OP_TYPE_NONE, /**< Invalid timer operation type. */ + TIMER_USER_OP_TYPE_START, /**< Timer operation type Start. */ + TIMER_USER_OP_TYPE_STOP, /**< Timer operation type Stop. */ + TIMER_USER_OP_TYPE_STOP_ALL /**< Timer operation type Stop All. */ +} timer_user_op_type_t; + +/**@brief Structure describing a timer start operation. */ +typedef struct +{ + uint32_t ticks_at_start; /**< Current RTC counter value when the timer was started. */ + uint32_t ticks_first_interval; /**< Number of ticks in the first timer interval. */ + uint32_t ticks_periodic_interval; /**< Timer period (for repeating timers). */ + void * p_context; /**< General purpose pointer. Will be passed to the timeout handler when the timer expires. */ +} timer_user_op_start_t; + +/**@brief Structure describing a timer operation. */ +typedef struct +{ + timer_user_op_type_t op_type; /**< Id of timer on which the operation is to be performed. */ + timer_node_t * p_node; + union + { + timer_user_op_start_t start; /**< Structure describing a timer start operation. */ + } params; +} timer_user_op_t; + +STATIC_ASSERT(sizeof(timer_user_op_t) <= APP_TIMER_USER_OP_SIZE); +STATIC_ASSERT(sizeof(timer_user_op_t) % 4 == 0); + +/**@brief Structure describing a timer user. + * + * @details For each user of the timer module, there will be a timer operations queue. This queue + * will hold timer operations issued by this user until the timer interrupt handler + * processes these operations. For the current implementation, there will be one user for + * each interrupt level available to the application (APP_HIGH, APP_LOW and THREAD_MODE), + * but the module can easily be modified to e.g. have one queue per process when using an + * RTOS. The purpose of the queues is to be able to have a completely lockless timer + * implementation. + */ +typedef struct +{ + uint8_t first; /**< Index of first entry to have been inserted in the queue (i.e. the next entry to be executed). */ + uint8_t last; /**< Index of last entry to have been inserted in the queue. */ + uint8_t user_op_queue_size; /**< Queue size. */ + timer_user_op_t * p_user_op_queue; /**< Queue buffer. */ +} timer_user_t; + +STATIC_ASSERT(sizeof(timer_user_t) == APP_TIMER_USER_SIZE); +STATIC_ASSERT(sizeof(timer_user_t) % 4 == 0); + +/**@brief User id type. + * + * @details In the current implementation, this will automatically be generated from the current + * interrupt level. + */ +typedef uint32_t timer_user_id_t; + +#define CONTEXT_QUEUE_SIZE_MAX (2) + +static uint8_t m_user_array_size; /**< Size of timer user array. */ +static timer_user_t * mp_users = NULL; /**< Array of timer users. */ +static timer_node_t * mp_timer_id_head; /**< First timer in list of running timers. */ +static uint32_t m_ticks_latest; /**< Last known RTC counter value. */ +static uint32_t m_ticks_elapsed[CONTEXT_QUEUE_SIZE_MAX]; /**< Timer internal elapsed ticks queue. */ +static uint8_t m_ticks_elapsed_q_read_ind; /**< Timer internal elapsed ticks queue read index. */ +static uint8_t m_ticks_elapsed_q_write_ind; /**< Timer internal elapsed ticks queue write index. */ +static app_timer_evt_schedule_func_t m_evt_schedule_func; /**< Pointer to function for propagating timeout events to the scheduler. */ +static bool m_rtc1_running; /**< Boolean indicating if RTC1 is running. */ +static bool m_rtc1_reset; /**< Boolean indicating if RTC1 counter has been reset due to last timer removed from timer list during the timer list handling. */ + +#ifdef APP_TIMER_WITH_PROFILER +static uint8_t m_max_user_op_queue_utilization; /**< Maximum observed timer user operations queue utilization. */ +#endif + +#define MODULE_INITIALIZED (mp_users != NULL) +#include "sdk_macros.h" + +/**@brief Function for initializing the RTC1 counter. + * + * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling. + */ +static void rtc1_init(uint32_t prescaler) +{ + NRF_RTC1->PRESCALER = prescaler; + NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI); +} + + +/**@brief Function for starting the RTC1 timer. + */ +static void rtc1_start(void) +{ + NRF_RTC1->EVTENSET = RTC_EVTEN_COMPARE0_Msk; + NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk; + + NVIC_ClearPendingIRQ(RTC1_IRQn); + NVIC_EnableIRQ(RTC1_IRQn); + + NRF_RTC1->TASKS_START = 1; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + + m_rtc1_running = true; +} + + +/**@brief Function for stopping the RTC1 timer. + */ +static void rtc1_stop(void) +{ + NVIC_DisableIRQ(RTC1_IRQn); + + NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; + NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk; + + NRF_RTC1->TASKS_STOP = 1; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + + NRF_RTC1->TASKS_CLEAR = 1; + m_ticks_latest = 0; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + + m_rtc1_running = false; +} + + +/**@brief Function for returning the current value of the RTC1 counter. + * + * @return Current value of the RTC1 counter. + */ +static __INLINE uint32_t rtc1_counter_get(void) +{ + return NRF_RTC1->COUNTER; +} + + +/**@brief Function for computing the difference between two RTC1 counter values. + * + * @return Number of ticks elapsed from ticks_old to ticks_now. + */ +static __INLINE uint32_t ticks_diff_get(uint32_t ticks_now, uint32_t ticks_old) +{ + return ((ticks_now - ticks_old) & MAX_RTC_COUNTER_VAL); +} + + +/**@brief Function for setting the RTC1 Capture Compare register 0, and enabling the corresponding + * event. + * + * @param[in] value New value of Capture Compare register 0. + */ +static __INLINE void rtc1_compare0_set(uint32_t value) +{ + NRF_RTC1->CC[0] = value; +} + + +/**@brief Function for inserting a timer in the timer list. + * + * @param[in] timer_id Id of timer to insert. + */ +static void timer_list_insert(timer_node_t * p_timer) +{ + if (mp_timer_id_head == NULL) + { + mp_timer_id_head = p_timer; + } + else + { + if (p_timer->ticks_to_expire <= mp_timer_id_head->ticks_to_expire) + { + mp_timer_id_head->ticks_to_expire -= p_timer->ticks_to_expire; + + p_timer->next = mp_timer_id_head; + mp_timer_id_head = p_timer; + } + else + { + timer_node_t * p_previous; + timer_node_t * p_current; + uint32_t ticks_to_expire; + + ticks_to_expire = p_timer->ticks_to_expire; + p_previous = mp_timer_id_head; + p_current = mp_timer_id_head; + + while ((p_current != NULL) && (ticks_to_expire > p_current->ticks_to_expire)) + { + ticks_to_expire -= p_current->ticks_to_expire; + p_previous = p_current; + p_current = p_current->next; + } + + if (p_current != NULL) + { + p_current->ticks_to_expire -= ticks_to_expire; + } + + p_timer->ticks_to_expire = ticks_to_expire; + p_timer->next = p_current; + p_previous->next = p_timer; + } + } +} + + +/**@brief Function for removing a timer from the timer queue. + * + * @param[in] timer_id Id of timer to remove. + */ +static void timer_list_remove(timer_node_t * p_timer) +{ + timer_node_t * p_previous; + timer_node_t * p_current; + uint32_t timeout; + + // Find the timer's position in timer list. + p_previous = mp_timer_id_head; + p_current = p_previous; + + while (p_current != NULL) + { + if (p_current == p_timer) + { + break; + } + p_previous = p_current; + p_current = p_current->next; + } + + // Timer not in active list. + if (p_current == NULL) + { + return; + } + + // Timer is the first in the list + if (p_previous == p_current) + { + mp_timer_id_head = mp_timer_id_head->next; + + // No more timers in the list. Reset RTC1 in case Start timer operations are present in the queue. + if (mp_timer_id_head == NULL) + { + NRF_RTC1->TASKS_CLEAR = 1; + m_ticks_latest = 0; + m_rtc1_reset = true; + } + } + + // Remaining timeout between next timeout. + timeout = p_current->ticks_to_expire; + + // Link previous timer with next of this timer, i.e. removing the timer from list. + p_previous->next = p_current->next; + + // If this is not the last timer, increment the next timer by this timer timeout. + p_current = p_previous->next; + if (p_current != NULL) + { + p_current->ticks_to_expire += timeout; + } +} + + +/**@brief Function for scheduling a check for timeouts by generating a RTC1 interrupt. + */ +static void timer_timeouts_check_sched(void) +{ + NVIC_SetPendingIRQ(RTC1_IRQn); +} + + +/**@brief Function for scheduling a timer list update by generating a SWI interrupt. + */ +static void timer_list_handler_sched(void) +{ + NVIC_SetPendingIRQ(SWI_IRQn); +} + + +/**@brief Function for executing an application timeout handler, either by calling it directly, or + * by passing an event to the @ref app_scheduler. + * + * @param[in] p_timer Pointer to expired timer. + */ +static void timeout_handler_exec(timer_node_t * p_timer) +{ + if (m_evt_schedule_func != NULL) + { + uint32_t err_code = m_evt_schedule_func(p_timer->p_timeout_handler, p_timer->p_context); + APP_ERROR_CHECK(err_code); + } + else + { + p_timer->p_timeout_handler(p_timer->p_context); + } +} + + +/**@brief Function for checking for expired timers. + */ +static void timer_timeouts_check(void) +{ + // Handle expired of timer + if (mp_timer_id_head != NULL) + { + timer_node_t * p_timer; + timer_node_t * p_previous_timer; + uint32_t ticks_elapsed; + uint32_t ticks_expired; + + // Initialize actual elapsed ticks being consumed to 0. + ticks_expired = 0; + + // ticks_elapsed is collected here, job will use it. + ticks_elapsed = ticks_diff_get(rtc1_counter_get(), m_ticks_latest); + + // Auto variable containing the head of timers expiring. + p_timer = mp_timer_id_head; + + // Expire all timers within ticks_elapsed and collect ticks_expired. + while (p_timer != NULL) + { + // Do nothing if timer did not expire. + if (ticks_elapsed < p_timer->ticks_to_expire) + { + break; + } + + // Decrement ticks_elapsed and collect expired ticks. + ticks_elapsed -= p_timer->ticks_to_expire; + ticks_expired += p_timer->ticks_to_expire; + + // Move to next timer. + p_previous_timer = p_timer; + p_timer = p_timer->next; + + // Execute Task. + if (p_previous_timer->is_running) + { + p_previous_timer->is_running = false; + timeout_handler_exec(p_previous_timer); + } + } + + // Prepare to queue the ticks expired in the m_ticks_elapsed queue. + if (m_ticks_elapsed_q_read_ind == m_ticks_elapsed_q_write_ind) + { + // The read index of the queue is equal to the write index. This means the new + // value of ticks_expired should be stored at a new location in the m_ticks_elapsed + // queue (which is implemented as a double buffer). + + // Check if there will be a queue overflow. + if (++m_ticks_elapsed_q_write_ind == CONTEXT_QUEUE_SIZE_MAX) + { + // There will be a queue overflow. Hence the write index should point to the start + // of the queue. + m_ticks_elapsed_q_write_ind = 0; + } + } + + // Queue the ticks expired. + m_ticks_elapsed[m_ticks_elapsed_q_write_ind] = ticks_expired; + + timer_list_handler_sched(); + } +} + + +/**@brief Function for acquiring the number of ticks elapsed. + * + * @param[out] p_ticks_elapsed Number of ticks elapsed. + * + * @return TRUE if elapsed ticks was read from queue, FALSE otherwise. + */ +static bool elapsed_ticks_acquire(uint32_t * p_ticks_elapsed) +{ + // Pick the elapsed value from queue. + if (m_ticks_elapsed_q_read_ind != m_ticks_elapsed_q_write_ind) + { + // Dequeue elapsed value. + m_ticks_elapsed_q_read_ind++; + if (m_ticks_elapsed_q_read_ind == CONTEXT_QUEUE_SIZE_MAX) + { + m_ticks_elapsed_q_read_ind = 0; + } + + *p_ticks_elapsed = m_ticks_elapsed[m_ticks_elapsed_q_read_ind]; + + m_ticks_latest += *p_ticks_elapsed; + m_ticks_latest &= MAX_RTC_COUNTER_VAL; + + return true; + } + else + { + // No elapsed value in queue. + *p_ticks_elapsed = 0; + return false; + } +} + + +/**@brief Function for handling the timer list deletions. + * + * @return TRUE if Capture Compare register must be updated, FALSE otherwise. + */ +static bool list_deletions_handler(void) +{ + timer_node_t * p_timer_old_head; + uint8_t user_id; + + // Remember the old head, so as to decide if new compare needs to be set. + p_timer_old_head = mp_timer_id_head; + + user_id = m_user_array_size; + while (user_id--) + { + timer_user_t * p_user = &mp_users[user_id]; + uint8_t user_ops_first = p_user->first; + + while (user_ops_first != p_user->last) + { + timer_user_op_t * p_user_op = &p_user->p_user_op_queue[user_ops_first]; + + // Traverse to next operation in queue. + user_ops_first++; + if (user_ops_first == p_user->user_op_queue_size) + { + user_ops_first = 0; + } + + switch (p_user_op->op_type) + { + case TIMER_USER_OP_TYPE_STOP: + // Delete node if timer is running. + timer_list_remove(p_user_op->p_node); + break; + + case TIMER_USER_OP_TYPE_STOP_ALL: + // Delete list of running timers, and mark all timers as not running. + while (mp_timer_id_head != NULL) + { + timer_node_t * p_head = mp_timer_id_head; + + p_head->is_running = false; + mp_timer_id_head = p_head->next; + } + break; + + default: + // No implementation needed. + break; + } + } + } + + // Detect change in head of the list. + return (mp_timer_id_head != p_timer_old_head); +} + + +/**@brief Function for updating the timer list for expired timers. + * + * @param[in] ticks_elapsed Number of elapsed ticks. + * @param[in] ticks_previous Previous known value of the RTC counter. + * @param[out] p_restart_list_head List of repeating timers to be restarted. + */ +static void expired_timers_handler(uint32_t ticks_elapsed, + uint32_t ticks_previous, + timer_node_t ** p_restart_list_head) +{ + uint32_t ticks_expired = 0; + + while (mp_timer_id_head != NULL) + { + timer_node_t * p_timer; + timer_node_t * p_timer_expired; + + // Auto variable for current timer node. + p_timer = mp_timer_id_head; + + // Do nothing if timer did not expire + if (ticks_elapsed < p_timer->ticks_to_expire) + { + p_timer->ticks_to_expire -= ticks_elapsed; + break; + } + + // Decrement ticks_elapsed and collect expired ticks. + ticks_elapsed -= p_timer->ticks_to_expire; + ticks_expired += p_timer->ticks_to_expire; + + // Timer expired, set ticks_to_expire zero. + p_timer->ticks_to_expire = 0; + + // Remove the expired timer from head. + p_timer_expired = mp_timer_id_head; + mp_timer_id_head = p_timer->next; + + // Timer will be restarted if periodic. + if (p_timer->ticks_periodic_interval != 0) + { + p_timer->ticks_at_start = (ticks_previous + ticks_expired) & MAX_RTC_COUNTER_VAL; + p_timer->ticks_first_interval = p_timer->ticks_periodic_interval; + p_timer->next = *p_restart_list_head; + *p_restart_list_head = p_timer_expired; + } + } +} + + +/**@brief Function for handling timer list insertions. + * + * @param[in] p_restart_list_head List of repeating timers to be restarted. + * + * @return TRUE if Capture Compare register must be updated, FALSE otherwise. + */ +static bool list_insertions_handler(timer_node_t * p_restart_list_head) +{ + timer_node_t * p_timer_id_old_head; + uint8_t user_id; + + // Remember the old head, so as to decide if new compare needs to be set. + p_timer_id_old_head = mp_timer_id_head; + + user_id = m_user_array_size; + while (user_id--) + { + timer_user_t * p_user = &mp_users[user_id]; + + // Handle insertions of timers. + while ((p_restart_list_head != NULL) || (p_user->first != p_user->last)) + { + timer_node_t * p_timer; + + if (p_restart_list_head != NULL) + { + p_timer = p_restart_list_head; + p_restart_list_head = p_timer->next; + } + else + { + timer_user_op_t * p_user_op = &p_user->p_user_op_queue[p_user->first]; + + p_user->first++; + if (p_user->first == p_user->user_op_queue_size) + { + p_user->first = 0; + } + + p_timer = p_user_op->p_node; + + if ((p_user_op->op_type != TIMER_USER_OP_TYPE_START) || p_timer->is_running) + { + continue; + } + + p_timer->ticks_at_start = p_user_op->params.start.ticks_at_start; + p_timer->ticks_first_interval = p_user_op->params.start.ticks_first_interval; + p_timer->ticks_periodic_interval = p_user_op->params.start.ticks_periodic_interval; + p_timer->p_context = p_user_op->params.start.p_context; + + if (m_rtc1_reset) + { + p_timer->ticks_at_start = 0; + } + } + + // Prepare the node to be inserted. + if ( + ((p_timer->ticks_at_start - m_ticks_latest) & MAX_RTC_COUNTER_VAL) + < + (MAX_RTC_COUNTER_VAL / 2) + ) + { + p_timer->ticks_to_expire = ticks_diff_get(p_timer->ticks_at_start, m_ticks_latest) + + p_timer->ticks_first_interval; + } + else + { + uint32_t delta_current_start; + + delta_current_start = ticks_diff_get(m_ticks_latest, p_timer->ticks_at_start); + if (p_timer->ticks_first_interval > delta_current_start) + { + p_timer->ticks_to_expire = p_timer->ticks_first_interval - delta_current_start; + } + else + { + p_timer->ticks_to_expire = 0; + } + } + + p_timer->ticks_at_start = 0; + p_timer->ticks_first_interval = 0; + p_timer->is_running = true; + p_timer->next = NULL; + + // Insert into list + timer_list_insert(p_timer); + } + } + + return (mp_timer_id_head != p_timer_id_old_head); +} + + +/**@brief Function for updating the Capture Compare register. + */ +static void compare_reg_update(timer_node_t * p_timer_id_head_old) +{ + // Setup the timeout for timers on the head of the list + if (mp_timer_id_head != NULL) + { + uint32_t ticks_to_expire = mp_timer_id_head->ticks_to_expire; + uint32_t pre_counter_val = rtc1_counter_get(); + uint32_t cc = m_ticks_latest; + uint32_t ticks_elapsed = ticks_diff_get(pre_counter_val, cc) + RTC_COMPARE_OFFSET_MIN; + + if (!m_rtc1_running) + { + // No timers were already running, start RTC + rtc1_start(); + } + + cc += (ticks_elapsed < ticks_to_expire) ? ticks_to_expire : ticks_elapsed; + cc &= MAX_RTC_COUNTER_VAL; + + rtc1_compare0_set(cc); + + uint32_t post_counter_val = rtc1_counter_get(); + + if ( + (ticks_diff_get(post_counter_val, pre_counter_val) + RTC_COMPARE_OFFSET_MIN) + > + ticks_diff_get(cc, pre_counter_val) + ) + { + // When this happens the COMPARE event may not be triggered by the RTC. + // The nRF51 Series User Specification states that if the COUNTER value is N + // (i.e post_counter_val = N), writing N or N+1 to a CC register may not trigger a + // COMPARE event. Hence the RTC interrupt is forcefully pended by calling the following + // function. + rtc1_compare0_set(rtc1_counter_get()); // this should prevent CC to fire again in the background while the code is in RTC-ISR + nrf_delay_us(MAX_RTC_TASKS_DELAY); + timer_timeouts_check_sched(); + } + } + else + { + // No timers are running, stop RTC + rtc1_stop(); + } +} + + +/**@brief Function for handling changes to the timer list. + */ +static void timer_list_handler(void) +{ + timer_node_t * p_restart_list_head = NULL; + + uint32_t ticks_elapsed; + uint32_t ticks_previous; + bool ticks_have_elapsed; + bool compare_update; + timer_node_t * p_timer_id_head_old; + +#ifdef APP_TIMER_WITH_PROFILER + { + unsigned int i; + + for (i = 0; i < APP_TIMER_INT_LEVELS; i++) + { + timer_user_t *p_user = &mp_users[i]; + uint8_t size = p_user->user_op_queue_size; + uint8_t first = p_user->first; + uint8_t last = p_user->last; + uint8_t utilization = (first <= last) ? (last - first) : (size + 1 - first + last); + + if (utilization > m_max_user_op_queue_utilization) + { + m_max_user_op_queue_utilization = utilization; + } + } + } +#endif + + // Back up the previous known tick and previous list head + ticks_previous = m_ticks_latest; + p_timer_id_head_old = mp_timer_id_head; + + // Get number of elapsed ticks + ticks_have_elapsed = elapsed_ticks_acquire(&ticks_elapsed); + + // Handle list deletions + compare_update = list_deletions_handler(); + + // Handle expired timers + if (ticks_have_elapsed) + { + expired_timers_handler(ticks_elapsed, ticks_previous, &p_restart_list_head); + compare_update = true; + } + + // Handle list insertions + if (list_insertions_handler(p_restart_list_head)) + { + compare_update = true; + } + + // Update compare register if necessary + if (compare_update) + { + compare_reg_update(p_timer_id_head_old); + } + m_rtc1_reset = false; +} + + +/**@brief Function for enqueueing a new operations queue entry. + * + * @param[in] p_user User that the entry is to be enqueued for. + * @param[in] last_index Index of the next last index to be enqueued. + */ +static void user_op_enque(timer_user_t * p_user, uint8_t last_index) +{ + p_user->last = last_index; +} + + +/**@brief Function for allocating a new operations queue entry. + * + * @param[in] p_user User that the entry is to be allocated for. + * @param[out] p_last_index Index of the next last index to be enqueued. + * + * @return Pointer to allocated queue entry, or NULL if queue is full. + */ +static timer_user_op_t * user_op_alloc(timer_user_t * p_user, uint8_t * p_last_index) +{ + uint8_t last; + timer_user_op_t * p_user_op; + + last = p_user->last + 1; + if (last == p_user->user_op_queue_size) + { + // Overflow case. + last = 0; + } + if (last == p_user->first) + { + // Queue is full. + return NULL; + } + + *p_last_index = last; + p_user_op = &p_user->p_user_op_queue[p_user->last]; + + return p_user_op; +} + + +/**@brief Function for scheduling a Timer Start operation. + * + * @param[in] user_id Id of user calling this function. + * @param[in] timer_id Id of timer to start. + * @param[in] timeout_initial Time (in ticks) to first timer expiry. + * @param[in] timeout_periodic Time (in ticks) between periodic expiries. + * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when + * the timer expires. + * @return NRF_SUCCESS on success, otherwise an error code. + */ +static uint32_t timer_start_op_schedule(timer_user_id_t user_id, + timer_node_t * p_node, + uint32_t timeout_initial, + uint32_t timeout_periodic, + void * p_context) +{ + uint8_t last_index; + + timer_user_op_t * p_user_op = user_op_alloc(&mp_users[user_id], &last_index); + if (p_user_op == NULL) + { + return NRF_ERROR_NO_MEM; + } + + p_user_op->op_type = TIMER_USER_OP_TYPE_START; + p_user_op->p_node = p_node; + p_user_op->params.start.ticks_at_start = rtc1_counter_get(); + p_user_op->params.start.ticks_first_interval = timeout_initial; + p_user_op->params.start.ticks_periodic_interval = timeout_periodic; + p_user_op->params.start.p_context = p_context; + + user_op_enque(&mp_users[user_id], last_index); + + timer_list_handler_sched(); + + return NRF_SUCCESS; +} + + +/**@brief Function for scheduling a Timer Stop operation. + * + * @param[in] user_id Id of user calling this function. + * @param[in] timer_id Id of timer to stop. + * + * @return NRF_SUCCESS on successful scheduling a timer stop operation. NRF_ERROR_NO_MEM when there + * is no memory left to schedule the timer stop operation. + */ +static uint32_t timer_stop_op_schedule(timer_user_id_t user_id, timer_node_t * p_node) +{ + uint8_t last_index; + + timer_user_op_t * p_user_op = user_op_alloc(&mp_users[user_id], &last_index); + if (p_user_op == NULL) + { + return NRF_ERROR_NO_MEM; + } + + p_user_op->op_type = TIMER_USER_OP_TYPE_STOP; + p_user_op->p_node = p_node; + + user_op_enque(&mp_users[user_id], last_index); + + timer_list_handler_sched(); + + return NRF_SUCCESS; +} + + +/**@brief Function for scheduling a Timer Stop All operation. + * + * @param[in] user_id Id of user calling this function. + */ +static uint32_t timer_stop_all_op_schedule(timer_user_id_t user_id) +{ + uint8_t last_index; + + timer_user_op_t * p_user_op = user_op_alloc(&mp_users[user_id], &last_index); + if (p_user_op == NULL) + { + return NRF_ERROR_NO_MEM; + } + + p_user_op->op_type = TIMER_USER_OP_TYPE_STOP_ALL; + p_user_op->p_node = NULL; + + user_op_enque(&mp_users[user_id], last_index); + + timer_list_handler_sched(); + + return NRF_SUCCESS; +} + + +/**@brief Function for handling the RTC1 interrupt. + * + * @details Checks for timeouts, and executes timeout handlers for expired timers. + */ +void RTC1_IRQHandler(void) +{ + // Clear all events (also unexpected ones) + NRF_RTC1->EVENTS_COMPARE[0] = 0; + NRF_RTC1->EVENTS_COMPARE[1] = 0; + NRF_RTC1->EVENTS_COMPARE[2] = 0; + NRF_RTC1->EVENTS_COMPARE[3] = 0; + NRF_RTC1->EVENTS_TICK = 0; + NRF_RTC1->EVENTS_OVRFLW = 0; + + // Check for expired timers + timer_timeouts_check(); +} + + +/**@brief Function for handling the SWI interrupt. + * + * @details Performs all updates to the timer list. + */ +void SWI_IRQHandler(void) +{ + timer_list_handler(); +} + + +uint32_t app_timer_init(uint32_t prescaler, + uint8_t op_queues_size, + void * p_buffer, + app_timer_evt_schedule_func_t evt_schedule_func) +{ + int i; + + // Check that buffer is correctly aligned + if (!is_word_aligned(p_buffer)) + { + return NRF_ERROR_INVALID_PARAM; + } + // Check for NULL buffer + if (p_buffer == NULL) + { + mp_users = NULL; + return NRF_ERROR_INVALID_PARAM; + } + + // Stop RTC to prevent any running timers from expiring (in case of reinitialization) + rtc1_stop(); + + m_evt_schedule_func = evt_schedule_func; + + // Initialize users array + m_user_array_size = APP_TIMER_INT_LEVELS; + mp_users = p_buffer; + + // Skip user array + p_buffer = &((uint8_t *)p_buffer)[APP_TIMER_INT_LEVELS * sizeof(timer_user_t)]; + + // Initialize operation queues + for (i = 0; i < APP_TIMER_INT_LEVELS; i++) + { + timer_user_t * p_user = &mp_users[i]; + + p_user->first = 0; + p_user->last = 0; + p_user->user_op_queue_size = op_queues_size; + p_user->p_user_op_queue = p_buffer; + + // Skip operation queue + p_buffer = &((uint8_t *)p_buffer)[op_queues_size * sizeof(timer_user_op_t)]; + } + + mp_timer_id_head = NULL; + m_ticks_elapsed_q_read_ind = 0; + m_ticks_elapsed_q_write_ind = 0; + +#ifdef APP_TIMER_WITH_PROFILER + m_max_user_op_queue_utilization = 0; +#endif + + NVIC_ClearPendingIRQ(SWI_IRQn); + NVIC_SetPriority(SWI_IRQn, SWI_IRQ_PRI); + NVIC_EnableIRQ(SWI_IRQn); + + rtc1_init(prescaler); + + m_ticks_latest = rtc1_counter_get(); + + return NRF_SUCCESS; +} + + +uint32_t app_timer_create(app_timer_id_t const * p_timer_id, + app_timer_mode_t mode, + app_timer_timeout_handler_t timeout_handler) +{ + // Check state and parameters + VERIFY_MODULE_INITIALIZED(); + + if (timeout_handler == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + if (p_timer_id == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + if (((timer_node_t*)*p_timer_id)->is_running) + { + return NRF_ERROR_INVALID_STATE; + } + + timer_node_t * p_node = (timer_node_t *)*p_timer_id; + p_node->is_running = false; + p_node->mode = mode; + p_node->p_timeout_handler = timeout_handler; + return NRF_SUCCESS; +} + + +/**@brief Function for creating a timer user id from the current interrupt level. + * + * @return Timer user id. +*/ +static timer_user_id_t user_id_get(void) +{ + timer_user_id_t ret; + + STATIC_ASSERT(APP_TIMER_INT_LEVELS == 3); + + switch (current_int_priority_get()) + { + case APP_IRQ_PRIORITY_HIGH: + ret = APP_HIGH_USER_ID; + break; + + case APP_IRQ_PRIORITY_LOW: + ret = APP_LOW_USER_ID; + break; + + default: + ret = THREAD_MODE_USER_ID; + break; + } + + return ret; +} + + +uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context) +{ + uint32_t timeout_periodic; + timer_node_t * p_node = (timer_node_t*)timer_id; + + // Check state and parameters + VERIFY_MODULE_INITIALIZED(); + + if (timer_id == 0) + { + return NRF_ERROR_INVALID_STATE; + } + if (timeout_ticks < APP_TIMER_MIN_TIMEOUT_TICKS) + { + return NRF_ERROR_INVALID_PARAM; + } + if (p_node->p_timeout_handler == NULL) + { + return NRF_ERROR_INVALID_STATE; + } + + // Schedule timer start operation + timeout_periodic = (p_node->mode == APP_TIMER_MODE_REPEATED) ? timeout_ticks : 0; + + return timer_start_op_schedule(user_id_get(), + p_node, + timeout_ticks, + timeout_periodic, + p_context); +} + + +uint32_t app_timer_stop(app_timer_id_t timer_id) +{ + timer_node_t * p_node = (timer_node_t*)timer_id; + // Check state and parameters + VERIFY_MODULE_INITIALIZED(); + + if ((timer_id == NULL) || (p_node->p_timeout_handler == NULL)) + { + return NRF_ERROR_INVALID_STATE; + } + + p_node->is_running = false; + // Schedule timer stop operation + return timer_stop_op_schedule(user_id_get(), p_node); +} + + +uint32_t app_timer_stop_all(void) +{ + // Check state + VERIFY_MODULE_INITIALIZED(); + + return timer_stop_all_op_schedule(user_id_get()); +} + + +uint32_t app_timer_cnt_get(uint32_t * p_ticks) +{ + *p_ticks = rtc1_counter_get(); + return NRF_SUCCESS; +} + + +uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to, + uint32_t ticks_from, + uint32_t * p_ticks_diff) +{ + *p_ticks_diff = ticks_diff_get(ticks_to, ticks_from); + return NRF_SUCCESS; +} + +#ifdef APP_TIMER_WITH_PROFILER +uint8_t app_timer_op_queue_utilization_get(void) +{ + return m_max_user_op_queue_utilization; +} +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.h new file mode 100644 index 0000000..ca46b40 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer.h @@ -0,0 +1,287 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup app_timer Application Timer + * @{ + * @ingroup app_common + * + * @brief Application timer functionality. + * + * @details This module enables the application to create multiple timer instances based on the RTC1 + * peripheral. Checking for time-outs and invokation of user time-out handlers is performed + * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0). + * Both interrupt handlers are running in APP_LOW priority level. + * + * @details When calling app_timer_start() or app_timer_stop(), the timer operation is just queued, + * and the software interrupt is triggered. The actual timer start/stop operation is + * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW, + * if the application code calling the timer function is running in APP_LOW or APP_HIGH, + * the timer operation will not be performed until the application handler has returned. + * This will be the case, for example, when stopping a timer from a time-out handler when not using + * the scheduler. + * + * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the + * @ref app_scheduler should be used or not. Even if the scheduler is + * not used, app_timer.h will include app_scheduler.h, so when + * compiling, app_scheduler.h must be available in one of the compiler include paths. + */ + +#ifndef APP_TIMER_H__ +#define APP_TIMER_H__ + +#include +#include +#include +#include "app_error.h" +#include "app_util.h" +#include "compiler_abstraction.h" + +#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */ +#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */ + +#define APP_TIMER_NODE_SIZE 32 /**< Size of app_timer.timer_node_t (used to allocate data). */ +#define APP_TIMER_USER_OP_SIZE 24 /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */ +#define APP_TIMER_USER_SIZE 8 /**< Size of app_timer.timer_user_t (only for use inside APP_TIMER_BUF_SIZE()). */ +#define APP_TIMER_INT_LEVELS 3 /**< Number of interrupt levels from where timer operations may be initiated (only for use inside APP_TIMER_BUF_SIZE()). */ + +/**@brief Compute number of bytes required to hold the application timer data structures. + * + * @param[in] OP_QUEUE_SIZE Size of queues holding timer operations that are pending execution. + * Note that due to the queue implementation, this size must be one more + * than the size that is actually needed. + * + * @return Required application timer buffer size (in bytes). + */ +#define APP_TIMER_BUF_SIZE(OP_QUEUE_SIZE) \ + ( \ + ( \ + APP_TIMER_INT_LEVELS \ + * \ + (APP_TIMER_USER_SIZE + ((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE) \ + ) \ + ) + +/**@brief Convert milliseconds to timer ticks. + * + * This macro uses 64-bit integer arithmetic, but as long as the macro parameters are + * constants (i.e. defines), the computation will be done by the preprocessor. + * + * When using this macro, ensure that the + * values provided as input result in an output value that is supported by the + * @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the + * maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768. + * This will result in a ticks value as 5. Any higher value for PRESCALER will result in a + * ticks value that is not supported by this module. + * + * @param[in] MS Milliseconds. + * @param[in] PRESCALER Value of the RTC1 PRESCALER register (must be the same value that was + * passed to APP_TIMER_INIT()). + * + * @return Number of timer ticks. + */ +#define APP_TIMER_TICKS(MS, PRESCALER)\ + ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000)) + +typedef struct app_timer_t { uint32_t data[CEIL_DIV(APP_TIMER_NODE_SIZE, sizeof(uint32_t))]; } app_timer_t; + +/**@brief Timer ID type. + * Never declare a variable of this type, but use the macro @ref APP_TIMER_DEF instead.*/ +typedef app_timer_t * app_timer_id_t; + +/** + * @brief Create a timer identifier and statically allocate memory for the timer. + * + * @param timer_id Name of the timer identifier variable that will be used to control the timer. + */ +#define APP_TIMER_DEF(timer_id) \ + static app_timer_t timer_id##_data = { {0} }; \ + static const app_timer_id_t timer_id = &timer_id##_data + + +/**@brief Application time-out handler type. */ +typedef void (*app_timer_timeout_handler_t)(void * p_context); + +/**@brief Type of function for passing events from the timer module to the scheduler. */ +typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler, + void * p_context); + +/**@brief Timer modes. */ +typedef enum +{ + APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */ + APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */ +} app_timer_mode_t; + +/**@brief Initialize the application timer module. + * + * @details This macro handles dimensioning and allocation of the memory buffer required by the timer, + * making sure that the buffer is correctly aligned. It will also connect the timer module + * to the scheduler (if specified). + * + * @note This module assumes that the LFCLK is already running. If it is not, the module will + * be non-functional, since the RTC will not run. If you do not use a SoftDevice, you + * must start the LFCLK manually. See the rtc_example's lfclk_config() function + * for an example of how to do this. If you use a SoftDevice, the LFCLK is started on + * SoftDevice init. + * + * + * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the + * timer tick rate. Set to 0 for no prescaling. + * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution. + * @param[in] SCHEDULER_FUNC Pointer to scheduler event handler + * + * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it + * several times as long as it is from the same location, for example, to do a re-initialization). + */ +/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */ +#define APP_TIMER_INIT(PRESCALER, OP_QUEUES_SIZE, SCHEDULER_FUNC) \ + do \ + { \ + static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE((OP_QUEUES_SIZE) + 1), \ + sizeof(uint32_t))]; \ + uint32_t ERR_CODE = app_timer_init((PRESCALER), \ + (OP_QUEUES_SIZE) + 1, \ + APP_TIMER_BUF, \ + SCHEDULER_FUNC); \ + APP_ERROR_CHECK(ERR_CODE); \ + } while (0) + + + +/**@brief Function for initializing the timer module. + * + * Normally, initialization should be done using the APP_TIMER_INIT() macro, because that macro will both + * allocate the buffers needed by the timer module (including aligning the buffers correctly) + * and take care of connecting the timer module to the scheduler (if specified). + * + * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling. + * @param[in] op_queues_size Size of queues holding timer operations that are pending + * execution. Note that due to the queue implementation, this size must + * be one more than the size that is actually needed. + * @param[in] p_buffer Pointer to memory buffer for internal use in the app_timer + * module. The size of the buffer can be computed using the + * APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a + * 4 byte boundary. + * @param[in] evt_schedule_func Function for passing time-out events to the scheduler. Point to + * app_timer_evt_schedule() to connect to the scheduler. Set to NULL + * to make the timer module call the time-out handler directly from + * the timer interrupt handler. + * + * @retval NRF_SUCCESS If the module was initialized successfully. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid (buffer not aligned to a 4 byte + * boundary or NULL). + */ +uint32_t app_timer_init(uint32_t prescaler, + uint8_t op_queues_size, + void * p_buffer, + app_timer_evt_schedule_func_t evt_schedule_func); + +/**@brief Function for creating a timer instance. + * + * @param[in] p_timer_id Pointer to timer identifier. + * @param[in] mode Timer mode. + * @param[in] timeout_handler Function to be executed when the timer expires. + * + * @retval NRF_SUCCESS If the timer was successfully created. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or + * the timer is running. + * + * @note This function does the timer allocation in the caller's context. It is also not protected + * by a critical region. Therefore care must be taken not to call it from several interrupt + * levels simultaneously. + * @note The function can be called again on the timer instance and will re-initialize the instance if + * the timer is not running. + * @attention The FreeRTOS and RTX app_timer implementation does not allow app_timer_create to + * be called on the previously initialized instance. + */ +uint32_t app_timer_create(app_timer_id_t const * p_timer_id, + app_timer_mode_t mode, + app_timer_timeout_handler_t timeout_handler); + +/**@brief Function for starting a timer. + * + * @param[in] timer_id Timer identifier. + * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to time-out event + * (minimum 5 ticks). + * @param[in] p_context General purpose pointer. Will be passed to the time-out handler when + * the timer expires. + * + * @retval NRF_SUCCESS If the timer was successfully started. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or the timer + * has not been created. + * @retval NRF_ERROR_NO_MEM If the timer operations queue was full. + * + * @note The minimum timeout_ticks value is 5. + * @note For multiple active timers, time-outs occurring in close proximity to each other (in the + * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks. + * @note When calling this method on a timer that is already running, the second start operation + * is ignored. + */ +uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context); + +/**@brief Function for stopping the specified timer. + * + * @param[in] timer_id Timer identifier. + * + * @retval NRF_SUCCESS If the timer was successfully stopped. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or the timer + * has not been created. + * @retval NRF_ERROR_NO_MEM If the timer operations queue was full. + */ +uint32_t app_timer_stop(app_timer_id_t timer_id); + +/**@brief Function for stopping all running timers. + * + * @retval NRF_SUCCESS If all timers were successfully stopped. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized. + * @retval NRF_ERROR_NO_MEM If the timer operations queue was full. + */ +uint32_t app_timer_stop_all(void); + +/**@brief Function for returning the current value of the RTC1 counter. + * + * @param[out] p_ticks Current value of the RTC1 counter. + * + * @retval NRF_SUCCESS If the counter was successfully read. + */ +uint32_t app_timer_cnt_get(uint32_t * p_ticks); + +/**@brief Function for computing the difference between two RTC1 counter values. + * + * @param[in] ticks_to Value returned by app_timer_cnt_get(). + * @param[in] ticks_from Value returned by app_timer_cnt_get(). + * @param[out] p_ticks_diff Number of ticks from ticks_from to ticks_to. + * + * @retval NRF_SUCCESS If the counter difference was successfully computed. + */ +uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to, + uint32_t ticks_from, + uint32_t * p_ticks_diff); + +#ifdef APP_TIMER_WITH_PROFILER +/**@brief Function for getting the maximum observed operation queue utilization. + * + * Function for tuning the module and determining OP_QUEUE_SIZE value and thus module RAM usage. + * + * @return Maximum number of events in queue observed so far. + */ +uint16_t app_timer_op_queue_utilization_get(void); +#endif + +#endif // APP_TIMER_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer_appsh.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer_appsh.c new file mode 100644 index 0000000..9755d78 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer_appsh.c @@ -0,0 +1,34 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_timer_appsh.h" +#include "app_scheduler.h" + +static void app_timer_evt_get(void * p_event_data, uint16_t event_size) +{ + app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data; + + APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t)); + p_timer_event->timeout_handler(p_timer_event->p_context); +} + +uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler, + void * p_context) +{ + app_timer_event_t timer_event; + + timer_event.timeout_handler = timeout_handler; + timer_event.p_context = p_context; + + return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get); +} + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer_appsh.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer_appsh.h new file mode 100644 index 0000000..f92629b --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/timer/app_timer_appsh.h @@ -0,0 +1,44 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + + #ifndef APP_TIMER_APPSH_H + #define APP_TIMER_APPSH_H + +#include "app_timer.h" + +#define APP_TIMER_SCHED_EVT_SIZE sizeof(app_timer_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */ + +/**@brief Macro for initializing the application timer module to use with app_scheduler. + * + * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the + * timer tick rate. Set to 0 for no prescaling. + * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution. + * @param[in] USE_SCHEDULER TRUE if the application is using the app_scheduler, + * FALSE otherwise. + * + * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it + * several times as long as it is from the same location, e.g. to do a reinitialization). + */ +#define APP_TIMER_APPSH_INIT(PRESCALER, OP_QUEUES_SIZE, USE_SCHEDULER) \ + APP_TIMER_INIT(PRESCALER, OP_QUEUES_SIZE, \ + (USE_SCHEDULER) ? app_timer_evt_schedule : NULL) + +typedef struct +{ + app_timer_timeout_handler_t timeout_handler; + void * p_context; +} app_timer_event_t; + +uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler, + void * p_context); +#endif // APP_TIMER_APPSH_H + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/trace/app_trace.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/trace/app_trace.c new file mode 100644 index 0000000..2f510f8 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/trace/app_trace.c @@ -0,0 +1,43 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include +#include +#include +#include + + +#ifdef ENABLE_DEBUG_LOG_SUPPORT +#include "app_trace.h" +#include "nrf_log.h" + +void app_trace_init(void) +{ + (void)NRF_LOG_INIT(); +} + +void app_trace_dump(uint8_t * p_buffer, uint32_t len) +{ + app_trace_log("\r\n"); + for (uint32_t index = 0; index < len; index++) + { + app_trace_log("0x%02X ", p_buffer[index]); + } + app_trace_log("\r\n"); +} + +#endif // ENABLE_DEBUG_LOG_SUPPORT + +/** + *@} + **/ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/trace/app_trace.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/trace/app_trace.h new file mode 100644 index 0000000..c746c63 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/trace/app_trace.h @@ -0,0 +1,56 @@ +#ifndef __DEBUG_H_ +#define __DEBUG_H_ + +#include +#include + +/** + * @defgroup app_trace Debug Logger + * @ingroup app_common + * @{ + * @brief Enables debug logs/ trace over UART. + * @details Enables debug logs/ trace over UART. Tracing is enabled only if + * ENABLE_DEBUG_LOG_SUPPORT is defined in the project. + */ +#ifdef ENABLE_DEBUG_LOG_SUPPORT +#include "nrf_log.h" +/** + * @brief Module Initialization. + * + * @details Initializes the module to use UART as trace output. + * + * @warning This function will configure UART using default board configuration. + * Do not call this function if UART is configured from a higher level in the application. + */ +void app_trace_init(void); + +/** + * @brief Log debug messages. + * + * @details This API logs messages over UART. The module must be initialized before using this API. + * + * @note Though this is currently a macro, it should be used used and treated as function. + */ +#define app_trace_log NRF_LOG_PRINTF + +/** + * @brief Dump auxiliary byte buffer to the debug trace. + * + * @details This API logs messages over UART. The module must be initialized before using this API. + * + * @param[in] p_buffer Buffer to be dumped on the debug trace. + * @param[in] len Size of the buffer. + */ +void app_trace_dump(uint8_t * p_buffer, uint32_t len); + +#else // ENABLE_DEBUG_LOG_SUPPORT + +#define app_trace_init(...) +#define app_trace_log(...) +#define app_trace_dump(...) + +#endif // ENABLE_DEBUG_LOG_SUPPORT + +/** @} */ + +#endif //__DEBUG_H_ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.c new file mode 100644 index 0000000..944ff21 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.c @@ -0,0 +1,132 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_uart.h" +#include "nrf_drv_uart.h" +#include "nrf_assert.h" +#include "sdk_common.h" + +static uint8_t tx_buffer[1]; +static uint8_t rx_buffer[1]; +static volatile bool rx_done; +static app_uart_event_handler_t m_event_handler; /**< Event handler function. */ + +void uart_event_handler(nrf_drv_uart_event_t * p_event, void* p_context) +{ + if (p_event->type == NRF_DRV_UART_EVT_RX_DONE) + { + app_uart_evt_t app_uart_event; + app_uart_event.evt_type = APP_UART_DATA; + app_uart_event.data.value = p_event->data.rxtx.p_data[0]; + (void)nrf_drv_uart_rx(rx_buffer,1); + rx_done = true; + m_event_handler(&app_uart_event); + } + else if (p_event->type == NRF_DRV_UART_EVT_ERROR) + { + app_uart_evt_t app_uart_event; + app_uart_event.evt_type = APP_UART_COMMUNICATION_ERROR; + app_uart_event.data.error_communication = p_event->data.error.error_mask; + (void)nrf_drv_uart_rx(rx_buffer,1); + m_event_handler(&app_uart_event); + } + else if (p_event->type == NRF_DRV_UART_EVT_TX_DONE) + { + // Last byte from FIFO transmitted, notify the application. + // Notify that new data is available if this was first byte put in the buffer. + app_uart_evt_t app_uart_event; + app_uart_event.evt_type = APP_UART_TX_EMPTY; + m_event_handler(&app_uart_event); + } +} + +uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, + app_uart_buffers_t * p_buffers, + app_uart_event_handler_t event_handler, + app_irq_priority_t irq_priority) +{ + nrf_drv_uart_config_t config = NRF_DRV_UART_DEFAULT_CONFIG; + config.baudrate = (nrf_uart_baudrate_t)p_comm_params->baud_rate; + config.hwfc = (p_comm_params->flow_control == APP_UART_FLOW_CONTROL_DISABLED) ? + NRF_UART_HWFC_DISABLED : NRF_UART_HWFC_ENABLED; + config.interrupt_priority = irq_priority; + config.parity = p_comm_params->use_parity ? NRF_UART_PARITY_INCLUDED : NRF_UART_PARITY_EXCLUDED; + config.pselcts = p_comm_params->cts_pin_no; + config.pselrts = p_comm_params->rts_pin_no; + config.pselrxd = p_comm_params->rx_pin_no; + config.pseltxd = p_comm_params->tx_pin_no; + + m_event_handler = event_handler; + + rx_done = false; + + if (p_comm_params->flow_control == APP_UART_FLOW_CONTROL_LOW_POWER) + { + return NRF_ERROR_NOT_SUPPORTED; + } + + uint32_t err_code = nrf_drv_uart_init(&config, uart_event_handler); + VERIFY_SUCCESS(err_code); + +#ifdef NRF52 + if (!config.use_easy_dma) +#endif + { + nrf_drv_uart_rx_enable(); + } + return nrf_drv_uart_rx(rx_buffer,1); +} + + +uint32_t app_uart_get(uint8_t * p_byte) +{ + ASSERT(p_byte); + uint32_t err_code = NRF_SUCCESS; + if (rx_done) + { + *p_byte = rx_buffer[0]; + } + else + { + err_code = NRF_ERROR_NOT_FOUND; + } + return err_code; +} + +uint32_t app_uart_put(uint8_t byte) +{ + tx_buffer[0] = byte; + ret_code_t ret = nrf_drv_uart_tx(tx_buffer,1); + if (NRF_ERROR_BUSY == ret) + { + return NRF_ERROR_NO_MEM; + } + else if (ret != NRF_SUCCESS) + { + return NRF_ERROR_INTERNAL; + } + else + { + return NRF_SUCCESS; + } +} + +uint32_t app_uart_flush(void) +{ + return NRF_SUCCESS; +} + +uint32_t app_uart_close(void) +{ + nrf_drv_uart_uninit(); + return NRF_SUCCESS; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.h new file mode 100644 index 0000000..8988cc8 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart.h @@ -0,0 +1,227 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup app_uart UART module + * @{ + * @ingroup app_common + * + * @brief UART module interface. + */ + +#ifndef APP_UART_H__ +#define APP_UART_H__ + +#include +#include +#include "app_util_platform.h" + +#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */ + +/**@brief UART Flow Control modes for the peripheral. + */ +typedef enum +{ + APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */ + APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */ + APP_UART_FLOW_CONTROL_LOW_POWER /**< Specialized UART Hw Flow Control is used. The Low Power setting allows the \nRFXX to Power Off the UART module when CTS is in-active, and re-enabling the UART when the CTS signal becomes active. This allows the \nRFXX to safe power by only using the UART module when it is needed by the remote site. */ +} app_uart_flow_control_t; + +/**@brief UART communication structure holding configuration settings for the peripheral. + */ +typedef struct +{ + uint8_t rx_pin_no; /**< RX pin number. */ + uint8_t tx_pin_no; /**< TX pin number. */ + uint8_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */ + uint8_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */ + app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ + bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ + uint32_t baud_rate; /**< Baud rate configuration. */ +} app_uart_comm_params_t; + +/**@brief UART buffer for transmitting/receiving data. + */ +typedef struct +{ + uint8_t * rx_buf; /**< Pointer to the RX buffer. */ + uint32_t rx_buf_size; /**< Size of the RX buffer. */ + uint8_t * tx_buf; /**< Pointer to the TX buffer. */ + uint32_t tx_buf_size; /**< Size of the TX buffer. */ +} app_uart_buffers_t; + +/**@brief Enumeration which defines events used by the UART module upon data reception or error. + * + * @details The event type is used to indicate the type of additional information in the event + * @ref app_uart_evt_t. + */ +typedef enum +{ + APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */ + APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */ + APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */ + APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */ + APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */ +} app_uart_evt_type_t; + +/**@brief Struct containing events from the UART module. + * + * @details The app_uart_evt_t is used to notify the application of asynchronous events when data + * are received on the UART peripheral or in case an error occured during data reception. + */ +typedef struct +{ + app_uart_evt_type_t evt_type; /**< Type of event. */ + union + { + uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from nrf5x_bitfields.h can be used to parse the error code. See also the \nRFXX Series Reference Manual for specification. */ + uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ + uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ + } data; +} app_uart_evt_t; + +/**@brief Function for handling app_uart event callback. + * + * @details Upon an event in the app_uart module this callback function will be called to notify + * the application about the event. + * + * @param[in] p_app_uart_event Pointer to UART event. + */ +typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event); + +/**@brief Macro for safe initialization of the UART module in a single user instance when using + * a FIFO together with UART. + * + * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t + * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO). + * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO). + * @param[in] EVT_HANDLER Event handler function to be called when an event occurs in the + * UART module. + * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. + * @param[out] ERR_CODE The return value of the UART initialization function will be + * written to this parameter. + * + * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow + * control is enabled, it must only be called once. + */ +#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ + do \ + { \ + app_uart_buffers_t buffers; \ + static uint8_t rx_buf[RX_BUF_SIZE]; \ + static uint8_t tx_buf[TX_BUF_SIZE]; \ + \ + buffers.rx_buf = rx_buf; \ + buffers.rx_buf_size = sizeof (rx_buf); \ + buffers.tx_buf = tx_buf; \ + buffers.tx_buf_size = sizeof (tx_buf); \ + ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO); \ + } while (0) + +/**@brief Macro for safe initialization of the UART module in a single user instance. + * + * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t + * @param[in] EVT_HANDLER Event handler function to be called when an event occurs in the + * UART module. + * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. + * @param[out] ERR_CODE The return value of the UART initialization function will be + * written to this parameter. + * + * @note Since this macro allocates registers the module as a GPIOTE user when flow control is + * enabled, it must only be called once. + */ +#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ + do \ + { \ + ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO); \ + } while (0) + +/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART + * module are needed. + * + * + * @note Normally single initialization should be done using the APP_UART_INIT() or + * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as + * that will allocate the buffers needed by the UART module (including aligning the buffer + * correctly). + + * @param[in] p_comm_params Pin and communication parameters. + * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used. + * @param[in] error_handler Function to be called in case of an error. + * @param[in] irq_priority Interrupt priority level. + * + * @retval NRF_SUCCESS If successful initialization. + * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two. + * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer. + * + * The below errors are propagated by the UART module to the caller upon registration when Hardware + * Flow Control is enabled. When Hardware Flow Control is not used, these errors cannot occur. + * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering + * the UART module as a user. + * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when + * registering the UART module as a user. + * Or the value pointed to by *p_uart_uid is not a valid + * GPIOTE number. + * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users. + */ +uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, + app_uart_buffers_t * p_buffers, + app_uart_event_handler_t error_handler, + app_irq_priority_t irq_priority); + +/**@brief Function for getting a byte from the UART. + * + * @details This function will get the next byte from the RX buffer. If the RX buffer is empty + * an error code will be returned and the app_uart module will generate an event upon + * reception of the first byte which is added to the RX buffer. + * + * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied. + * + * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided. + * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module. + */ +uint32_t app_uart_get(uint8_t * p_byte); + +/**@brief Function for putting a byte on the UART. + * + * @details This call is non-blocking. + * + * @param[in] byte Byte to be transmitted on the UART. + * + * @retval NRF_SUCCESS If the byte was successfully put on the TX buffer for transmission. + * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer. + * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal + * is high for a long period and the buffer fills up. + * @retval NRF_ERROR_INTERNAL If UART driver reported error. + */ +uint32_t app_uart_put(uint8_t byte); + +/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used). + * This function does nothing if FIFO is not used. + * + * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed). + */ +uint32_t app_uart_flush(void); + +/**@brief Function for closing the UART module. + * + * @retval NRF_SUCCESS If successfully closed. + * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from + * the current active user. + */ +uint32_t app_uart_close(void); + + +#endif //APP_UART_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart_fifo.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart_fifo.c new file mode 100644 index 0000000..d4c1562 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/app_uart_fifo.c @@ -0,0 +1,191 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_uart.h" +#include "app_fifo.h" +#include "nrf_drv_uart.h" +#include "nrf_assert.h" +#include "sdk_common.h" + +static __INLINE uint32_t fifo_length(app_fifo_t * const fifo) +{ + uint32_t tmp = fifo->read_pos; + return fifo->write_pos - tmp; +} + +#define FIFO_LENGTH(F) fifo_length(&F) /**< Macro to calculate length of a FIFO. */ + + +static app_uart_event_handler_t m_event_handler; /**< Event handler function. */ +static uint8_t tx_buffer[1]; +static uint8_t rx_buffer[1]; + +static app_fifo_t m_rx_fifo; /**< RX FIFO buffer for storing data received on the UART until the application fetches them using app_uart_get(). */ +static app_fifo_t m_tx_fifo; /**< TX FIFO buffer for storing data to be transmitted on the UART when TXD is ready. Data is put to the buffer on using app_uart_put(). */ + +static void uart_event_handler(nrf_drv_uart_event_t * p_event, void* p_context) +{ + app_uart_evt_t app_uart_event; + + if (p_event->type == NRF_DRV_UART_EVT_RX_DONE) + { + // Write received byte to FIFO + uint32_t err_code = app_fifo_put(&m_rx_fifo, p_event->data.rxtx.p_data[0]); + if (err_code != NRF_SUCCESS) + { + app_uart_event.evt_type = APP_UART_FIFO_ERROR; + app_uart_event.data.error_code = err_code; + m_event_handler(&app_uart_event); + } + // Notify that new data is available if this was first byte put in the buffer. + else if (FIFO_LENGTH(m_rx_fifo) == 1) + { + app_uart_event.evt_type = APP_UART_DATA_READY; + m_event_handler(&app_uart_event); + } + else + { + // Do nothing, only send event if first byte was added or overflow in FIFO occurred. + } + if (FIFO_LENGTH(m_rx_fifo) <= m_rx_fifo.buf_size_mask) + { + (void)nrf_drv_uart_rx(rx_buffer, 1); + } + } + else if (p_event->type == NRF_DRV_UART_EVT_ERROR) + { + app_uart_event.evt_type = APP_UART_COMMUNICATION_ERROR; + app_uart_event.data.error_communication = p_event->data.error.error_mask; + (void)nrf_drv_uart_rx(rx_buffer, 1); + m_event_handler(&app_uart_event); + } + else if (p_event->type == NRF_DRV_UART_EVT_TX_DONE) + { + // Get next byte from FIFO. + if (app_fifo_get(&m_tx_fifo, tx_buffer) == NRF_SUCCESS) + { + (void)nrf_drv_uart_tx(tx_buffer, 1); + } + if (FIFO_LENGTH(m_tx_fifo) == 0) + { + // Last byte from FIFO transmitted, notify the application. + app_uart_event.evt_type = APP_UART_TX_EMPTY; + m_event_handler(&app_uart_event); + } + } +} + +uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, + app_uart_buffers_t * p_buffers, + app_uart_event_handler_t event_handler, + app_irq_priority_t irq_priority) +{ + uint32_t err_code; + + m_event_handler = event_handler; + + if (p_buffers == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + + // Configure buffer RX buffer. + err_code = app_fifo_init(&m_rx_fifo, p_buffers->rx_buf, p_buffers->rx_buf_size); + VERIFY_SUCCESS(err_code); + + // Configure buffer TX buffer. + err_code = app_fifo_init(&m_tx_fifo, p_buffers->tx_buf, p_buffers->tx_buf_size); + VERIFY_SUCCESS(err_code); + + nrf_drv_uart_config_t config = NRF_DRV_UART_DEFAULT_CONFIG; + config.baudrate = (nrf_uart_baudrate_t)p_comm_params->baud_rate; + config.hwfc = (p_comm_params->flow_control == APP_UART_FLOW_CONTROL_DISABLED) ? + NRF_UART_HWFC_DISABLED : NRF_UART_HWFC_ENABLED; + config.interrupt_priority = irq_priority; + config.parity = p_comm_params->use_parity ? NRF_UART_PARITY_INCLUDED : NRF_UART_PARITY_EXCLUDED; + config.pselcts = p_comm_params->cts_pin_no; + config.pselrts = p_comm_params->rts_pin_no; + config.pselrxd = p_comm_params->rx_pin_no; + config.pseltxd = p_comm_params->tx_pin_no; + + err_code = nrf_drv_uart_init(&config, uart_event_handler); + VERIFY_SUCCESS(err_code); + +#ifdef NRF52 + if (!config.use_easy_dma) +#endif + { + nrf_drv_uart_rx_enable(); + } + return nrf_drv_uart_rx(rx_buffer,1); +} + +uint32_t app_uart_flush(void) +{ + uint32_t err_code; + + err_code = app_fifo_flush(&m_rx_fifo); + VERIFY_SUCCESS(err_code); + + err_code = app_fifo_flush(&m_tx_fifo); + VERIFY_SUCCESS(err_code); + + return NRF_SUCCESS; +} + +uint32_t app_uart_get(uint8_t * p_byte) +{ + ASSERT(p_byte); + // If FIFO was full new request to receive one byte was not scheduled. Must be done here. + if (FIFO_LENGTH(m_rx_fifo) == m_rx_fifo.buf_size_mask) + { + uint32_t err_code = nrf_drv_uart_rx(rx_buffer,1); + if (err_code != NRF_SUCCESS) + { + return NRF_ERROR_NOT_FOUND; + } + } + return app_fifo_get(&m_rx_fifo, p_byte); +} + +uint32_t app_uart_put(uint8_t byte) +{ + uint32_t err_code; + + err_code = app_fifo_put(&m_tx_fifo, byte); + if (err_code == NRF_SUCCESS) + { + // The new byte has been added to FIFO. It will be picked up from there + // (in 'uart_event_handler') when all preceding bytes are transmitted. + // But if UART is not transmitting anything at the moment, we must start + // a new transmission here. + if (!nrf_drv_uart_tx_in_progress()) + { + // This operation should be almost always successful, since we've + // just added a byte to FIFO, but if some bigger delay occurred + // (some heavy interrupt handler routine has been executed) since + // that time, FIFO might be empty already. + if (app_fifo_get(&m_tx_fifo, tx_buffer) == NRF_SUCCESS) + { + err_code = nrf_drv_uart_tx(tx_buffer, 1); + } + } + } + + return err_code; +} + +uint32_t app_uart_close(void) +{ + nrf_drv_uart_uninit(); + return NRF_SUCCESS; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/retarget.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/retarget.c new file mode 100644 index 0000000..a34fa1c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/uart/retarget.c @@ -0,0 +1,101 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#if !defined(NRF_LOG_USES_RTT) || NRF_LOG_USES_RTT != 1 +#if !defined(HAS_SIMPLE_UART_RETARGET) + +#include +#include +#include "app_uart.h" +#include "nordic_common.h" +#include "nrf_error.h" + +#if !defined(__ICCARM__) +struct __FILE +{ + int handle; +}; +#endif + +FILE __stdout; +FILE __stdin; + + +#if defined(__CC_ARM) || defined(__ICCARM__) +int fgetc(FILE * p_file) +{ + uint8_t input; + while (app_uart_get(&input) == NRF_ERROR_NOT_FOUND) + { + // No implementation needed. + } + return input; +} + + +int fputc(int ch, FILE * p_file) +{ + UNUSED_PARAMETER(p_file); + + UNUSED_VARIABLE(app_uart_put((uint8_t)ch)); + return ch; +} + +#elif defined(__GNUC__) + + +int _write(int file, const char * p_char, int len) +{ + int i; + + UNUSED_PARAMETER(file); + + for (i = 0; i < len; i++) + { + UNUSED_VARIABLE(app_uart_put(*p_char++)); + } + + return len; +} + + +int _read(int file, char * p_char, int len) +{ + UNUSED_PARAMETER(file); + while (app_uart_get((uint8_t *)p_char) == NRF_ERROR_NOT_FOUND) + { + // No implementation needed. + } + + return 1; +} +#endif + +#if defined(__ICCARM__) + +__ATTRIBUTES size_t __write(int file, const unsigned char * p_char, size_t len) +{ + int i; + + UNUSED_PARAMETER(file); + + for (i = 0; i < len; i++) + { + UNUSED_VARIABLE(app_uart_put(*p_char++)); + } + + return len; +} + +#endif +#endif // !defined(HAS_SIMPLE_UART_RETARGET) +#endif // NRF_LOG_USES_RTT != 1 diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.c new file mode 100644 index 0000000..8d9aaa9 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.c @@ -0,0 +1,124 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup app_error Common application error handler + * @{ + * @ingroup app_common + * + * @brief Common application error handler. + */ + +#include "nrf.h" +#include +#include "app_error.h" +#include "nordic_common.h" +#include "sdk_errors.h" +#include "nrf_log.h" + +#ifdef DEBUG +#include "bsp.h" +#endif + + + +/**@brief Function for error handling, which is called when an error has occurred. + * + * @warning This handler is an example only and does not fit a final product. You need to analyze + * how your product is supposed to react in case of error. + * + * @param[in] error_code Error code supplied to the handler. + * @param[in] line_num Line number where the handler is called. + * @param[in] p_file_name Pointer to the file name. + */ + +/*lint -save -e14 */ +void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) +{ + error_info_t error_info = + { + .line_num = line_num, + .p_file_name = p_file_name, + .err_code = error_code, + }; + app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info)); + + UNUSED_VARIABLE(error_info); +} + +/*lint -save -e14 */ +void app_error_handler_bare(ret_code_t error_code) +{ + error_info_t error_info = + { + .line_num = 0, + .p_file_name = NULL, + .err_code = error_code, + }; + app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info)); + + UNUSED_VARIABLE(error_info); +} + + +void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info) +{ + /* static error variables - in order to prevent removal by optimizers */ + static volatile struct + { + uint32_t fault_id; + uint32_t pc; + uint32_t error_info; + assert_info_t * p_assert_info; + error_info_t * p_error_info; + ret_code_t err_code; + uint32_t line_num; + const uint8_t * p_file_name; + } m_error_data = {0}; + + // The following variable helps Keil keep the call stack visible, in addition, it can be set to + // 0 in the debugger to continue executing code after the error check. + volatile bool loop = true; + UNUSED_VARIABLE(loop); + + m_error_data.fault_id = id; + m_error_data.pc = pc; + m_error_data.error_info = info; + + switch (id) + { + case NRF_FAULT_ID_SDK_ASSERT: + m_error_data.p_assert_info = (assert_info_t *)info; + m_error_data.line_num = m_error_data.p_assert_info->line_num; + m_error_data.p_file_name = m_error_data.p_assert_info->p_file_name; + break; + + case NRF_FAULT_ID_SDK_ERROR: + m_error_data.p_error_info = (error_info_t *)info; + m_error_data.err_code = m_error_data.p_error_info->err_code; + m_error_data.line_num = m_error_data.p_error_info->line_num; + m_error_data.p_file_name = m_error_data.p_error_info->p_file_name; + break; + } + + UNUSED_VARIABLE(m_error_data); + + // If printing is disrupted, remove the irq calls, or set the loop variable to 0 in the debugger. + __disable_irq(); + + while(loop); + + __enable_irq(); +} + +/*lint -restore */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.h new file mode 100644 index 0000000..c87a6df --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error.h @@ -0,0 +1,201 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup app_error Common application error handler + * @{ + * @ingroup app_common + * + * @brief Common application error handler and macros for utilizing a common error handler. + */ + +#ifndef APP_ERROR_H__ +#define APP_ERROR_H__ + +#include +#include +#include +#include "nrf.h" +#include "sdk_errors.h" +#include "nordic_common.h" +#include "nrf_log.h" +#include "app_error_weak.h" + +#define NRF_FAULT_ID_SDK_RANGE_START 0x00004000 /**< The start of the range of error IDs defined in the SDK. */ + +/**@defgroup APP_ERROR_FAULT_IDS Fault ID types + * @{ */ +#define NRF_FAULT_ID_SDK_ERROR NRF_FAULT_ID_SDK_RANGE_START + 1 /**< An error stemming from a call to @ref APP_ERROR_CHECK or @ref APP_ERROR_CHECK_BOOL. The info parameter is a pointer to an @ref error_info_t variable. */ +#define NRF_FAULT_ID_SDK_ASSERT NRF_FAULT_ID_SDK_RANGE_START + 2 /**< An error stemming from a call to ASSERT (nrf_assert.h). The info parameter is a pointer to an @ref assert_info_t variable. */ +/**@} */ + +/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ERROR. + */ +typedef struct +{ + uint16_t line_num; /**< The line number where the error occurred. */ + uint8_t const * p_file_name; /**< The file in which the error occurred. */ + uint32_t err_code; /**< The error code representing the error that occurred. */ +} error_info_t; + +/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ASSERT. + */ +typedef struct +{ + uint16_t line_num; /**< The line number where the error occurred. */ + uint8_t const * p_file_name; /**< The file in which the error occurred. */ +} assert_info_t; + +/**@brief Function for error handling, which is called when an error has occurred. + * + * @param[in] error_code Error code supplied to the handler. + * @param[in] line_num Line number where the handler is called. + * @param[in] p_file_name Pointer to the file name. + */ +void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name); + +/**@brief Function for error handling, which is called when an error has occurred. + * + * @param[in] error_code Error code supplied to the handler. + */ +void app_error_handler_bare(ret_code_t error_code); + +/**@brief Function for saving the parameters and entering an eternal loop, for debug purposes. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if + * unavailable. + * @param[in] info Optional additional information regarding the fault. Refer to each fault + * identifier for details. + */ +void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info); + +/**@brief Function for printing all error info (using nrf_log). + * + * @details Nrf_log library must be initialized using NRF_LOG_INIT macro before calling + * this function. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if + * unavailable. + * @param[in] info Optional additional information regarding the fault. Refer to each fault + * identifier for details. + */ +static __INLINE void app_error_log(uint32_t id, uint32_t pc, uint32_t info) +{ + switch (id) + { + case NRF_FAULT_ID_SDK_ASSERT: + NRF_LOG(NRF_LOG_COLOR_RED "\n*** ASSERTION FAILED ***\n"); + if (((assert_info_t *)(info))->p_file_name) + { + NRF_LOG_PRINTF(NRF_LOG_COLOR_WHITE "Line Number: %u\n", (unsigned int) ((assert_info_t *)(info))->line_num); + NRF_LOG_PRINTF("File Name: %s\n", ((assert_info_t *)(info))->p_file_name); + } + NRF_LOG_PRINTF(NRF_LOG_COLOR_DEFAULT "\n"); + break; + + case NRF_FAULT_ID_SDK_ERROR: + NRF_LOG(NRF_LOG_COLOR_RED "\n*** APPLICATION ERROR *** \n" NRF_LOG_COLOR_WHITE); + if (((error_info_t *)(info))->p_file_name) + { + NRF_LOG_PRINTF("Line Number: %u\n", (unsigned int) ((error_info_t *)(info))->line_num); + NRF_LOG_PRINTF("File Name: %s\n", ((error_info_t *)(info))->p_file_name); + } + NRF_LOG_PRINTF("Error Code: 0x%X\n" NRF_LOG_COLOR_DEFAULT "\n", (unsigned int) ((error_info_t *)(info))->err_code); + break; + } +} + +/**@brief Function for printing all error info (using printf). + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if + * unavailable. + * @param[in] info Optional additional information regarding the fault. Refer to each fault + * identifier for details. + */ +//lint -save -e438 +static __INLINE void app_error_print(uint32_t id, uint32_t pc, uint32_t info) +{ + unsigned int tmp = id; + printf("app_error_print():\r\n"); + printf("Fault identifier: 0x%X\r\n", tmp); + printf("Program counter: 0x%X\r\n", tmp = pc); + printf("Fault information: 0x%X\r\n", tmp = info); + + switch (id) + { + case NRF_FAULT_ID_SDK_ASSERT: + printf("Line Number: %u\r\n", tmp = ((assert_info_t *)(info))->line_num); + printf("File Name: %s\r\n", ((assert_info_t *)(info))->p_file_name); + break; + + case NRF_FAULT_ID_SDK_ERROR: + printf("Line Number: %u\r\n", tmp = ((error_info_t *)(info))->line_num); + printf("File Name: %s\r\n", ((error_info_t *)(info))->p_file_name); + printf("Error Code: 0x%X\r\n", tmp = ((error_info_t *)(info))->err_code); + break; + } +} +//lint -restore + + +/**@brief Macro for calling error handler function. + * + * @param[in] ERR_CODE Error code supplied to the error handler. + */ +#ifdef DEBUG +#define APP_ERROR_HANDLER(ERR_CODE) \ + do \ + { \ + app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \ + } while (0) +#else +#define APP_ERROR_HANDLER(ERR_CODE) \ + do \ + { \ + app_error_handler_bare((ERR_CODE)); \ + } while (0) +#endif +/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. + * + * @param[in] ERR_CODE Error code supplied to the error handler. + */ +#define APP_ERROR_CHECK(ERR_CODE) \ + do \ + { \ + const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \ + if (LOCAL_ERR_CODE != NRF_SUCCESS) \ + { \ + APP_ERROR_HANDLER(LOCAL_ERR_CODE); \ + } \ + } while (0) + +/**@brief Macro for calling error handler function if supplied boolean value is false. + * + * @param[in] BOOLEAN_VALUE Boolean value to be evaluated. + */ +#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ + do \ + { \ + const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ + if (!LOCAL_BOOLEAN_VALUE) \ + { \ + APP_ERROR_HANDLER(0); \ + } \ + } while (0) + +#endif // APP_ERROR_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error_weak.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error_weak.c new file mode 100644 index 0000000..eccc0a6 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error_weak.c @@ -0,0 +1,53 @@ +/* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_error.h" + +#ifdef DEBUG +#include "bsp.h" +#endif + +/*lint -save -e14 */ + +/** + * Function is implemented as weak so that it can be overwritten by custom application error handler + * when needed. + */ +__WEAK void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info) +{ + // On assert, the system can only recover with a reset. +#ifndef DEBUG + NVIC_SystemReset(); +#else + +#ifdef BSP_DEFINES_ONLY + LEDS_ON(LEDS_MASK); +#else + UNUSED_VARIABLE(bsp_indication_set(BSP_INDICATE_FATAL_ERROR)); + // This call can be used for debug purposes during application development. + // @note CAUTION: Activating this code will write the stack to flash on an error. + // This function should NOT be used in a final product. + // It is intended STRICTLY for development/debugging purposes. + // The flash write will happen EVEN if the radio is active, thus interrupting + // any communication. + // Use with care. Uncomment the line below to use. + //ble_debug_assert_handler(error_code, line_num, p_file_name); +#endif // BSP_DEFINES_ONLY + + app_error_save_and_stop(id, pc, info); + +#endif // DEBUG +} + +/*lint -restore */ + + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error_weak.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error_weak.h new file mode 100644 index 0000000..551a431 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_error_weak.h @@ -0,0 +1,51 @@ +/* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef APP_ERROR_WEAK_H__ +#define APP_ERROR_WEAK_H__ + +/** @file + * + * @defgroup app_error Common application error handler + * @{ + * @ingroup app_common + * + * @brief Common application error handler. + */ + +/**@brief Callback function for asserts in the SoftDevice. + * + * @details A pointer to this function will be passed to the SoftDevice. This function will be + * called by the SoftDevice if certain unrecoverable errors occur within the + * application or SoftDevice. + * + * See @ref nrf_fault_handler_t for more details. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if + * unavailable. + * @param[in] info Optional additional information regarding the fault. Refer to each fault + * identifier for details. + * + * @remarks Function is implemented as weak so that it can be overwritten by custom application + * error handler when needed. + */ +#ifdef __CC_ARM + void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info); +#else +__WEAK void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info); +#endif + + +/** @} */ + +#endif // APP_ERROR_WEAK_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util.h new file mode 100644 index 0000000..774bc28 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util.h @@ -0,0 +1,493 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup app_util Utility Functions and Definitions + * @{ + * @ingroup app_common + * + * @brief Various types and definitions available to all applications. + */ + +#ifndef APP_UTIL_H__ +#define APP_UTIL_H__ + +#include +#include +#include "compiler_abstraction.h" +#include "nrf.h" + +//lint -save -e27 -e10 -e19 +#if defined ( __CC_ARM ) +extern char STACK$$Base; +extern char STACK$$Length; +#define STACK_BASE &STACK$$Base +#define STACK_TOP ((void*)((uint32_t)STACK_BASE + (uint32_t)&STACK$$Length)) +#elif defined ( __ICCARM__ ) +extern char CSTACK$$Base; +extern char CSTACK$$Length; +#define STACK_BASE &CSTACK$$Base +#define STACK_TOP ((void*)((uint32_t)STACK_BASE + (uint32_t)&CSTACK$$Length)) +#elif defined ( __GNUC__ ) +extern uint32_t __StackTop; +extern uint32_t __StackLimit; +#define STACK_BASE &__StackLimit +#define STACK_TOP &__StackTop +#endif +//lint -restore + +enum +{ + UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */ + UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */ + UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */ +}; + + +/**@brief Implementation specific macro for delayed macro expansion used in string concatenation +* +* @param[in] lhs Left hand side in concatenation +* @param[in] rhs Right hand side in concatenation +*/ +#define STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs + + +/**@brief Macro used to concatenate string using delayed macro expansion +* +* @note This macro will delay concatenation until the expressions have been resolved +* +* @param[in] lhs Left hand side in concatenation +* @param[in] rhs Right hand side in concatenation +*/ +#define STRING_CONCATENATE(lhs, rhs) STRING_CONCATENATE_IMPL(lhs, rhs) + + +// Disable lint-warnings/errors for STATIC_ASSERT +//lint --emacro(10,STATIC_ASSERT) +//lint --emacro(18,STATIC_ASSERT) +//lint --emacro(19,STATIC_ASSERT) +//lint --emacro(30,STATIC_ASSERT) +//lint --emacro(37,STATIC_ASSERT) +//lint --emacro(42,STATIC_ASSERT) +//lint --emacro(26,STATIC_ASSERT) +//lint --emacro(102,STATIC_ASSERT) +//lint --emacro(533,STATIC_ASSERT) +//lint --emacro(534,STATIC_ASSERT) +//lint --emacro(132,STATIC_ASSERT) +//lint --emacro(414,STATIC_ASSERT) +//lint --emacro(578,STATIC_ASSERT) +//lint --emacro(628,STATIC_ASSERT) +//lint --emacro(648,STATIC_ASSERT) +//lint --emacro(830,STATIC_ASSERT) + + +/**@brief Macro for doing static (i.e. compile time) assertion. +* +* @note If the EXPR isn't resolvable, then the error message won't be shown. +* +* @note The output of STATIC_ASSERT will be different across different compilers. +* +* @param[in] EXPR Constant expression to be verified. +*/ +#if defined ( __COUNTER__ ) + +#define STATIC_ASSERT(EXPR) \ + ;enum { STRING_CONCATENATE(static_assert_, __COUNTER__) = 1/(!!(EXPR)) } + +#else + +#define STATIC_ASSERT(EXPR) \ + ;enum { STRING_CONCATENATE(assert_line_, __LINE__) = 1/(!!(EXPR)) } + +#endif + + +/**@brief Implementation details for NUM_VAR_ARGS */ +#define NUM_VA_ARGS_IMPL( \ + _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, N, ...) N + + +/**@brief Macro to get the number of arguments in a call variadic macro call + * + * param[in] ... List of arguments + * + * @retval Number of variadic arguments in the argument list + */ +#define NUM_VA_ARGS(...) NUM_VA_ARGS_IMPL(__VA_ARGS__, 63, 62, 61, \ + 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ + 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, \ + 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, \ + 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, \ + 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, \ + 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) + + +/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */ +typedef uint8_t uint16_le_t[2]; + +/**@brief Type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */ +typedef uint8_t uint32_le_t[4]; + +/**@brief Byte array type. */ +typedef struct +{ + uint16_t size; /**< Number of array entries. */ + uint8_t * p_data; /**< Pointer to array entries. */ +} uint8_array_t; + + +/**@brief Macro for performing rounded integer division (as opposed to truncating the result). + * + * @param[in] A Numerator. + * @param[in] B Denominator. + * + * @return Rounded (integer) result of dividing A by B. + */ +#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B)) + + +/**@brief Macro for checking if an integer is a power of two. + * + * @param[in] A Number to be tested. + * + * @return true if value is power of two. + * @return false if value not power of two. + */ +#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) ) + + +/**@brief Macro for converting milliseconds to ticks. + * + * @param[in] TIME Number of milliseconds to convert. + * @param[in] RESOLUTION Unit to be converted to in [us/ticks]. + */ +#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) + + +/**@brief Macro for performing integer division, making sure the result is rounded up. + * + * @details One typical use for this is to compute the number of objects with size B is needed to + * hold A number of bytes. + * + * @param[in] A Numerator. + * @param[in] B Denominator. + * + * @return Integer result of dividing A by B, rounded up. + */ +#define CEIL_DIV(A, B) \ + (((A) + (B) - 1) / (B)) + + +/**@brief Macro for creating a buffer aligned to 4 bytes. + * + * @param[in] NAME Name of the buffor. + * @param[in] MIN_SIZE Size of this buffor (it will be rounded up to multiples of 4 bytes). + */ +#define WORD_ALIGNED_MEM_BUFF(NAME, MIN_SIZE) static uint32_t NAME[CEIL_DIV(MIN_SIZE, sizeof(uint32_t))] + + +/**@brief Macro for calculating the number of words that are needed to hold a number of bytes. + * + * @details Adds 3 and divides by 4. + * + * @param[in] n_bytes The number of bytes. + * + * @return The number of words that @p n_bytes take up (rounded up). + */ +#define BYTES_TO_WORDS(n_bytes) (((n_bytes) + 3) >> 2) + + +/**@brief The number of bytes in a word. + */ +#define BYTES_PER_WORD (4) + + +/**@brief Macro for increasing a number to the nearest (larger) multiple of another number. + * + * @param[in] alignment The number to align to. + * @param[in] number The number to align (increase). + * + * @return The aligned (increased) @p number. + */ +#define ALIGN_NUM(alignment, number) ((number - 1) + alignment - ((number - 1) % alignment)) + + +/**@brief Function for changing the value unit. + * + * @param[in] value Value to be rescaled. + * @param[in] old_unit_reversal Reversal of the incoming unit. + * @param[in] new_unit_reversal Reversal of the desired unit. + * + * @return Number of bytes written. + */ +static __INLINE uint64_t value_rescale(uint32_t value, uint32_t old_unit_reversal, uint16_t new_unit_reversal) +{ + return (uint64_t)ROUNDED_DIV((uint64_t)value * new_unit_reversal, old_unit_reversal); +} + +/**@brief Function for encoding a uint16 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8); + return sizeof(uint16_t); +} + +/**@brief Function for encoding a three-byte value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint24_encode(uint32_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); + return 3; +} + +/**@brief Function for encoding a uint32 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24); + return sizeof(uint32_t); +} + +/**@brief Function for encoding a uint48 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint48_encode(uint64_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x0000000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x00000000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x000000FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((value & 0x0000FF000000) >> 24); + p_encoded_data[4] = (uint8_t) ((value & 0x00FF00000000) >> 32); + p_encoded_data[5] = (uint8_t) ((value & 0xFF0000000000) >> 40); + return 6; +} + +/**@brief Function for decoding a uint16 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) | + (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 )); +} + +/**@brief Function for decoding a uint16 value in big-endian format. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint16_t uint16_big_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint16_t)((uint8_t *)p_encoded_data)[0]) << 8 ) | + (((uint16_t)((uint8_t *)p_encoded_data)[1])) ); +} + +/**@brief Function for decoding a three-byte value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value (uint32_t). + */ +static __INLINE uint32_t uint24_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16)); +} + +/**@brief Function for decoding a uint32 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 )); +} + +/**@brief Function for decoding a uint32 value in big-endian format. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint32_t uint32_big_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 24) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 16) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 0) ); +} + +/**@brief Function for encoding a uint32 value in big-endian format. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data will be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint32_big_encode(uint32_t value, uint8_t * p_encoded_data) +{ +#ifdef NRF51 + p_encoded_data[0] = (uint8_t) ((value & 0xFF000000) >> 24); + p_encoded_data[1] = (uint8_t) ((value & 0x00FF0000) >> 16); + p_encoded_data[2] = (uint8_t) ((value & 0x0000FF00) >> 8); + p_encoded_data[3] = (uint8_t) ((value & 0x000000FF) >> 0); +#elif NRF52 + *(uint32_t *)p_encoded_data = __REV(value); +#endif + return sizeof(uint32_t); +} + +/**@brief Function for decoding a uint48 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. (uint64_t) + */ +static __INLINE uint64_t uint48_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24) | + (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32) | + (((uint64_t)((uint8_t *)p_encoded_data)[5]) << 40 )); +} + +/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts. + * + * @details The calculation is based on a linearized version of the battery's discharge + * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and + * is considered to be the lower boundary. + * + * The discharge curve for CR2032 is non-linear. In this model it is split into + * 4 linear sections: + * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV) + * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV) + * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV) + * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV) + * + * These numbers are by no means accurate. Temperature and + * load in the actual application is not accounted for! + * + * @param[in] mvolts The voltage in mV + * + * @return Battery level in percent. +*/ +static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts) +{ + uint8_t battery_level; + + if (mvolts >= 3000) + { + battery_level = 100; + } + else if (mvolts > 2900) + { + battery_level = 100 - ((3000 - mvolts) * 58) / 100; + } + else if (mvolts > 2740) + { + battery_level = 42 - ((2900 - mvolts) * 24) / 160; + } + else if (mvolts > 2440) + { + battery_level = 18 - ((2740 - mvolts) * 12) / 300; + } + else if (mvolts > 2100) + { + battery_level = 6 - ((2440 - mvolts) * 6) / 340; + } + else + { + battery_level = 0; + } + + return battery_level; +} + +/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary. + * + * @param[in] p Pointer value to be checked. + * + * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise. + */ +static __INLINE bool is_word_aligned(void const* p) +{ + return (((uintptr_t)p & 0x03) == 0); +} + +/** + * @brief Function for checking if provided address is located in stack space. + * + * @param[in] ptr Pointer to be checked. + * + * @return true if address is in stack space, false otherwise. + */ +static __INLINE bool is_address_from_stack(void * ptr) +{ + if (((uint32_t)ptr >= (uint32_t)STACK_BASE) && + ((uint32_t)ptr < (uint32_t)STACK_TOP) ) + { + return true; + } + else + { + return false; + } +} + +#endif // APP_UTIL_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_bds.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_bds.h new file mode 100644 index 0000000..7547ad8 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_bds.h @@ -0,0 +1,413 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup app_util Utility Functions and Definitions + * @{ + * @ingroup app_common + * + * @brief Various types and definitions available to all applications. + */ + +#ifndef APP_UTIL_BDS_H__ +#define APP_UTIL_BDS_H__ + +#include +#include +#include +#include "compiler_abstraction.h" +#include "app_util.h" +#include "ble_srv_common.h" +#include "nordic_common.h" + +typedef uint8_t nibble_t; +typedef uint32_t uint24_t; +typedef uint64_t uint40_t; + +/**@brief IEEE 11073-20601 Regulatory Certification Data List Structure */ +typedef struct +{ + uint8_t * p_list; /**< Pointer the byte array containing the encoded opaque structure based on IEEE 11073-20601 specification. */ + uint8_t list_len; /**< Length of the byte array. */ +} regcertdatalist_t; + +/**@brief SFLOAT format (IEEE-11073 16-bit FLOAT, meaning 4 bits for exponent (base 10) and 12 bits mantissa) */ +typedef struct +{ + int8_t exponent; /**< Base 10 exponent, should be using only 4 bits */ + int16_t mantissa; /**< Mantissa, should be using only 12 bits */ +} sfloat_t; + +/**@brief Date and Time structure. */ +typedef struct +{ + uint16_t year; + uint8_t month; + uint8_t day; + uint8_t hours; + uint8_t minutes; + uint8_t seconds; +} ble_date_time_t; + + +/**@brief Function for encoding a uint16 value. + * + * @param[in] p_value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t bds_uint16_encode(const uint16_t * p_value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((*p_value & 0x00FF) >> 0); + p_encoded_data[1] = (uint8_t) ((*p_value & 0xFF00) >> 8); + return sizeof(uint16_t); +} + +static __INLINE uint8_t bds_int16_encode(const int16_t * p_value, uint8_t * p_encoded_data) +{ + uint16_t tmp = *p_value; + return bds_uint16_encode(&tmp, p_encoded_data); +} + +/**@brief Function for encoding a uint24 value. + * + * @param[in] p_value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t bds_uint24_encode(const uint32_t * p_value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16); + return (3); +} + + +/**@brief Function for encoding a uint32 value. + * + * @param[in] p_value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t bds_uint32_encode(const uint32_t * p_value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((*p_value & 0xFF000000) >> 24); + return sizeof(uint32_t); +} + + +/**@brief Function for encoding a uint40 value. + * + * @param[in] p_value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t bds_uint40_encode(const uint64_t * p_value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((*p_value & 0x00000000000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((*p_value & 0x000000000000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((*p_value & 0x0000000000FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((*p_value & 0x00000000FF000000) >> 24); + p_encoded_data[4] = (uint8_t) ((*p_value & 0x000000FF00000000) >> 32); + return 5; +} + +/**@brief Function for encoding a sfloat value. + * + * @param[in] p_value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t bds_sfloat_encode(const sfloat_t * p_value, uint8_t * p_encoded_data) +{ + uint16_t encoded_val; + + encoded_val = ((p_value->exponent << 12) & 0xF000) | + ((p_value->mantissa << 0) & 0x0FFF); + + return(bds_uint16_encode(&encoded_val, p_encoded_data)); +} + + +/**@brief Function for encoding a uint8_array value. + * + * @param[in] p_value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + */ +static __INLINE uint8_t bds_uint8_array_encode(const uint8_array_t * p_value, + uint8_t * p_encoded_data) +{ + memcpy(p_encoded_data, p_value->p_data, p_value->size); + return p_value->size; +} + + +/**@brief Function for encoding a utf8_str value. + * + * @param[in] p_value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + + */ +static __INLINE uint8_t bds_ble_srv_utf8_str_encode(const ble_srv_utf8_str_t * p_value, + uint8_t * p_encoded_data) +{ + memcpy(p_encoded_data, p_value->p_str, p_value->length); + return p_value->length; +} + +/**@brief Function for encoding a regcertdatalist value. + * + * @param[in] p_value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + + */ +static __INLINE uint8_t bds_regcertdatalist_encode(const regcertdatalist_t * p_value, + uint8_t * p_encoded_data) +{ + memcpy(p_encoded_data, p_value->p_list, p_value->list_len); + return p_value->list_len; +} + + +/**@brief Function for decoding a date_time value. + * + * @param[in] p_date_time pointer to the date_time structure to encode. + * @param[in] p_encoded_data pointer to the encoded data + * @return length of the encoded field. + */ +static __INLINE uint8_t bds_ble_date_time_encode(const ble_date_time_t * p_date_time, + uint8_t * p_encoded_data) +{ + uint8_t len = bds_uint16_encode(&p_date_time->year, &p_encoded_data[0]); + + p_encoded_data[len++] = p_date_time->month; + p_encoded_data[len++] = p_date_time->day; + p_encoded_data[len++] = p_date_time->hours; + p_encoded_data[len++] = p_date_time->minutes; + p_encoded_data[len++] = p_date_time->seconds; + + return len; +} + + +/**@brief Function for decoding a uint16 value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_decoded_val pointer to the decoded value + * @return length of the decoded field. + */ +static __INLINE uint8_t bds_uint16_decode(const uint8_t len, + const uint8_t * p_encoded_data, + uint16_t * p_decoded_val) +{ + UNUSED_VARIABLE(len); + *p_decoded_val = (((uint16_t)((uint8_t *)p_encoded_data)[0])) | + (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ); + return (sizeof(uint16_t)); +} + + +/**@brief Function for decoding a int16 value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_decoded_val pointer to the decoded value + * @return length of the decoded field. + */ +static __INLINE uint8_t bds_int16_decode(const uint8_t len, + const uint8_t * p_encoded_data, + int16_t * p_decoded_val) +{ + UNUSED_VARIABLE(len); + uint16_t tmp = 0; + uint8_t retval = bds_uint16_decode(len, p_encoded_data, &tmp); + *p_decoded_val = (int16_t)tmp; + return retval; +} + + +/**@brief Function for decoding a uint24 value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_decoded_val pointer to the decoded value + * + * @return length of the decoded field. + */ +static __INLINE uint8_t bds_uint24_decode(const uint8_t len, + const uint8_t * p_encoded_data, + uint32_t * p_decoded_val) +{ + UNUSED_VARIABLE(len); + *p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16); + return (3); +} + + +/**@brief Function for decoding a uint32 value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_decoded_val pointer to the decoded value + * + * @return length of the decoded field. + */ +static __INLINE uint8_t bds_uint32_decode(const uint8_t len, + const uint8_t * p_encoded_data, + uint32_t * p_decoded_val) +{ + UNUSED_VARIABLE(len); + *p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ); + return (sizeof(uint32_t)); +} + + +/**@brief Function for decoding a uint40 value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_decoded_val pointer to the decoded value + * + * @return length of the decoded field. + */ +static __INLINE uint8_t bds_uint40_decode(const uint8_t len, + const uint8_t * p_encoded_data, + uint64_t * p_decoded_val) +{ + UNUSED_VARIABLE(len); + *p_decoded_val = (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24 )| + (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32 ); + return (40); +} + + +/**@brief Function for decoding a sfloat value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_decoded_val pointer to the decoded value + * + * @return length of the decoded field. + + */ +static __INLINE uint8_t bds_sfloat_decode(const uint8_t len, + const uint8_t * p_encoded_data, + sfloat_t * p_decoded_val) +{ + + p_decoded_val->exponent = 0; + bds_uint16_decode(len, p_encoded_data, (uint16_t*)&p_decoded_val->mantissa); + p_decoded_val->exponent = (uint8_t)((p_decoded_val->mantissa & 0xF000) >> 12); + p_decoded_val->mantissa &= 0x0FFF; + return len; +} + + +/**@brief Function for decoding a uint8_array value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_decoded_val pointer to the decoded value + * + * @return length of the decoded field. + */ +static __INLINE uint8_t bds_uint8_array_decode(const uint8_t len, + const uint8_t * p_encoded_data, + uint8_array_t * p_decoded_val) +{ + memcpy(p_decoded_val->p_data, p_encoded_data, len); + p_decoded_val->size = len; + return p_decoded_val->size; +} + + +/**@brief Function for decoding a utf8_str value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_decoded_val pointer to the decoded value + * + * @return length of the decoded field. + */ +static __INLINE uint8_t bds_ble_srv_utf8_str_decode(const uint8_t len, + const uint8_t * p_encoded_data, + ble_srv_utf8_str_t * p_decoded_val) +{ + p_decoded_val->p_str = (uint8_t*)p_encoded_data; + p_decoded_val->length = len; + return p_decoded_val->length; +} + + +/**@brief Function for decoding a regcertdatalist value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_decoded_val pointer to the decoded value + * + * @return length of the decoded field. + */ +static __INLINE uint8_t bds_regcertdatalist_decode(const uint8_t len, + const uint8_t * p_encoded_data, + regcertdatalist_t * p_decoded_val) +{ + memcpy(p_decoded_val->p_list, p_encoded_data, len); + p_decoded_val->list_len = len; + return p_decoded_val->list_len; +} + + +/**@brief Function for decoding a date_time value. + * + * @param[in] len length of the field to be decoded. + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * @param[in] p_date_time pointer to the decoded value + * + * @return length of the decoded field. + */ +static __INLINE uint8_t bds_ble_date_time_decode(const uint8_t len, + const uint8_t * p_encoded_data, + ble_date_time_t * p_date_time) +{ + UNUSED_VARIABLE(len); + uint8_t pos = bds_uint16_decode(len, &p_encoded_data[0], &p_date_time->year); + p_date_time->month = p_encoded_data[pos++]; + p_date_time->day = p_encoded_data[pos++]; + p_date_time->hours = p_encoded_data[pos++]; + p_date_time->minutes = p_encoded_data[pos++]; + p_date_time->seconds = p_encoded_data[pos++]; + + return pos; +} + +#endif // APP_UTIL_BDS_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.c new file mode 100644 index 0000000..5e8c0ad --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.c @@ -0,0 +1,60 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "app_util_platform.h" + +static uint32_t m_in_critical_region = 0; + +void app_util_disable_irq(void) +{ + __disable_irq(); + m_in_critical_region++; +} + +void app_util_enable_irq(void) +{ + m_in_critical_region--; + if (m_in_critical_region == 0) + { + __enable_irq(); + } +} + +void app_util_critical_region_enter(uint8_t *p_nested) +{ +#ifdef NRF52 + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif + +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + (void) sd_nvic_critical_region_enter(p_nested); +#else + app_util_disable_irq(); +#endif +} + +void app_util_critical_region_exit(uint8_t nested) +{ +#ifdef NRF52 + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif + +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + (void) sd_nvic_critical_region_exit(nested); +#else + app_util_enable_irq(); +#endif +} + + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.h new file mode 100644 index 0000000..e0142ae --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/app_util_platform.h @@ -0,0 +1,211 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup app_util_platform Utility Functions and Definitions (Platform) + * @{ + * @ingroup app_common + * + * @brief Various types and definitions available to all applications when using SoftDevice. + */ + +#ifndef APP_UTIL_PLATFORM_H__ +#define APP_UTIL_PLATFORM_H__ + +#include +#include "compiler_abstraction.h" +#include "nrf.h" +#ifdef SOFTDEVICE_PRESENT +#include "nrf_soc.h" +#include "nrf_nvic.h" +#endif +#include "nrf_assert.h" +#include "app_error.h" + +#if defined(NRF51) +#define _PRIO_SD_HIGH 0 +#define _PRIO_APP_HIGH 1 +#define _PRIO_APP_MID 1 +#define _PRIO_SD_LOW 2 +#define _PRIO_APP_LOW 3 +#define _PRIO_APP_LOWEST 3 +#define _PRIO_THREAD 4 +#elif defined(NRF52) +#define _PRIO_SD_HIGH 0 +#define _PRIO_SD_MID 1 +#define _PRIO_APP_HIGH 2 +#define _PRIO_APP_MID 3 +#define _PRIO_SD_LOW 4 +#define _PRIO_SD_LOWEST 5 +#define _PRIO_APP_LOW 6 +#define _PRIO_APP_LOWEST 7 +#define _PRIO_THREAD 15 +#else + #error "No platform defined" +#endif + +/**@brief The interrupt priorities available to the application while the SoftDevice is active. */ +typedef enum +{ +#ifdef SOFTDEVICE_PRESENT + APP_IRQ_PRIORITY_HIGHEST = _PRIO_SD_HIGH, +#else + APP_IRQ_PRIORITY_HIGHEST = _PRIO_APP_HIGH, +#endif + APP_IRQ_PRIORITY_HIGH = _PRIO_APP_HIGH, +#ifndef SOFTDEVICE_PRESENT + APP_IRQ_PRIORITY_MID = _PRIO_SD_LOW, +#else + APP_IRQ_PRIORITY_MID = _PRIO_APP_MID, +#endif + APP_IRQ_PRIORITY_LOW = _PRIO_APP_LOW, + APP_IRQ_PRIORITY_LOWEST = _PRIO_APP_LOWEST, + APP_IRQ_PRIORITY_THREAD = _PRIO_THREAD /**< "Interrupt level" when running in Thread Mode. */ +} app_irq_priority_t; + +/*@brief The privilege levels available to applications in Thread Mode */ +typedef enum +{ + APP_LEVEL_UNPRIVILEGED, + APP_LEVEL_PRIVILEGED +} app_level_t; + +/**@cond NO_DOXYGEN */ +#define EXTERNAL_INT_VECTOR_OFFSET 16 +/**@endcond */ + +#define PACKED(TYPE) __packed TYPE + +void app_util_critical_region_enter (uint8_t *p_nested); +void app_util_critical_region_exit (uint8_t nested); + +/**@brief Macro for entering a critical region. + * + * @note Due to implementation details, there must exist one and only one call to + * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located + * in the same scope. + */ +#ifdef SOFTDEVICE_PRESENT +#define CRITICAL_REGION_ENTER() \ + { \ + uint8_t __CR_NESTED = 0; \ + app_util_critical_region_enter(&__CR_NESTED); +#else +#define CRITICAL_REGION_ENTER() app_util_critical_region_enter(NULL) +#endif + +/**@brief Macro for leaving a critical region. + * + * @note Due to implementation details, there must exist one and only one call to + * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located + * in the same scope. + */ +#ifdef SOFTDEVICE_PRESENT +#define CRITICAL_REGION_EXIT() \ + app_util_critical_region_exit(__CR_NESTED); \ + } +#else +#define CRITICAL_REGION_EXIT() app_util_critical_region_exit(0) +#endif + +/* Workaround for Keil 4 */ +#ifndef IPSR_ISR_Msk +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ +#endif + + + +/**@brief Macro to enable anonymous unions from a certain point in the code. + */ +#if defined(__CC_ARM) + #define ANON_UNIONS_ENABLE _Pragma("push") \ + _Pragma("anon_unions") +#elif defined(__ICCARM__) + #define ANON_UNIONS_ENABLE _Pragma("language=extended") +#else + #define ANON_UNIONS_ENABLE + // No action will be taken. + // For GCC anonymous unions are enabled by default. +#endif + +/**@brief Macro to disable anonymous unions from a certain point in the code. + * @note Call only after first calling @ref ANON_UNIONS_ENABLE. + */ +#if defined(__CC_ARM) + #define ANON_UNIONS_DISABLE _Pragma("pop") +#elif defined(__ICCARM__) + #define ANON_UNIONS_DISABLE + // for IAR leave anonymous unions enabled +#else + #define ANON_UNIONS_DISABLE + // No action will be taken. + // For GCC anonymous unions are enabled by default. +#endif + + +/* Workaround for Keil 4 */ +#ifndef CONTROL_nPRIV_Msk +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ +#endif + +/**@brief Function for finding the current interrupt level. + * + * @return Current interrupt level. + * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level. + * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level. + * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode. + */ +static __INLINE uint8_t current_int_priority_get(void) +{ + uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ; + if (isr_vector_num > 0) + { + int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET); + return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF); + } + else + { + return APP_IRQ_PRIORITY_THREAD; + } +} + +/**@brief Function for finding out the current privilege level. + * + * @return Current privilege level. + * @retval APP_LEVEL_UNPRIVILEGED We are running in unprivileged level. + * @retval APP_LEVEL_PRIVILEGED We are running in privileged level. + */ +static __INLINE uint8_t privilege_level_get(void) +{ +#if defined(NRF51) + /* the Cortex-M0 has no concept of privilege */ + return APP_LEVEL_PRIVILEGED; +#elif defined(NRF52) + uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ; + if (0 == isr_vector_num) + { + /* Thread Mode, check nPRIV */ + int32_t control = __get_CONTROL(); + return control & CONTROL_nPRIV_Msk ? APP_LEVEL_UNPRIVILEGED : APP_LEVEL_PRIVILEGED; + } + else + { + /* Handler Mode, always privileged */ + return APP_LEVEL_PRIVILEGED; + } +#endif +} + +#endif // APP_UTIL_PLATFORM_H__ + +/** @} */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/common.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/common.h new file mode 100644 index 0000000..e08d52d --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/common.h @@ -0,0 +1,38 @@ + /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef COMMON_H +#define COMMON_H + +/*lint ++flb "Enter library region" */ + +#include +#include + +/* @file +* @brief Common header file for generic macros and definitions + * + */ + +/* + * GPIO glue macros, this can be used to define a pin number in source/header file and use that macro for pin + * configuration using this expansion. + * example: + * #define RESET_PIN 8 + * NRF_GPIO->PINCNF(RESET_PIN) = XXX ; // Expanded NRF_GPIO->PIN_CNF[8] = XXX + */ +#define PINX_GLUE(x, y, z) x##y##_##z /*!< first level glue for pin macros */ +#define PINCNF(p) PINX_GLUE(PIN,p,CNF) /*!< gpio configure pin number 'p' */ +#define PINOUT(p) PINX_GLUE(PIN,p,OUT) /*!< gpio out pin number 'p' */ + +/*lint --flb "Leave library region" */ +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nordic_common.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nordic_common.h new file mode 100644 index 0000000..4468c0a --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nordic_common.h @@ -0,0 +1,108 @@ +/* Copyright (c) 2008 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + */ + +/** @file + * @brief Common defines and macros for firmware developed by Nordic Semiconductor. + */ + +#ifndef NORDIC_COMMON_H__ +#define NORDIC_COMMON_H__ + +/** The upper 8 bits of a 32 bit value */ +//lint -emacro(572,MSB) // Suppress warning 572 "Excessive shift value" +#define MSB_32(a) (((a) & 0xFF000000) >> 24) +/** The lower 8 bits (of a 32 bit value) */ +#define LSB_32(a) ((a) & 0x000000FF) + +/** The upper 8 bits of a 16 bit value */ +//lint -emacro(572,MSB_16) // Suppress warning 572 "Excessive shift value" +#define MSB_16(a) (((a) & 0xFF00) >> 8) +/** The lower 8 bits (of a 16 bit value) */ +#define LSB_16(a) ((a) & 0x00FF) + +/** Leaves the minimum of the two 32-bit arguments */ +/*lint -emacro(506, MIN) */ /* Suppress "Constant value Boolean */ +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +/** Leaves the maximum of the two 32-bit arguments */ +/*lint -emacro(506, MAX) */ /* Suppress "Constant value Boolean */ +#define MAX(a, b) ((a) < (b) ? (b) : (a)) + +/** Concatenates two parameters. Useful as a second level of indirection, + * when a parameter can be macro itself. */ +#define CONCAT_2(p1, p2) p1##p2 +/** Concatenates three parameters. Useful as a second level of indirection, + * when a parameter can be macro itself. */ +#define CONCAT_3(p1, p2, p3) p1##p2##p3 + +/**@brief Set a bit in the uint32 word. + * + * @param[in] W Word whose bit is being set. + * @param[in] B Bit number in the word to be set. + */ +#define SET_BIT(W,B) ((W) |= (uint32_t)(1U << (B))) + + +/**@brief Clears a bit in the uint32 word. + * + * @param[in] W Word whose bit is to be cleared. + * @param[in] B Bit number in the word to be cleared. + */ +#define CLR_BIT(W, B) ((W) &= (~((uint32_t)1 << (B)))) + + +/**@brief Checks if a bit is set. + * + * @param[in] W Word whose bit is to be checked. + * @param[in] B Bit number in the word to be checked. + * + * @retval 1 if bit is set. + * @retval 0 if bit is not set. + */ +#define IS_SET(W,B) (((W) >> (B)) & 1) + +#define BIT_0 0x01 /**< The value of bit 0 */ +#define BIT_1 0x02 /**< The value of bit 1 */ +#define BIT_2 0x04 /**< The value of bit 2 */ +#define BIT_3 0x08 /**< The value of bit 3 */ +#define BIT_4 0x10 /**< The value of bit 4 */ +#define BIT_5 0x20 /**< The value of bit 5 */ +#define BIT_6 0x40 /**< The value of bit 6 */ +#define BIT_7 0x80 /**< The value of bit 7 */ +#define BIT_8 0x0100 /**< The value of bit 8 */ +#define BIT_9 0x0200 /**< The value of bit 9 */ +#define BIT_10 0x0400 /**< The value of bit 10 */ +#define BIT_11 0x0800 /**< The value of bit 11 */ +#define BIT_12 0x1000 /**< The value of bit 12 */ +#define BIT_13 0x2000 /**< The value of bit 13 */ +#define BIT_14 0x4000 /**< The value of bit 14 */ +#define BIT_15 0x8000 /**< The value of bit 15 */ +#define BIT_16 0x00010000 /**< The value of bit 16 */ +#define BIT_17 0x00020000 /**< The value of bit 17 */ +#define BIT_18 0x00040000 /**< The value of bit 18 */ +#define BIT_19 0x00080000 /**< The value of bit 19 */ +#define BIT_20 0x00100000 /**< The value of bit 20 */ +#define BIT_21 0x00200000 /**< The value of bit 21 */ +#define BIT_22 0x00400000 /**< The value of bit 22 */ +#define BIT_23 0x00800000 /**< The value of bit 23 */ +#define BIT_24 0x01000000 /**< The value of bit 24 */ +#define BIT_25 0x02000000 /**< The value of bit 25 */ +#define BIT_26 0x04000000 /**< The value of bit 26 */ +#define BIT_27 0x08000000 /**< The value of bit 27 */ +#define BIT_28 0x10000000 /**< The value of bit 28 */ +#define BIT_29 0x20000000 /**< The value of bit 29 */ +#define BIT_30 0x40000000 /**< The value of bit 30 */ +#define BIT_31 0x80000000 /**< The value of bit 31 */ + +#define UNUSED_VARIABLE(X) ((void)(X)) +#define UNUSED_PARAMETER(X) UNUSED_VARIABLE(X) +#define UNUSED_RETURN_VALUE(X) UNUSED_VARIABLE(X) + +#endif // NORDIC_COMMON_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.c new file mode 100644 index 0000000..3596565 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.c @@ -0,0 +1,28 @@ +/* Copyright (c) 2006 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#include "nrf_assert.h" +#include "app_error.h" +#include "nordic_common.h" + +#if defined(DEBUG_NRF) +void assert_nrf_callback(uint16_t line_num, const uint8_t * file_name) +{ + assert_info_t assert_info = + { + .line_num = line_num, + .p_file_name = file_name, + }; + app_error_fault_handler(NRF_FAULT_ID_SDK_ASSERT, 0, (uint32_t)(&assert_info)); + + UNUSED_VARIABLE(assert_info); +} +#endif /* DEBUG_NRF */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.h new file mode 100644 index 0000000..a15b089 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_assert.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is confidential property of Nordic Semiconductor. The use, + * copying, transfer or disclosure of such information is prohibited except by express written + * agreement with Nordic Semiconductor. + * + */ + +/** @file + * @brief Utilities for verifying program logic + */ + +#ifndef NRF_ASSERT_H_ +#define NRF_ASSERT_H_ + +#include +#include "nrf.h" +#include "app_error.h" + +#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER) + +/** @brief Function for handling assertions. + * + * + * @note + * This function is called when an assertion has triggered. + * + * + * @post + * All hardware is put into an idle non-emitting state (in particular the radio is highly + * important to switch off since the radio might be in a state that makes it send + * packets continiously while a typical final infinit ASSERT loop is executing). + * + * + * @param line_num The line number where the assertion is called + * @param file_name Pointer to the file name + */ +void assert_nrf_callback(uint16_t line_num, const uint8_t *file_name); + +/*lint -emacro(506, ASSERT) */ /* Suppress "Constant value Boolean */ +/*lint -emacro(774, ASSERT) */ /* Suppress "Boolean within 'if' always evaluates to True" */ \ + +/** @brief Function for checking intended for production code. + * + * Check passes if "expr" evaluates to true. */ +#define ASSERT(expr) \ +if (expr) \ +{ \ +} \ +else \ +{ \ + assert_nrf_callback((uint16_t)__LINE__, (uint8_t *)__FILE__); \ +} +#else +#define ASSERT(expr) //!< Assert empty when disabled +__WEAK void assert_nrf_callback(uint16_t line_num, const uint8_t *file_name); +#endif /* defined(DEBUG_NRF) || defined(DEBUG_NRF_USER) */ + +#endif /* NRF_ASSERT_H_ */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.c new file mode 100644 index 0000000..480d7b5 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.c @@ -0,0 +1,425 @@ +#include "nrf.h" +#include "nrf_log.h" +#include "nrf_error.h" +#include +#include +#include + +#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1 + +#include +#include + +static char buf_normal_up[BUFFER_SIZE_UP]; +static char buf_down[BUFFER_SIZE_DOWN]; + +uint32_t log_rtt_init(void) +{ + static bool initialized = false; + if (initialized) + { + return NRF_SUCCESS; + } + + if (SEGGER_RTT_ConfigUpBuffer(LOG_TERMINAL_NORMAL, + "Normal", + buf_normal_up, + BUFFER_SIZE_UP, + SEGGER_RTT_MODE_NO_BLOCK_TRIM + ) + != 0) + { + return NRF_ERROR_INVALID_STATE; + } + + if (SEGGER_RTT_ConfigDownBuffer(LOG_TERMINAL_INPUT, + "Input", + buf_down, + BUFFER_SIZE_DOWN, + SEGGER_RTT_MODE_NO_BLOCK_SKIP + ) + != 0) + { + return NRF_ERROR_INVALID_STATE; + } + + initialized = true; + + return NRF_SUCCESS; +} + +// Forward declaration of SEGGER RTT vprintf function +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); + +void log_rtt_printf(int terminal_index, char * format_msg, ...) +{ + //lint -save -e526 -e628 -e530 + va_list p_args; + va_start(p_args, format_msg); + (void)SEGGER_RTT_vprintf(terminal_index, format_msg, &p_args); + va_end(p_args); + //lint -restore +} + +__INLINE void log_rtt_write_string(int terminal_index, int num_args, ...) +{ + const char* msg; + //lint -save -e516 -e530 + va_list p_args; + va_start(p_args, num_args); + //lint -restore + + for (int i = 0; i < num_args; i++) + { + //lint -save -e26 -e10 -e64 -e526 -e628 -e530 + msg = va_arg(p_args, const char*); + //lint -restore + (void)SEGGER_RTT_WriteString(terminal_index, msg); + } + va_end(p_args); +} + +void log_rtt_write_hex(int terminal_index, uint32_t value) +{ + char temp[11]; + temp[0] = '0'; + temp[1] = 'x'; + temp[10] = 0; // Null termination + uint8_t nibble; + uint8_t i = 8; + + while(i-- != 0) + { + nibble = (value >> (4 * i)) & 0x0F; + temp[9-i] = (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble); + } + + (void)SEGGER_RTT_WriteString(terminal_index, temp); +} + +void log_rtt_write_hex_char(int terminal_index, uint8_t value) +{ + char temp[3]; + temp[2] = 0; // Null termination + uint8_t nibble; + uint8_t i = 2; + + while(i-- != 0) + { + nibble = (value >> (4 * i)) & 0x0F; + temp[1-i] = (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble); + } + + (void)SEGGER_RTT_WriteString(terminal_index, temp); +} + +__INLINE int log_rtt_has_input() +{ + return SEGGER_RTT_HasKey(); +} + +uint32_t log_rtt_read_input(char * c) +{ + int r; + + r = SEGGER_RTT_Read(LOG_TERMINAL_INPUT, c, 1); + if (r == 1) + return NRF_SUCCESS; + else + return NRF_ERROR_NULL; +} + +#elif defined(NRF_LOG_USES_UART) && NRF_LOG_USES_UART == 1 + +#include "app_uart.h" +#include "app_error.h" +#include +#include +#include "nrf.h" +#include "bsp.h" + +#define MAX_TEST_DATA_BYTES (15U) /**< max number of test bytes to be used for tx and rx. */ +#define UART_TX_BUF_SIZE 512 /**< UART TX buffer size. */ +#define UART_RX_BUF_SIZE 1 /**< UART RX buffer size. */ + +static uint8_t m_uart_data; +static bool m_uart_has_input; + +void uart_error_cb(app_uart_evt_t * p_event) +{ + if (p_event->evt_type == APP_UART_COMMUNICATION_ERROR) + { + APP_ERROR_HANDLER(p_event->data.error_communication); + } + else if (p_event->evt_type == APP_UART_FIFO_ERROR) + { + APP_ERROR_HANDLER(p_event->data.error_code); + } +} + +uint32_t log_uart_init() +{ + static bool initialized = false; + if (initialized) + { + return NRF_SUCCESS; + } + + uint32_t err_code; + const app_uart_comm_params_t comm_params = + { + RX_PIN_NUMBER, + TX_PIN_NUMBER, + RTS_PIN_NUMBER, + CTS_PIN_NUMBER, + APP_UART_FLOW_CONTROL_ENABLED, + false, + UART_BAUDRATE_BAUDRATE_Baud115200 + }; + + APP_UART_FIFO_INIT(&comm_params, + UART_RX_BUF_SIZE, + UART_TX_BUF_SIZE, + uart_error_cb, + APP_IRQ_PRIORITY_LOW, + err_code); + + initialized = true; + + return err_code; +} + +//lint -save -e530 -e64 +void log_uart_printf(const char * format_msg, ...) +{ + va_list p_args; + va_start(p_args, format_msg); + (void)vprintf(format_msg, p_args); + va_end(p_args); +} + +__INLINE void log_uart_write_string_many(int num_args, ...) +{ + const char* msg; + va_list p_args; + va_start(p_args, num_args); + + for (int i = 0; i < num_args; i++) + { + msg = va_arg(p_args, const char*); + log_uart_write_string(msg); + } + va_end(p_args); +} + +__INLINE void log_uart_write_string(const char* msg) +{ + while( *msg ) + { + (void)app_uart_put(*msg++); + } +} +//lint -restore + +void log_uart_write_hex(uint32_t value) +{ + uint8_t nibble; + uint8_t i = 8; + + (void)app_uart_put('0'); + (void)app_uart_put('x'); + while( i-- != 0 ) + { + nibble = (value >> (4 * i)) & 0x0F; + (void)app_uart_put( (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble) ); + } +} + +void log_uart_write_hex_char(uint8_t c) +{ + uint8_t nibble; + uint8_t i = 2; + + while( i-- != 0 ) + { + nibble = (c >> (4 * i)) & 0x0F; + (void)app_uart_put( (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble) ); + } +} + +__INLINE int log_uart_has_input() +{ + if (m_uart_has_input) return 1; + if (app_uart_get(&m_uart_data) == NRF_SUCCESS) + { + m_uart_has_input = true; + return 1; + } + return 0; +} + +uint32_t log_uart_read_input(char * c) +{ + if (m_uart_has_input) + { + *c = (char)m_uart_data; + m_uart_has_input = false; + return NRF_SUCCESS; + } + if (app_uart_get((uint8_t *)c) == NRF_SUCCESS) + { + return NRF_SUCCESS; + } + return NRF_ERROR_NULL; +} + +#elif defined(NRF_LOG_USES_RAW_UART) && NRF_LOG_USES_RAW_UART == 1 + +#include "app_uart.h" +#include +#include +#include "bsp.h" + +uint32_t log_raw_uart_init() +{ + // Disable UART + NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Disabled; + + // Configure RX/TX pins + nrf_gpio_cfg_output( TX_PIN_NUMBER ); + nrf_gpio_cfg_input(RX_PIN_NUMBER, NRF_GPIO_PIN_NOPULL); + + // Set a default baud rate of UART0_CONFIG_BAUDRATE + NRF_UART0->PSELTXD = TX_PIN_NUMBER; + NRF_UART0->BAUDRATE = UART0_CONFIG_BAUDRATE; + + NRF_UART0->PSELRTS = 0xFFFFFFFF; + NRF_UART0->PSELCTS = 0xFFFFFFFF; + + // Disable parity and interrupt + NRF_UART0->CONFIG = (UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos ); + NRF_UART0->CONFIG |= (UART_CONFIG_HWFC_Disabled << UART_CONFIG_HWFC_Pos ); + + // Re-enable the UART + NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Enabled; + NRF_UART0->INTENSET = 0; + NRF_UART0->TASKS_STARTTX = 1; + NRF_UART0->TASKS_STARTRX = 1; + + return NRF_SUCCESS; +} + +void log_raw_uart_printf(const char * format_msg, ...) +{ + static char buffer[256]; + + va_list p_args; + va_start(p_args, format_msg); + sprintf(buffer, format_msg, p_args); + va_end(p_args); + + log_raw_uart_write_string(buffer); +} + +__INLINE void log_raw_uart_write_char(const char c) +{ + NRF_UART0->TXD = c; + while( NRF_UART0->EVENTS_TXDRDY != 1 ); + NRF_UART0->EVENTS_TXDRDY = 0; +} + +__INLINE void log_raw_uart_write_string_many(int num_args, ...) +{ + + const char* msg; + va_list p_args; + va_start(p_args, num_args); + + for (int i = 0; i < num_args; i++) + { + msg = va_arg(p_args, const char*); + log_raw_uart_write_string(msg); + } + va_end(p_args); +} + +__INLINE void log_raw_uart_write_string(const char* msg) +{ + while( *msg ) + { + NRF_UART0->TXD = *msg++; + while( NRF_UART0->EVENTS_TXDRDY != 1 ); + NRF_UART0->EVENTS_TXDRDY = 0; + } +} + +void log_raw_uart_write_hex(uint32_t value) +{ + uint8_t nibble; + uint8_t i = 8; + + log_raw_uart_write_string( "0x" ); + while( i-- != 0 ) + { + nibble = (value >> (4 * i)) & 0x0F; + log_raw_uart_write_char( (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble) ); + } +} + +void log_raw_uart_write_hex_char(uint8_t c) +{ + uint8_t nibble; + uint8_t i = 2; + + while( i-- != 0 ) + { + nibble = (c >> (4 * i)) & 0x0F; + log_raw_uart_write_hex( (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble) ); + } +} + +__INLINE int log_raw_uart_has_input() +{ + return 0; +} + +uint32_t log_raw_uart_read_input(char * c) +{ + return NRF_ERROR_NULL; +} + +#endif // NRF_LOG_USES_RAW_UART == 1 + + +const char* log_hex_char(const char c) +{ + static volatile char hex_string[3]; + hex_string[2] = 0; // Null termination + uint8_t nibble; + uint8_t i = 2; + while(i-- != 0) + { + nibble = (c >> (4 * i)) & 0x0F; + hex_string[1-i] = (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble); + } + return (const char*) hex_string; +} + +const char* log_hex(uint32_t value) +{ + static volatile char hex_string[11]; + hex_string[0] = '0'; + hex_string[1] = 'x'; + hex_string[10] = 0; + uint8_t nibble; + uint8_t i = 8; + + while(i-- != 0) + { + nibble = (value >> (4 * i)) & 0x0F; + hex_string[9-i] = (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble); + } + + return (const char*)hex_string; +} + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.h new file mode 100644 index 0000000..5279d9f --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/nrf_log.h @@ -0,0 +1,699 @@ +#ifndef NRF_LOG_H_ +#define NRF_LOG_H_ + +#ifndef DOXYGEN + +#include +#include +#include + +#ifndef NRF_LOG_USES_RTT +#define NRF_LOG_USES_RTT 0 +#endif + +#ifndef NRF_LOG_USES_UART +#define NRF_LOG_USES_UART 0 +#endif + +#ifndef NRF_LOG_USES_RAW_UART +#define NRF_LOG_USES_RAW_UART 0 +#endif + +#ifndef NRF_LOG_USES_COLORS + #define NRF_LOG_USES_COLORS 1 +#endif + +#if NRF_LOG_USES_COLORS == 1 + #define NRF_LOG_COLOR_DEFAULT "\x1B[0m" + #define NRF_LOG_COLOR_BLACK "\x1B[1;30m" + #define NRF_LOG_COLOR_RED "\x1B[1;31m" + #define NRF_LOG_COLOR_GREEN "\x1B[1;32m" + #define NRF_LOG_COLOR_YELLOW "\x1B[1;33m" + #define NRF_LOG_COLOR_BLUE "\x1B[1;34m" + #define NRF_LOG_COLOR_MAGENTA "\x1B[1;35m" + #define NRF_LOG_COLOR_CYAN "\x1B[1;36m" + #define NRF_LOG_COLOR_WHITE "\x1B[1;37m" +#else + #define NRF_LOG_COLOR_DEFAULT + #define NRF_LOG_COLOR_BLACK + #define NRF_LOG_COLOR_RED + #define NRF_LOG_COLOR_GREEN + #define NRF_LOG_COLOR_YELLOW + #define NRF_LOG_COLOR_BLUE + #define NRF_LOG_COLOR_MAGENTA + #define NRF_LOG_COLOR_CYAN + #define NRF_LOG_COLOR_WHITE +#endif + +#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1 + +#define LOG_TERMINAL_NORMAL (0) +#define LOG_TERMINAL_ERROR (1) +#define LOG_TERMINAL_INPUT (0) + +/**@brief Function for initializing the SEGGER RTT logger. + * + * @details See segger.com + * for information about SEGGER Real Time Transfer (RTT). + * + * This function is available only when NRF_LOG_USES_RTT is defined as 1. + * + * @note Do not call this function directly. Use the macro @ref NRF_LOG_INIT instead. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR Otherwise. + */ +uint32_t log_rtt_init(void); + +/**@brief Function for writing a printf string using RTT. + * + * @details The printf implementation in SEGGER's RTT is more efficient than + * the standard implementation. However, printf requires more processor time + * than other logging functions. Therefore, applications that require logging + * but need it to interfere as little as possible with the execution, should + * avoid using printf. + * + * This function is available only when NRF_LOG_USES_RTT is defined as 1. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG_PRINTF + * - @ref NRF_LOG_PRINTF_DEBUG + * - @ref NRF_LOG_PRINTF_ERROR + * + * @param terminal_index Segger RTT terminal index to use as output. + * @param format_msg Printf format string. + */ +void log_rtt_printf(int terminal_index, char * format_msg, ...); + +/**@brief Function for writing a string using RTT. + * + * @details The string to write must be null-terminated, but the null termination will not be stored + * in the ring buffer. + * The impact of running this function should be very low compared to writing to UART. + * + * This function is available only when NRF_LOG_USES_RTT is defined as 1. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG + * - @ref NRF_LOG_DEBUG + * - @ref NRF_LOG_ERROR + * + * @param terminal_index Segger RTT terminal index to use as output. + * @param num_args Number of arguments. + */ +void log_rtt_write_string(int terminal_index, int num_args, ...); + +/**@brief Function for writing an integer as HEX using RTT. + * + * The output data is formatted as, for example, 0x89ABCDEF. + * + * This function is available only when NRF_LOG_USES_RTT is defined as 1. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG_HEX + * - @ref NRF_LOG_HEX_DEBUG + * - @ref NRF_LOG_HEX_ERROR + * + * @param terminal_index Segger RTT terminal index to use as output. + * @param value Integer value to be printed as HEX. + */ +void log_rtt_write_hex(int terminal_index, uint32_t value); + +/**@brief Function for writing a single character as HEX using RTT. + * + * The output string is formatted as, for example, AA. + * + * This function is available only when NRF_LOG_USES_RTT is defined as 1. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG_HEX_CHAR + * - @ref NRF_LOG_HEX_CHAR_DEBUG + * - @ref NRF_LOG_HEX_CHAR_ERROR + * + * @param terminal_index Segger RTT terminal index to use as output. + * @param value Character to print as HEX. + */ +void log_rtt_write_hex_char(int terminal_index, uint8_t value); + +/**@brief Function for checking if data is available in the input buffer. + * + * This function is available only when NRF_LOG_USES_RTT is defined as 1. + * + * @note Do not call this function directly. Use @ref NRF_LOG_HAS_INPUT instead. + * + * @retval 1 If characters are available to read. + * @retval 0 If no characters are available. + */ +int log_rtt_has_input(void); + +/**@brief Function for reading one character from the input buffer. + * + * @param[out] p_char Pointer where to store the character. + * + * This function is available only when NRF_LOG_USES_RTT is defined as 1. + * + * @note Do not call this function directly. Use @ref NRF_LOG_READ_INPUT instead. + * + * @retval NRF_SUCCESS If the character was read out. + * @retval NRF_ERROR_INVALID_DATA If no character could be read. + */ +uint32_t log_rtt_read_input(char* p_char); + +#define NRF_LOG_INIT() log_rtt_init() /*!< Initialize the module. */ + +#define NRF_LOG_PRINTF(...) log_rtt_printf(LOG_TERMINAL_NORMAL, ##__VA_ARGS__) /*!< Print a log message using printf. */ +#define NRF_LOG_PRINTF_DEBUG(...) log_rtt_printf(LOG_TERMINAL_NORMAL, ##__VA_ARGS__) /*!< If DEBUG is set, print a log message using printf. */ +#define NRF_LOG_PRINTF_ERROR(...) log_rtt_printf(LOG_TERMINAL_ERROR, ##__VA_ARGS__) /*!< Print a log message using printf to the error stream. */ + +#define NRF_LOG(...) log_rtt_write_string(LOG_TERMINAL_NORMAL, NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__) /*!< Print a log message. The input string must be null-terminated. */ +#define NRF_LOG_DEBUG(...) log_rtt_write_string(LOG_TERMINAL_NORMAL, NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__) /*!< If DEBUG is set, print a log message. The input string must be null-terminated. */ +#define NRF_LOG_ERROR(...) log_rtt_write_string(LOG_TERMINAL_ERROR, NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__) /*!< Print a log message to the error stream. The input string must be null-terminated. */ + +#define NRF_LOG_HEX(val) log_rtt_write_hex(LOG_TERMINAL_NORMAL, val) /*!< Log an integer as HEX value (example output: 0x89ABCDEF). */ +#define NRF_LOG_HEX_DEBUG(val) log_rtt_write_hex(LOG_TERMINAL_NORMAL, val) /*!< If DEBUG is set, log an integer as HEX value (example output: 0x89ABCDEF). */ +#define NRF_LOG_HEX_ERROR(val) log_rtt_write_hex(LOG_TERMINAL_ERROR, val) /*!< Log an integer as HEX value to the error stream (example output: 0x89ABCDEF). */ + +#define NRF_LOG_HEX_CHAR(val) log_rtt_write_hex_char(LOG_TERMINAL_NORMAL, val) /*!< Log a character as HEX value (example output: AA). */ +#define NRF_LOG_HEX_CHAR_DEBUG(val) log_rtt_write_hex_char(LOG_TERMINAL_NORMAL, val) /*!< If DEBUG is set, log a character as HEX value (example output: AA). */ +#define NRF_LOG_HEX_CHAR_ERROR(val) log_rtt_write_hex_char(LOG_TERMINAL_ERROR, val) /*!< Log a character as HEX value to the error stream (example output: AA). */ + +#define NRF_LOG_HAS_INPUT() log_rtt_has_input() /*!< Check if the input buffer has unconsumed characters. */ +#define NRF_LOG_READ_INPUT(p_char) log_rtt_read_input(p_char) /*!< Consume a character from the input buffer. */ + +#if !defined(DEBUG) && !defined(DOXYGEN) + +#undef NRF_LOG_DEBUG +#define NRF_LOG_DEBUG(...) + +#undef NRF_LOG_STR_DEBUG +#define NRF_LOG_STR_DEBUG(...) + +#undef NRF_LOG_HEX_DEBUG +#define NRF_LOG_HEX_DEBUG(...) + +#undef NRF_LOG_HEX_CHAR_DEBUG +#define NRF_LOG_HEX_CHAR_DEBUG(...) + +#endif // !defined(DEBUG) && !defined(DOXYGEN) + +#elif defined(NRF_LOG_USES_UART) && NRF_LOG_USES_UART == 1 + +/**@brief Function for initializing the UART logger. + * + * This function is available only when NRF_LOG_USES_UART is defined as 1. + * + * @note Do not call this function directly. Use the macro @ref NRF_LOG_INIT instead. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR Otherwise. + */ +uint32_t log_uart_init(void); + +/**@brief Function for logging a printf string to UART. + * + * @details Printf requires more processor time + * than other logging functions. Therefore, applications that require logging + * but need it to interfere as little as possible with the execution, should + * avoid using printf. + * + * This function is available only when NRF_LOG_USES_UART is defined as 1. + * + * @note This function is non-blocking. If too much data is sent to the UART, + * some characters might be skipped. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG_PRINTF + * - @ref NRF_LOG_PRINTF_DEBUG + * - @ref NRF_LOG_PRINTF_ERROR + * + * @param format_msg Printf format string. + */ +void log_uart_printf(const char * format_msg, ...); + +/**@brief Function for logging a single character to UART. + * + * This function is available only when NRF_LOG_USES_UART is defined as 1. + * + * @param c Character. + */ +void log_uart_write_char(const char c); + +/**@brief Function for logging null-terminated strings to UART. + * + * @details This function is more efficient than using printf. + * The null termination will not be logged. + * + * This function is available only when NRF_LOG_USES_UART is defined as 1. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG + * - @ref NRF_LOG_DEBUG + * - @ref NRF_LOG_ERROR + * + * @param num_args Number of arguments. + */ +void log_uart_write_string_many(int num_args, ...); + + +/**@brief Function for logging a null-terminated string to UART. + * + * @details This function is more efficient than using printf. + * The null termination will not be logged. + * + * This function is available only when NRF_LOG_USES_UART is defined as 1. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG + * - @ref NRF_LOG_DEBUG + * - @ref NRF_LOG_ERROR + * + * @param msg Null-terminated string. + */ +void log_uart_write_string(const char* msg); + + +/**@brief Function for logging an integer value as HEX to UART. + * + * @details The output data is formatted as, for example, 0x89ABCDEF. + * This function is more efficient than printf. + * + * This function is available only when NRF_LOG_USES_UART is defined as 1. + * + * @note This function is non-blocking. If too much data is sent to the UART, + * some characters might be skipped. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG_HEX + * - @ref NRF_LOG_HEX_DEBUG + * - @ref NRF_LOG_HEX_ERROR + * + * @param value Integer value to be printed as HEX. + */ +void log_uart_write_hex(uint32_t value); + +/**@brief Function for logging a single character as HEX to UART. + * + * @details The output string is formatted as, for example, AA. + * + * This function is available only when NRF_LOG_USES_UART is defined as 1. + * + * @note This function is non-blocking. If too much data is sent to the UART, + * some characters might be skipped. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG_HEX_CHAR + * - @ref NRF_LOG_HEX_CHAR_DEBUG + * - @ref NRF_LOG_HEX_CHAR_ERROR + * + * @param c Character. + */ +void log_uart_write_hex_char(uint8_t c); + +/**@brief Function for checking if data is available in the input buffer. + * + * This function is available only when NRF_LOG_USES_UART is defined as 1. + * + * @note Do not call this function directly. Use @ref NRF_LOG_HAS_INPUT instead. + * + * @retval 1 If characters are available to read. + * @retval 0 If no characters are available. + */ +int log_uart_has_input(void); + +/**@brief Function for reading one character from the input buffer. + * + * @param[out] p_char Pointer where to store the character. + * + * This function is available only when NRF_LOG_USES_UART is defined as 1. + * + * @note Do not call this function directly. Use NRF_LOG_READ_INPUT instead. + * + * @retval NRF_SUCCESS If the character was read out. + * @retval NRF_ERROR_INVALID_DATA If no character could be read. + */ +uint32_t log_uart_read_input(char* p_char); + + +#define NRF_LOG_INIT() log_uart_init() /*!< Initialize the module. */ + +#define NRF_LOG_PRINTF(...) log_uart_printf(__VA_ARGS__) /*!< Print a log message using printf. */ +#define NRF_LOG_PRINTF_DEBUG(...) log_uart_printf(__VA_ARGS__) /*!< If DEBUG is set, print a log message using printf. */ +#define NRF_LOG_PRINTF_ERROR(...) log_uart_printf(__VA_ARGS__) /*!< Print a log message using printf to the error stream. */ + +#define NRF_LOG(...) log_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__) /*!< Print a log message. The input string must be null-terminated. */ +#define NRF_LOG_DEBUG(...) log_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__) /*!< If DEBUG is set, print a log message. The input string must be null-terminated. */ +#define NRF_LOG_ERROR(...) log_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__) /*!< Print a log message to the error stream. The input string must be null-terminated. */ + +#define NRF_LOG_HEX(val) log_uart_write_hex(val) /*!< Log an integer as HEX value (example output: 0x89ABCDEF). */ +#define NRF_LOG_HEX_DEBUG(val) log_uart_write_hex(val) /*!< If DEBUG is set, log an integer as HEX value (example output: 0x89ABCDEF). */ +#define NRF_LOG_HEX_ERROR(val) log_uart_write_hex(val) /*!< Log an integer as HEX value to the error stream (example output: 0x89ABCDEF). */ + +#define NRF_LOG_HEX_CHAR(val) log_uart_write_hex_char(val) /*!< Log a character as HEX value (example output: AA). */ +#define NRF_LOG_HEX_CHAR_DEBUG(val) log_uart_write_hex_char(val) /*!< If DEBUG is set, log a character as HEX value (example output: AA). */ +#define NRF_LOG_HEX_CHAR_ERROR(val) log_uart_write_hex_char(val) /*!< Log a character as HEX value to the error stream (example output: AA). */ + +#define NRF_LOG_HAS_INPUT() log_uart_has_input() /*!< Check if the input buffer has unconsumed characters. */ +#define NRF_LOG_READ_INPUT(p_char) log_uart_read_input(p_char) /*!< Consume a character from the input buffer. */ + +#if !defined(DEBUG) && !defined(DOXYGEN) + +#undef NRF_LOG_DEBUG +#define NRF_LOG_DEBUG(...) + +#undef NRF_LOG_PRINTF_DEBUG +#define NRF_LOG_PRINTF_DEBUG(...) + +#undef NRF_LOG_STR_DEBUG +#define NRF_LOG_STR_DEBUG(...) + +#undef NRF_LOG_HEX_DEBUG +#define NRF_LOG_HEX_DEBUG(...) + +#undef NRF_LOG_HEX_CHAR_DEBUG +#define NRF_LOG_HEX_CHAR_DEBUG(...) + +#endif // !defined(DEBUG) && !defined(DOXYGEN) + +#elif defined(NRF_LOG_USES_RAW_UART) && NRF_LOG_USES_RAW_UART == 1 + +/**@brief Function for initializing the raw UART logger. + * + * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1. + * + * @note Do not call this function directly. Use the macro @ref NRF_LOG_INIT instead. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR Otherwise. + */ +uint32_t log_raw_uart_init(void); + +/**@brief Function for logging a printf string to raw UART. + * + * @details Printf requires more processor time + * than other logging functions. Therefore, applications that require logging + * but need it to interfere as little as possible with the execution, should + * avoid using printf. + * + * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1. + * + * @note This function is non-blocking. If too much data is sent to the UART, + * some characters might be skipped. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG_PRINTF + * - @ref NRF_LOG_PRINTF_DEBUG + * - @ref NRF_LOG_PRINTF_ERROR + * + * @param format_msg Printf format string. + */ +void log_raw_uart_printf(const char * format_msg, ...); + +/**@brief Function for logging a single character to raw UART. + * + * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1. + * + * @param c Character. + */ +void log_raw_uart_write_char(const char c); + +/**@brief Function for logging null-terminated strings to raw UART. + * + * @details This function is more efficient than using printf. + * The null termination will not be logged. + * + * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG + * - @ref NRF_LOG_DEBUG + * - @ref NRF_LOG_ERROR + * + * @param num_args Number of arguments. + */ +void log_raw_uart_write_string_many(int num_args, ...); + + +/**@brief Function for logging a null-terminated string to raw UART. + * + * @details This function is more efficient than using printf. + * The null termination will not be logged. + * + * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG + * - @ref NRF_LOG_DEBUG + * - @ref NRF_LOG_ERROR + * + * @param str Null-terminated string. + */ +void log_raw_uart_write_string(const char * str); + +/**@brief Function for logging an integer value as HEX to raw UART. + * + * @details The output data is formatted as, for example, 0x89ABCDEF. + * This function is more efficient than printf. + * + * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1. + * + * @note This function is non-blocking. If too much data is sent to the UART, + * some characters might be skipped. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG_HEX + * - @ref NRF_LOG_HEX_DEBUG + * - @ref NRF_LOG_HEX_ERROR + * + * @param value Integer value to be printed as HEX. + */ +void log_raw_uart_write_hex(uint32_t value); + +/**@brief Function for logging a single character as HEX to raw UART. + * + * @details The output string is formatted as, for example, AA. + * + * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1. + * + * @note This function is non-blocking. If too much data is sent to the UART, + * some characters might be skipped. + * + * @note Do not call this function directly. Use one of the following macros instead: + * - @ref NRF_LOG_HEX_CHAR + * - @ref NRF_LOG_HEX_CHAR_DEBUG + * - @ref NRF_LOG_HEX_CHAR_ERROR + * + * @param c Character. + */ +void log_raw_uart_write_hex_char(uint8_t c); + +/**@brief Function for checking if data is available in the input buffer. + * + * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1. + * + * @note Do not call this function directly. Use @ref NRF_LOG_HAS_INPUT instead. + * + * @retval 1 If characters are available to read. + * @retval 0 If no characters are available. + */ +int log_raw_uart_has_input(void); + +/**@brief Function for reading one character from the input buffer. + * + * @param[out] p_char Pointer where to store the character. + * + * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1. + * + * @note Do not call this function directly. Use NRF_LOG_READ_INPUT instead. + * + * @retval NRF_SUCCESS If the character was read out. + * @retval NRF_ERROR_INVALID_DATA If no character could be read. + */ + +uint32_t log_raw_uart_read_input(char* p_char); + +#define NRF_LOG_INIT() log_raw_uart_init() /*!< nitialize the module. */ + +#define NRF_LOG_PRINTF(...) log_raw_uart_printf(__VA_ARGS__) /*!< Print a log message using printf. */ +#define NRF_LOG_PRINTF_DEBUG(...) log_raw_uart_printf(__VA_ARGS__) /*!< If DEBUG is set, print a log message using printf. */ +#define NRF_LOG_PRINTF_ERROR(...) log_raw_uart_printf(__VA_ARGS__) /*!< Print a log message using printf to the error stream. */ + +#define NRF_LOG(...) log_raw_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__) /*!< Print a log message. The input string must be null-terminated. */ +#define NRF_LOG_DEBUG(...) log_raw_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__) /*!< If DEBUG is set, print a log message. The input string must be null-terminated. */ +#define NRF_LOG_ERROR(...) log_raw_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__) /*!< Print a log message to the error stream. The input string must be null-terminated. */ + +#define NRF_LOG_HEX(val) log_raw_uart_write_hex(val) /*!< Log an integer as HEX value (example output: 0x89ABCDEF). */ +#define NRF_LOG_HEX_DEBUG(val) log_raw_uart_write_hex(val) /*!< If DEBUG is set, log an integer as HEX value (example output: 0x89ABCDEF). */ +#define NRF_LOG_HEX_ERROR(val) log_raw_uart_write_hex(val) /*!< Log an integer as HEX value to the error stream (example output: 0x89ABCDEF). */ + +#define NRF_LOG_HEX_CHAR(val) log_raw_uart_write_hex_char(val) /*!< Log a character as HEX value (example output: AA). */ +#define NRF_LOG_HEX_CHAR_DEBUG(val) log_raw_uart_write_hex_char(val) /*!< If DEBUG is set, log a character as HEX value (example output: AA). */ +#define NRF_LOG_HEX_CHAR_ERROR(val) log_raw_uart_write_hex_char(val) /*!< Log a character as HEX value to the error stream (example output: AA). */ + +#define NRF_LOG_HAS_INPUT() log_raw_uart_has_input() /*!< Check if the input buffer has unconsumed characters. */ +#define NRF_LOG_READ_INPUT(p_char) log_raw_uart_read_input(p_char) /*!< Consume a character from the input buffer. */ + +#if !defined(DEBUG) && !defined(DOXYGEN) + +#undef NRF_LOG_DEBUG +#define NRF_LOG_DEBUG(...) + +#undef NRF_LOG_PRINTF_DEBUG +#define NRF_LOG_PRINTF_DEBUG(...) + +#undef NRF_LOG_STR_DEBUG +#define NRF_LOG_STR_DEBUG(...) + +#undef NRF_LOG_HEX_DEBUG +#define NRF_LOG_HEX_DEBUG(...) + +#undef NRF_LOG_HEX_CHAR_DEBUG +#define NRF_LOG_HEX_CHAR_DEBUG(...) + +#endif // !defined(DEBUG) && !defined(DOXYGEN) + +#else + +#include "nrf_error.h" +#include "nordic_common.h" + +// Empty definitions + +#define NRF_LOG_INIT() NRF_SUCCESS +#define NRF_LOG(...) +#define NRF_LOG_DEBUG(...) +#define NRF_LOG_ERROR(...) + +#define NRF_LOG_PRINTF(...) +#define NRF_LOG_PRINTF_DEBUG(...) +#define NRF_LOG_PRINTF_ERROR(...) + +#define NRF_LOG_HEX(val) +#define NRF_LOG_HEX_DEBUG(val) +#define NRF_LOG_HEX_ERROR(val) + +#define NRF_LOG_HEX_CHAR(val) +#define NRF_LOG_HEX_CHAR_DEBUG(val) +#define NRF_LOG_HEX_CHAR_ERROR(val) + +#define NRF_LOG_HAS_INPUT() 0 +#define NRF_LOG_READ_INPUT(ignore) NRF_SUCCESS + +#endif + +/**@brief Function for writing HEX values. + * + * @note This function not thread-safe. It is written for convenience. + * If you log from different application contexts, you might get different results. + * + * @retval NULL By default. + */ +const char* log_hex(uint32_t value); + +/**@brief Function for writing HEX characters. + * + * @note This function not thread-safe. It is written for convenience. + * If you log from different application contexts, you might get different results. + * + * @retval NULL By default. + */ +const char* log_hex_char(const char value); + + + + +#else // DOXYGEN + +/** @defgroup nrf_log UART/RTT logging + * @{ + * @ingroup app_common + * + * @brief Library to output logging information over SEGGER's Real Time Transfer + * (RTT), UART, or raw UART. + * + * This library provides macros that call the respective functions depending on + * which protocol is used. Define LOG_USES_RTT=1 to enable logging over RTT, + * NRF_LOG_USES_UART=1 to enable logging over UART, or NRF_LOG_USES_RAW_UART=1 + * to enable logging over raw UART. One of these defines must be set for any of + * the macros to have effect. If you choose to not output information, all + * logging macros can be left in the code without any cost; they will just be + * ignored. + */ + + + +/**@brief Macro for initializing the logger. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR Otherwise. + */ +uint32_t NRF_LOG_INIT(void); + +/**@brief Macro for logging null-terminated strings. + * + * @details This function is more efficient than using printf. + * The null termination will not be logged. + * + * @param msg Null-terminated string. + */ +void NRF_LOG(const char* msg); + +/**@brief Macro for logging a printf string. + * + * @details Printf requires more processor time + * than other logging functions. Therefore, applications that require logging + * but need it to interfere as little as possible with the execution, should + * avoid using printf. + * + * @note When NRF_LOG_USES_UART is set to 1, this macro is non-blocking. + * If too much data is sent, some characters might be skipped. + * + * @param format_msg Printf format string. + * @param ... Additional arguments replacing format specifiers in format_msg. + */ +void NRF_LOG_PRINTF(const char * format_msg, ...); + +/**@brief Macro for logging an integer value as HEX. + * + * @details The output data is formatted as, for example, 0x89ABCDEF. + * This function is more efficient than printf. + * + * @note When NRF_LOG_USES_UART is set to 1, this macro is non-blocking. + * If too much data is sent, some characters might be skipped. + * + * @param value Integer value to be printed as HEX. + */ +void NRF_LOG_HEX(uint32_t value); + +/**@brief Macro for logging a single character as HEX. + * + * @details The output string is formatted as, for example, AA. + * + * @note When NRF_LOG_USES_UART is set to 1, this macro is non-blocking. + * If too much data is sent, some characters might be skipped. + * + * @param c Character. + */ +void NRF_LOG_HEX_CHAR(uint8_t c); + +/**@brief Macro for checking if data is available in the input buffer. + * + * @note When NRF_LOG_USES_UART is set to 1, this macro is non-blocking. + * If too much data is sent, some characters might be skipped. + * + * @retval 1 If characters are available to read. + * @retval 0 If no characters are available. + */ +int NRF_LOG_HAS_INPUT(void); + +/**@brief Macro for reading one character from the input buffer. + * + * @param[out] p_char Pointer where to store the character. + * + * @retval NRF_SUCCESS If the character was read out. + * @retval NRF_ERROR_INVALID_DATA If no character could be read. + */ +uint32_t NRF_LOG_READ_INPUT(char* p_char); + +/** @} */ +#endif // DOXYGEN +#endif // NRF_LOG_H_ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_common.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_common.h new file mode 100644 index 0000000..ced9c6c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_common.h @@ -0,0 +1,174 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @cond */ +/**@file + * + * @ingroup experimental_api + * @defgroup sdk_common SDK Common Header + * @breif All common headers needed for SDK examples will be included here so that application + * developer does not have to include headers on him/herself. + * @{ + */ + +#ifndef SDK_COMMON_H__ +#define SDK_COMMON_H__ + +#include +#include +#include +#include "nordic_common.h" +#include "compiler_abstraction.h" +#include "sdk_os.h" +#include "sdk_errors.h" +#include "app_util.h" + +/**@brief Macro for verifying that the module is initialized. It will cause the function to return + * if not. + * + * @param[in] param The variable to check if is NULL. + */ +#ifndef DISABLE_PARAM_CHECK +#define VERIFY_PARAM_NOT_NULL(param) \ +do \ +{ \ + if (param == NULL) \ + { \ + return NRF_ERROR_NULL; \ + } \ +} while(0) +#else +#define VERIFY_PARAM_NOT_NULL() +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying that the module is initialized. It will cause the function to return + * if not. + * + * @param[in] param The variable to check if is NULL. + */ +#ifndef DISABLE_PARAM_CHECK +#define VERIFY_PARAM_NOT_NULL_VOID(param) \ +do \ +{ \ + if (param == NULL) \ + { \ + return; \ + } \ +} while(0) +#else +#define VERIFY_PARAM_NOT_NULL_VOID() +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying that a function returned NRF_SUCCESS. Will return the err code + * if not. + * + * @param[in] err_code The error code to check. + */ +#ifndef DISABLE_PARAM_CHECK +#define VERIFY_SUCCESS(err_code) \ +do \ +{ \ + if (err_code != NRF_SUCCESS) \ + { \ + return err_code; \ + } \ +} while(0) +#else +#define VERIFY_SUCCESS() +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying that a function returned NRF_SUCCESS. Will return if not. + * + * @param[in] err_code The error code to check. + */ +#ifndef DISABLE_PARAM_CHECK +#define VERIFY_SUCCESS_VOID(err_code) \ +do \ +{ \ + if (err_code != NRF_SUCCESS) \ + { \ + return; \ + } \ +} while(0) +#else +#define VERIFY_SUCCESS_VOID() +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying statement to be true. Will return err_code if not. +* +* @param[in] statement Statement to test. +* @param[in] err_code Error value to return if test was invalid. +* +* @retval err_code if test fails. +*/ +#define VERIFY_TRUE(statement, err_code) \ +do \ +{ \ + if (!(statement)) \ + { \ + return err_code; \ + } \ +} while(0) + + +/**@brief Macro for verifying statement to be true. Will return if not. +* +* @param[in] statement Statement to test. +*/ +#define VERIFY_TRUE_VOID(statement) \ +do \ +{ \ + if (!(statement)) \ + { \ + return; \ + } \ +} while(0) + + +/**@brief Macro for verifying statement to be false. Will return err_code if not. +* +* @param[in] statement Statement to test. +* @param[in] err_code Error value to return if test was invalid. +* +* @retval err_code if test fails. +*/ +#define VERIFY_FALSE(statement, err_code) \ +do \ +{ \ + if ((statement)) \ + { \ + return err_code; \ + } \ +} while(0) + + +/**@brief Macro for verifying statement to be false. Will return if not. +* +* @param[in] statement Statement to test. +*/ +#define VERIFY_FALSE_VOID(statement) \ +do \ +{ \ + if ((statement)) \ + { \ + return; \ + } \ +} while(0) + +/** @} */ +/** @endcond */ +#endif // SDK_COMMON_H__ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_errors.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_errors.h new file mode 100644 index 0000000..b72b85e --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_errors.h @@ -0,0 +1,115 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup sdk_error SDK Error codes + * @{ + * @ingroup app_common + * @{ + * @details Error codes are 32-bit unsigned integers with the most significant 16-bit reserved for + * identifying the module where the error occurred while the least least significant LSB + * are used to provide the cause or nature of error. Each module is assigned a 16-bit + * unsigned integer. Which it will use to identify all errors that occurred in it. 16-bit + * LSB range is with module id as the MSB in the 32-bit error code is reserved for the + * module. As an example, if 0x8800 identifies a certain SDK module, all values from + * 0x88000000 - 0x8800FFFF are reserved for this module. + * It should be noted that common error reasons have been assigned values to make it + * possible to decode error reason easily. As an example, lets module uninitialized has + * been assigned an error code 0x000A0. Then, if application encounters an error code + * 0xZZZZ00A0, it knows that it accessing a certain module without initializing it. + * Apart from this, each module is allowed to define error codes that are not covered by + * the common ones, however, these values are defined in a range that does not conflict + * with common error values. For module, specific error however, it is possible that the + * same error value is used by two different modules to indicated errors of very different + * nature. If error is already defined by the NRF common error codes, these are reused. + * A range is reserved for application as well, it can use this range for defining + * application specific errors. + * + * @note Success code, NRF_SUCCESS, does not include any module identifier. + + */ + +#ifndef SDK_ERRORS_H__ +#define SDK_ERRORS_H__ + +#include +#include "nrf_error.h" + +/** + * @defgroup sdk_err_base Base defined for SDK Modules + * @{ + */ +#define SDK_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x8000) /**< Base value defined for SDK module identifiers. */ +#define SDK_COMMON_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x0080) /**< Base error value to be used for SDK error values. */ +/* @} */ + +/** + * @defgroup sdk_module_codes Codes reserved as identification for module where the error occurred. + * @{ + */ +#define DEVICE_MANAGER_ERR_BASE (0x8000) +#define MEMORY_MANAGER_ERR_BASE (0x8100) +/* @} */ + + +/** + * @defgroup sdk_iot_errors Codes reserved as identification for IoT errors. + * @{ + */ +#define IOT_ERR_BASE_START (0xA000) +#define IOT_ERR_BASE_STOP (0xAFFF) +/* @} */ + + +/** + * @defgroup sdk_common_errors Codes reserved as identification for common errors. + * @{ + */ +#define MODULE_NOT_INITIALZED (SDK_COMMON_ERROR_BASE + 0x0000) +#define MUTEX_INIT_FAILED (SDK_COMMON_ERROR_BASE + 0x0001) +#define MUTEX_LOCK_FAILED (SDK_COMMON_ERROR_BASE + 0x0002) +#define MUTEX_UNLOCK_FAILED (SDK_COMMON_ERROR_BASE + 0x0003) +#define MUTEX_COND_INIT_FAILED (SDK_COMMON_ERROR_BASE + 0x0004) +#define MODULE_ALREADY_INITIALIZED (SDK_COMMON_ERROR_BASE + 0x0005) +#define API_NOT_IMPLEMENTED (SDK_COMMON_ERROR_BASE + 0x0010) +#define FEATURE_NOT_ENABLED (SDK_COMMON_ERROR_BASE + 0x0011) +/* @} */ + + +/** + * @defgroup dm_specific_errors Error / status codes specific to device manager. + * @{ + */ +#define DM_NO_APP_CONTEXT (DEVICE_MANAGER_ERR_BASE + 0x0040) +#define DM_SERVICE_CONTEXT_NOT_APPLIED (DEVICE_MANAGER_ERR_BASE + 0x0041) +#define DM_CONTEXT_INFO_LOST (DEVICE_MANAGER_ERR_BASE + 0x0042) +#define DM_DEVICE_CONTEXT_FULL (DEVICE_MANAGER_ERR_BASE + 0x0043) +/* @} */ + +/** + * @brief API Result. + * + * @details Indicates success or failure of an API procedure. In case of failure, a comprehensive + * error code indicating cause or reason for failure is provided. + * + * Though called an API result, it could used in Asynchronous notifications callback along + * with asynchronous callback as event result. This mechanism is employed when an event + * marks the end of procedure initiated using API. API result, in this case, will only be + * an indicative of whether the procedure has been requested successfully. + */ +typedef uint32_t ret_code_t; +/** @} */ +/** @} */ + +#endif // SDK_ERRORS_H__ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_macros.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_macros.h new file mode 100644 index 0000000..f916b6e --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_macros.h @@ -0,0 +1,72 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @cond */ +/**@file + * + * @ingroup sdk_util + * @defgroup sdk_common_macros SDK Common Header + * @breif Macros for parameter checking and similar tasks + * @{ + */ + +#ifndef SDK_MACROS_H__ +#define SDK_MACROS_H__ + +/**@brief Macro for verifying that the module is initialized. It will cause the function to return + * @ref NRF_ERROR_INVALID_STATE if not. + */ +#ifdef DISABLE_PARAM_CHECK +#define VERIFY_MODULE_INITIALIZED() +#else +#ifdef MODULE_INITIALIZED +#define VERIFY_MODULE_INITIALIZED() \ +do \ +{ \ + if (!MODULE_INITIALIZED) \ + { \ + return NRF_ERROR_INVALID_STATE; \ + } \ +} while(0) +#else +#define VERIFY_MODULE_INITIALIZED() +#endif /* MODULE_INITIALIZED */ +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying that the module is initialized. It will cause the function to return + * if not. + */ +#ifdef DISABLE_PARAM_CHECK +#define VERIFY_MODULE_INITIALIZED_VOID() +#else +#ifdef MODULE_INITIALIZED +#define VERIFY_MODULE_INITIALIZED_VOID() \ +do \ +{ \ + if (!MODULE_INITIALIZED) \ + { \ + return; \ + } \ +} while(0) +#else +#define VERIFY_MODULE_INITIALIZED_VOID() +#endif /* MODULE_INITIALIZED */ +#endif /* DISABLE_PARAM_CHECK */ + + + + +/** @} */ +/** @endcond */ +#endif // SDK_MACROS_H__ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.c b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.c new file mode 100644 index 0000000..697dd3f --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.c @@ -0,0 +1,161 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "sdk_mapped_flags.h" +#include +#include +#include +#include "compiler_abstraction.h" + + +/**@brief Function for setting the state of a flag to true. + * + * @note This function does not check whether the index is valid. + * + * @param[in] p_flags The collection of flags to modify. + * @param[in] index The index of the flag to modify. + */ +static __INLINE void sdk_mapped_flags_set_by_index(sdk_mapped_flags_t * p_flags, uint16_t index) +{ + *p_flags |= (1U << index); +} + + +/**@brief Function for setting the state of a flag to false. + * + * @note This function does not check whether the index is valid. + * + * @param[in] p_flags The collection of flags to modify. + * @param[in] index The index of the flag to modify. + */ +static __INLINE void sdk_mapped_flags_clear_by_index(sdk_mapped_flags_t * p_flags, uint16_t index) +{ + *p_flags &= ~(1U << index); +} + + +/**@brief Function for getting the state of a flag. + * + * @note This function does not check whether the index is valid. + * + * @param[in] p_flags The collection of flags to read. + * @param[in] index The index of the flag to get. + */ +static __INLINE bool sdk_mapped_flags_get_by_index(sdk_mapped_flags_t flags, uint16_t index) +{ + return ((flags & (1 << index)) != 0); +} + + + +uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags) +{ + for (uint16_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) + { + if (sdk_mapped_flags_get_by_index(flags, i)) + { + return i; + } + } + return SDK_MAPPED_FLAGS_INVALID_INDEX; +} + + +void sdk_mapped_flags_update_by_key(uint16_t * p_keys, + sdk_mapped_flags_t * p_flags, + uint16_t key, + bool value) +{ + sdk_mapped_flags_bulk_update_by_key(p_keys, p_flags, 1, key, value); +} + + +void sdk_mapped_flags_bulk_update_by_key(uint16_t * p_keys, + sdk_mapped_flags_t * p_flags, + uint32_t n_flag_collections, + uint16_t key, + bool value) +{ + if ((p_keys != NULL) && (p_flags != NULL) && (n_flag_collections > 0)) + { + for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) + { + if (p_keys[i] == key) + { + for (uint32_t j = 0; j < n_flag_collections; j++) + { + if (value) + { + sdk_mapped_flags_set_by_index(&p_flags[j], i); + } + else + { + sdk_mapped_flags_clear_by_index(&p_flags[j], i); + } + } + return; + } + } + } +} + + +bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key) +{ + if (p_keys != NULL) + { + for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) + { + if (p_keys[i] == key) + { + return sdk_mapped_flags_get_by_index(flags, i); + } + } + } + return false; +} + + +sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t * p_keys, + sdk_mapped_flags_t flags) +{ + sdk_mapped_flags_key_list_t key_list; + key_list.len = 0; + + if (p_keys != NULL) + { + for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) + { + if (sdk_mapped_flags_get_by_index(flags, i)) + { + key_list.flag_keys[key_list.len++] = p_keys[i]; + } + } + } + + return key_list; +} + + +uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags) +{ + uint32_t n_flags_set = 0; + + for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) + { + if (sdk_mapped_flags_get_by_index(flags, i)) + { + n_flags_set += 1; + } + } + return n_flags_set; +} diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.h new file mode 100644 index 0000000..58474c2 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_mapped_flags.h @@ -0,0 +1,153 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef SDK_MAPPED_FLAGS_H__ +#define SDK_MAPPED_FLAGS_H__ + +#include +#include +#include "app_util.h" +#include "compiler_abstraction.h" + +/** + * @file + * @defgroup sdk_mapped_flags Mapped flags + * @ingroup app_common + * @{ + * @brief Module for writing and reading flags that are associated + * with keys. + * + * @details The flags are represented as bits in a bitmap called a flag collection. The keys + * are uint16_t. Each flag collection contains all flags of the same type, one flag for + * each key. + * + * The mapped flags module does not keep the flag states, nor the list of keys. These are + * provided in the API calls. A key's index in the key list determines which bit in the + * flag collection is associated with it. This module does not ever edit the key list, and + * does not edit flags except in function calls that take the flag collection as a pointer. + * + */ + +#define SDK_MAPPED_FLAGS_N_KEYS 8 /**< The number of keys to keep flags for. This is also the number of flags in a flag collection. If changing this value, you might also need change the width of the sdk_mapped_flags_t type. */ +#define SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE 8 /**< The number of flags that fit in one byte. */ +#define SDK_MAPPED_FLAGS_INVALID_INDEX 0xFFFF /**< A flag index guaranteed to be invalid. */ + +typedef uint8_t sdk_mapped_flags_t; /**< The bitmap to hold flags. Each flag is one bit, and each bit represents the flag state associated with one key. */ + + +// Test whether the flag collection type is large enough to hold all the flags. If this fails, +// reduce SDK_MAPPED_FLAGS_N_KEYS or increase the size of sdk_mapped_flags_t. +STATIC_ASSERT(( + sizeof(sdk_mapped_flags_t)*SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE) >= SDK_MAPPED_FLAGS_N_KEYS); + + +/**@brief Type used to present a subset of the registered keys. + */ +typedef struct +{ + uint32_t len; /**< The length of the list. */ + uint16_t flag_keys[SDK_MAPPED_FLAGS_N_KEYS]; /**< The list of keys. */ +} sdk_mapped_flags_key_list_t; + + +/**@brief Function for getting the first index at which the flag is true in the provided + * collection. + * + * @param[in] flags The flag collection to search for a flag set to true. + * + * @return The first index that has its flag set to true. If none were found, the + * function returns @ref SDK_MAPPED_FLAGS_INVALID_INDEX. + */ +uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags); + + +/**@brief Function for updating the state of a flag. + * + * @param[in] p_keys The list of associated keys (assumed to have a length of + * @ref SDK_MAPPED_FLAGS_N_KEYS). + * @param[out] p_flags The flag collection to modify. + * @param[in] key The key to modify the flag of. + * @param[in] value The state to set the flag to. + */ +void sdk_mapped_flags_update_by_key(uint16_t * p_keys, + sdk_mapped_flags_t * p_flags, + uint16_t key, + bool value); + + +/**@brief Function for updating the state of the same flag in multiple flag collections. + * + * @details The key and value are the same for all flag collections in the p_flags array. + * + * @param[in] p_keys The list of associated keys (assumed to have a length of + * @ref SDK_MAPPED_FLAGS_N_KEYS). + * @param[out] p_flags The flag collections to modify. + * @param[out] n_flag_collections The number of flag collections in p_flags. + * @param[in] key The key to modify the flag of. + * @param[in] value The state to set the flag to. + */ +void sdk_mapped_flags_bulk_update_by_key(uint16_t * p_keys, + sdk_mapped_flags_t * p_flags, + uint32_t n_flag_collections, + uint16_t key, + bool value); + + +/**@brief Function for getting the state of a specific flag. + * + * @param[in] p_keys The list of associated keys (assumed to have a length of + * @ref SDK_MAPPED_FLAGS_N_KEYS). + * @param[in] flags The flag collection to read from. + * @param[in] key The key to get the flag for. + * + * @return The state of the flag. + */ +bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key); + + +/**@brief Function for getting a list of all keys that have a specific flag set to true. + * + * @param[in] p_keys The list of associated keys (assumed to have a length of + * @ref SDK_MAPPED_FLAGS_N_KEYS). + * @param[in] flags The flag collection to search. + * + * @return The list of keys. + */ +sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t * p_keys, + sdk_mapped_flags_t flags); + + +/**@brief Function for getting the number of keys that have a specific flag set to true. + * + * @param[in] flags The flag collection to search. + * + * @return The number of keys. + */ +uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags); + + +/**@brief Function for querying whether any flags in the collection are set. + * + * @param[in] flags The flag collection to query. + * + * @retval true If one or more flags are set to true. + * @retval false Otherwise. + */ +static __INLINE bool sdk_mapped_flags_any_set(sdk_mapped_flags_t flags) +{ + return (flags != 0); +} + + +/** @} */ + +#endif /* SDK_MAPPED_FLAGS_H__ */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_os.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_os.h new file mode 100644 index 0000000..5a736c6 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_os.h @@ -0,0 +1,40 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + + /** @cond */ +/**@file + * + * @defgroup sdk_os SDK OS Abstraction + * @ingroup experimental_api + * @details In order to made SDK modules independent of use of an embedded OS, and permit + * application with varied task architecture, SDK abstracts the OS specific + * elements here in order to make all other modules agnostic to the OS or task + * architecture. + * @{ + */ + +#ifndef SDK_OS_H__ +#define SDK_OS_H__ + +#define SDK_MUTEX_DEFINE(X) +#define SDK_MUTEX_INIT(X) +#define SDK_MUTEX_LOCK(X) +#define SDK_MUTEX_UNLOCK(X) + +/** + * @defgroup os_data_type Data types. + */ + +/** @} */ +/** @endcond */ +#endif // SDK_OS_H__ + diff --git a/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_resources.h b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_resources.h new file mode 100644 index 0000000..8d38348 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/libraries/util/sdk_resources.h @@ -0,0 +1,50 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + */ + +/** @file + * @brief Definition file for resource usage by SoftDevice, ESB and Gazell. + */ + +#ifndef APP_RESOURCES_H__ +#define APP_RESOURCES_H__ + +#ifdef SOFTDEVICE_PRESENT + #include "nrf_sd_def.h" +#else + #define SD_PPI_RESTRICTED 0uL /**< 1 if PPI peripheral is restricted, 0 otherwise. */ + #define SD_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by SotfDevice (not available to th spplication). */ + #define SD_PPI_GROUPS_USED 0uL /**< PPI groups utilized by SotfDevice (not available to th spplication). */ + #define SD_TIMERS_USED 0uL /**< Timers used by SoftDevice. */ + #define SD_SWI_USED 0uL /**< Software interrupts used by SoftDevice. */ +#endif + +#ifdef GAZELL_PRESENT + #include "nrf_gzll_resources.h" +#else + #define GZLL_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by Gazell (not available to th spplication). */ + #define GZLL_TIMERS_USED 0uL /**< Timers used by Gazell. */ + #define GZLL_SWI_USED 0uL /**< Software interrupts used by Gazell */ +#endif + +#ifdef ESB_PRESENT + #include "nrf_esb_resources.h" +#else + #define ESB_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by ESB (not available to th spplication). */ + #define ESB_TIMERS_USED 0uL /**< Timers used by ESB. */ + #define ESB_SWI_USED 0uL /**< Software interrupts used by ESB */ +#endif + +#define NRF_PPI_CHANNELS_USED (SD_PPI_CHANNELS_USED | GZLL_PPI_CHANNELS_USED | ESB_PPI_CHANNELS_USED) +#define NRF_PPI_GROUPS_USED (SD_PPI_GROUPS_USED) +#define NRF_SWI_USED (SD_SWI_USED | GZLL_SWI_USED | ESB_SWI_USED) +#define NRF_TIMERS_USED (SD_TIMERS_USED | GZLL_TIMERS_USED | ESB_TIMERS_USED) + +#endif // APP_RESOURCES_H__ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_common_tables.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_common_tables.h new file mode 100644 index 0000000..d5d7241 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. October 2015 +* $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_const_structs.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_const_structs.h new file mode 100644 index 0000000..54595f5 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_math.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_math.h new file mode 100644 index 0000000..580cbbd --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/arm_math.h @@ -0,0 +1,7154 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 20. October 2015 +* $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc.h new file mode 100644 index 0000000..f2bb66a --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc_V6.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc_V6.h new file mode 100644 index 0000000..d714e9b --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_gcc.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_gcc.h new file mode 100644 index 0000000..d868f2e --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0.h new file mode 100644 index 0000000..fdee521 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0plus.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0plus.h new file mode 100644 index 0000000..7614450 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm3.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm3.h new file mode 100644 index 0000000..34ed84c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm4.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm4.h new file mode 100644 index 0000000..01cb73b --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm7.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm7.h new file mode 100644 index 0000000..20963c1 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmFunc.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmFunc.h new file mode 100644 index 0000000..ca319a5 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmInstr.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmInstr.h new file mode 100644 index 0000000..a0a5064 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmSimd.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmSimd.h new file mode 100644 index 0000000..4d76bf9 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/cmsis/include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/gcc_startup_nrf52.S b/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/gcc_startup_nrf52.S new file mode 100644 index 0000000..a321e72 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/gcc_startup_nrf52.S @@ -0,0 +1,524 @@ +/* Copyright (c) 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + .syntax unified + .arch armv7e-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 8192 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 8192 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SVC_Handler + .long DebugMonitor_Handler + .long 0 /*Reserved */ + .long PendSV_Handler + .long SysTick_Handler + + /* External Interrupts */ + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .long NFCT_IRQHandler + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_EGU2_IRQHandler + .long SWI3_EGU3_IRQHandler + .long SWI4_EGU4_IRQHandler + .long SWI5_EGU5_IRQHandler + .long TIMER3_IRQHandler + .long TIMER4_IRQHandler + .long PWM0_IRQHandler + .long PDM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long MWU_IRQHandler + .long PWM1_IRQHandler + .long PWM2_IRQHandler + .long SPIM2_SPIS2_SPI2_IRQHandler + .long RTC2_IRQHandler + .long I2S_IRQHandler + .long FPU_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to. + * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ + * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__bss_start__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 + +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + bl SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler,.-Reset_Handler + + .section ".text" + + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + + .weak MemoryManagement_Handler + .type MemoryManagement_Handler, %function +MemoryManagement_Handler: + b . + .size MemoryManagement_Handler, . - MemoryManagement_Handler + + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + + .weak DebugMonitor_Handler + .type DebugMonitor_Handler, %function +DebugMonitor_Handler: + b . + .size DebugMonitor_Handler, . - DebugMonitor_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ POWER_CLOCK_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + IRQ NFCT_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ SWI2_EGU2_IRQHandler + IRQ SWI3_EGU3_IRQHandler + IRQ SWI4_EGU4_IRQHandler + IRQ SWI5_EGU5_IRQHandler + IRQ TIMER3_IRQHandler + IRQ TIMER4_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + IRQ MWU_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM2_IRQHandler + IRQ SPIM2_SPIS2_SPI2_IRQHandler + IRQ RTC2_IRQHandler + IRQ I2S_IRQHandler + IRQ FPU_IRQHandler + + .end diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_common.ld b/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_common.ld new file mode 100644 index 0000000..75e2f4c --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_common.ld @@ -0,0 +1,160 @@ +/* Linker script for Nordic Semiconductor nRF52 devices + * + * Version: Sourcery G++ 4.5-1 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_xxaa.ld b/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_xxaa.ld new file mode 100644 index 0000000..bc89f44 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf52_xxaa.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 +} + + +INCLUDE "nrf52_common.ld" diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf5x_common.ld b/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf5x_common.ld new file mode 100644 index 0000000..69c98f8 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/nrf5x_common.ld @@ -0,0 +1,160 @@ +/* Linker script for Nordic Semiconductor nRF51 devices + * + * Version: Sourcery G++ 4.5-1 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.c b/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.c new file mode 100644 index 0000000..18c0754 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.c @@ -0,0 +1,301 @@ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +#include +#include "nrf.h" +#include "system_nrf52.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK_64M (64000000UL) + +static bool errata_16(void); +static bool errata_31(void); +static bool errata_32(void); +static bool errata_36(void); +static bool errata_37(void); +static bool errata_57(void); +static bool errata_66(void); + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_16()){ + *(volatile uint32_t *)0x4007C074 = 3131961357ul; + } + + /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_31()){ + *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; + } + + /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_32()){ + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } + + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + + /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_37()){ + *(volatile uint32_t *)0x400005A0 = 0x3; + } + + /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_57()){ + *(volatile uint32_t *)0x40005610 = 0x00000005; + *(volatile uint32_t *)0x40005688 = 0x00000001; + *(volatile uint32_t *)0x40005618 = 0x00000000; + *(volatile uint32_t *)0x40005614 = 0x0000003F; + } + + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, + two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as + normal GPIOs. */ + #if defined (CONFIG_NFCT_PINS_AS_GPIOS) + if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[0] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[1] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product + Specification to see which one). */ + #if defined (ENABLE_SWO) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + SystemCoreClockUpdate(); +} + + +static bool errata_16(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; + } + } + + return false; +} + +static bool errata_31(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) + { + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) + { + return true; + } + } + + return false; +} + +static bool errata_32(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; + } + } + + return false; +} + +static bool errata_36(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) + { + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) + { + return true; + } + } + + return false; +} + +static bool errata_37(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; + } + } + + return false; +} + +static bool errata_57(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; + } + } + + return false; +} + +static bool errata_66(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) + { + return true; + } + } + + return false; +} + + +/*lint --flb "Leave library region" */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.h new file mode 100644 index 0000000..d16037f --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.h @@ -0,0 +1,69 @@ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef SYSTEM_NRF52_H +#define SYSTEM_NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52_H */ diff --git a/nRF5_SDK_11.0.0_89a8197/documentation/license.txt b/nRF5_SDK_11.0.0_89a8197/documentation/license.txt new file mode 100644 index 0000000..2322a73 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/documentation/license.txt @@ -0,0 +1,117 @@ +This text contains two licenses (License #1, License #2). +License #1 applies to the whole SDK, except i) files including Dynastream copyright notices and ii) source files including BSD 3-clause license texts. +License #2 applies only to files including Dynastream copyright notices. +All must be read and accepted before proceeding. + + +License #1 + +License Agreement +Nordic Semiconductor ASA ("Nordic") +Software Development Kit + + +You ("You" or "Licensee") must carefully and thoroughly read this License Agreement ("Agreement"), and accept to adhere to this Agreement before downloading, installing and/or using any software or content in the Software Development Kit ("SDK") provided herewith. + +YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SDK, IN THIS CASE YOU AGREE THAT THE USE OF THE SDK CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS. + +IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SDK OR RELATED CONTENT. + + +1. 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The ANT+ Network Key is available to ANT+ Adopters. + Please refer to http://thisisant.com to become an ANT+ + Adopter and access the key. + + 2) Reverse engineering, decompilation, and/or disassembly of + software provided in binary form under this license. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE HEREBY +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; DAMAGE TO ANY DEVICE, LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +OF THE POSSIBILITY OF SUCH DAMAGE. SOME STATES DO NOT ALLOW +THE EXCLUSION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES, SO THE +ABOVE LIMITATIONS MAY NOT APPLY TO YOU. diff --git a/nRF5_SDK_11.0.0_89a8197/documentation/release_notes.txt b/nRF5_SDK_11.0.0_89a8197/documentation/release_notes.txt new file mode 100644 index 0000000..09e8346 --- /dev/null +++ b/nRF5_SDK_11.0.0_89a8197/documentation/release_notes.txt @@ -0,0 +1,3267 @@ +nRF5 SDK v11.0.0 +---------------- +Release date: Week 10, 2016 + +Highlights: +- Combined SDK supporting both the nRF51 and the nRF52 Series +- Moved Peer Manager out of experimental +- Moved NFC libraries out of experimental and added support for low + power mode +- Added drivers for all nRF52 peripherals +- Added serialization of the S132 and S130 SoftDevices +- Added support for SoftDevices S130 v2.0.0, S132 v2.0.0, S212 v0.9.x, + and S332 v0.9.x +- Replaced the Enhanced ShockBurst library with a new implementation + (based on µESB) +- Included a critical MDK update (v8.5.0) +- Removed support for CMSIS Packs + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.16a +- GCC: GCC ARM Embedded 4.9 2015q1 +- IAR: IAR Workbench 7.30.4 + +Supported SoftDevices: +- S130 v2.0.0 +- S132 v2.0.0 +- S212 v0.9.x +- S332 v0.9.x + +Supported IC revisions: +- nRF51 IC revision 3 +- nRF52 IC revision 1 +- nRF52 Engineering C +- nRF52 Engineering A and Engineering B (see Compatibility) + +Supported boards: +- PCA10028 +- PCA10031 +- PCA10036 (see Compatibility) +- PCA10040 (see Compatibility) +- PCA20006 (only for beacon examples) +For other devices and boards, see the SDK documentation, section +"Using the SDK with other boards". + +Compatibility: +The SoftDevices that are supported in this SDK are not compatible +out-of-the-box with nRF52 Engineering A and Engineering B (the +IC revisions present on all versions of PCA10036 and on PCA10040 +v0.9.0). +However, you can use the latest SoftDevices on Engineering A and B +nRF52 chips for development purposes if you implement the +workaround for anomaly 73 (TIMER: Event lost, see +http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52/dita/nrf52/errata.html). + +*** New features +**************** + +** Drivers and libraries ** +- Added a COMP driver (nRF52 only) + +** BLE ** +- Extended the Peer Manager functionality: + - Added an additional data unit (Peer Rank) that can be used for + tracking which bonds are most (and least) recently used + - Added support for LE Secure Connections in Peer Manager + (experimental) +- Added an example application for LE Secure Connections (experimental, + support for Keil5, IAR, and GCC only) + +** ANT ** +- Added new examples (experimental): + - Advanced Burst + - Asynchronous Transmitter + - Continuous Scanning Controller + - Debug Demo + - IO Demo + - Message Types + - Search Sharing + - Search Uplink +- ANT OTA bootloader application now uses the SoCLibrary API to perform + NVIC operations instead of direct operations +- Added multiprotocol examples for the S332 SoftDevice: + - Heart Rate Monitor Relay Application + - Shared Channels (experimental) + +** Serialization ** +- Added serialization of the S130 and S132 v2.0.0 SoftDevices + +** NFC ** +- Added a generic NDEF message parser that can parse NDEF messages to + the format that is used by the generic NFC NDEF message builder +- Added a module and example for creating NDEF text records +- Added and modified NFC pairing examples (experimental): + - HID Keyboard Application with BLE pairing using NFC (new) + - Heart Rate Application with BLE pairing using NFC (improved user + experience) + +** Proprietary ** +- Added a Low Power Transmitter/Receiver example for ESB + +*** Changes +*********** + +** Overall ** +- Support for CMSIS Packs has been removed. The SDK is delivered as zip + file only. + +** Drivers and libraries ** +- The MSB and LSB macros have been renamed to MSB_32 and LSB_32. Code + using these macros should be changed to use either the 16- or the + 32-bit variant. + +** BLE ** +- Multi-instance handling of Service client modules has been greatly + improved. The client examples now handle service discovery in the main + application context. The main application context must manage which + client instance belongs to which connection link. +- The Multi-link Example has been modified to demonstrate multiple + client instances in a better way. +- The ble_app_multilink_peripheral example has been removed. + ble_app_blinky now acts as the peripheral for ble_app_multilink_central. +- Heart Rate Application with RTX: Support for nRF52 has been removed. +- The Peer Manager is no longer experimental. +- The following BLE examples now use Peer Manager: + - Central: + Running Speed and Cadence Collector (ble_app_rscs_c) + - Central and Peripheral: + BLE Relay (ble_app_hrs_rscs_relay) + BLE LE Secure Connections Multirole (ble_app_multirole_lesc) + - Peripheral: + Alert Notification (ble_app_alert_notification) + Proximity (ble_app_proximity) + Glucose (ble_app_gls) + HID Keyboard Application with BLE pairing using NFC (experimental_ble_app_hids_keyboard_pairing_nfc) +- The behavior of Peer Manager and Device Manager has changed to reject + pairing requests from already bonded peer centrals. +- Several BLE peripheral examples now support the S332 SoftDevice. +- Minor bugfixes in DFU. + +** ANT ** +- The ANT bootloader was aligned to MBR version 2.0.0. +- The following ANT examples now support the S332 SoftDevice + (experimental): + - ANT Bootloader/DFU + - Message Types + +** NFC ** +- The Adafruit Tag Reader Example has been extended to show added NDEF + parsing functionality. +- The NFC Type 2 Tag HAL was improved with a workaround for supporting + low power mode. + +** Proprietary ** +- A new implementation of the Enhanced ShockBurst (ESB) protocol + supporting both nRF51 and nRF52 has been added. + +*** Fixed issues +**************** + +** Drivers and libraries ** +- GPIOTE: Fixed the problem of lost events in low-accuracy sense toggle + mode +- SAADC: Added functionality to use one AIN with multiple channels +- UART: Fixed a glitch on TX pin when initializing the driver +- UART: Fixed the problem that TX bytes were sent in wrong order in + app_uart_fifo + +** BLE ** +- Removed a vulnerability in Peer Manager and Device Manager that would + allow malicious attackers to overwrite the bonding information of a + bonded device + +** ANT ** +- Fixed the handling of send-until-success request types in the ANT + request controller +- Fixed an ant_evt_t structure member alignment bug + +** NFC ** +- Fixed the NFC examples to work when the UART logger is enabled +- Fixed a buffer leakage bug in the module for creating + application/vnd.bluetooth.le.oob records + +*** Known issues +**************** + +** Drivers and libraries ** +- Using the NVIC API directly and not through a SoftDevice causes + problems, especially when NVIC_EnableIRQ or NVIC_DisableIRQ are called + from critical sections. + +** BLE ** +- All BLE examples have been tested only on PCA10028 and PCA10040. +- BLE Examples that use pairing are incompatible with examples in SDK + version 6.1 and earlier that do not use pairing. + +** ANT ** +- Previous versions of the ANT DFU example are incompatible with the ANT + S212/S332 SoftDevices version 0.9.x. + +** NFC ** +- NFCT requires using TIMER4 on nRF52832. + +** FPU ** +- When the FPU is in use, it triggers the FPU_IRQn interrupt when one of + the six exception flags (IDC, IXC, UFC, OFC, DZC, IOC) is set. + The FPU interrupt will always set the pending flag (even if the + interrupt is not enabled), irrespective of whether the user is + interested in the exception bit. + The pending flag then prevents the SoftDevice from going into low + power mode when sd_app_evt_wait() is called. + Therefore, always clear the exception bits and the pending interrupt + before calling sd_app_evt_wait(). See the code below for an example + implementation. + FPU exception bit definition: + http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/BABBFJEC.html + Example code: + { + // Set bit 7 and bits 4..0 in the mask to one (0x ...00 1001 1111) + #define FPU_EXCEPTION_MASK 0x0000009F + + ... + /* Clear exceptions and PendingIRQ from the FPU unit */ + __set_FPSCR(__get_FPSCR() & ~(FPU_EXCEPTION_MASK)); + (void) __get_FPSCR(); + NVIC_ClearPendingIRQ(FPU_IRQn); + + /* Call SoftDevice Wait For event */ + error_code = sd_app_evt_wait(); + } + + +======================================================================== + +nRF5 SDK v11.0.0-2.alpha +------------------------ +Release date: Week 51, 2015 + +Highlights: +- Common SDK supporting both the nRF51 and the nRF52 Series +- Added support for SoftDevices S130 v2.0.0, S132 v2.0.0, and S212 v0.5.1 +- Permanently removed support for SoftDevices S110 and S120 +- Temporarily removed support for ANTBLE SoftDevices +- Enhanced Peer Manager and FDS modules +- Enhanced DFU module +- Configured nrf_log to use UART by default +- Added HardFault handler +- Added drivers for nRF52 peripherals: nrf_drv_i2s, nrf_drv_pdm, + nrf_drv_pwm +- Enhanced drivers to work for both nRF51 and nRF52: nrf_drv_twi, + nrf_drv_spi, nrf_drv_uart, nrf_drv_timer, nrf_drv_ppi, nrf_drv_clock +- Added FreeRTOS and RTX support for nRF52 +- Added NFC modules: Type 2 Tag parser, generic NDEF message builder, + new NFC records and messages +- Added support for Adafruit PN532 NFC shield to provide NFC Forum + Device (Poller) functionality +- Improved support for NFC: enhanced NFC Type 2 Tag library and + Connection Handover module + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.16a +- GCC: GCC ARM Embedded 4.9 2015q1 +- IAR: IAR Workbench 7.30.4 +- Windows XP SP3 32-bit +- Windows 7 SP1 64-bit +- Windows 8.1 + +Supported SoftDevices: +- S130 v2.0.0-7.alpha +- S132 v2.0.0-7.alpha +- S210 v5.0.0 +- S212 v0.5.1.alpha + +Supported boards: +- PCA10028 +- PCA10031 +- PCA10036 +- PCA10040 +- PCA20006 (only for beacon examples) +- Dynastream's N5DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +Drivers and libraries: + + New features: + - Added driver and example for PWM peripheral (nrf_drv_pwm). + - Added driver and example for I2S peripheral (nrf_drv_i2s). + - Added driver for PDM peripheral (nrf_drv_pdm). + - Enhanced nrf_drv_twi and nrf_drv_spi to support AUTOLOG and + triggering transfers from PPI. + - Added double buffering of RX buffers to nrf_drv_uart. + - Extended nrf_drv_timer to support more compare channels and low + power counter mode in nRF52. + - Extended nrf_drv_ppi API to support forks. + - Added support for FreeRTOS and RTX on nRF52. + - Simplified SPI and SPIS examples. + + Fixed issues: + - In certain cases, FreeRTOS on nRF51 kept interrupts disabled after + context switch (see https://devzone.nordicsemi.com/question/57993/tickless-freertos-in-sdk-100-app_uart). + + Known issues: + - The FreeRTOS nRF51 port has a wrong assertion during system startup. + If you are using assertions, you can safely ignore it. Alternatively, + comment out line 188 in port_cmsis.c. + + Changes: + - Enhanced nrf_drv_clock driver (asynchronous clock management). + + +Serialization: + + - Work in progress; not included in this release. + + +ANT: + + New features: + - Added support for the S212 SoftDevice v0.5.1.alpha. + - Added ANT DFU support for nRF52. + + Known issues: + - When using the ANT OTA Updater v1.2. for nRF52, there is a flash + memory address limitation of 0x40000 (256 KB) for the application. + + +BLE: + + Changes: + - All BLE examples have been tested only on PCA10028 and PCA10040. + - The S13x SoftDevice v2.0.0-7.alpha is configurable, which leads to a + variable RAM setup: + - Added a macro to the softdevice_handler module to check the RAM + configuration against the SoftDevice parameters. + - Added a wrapper function for the sd_enable function to the + softdevice_handler module, which can output the required RAM + start address if the one passed to the SoftDevice is not + correct. + - DFU: + - Added an experimental nRF52 bootloader. + - Updated the SoftDevice initalization according to API changes in + S132 v2.0.0-7.alpha. + - Updated to MBR version v2.0.0-1 alpha. + - Introduced nrf_log as default logging module (UART) in all BLE + examples. + - Peer Manager & FDS have received incremental improvements and bug + fixes. + + Known issues: + - In the HRS/RSCS Relay example, button presses do not have any effect. + - ble_app_cts_c requires an increased UART_TX_BUF_SIZE. The size can be + set in nrf_log.c. + - DTM for nRF52 does not support long packets according to the + Bluetooth 4.2 specification. + - Inconsistent behavior in DFU with devices running Android v6.0.1. + - The BLE and serial DFU examples do not work when using CMSIS Packs. + Use the zip version of the SDK instead. + + +NFC: + + New features: + - Added a Type 2 Tag parser. + - Added a generic NFC NDEF message builder (the builder is used to + implement all specific records and messages). + - Added modules to create Windows LaunchApp records, Android + Application Records, and common application launch messages. Added + an associated example. + - Ported the Adafruit NFC library for the Adafruit PN532 Shield, which + provides NFC Forum Device capabilities. Added an associated example + to read tags. + - Added modules to create application/vnd.bluetooth.le.oob records, + application/vnd.bluetooth.ep.oob records, ac records, Hs records, + and BLE pairing messages. + + Changes: + - Improved the NFC Type 2 Tag library: tested and power-optimized the + library and enhanced it with RTT logger capability. + - Re-implemented NFC URI record and message. Refactored the associated + example. + - Enhanced and re-implemented the NFC Connection Handover solution + (pairing using NFC). + - Re-implemented the BLE NFC pairing example. + + Known issues: + - NFC examples do not work when UART logger is enabled. + + +======================================================================== + +nRF51 SDK v10.0.0 +----------------- +Release date: Week 46, 2015 + +Highlights: + - New BLE Peer Manager (experimental), replacement for the BLE Device + Manager + - FreeRTOS support + - New ANT modules, additional examples, and new and expanded ANT+ + profiles + - Support for Dynastream's N5 Starter Kit + - Three new BLE Services + - Precompiled HEX files + +The following toolchains/devices have been used for testing and +verification: + - ARM: MDK-ARM version 5.14.0.0 and 5.16a + - GCC: GCC ARM Embedded 4.9 2015q1 + - IAR: IAR Workbench 7.30.4 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported SoftDevices: + - S110 v8.0.0 + - S120 v2.1.0 + - S130 v1.0.0 + - S210 v5.0.0 + - S310 v3.0.0 + +Supported boards: + - PCA10028 + - PCA10031 + - Dynastream's N5DK1 (only for ANT examples) + + For other devices and boards, see the SDK documentation, section "Using + the SDK with other boards". + +Changes: + + Drivers and libraries: + New features: + - Ported FreeRTOS to run on nRF51. Added two FreeRTOS examples: one + to run on bare metal and one running a BLE HRS example using the + S110 and S130 SoftDevices. + - Added a TWI transaction manager module for managing access to an + I2C bus. Added an example that uses this module to control two + sensors on the same I2C bus. + - Added an example that shows how to use the TWI driver. + - Added a low-power PWM module (software-controlled low-accuracy + PWM). Added an example that shows how to use this module. + - Added an LED softblink module that uses the low-power PWM. Added + an example that shows how to use this module. + - Ported app_uart to use the UART driver and moved it to the + libraries folder. + - Ported app_gpiote to use the GPIOTE driver. + - Added nrf_log, a logging module that supports printf and that can + use either UART or SEGGER RTT as transport medium. + Fixed issues: + - Mailbox module moved out of serialization. + - Bug fixes in app_timer module. + - App_timer module no longer requires to define the number of + timers used in the application. + - Bug fixes in PWM module. + Changes: + - FIFO library: Extended APIs for multi-byte read and write to the + FIFO. + - Memory Manager module: + - Extended number of block categories to 7 (from 3). + - More RAM-efficient management of memory blocks. + - Added a diagnostic function to help determine the right + configuration needed for the application. + + Serialization: + New features: + - Added a command for resetting the connectivity chip. + + ANT: + New features: + - Added the following new ANT modules: + - ant_encryption + - ant_key_manager + - ant_search_config + - Extended/changed the following existing ANT modules: + - ant_channel_config + - ant_stack_config + - ant_state_indicator + - Refactored the ANT/ANT+ examples and profiles to make them look more + similar to the BLE profiles and examples: + - The following ANT+ profiles have been extracted and extended: + Bicycle Power (ant_bpwr), Bicycle Speed & Cadence (ant_bsc), + Stride Based Speed & Distance (ant_sdm) + - All ANT+ examples have been refactored to use extracted + profiles. + - All ANT+/ANT examples have been refactored to use created + modules. + - Added three new ANT examples: + - ant_scalable + - ant_scalable_encrypted + - ant_scan_and_forward + + BLE: + - Added an experimental module named Peer Manager. This module will + eventually replace the existing Device Manager. The new Peer Manager + improves on the Device Manager in multiple ways, mainly by + supporting concurrent central and peripheral connections. + - Added an experimental flash memory module named Flash Data Storage + (FDS), which greatly reduces the need for time-consuming write and + clear operations. When using FDS, data can be arbitrarily long or + short (within about a page). All pieces of data are tagged with + types, which makes it easy to version data. + - Updated the experimental HRS/RSCS Relay example: + - It now uses the new Peer Manager instead of the Device Manager. + Therefore, it now supports bonding in both central and peripheral + roles. + - It uses the new nrf_log module, which can use SEGGER RTT. + - Removed the app_s130_demo example. + - Added an experimental example supporting the Eddystone beacon + format. + - Added the BLE Connection State module, which keeps track of certain + states of each connection (for example, whether it is encrypted) and + can also keep track of user-defined states. + - Added the Mapped Flags module, which keeps track of flags that are + mapped to keys. It is used by the BLE Connection State module. + - Added ble_gatt_db.h (containing a GATT service structure) and + modified ble_db_discovery module to use it. + BLE Services: + - Updated the Bluetoothds_template application (experimental) to be + compatible with Bluetooth Developer Studio v1.0 and the Nordic + Semiconductor NRF5X v1.1.8 plugin. + - Added three new services: + - Location Navigation Service (experimental) + - Proprietary LED Button Service (experimental) + - Nordic UART Client Service (experimental) + +Fixed issues: + - App_pwm occasionally gives inverted signal. + +Known issues: + - Device Manager is not supported in multi-role S130 operation. + - Device Manager works in peripheral or central only operation on + S130. This must be decided at compile time. + - The DFU over BLE example has been tested to work with a minimum + connection interval of 11.25 ms. The application cannot handle + connection intervals lower than 11.25 ms and may undergo a system + reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware + update process, consider increasing the connection + interval used by the master. + - The old manual procedure for testing buttonless DFU, as specified in + the documentation, can lead to the DFU process hanging or returning + an error when used with Master Control Panel 3.8 and newer. + - Bootloader binaries (.bin files) generated with the GCC makefile + should not be used. Instead, generate the bootloader bin files using + nrfutils, found on GitHub. + +======================================================================== + +nRF52 SDK v0.9.2 +---------------- +Release date: Week 42, 2015 + +This is an amendment to nRF52 SDK v0.9.1. + +Highlights: + - New targets to enable the two near field communication (NFC) + examples to run on the new PCA10040 development board with + nRF52832 IC rev. Engineering B. + +Libraries: + - Extended the NFC HAL layer of the NFC library to support the NFCT + peripherial for both the chip version delivered with the nRF52 + Preview Development Kit (Engineering A: QFAA-AA0, QFAA-AC0, + CGAA-AA0) and the chip version delivered with the nRF52 Development + Kit (Engineering B: QFAA-BA0, QFAA-BB0, CHAA-AA0, CHAA-AB0). + +Examples: + - Added PCA10040 as target bord for the following examples: + - Heart Rate Example with pairing over NFC + - NFC URL Record Application + +Known issues/workarounds: + - To use the software workarounds implemented for PCA10036 (part + of nRF52 Preview Development Kit), globally define + HAL_NFC_ENGINEERING_A_FTPAN_WORKAROUND in your project. + - The TIMER4 peripheral is used to implement one of the workarounds + for PCA10036. This workaround is not used for PCA10040. + - The ble_app_hrs_pairing_nfc example is unable to wake up from + system off. + +======================================================================== + +nRF52 SDK v0.9.1 +---------------- +Release date: Week 29, 2015 + +This is an amendment to nRF52 SDK v0.9.0. + +Highlights: + - Support for near field communication (NFC) + +Libraries/Services: + - Added a library that supports Type 2 NFC-A tag functionality in + read-only state + - Added a module to generate NFC NDEF messages for BLE pairing over NFC + - Added a module to generate NFC NDEF messages with an URI record type + - Extended the ble_advdata module + +Examples: + - Added ble_app_hrs_pairing_nfc example that demonstrates pairing over + NFC (with S132 SoftDevice) + - Added record_url NFC example that demonstrates exposing a URL record + (without SoftDevice) + +Limitations: + - The current version of the NFC library uses TIMER4. + - The ble_app_hrs_pairing_nfc example has been tested only with Samsung + Galaxy S6. + - If the path to the SDK directory is too long, compilation in Keil fails. + To work around this problem, move the SDK higher in the folder tree + or use shorter folder names. + +======================================================================== + +nRF51 SDK v9.0.0 +---------------- +Release Date: Week 28, 2015 + +Highlights: + - Support for S210 SoftDevice v5.0.0 + - Support for S310 SoftDevice v3.0.0 + - Documentation moved to Infocenter + - DFU Signing using Elliptic Curve Cryptography added as experimental + - Available in the zip file only + - Running Speed and Cadence relay example showing concurrent + central/peripheral functionality of S130 + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM version 5.14.0.0 + - GCC: GCC ARM Embedded 4.9 2015q1 + - IAR: IAR Workbench 7.20 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported SoftDevices: + - S110 v8.0.0 + - S120 v2.1.0 + - S130 v1.0.0 + - S210 v5.0.0 + - S310 v3.0.0 + +Supported boards: + - PCA10028 + - PCA10031 + + For other devices and boards, see the SDK documentation, section + "Using the SDK with other boards". + +Changes: + + - Flash access module has been refactored (pstorage). + + ANT: + - Both the S310 and the S210 SoftDevices now support an extended + number of ANT channels (16). + + + Libraries: + - Heart Rate Monitor Profile + - ANT stack configuration + - ANT channel configuration + - ANT channel state indicator + - ANT pulse simulator + + Examples: + - The ANT HRM examples have been refactored. + - The Bicycle Power examples (ant_bicycle_pwr) support S310. + + ANT + BLE (S310): + The following examples were added: + - Bluetooth LE and ANT combined heart rate example (ble_ant_app_hrm). + - Experimental ANT Shared Channels (experimental_ant_shared_channel_master_to_master, + experimental_ant_shared_channel_slave). + + BLE: + - Advertising module has a new mode: Low Duty Cycle Directed Advertising. + - Running Speed and Cadence Client added as experimental. + - Bluetooth Developer Studio template added as experimental. + - Heart Rate Sensor example (ble_app_hrs) supports S310. + - Running Speed and Cadence example (ble_app_rscs) supports S310. + - Combined Peripheral and Central example added as experimental. + - DFU Signing using Elliptic Curve Cryptography added as experimental + (using the same elliptic curve and hashing algorithm as Bluetooth + Low Energy 4.2 Secure Connections). + +Fixed issues: + - Pstorage now supports updates of bond split across two pages. + - Advertising module can be set to infinite time-out. + - Corrected clock source in BLE multiactivity beacon example. + - Serialization HCI transport layer: Receiving packet-buffer is not + freed while sending ACK or NACK. + +Known issues: + - Device Manager is not supported in multi-role S130 operation. + - Device Manager works in peripheral or central only operation on + S130. This must be decided at compile time. + - The DFU over BLE example has been tested to work with a minimum + connection interval of 11.25 ms. The application cannot handle + connection intervals lower than 11.25 ms and may undergo a system + reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware + update process, consider increasing the connection interval used + by the master. + - App_pwm occasionally gives inverted signal. + - The old manual procedure for testing buttonless DFU, as specified in + the documentation, can lead to the DFU process hanging or returning + an error when used with Master Control Panel 3.8 and newer. + +======================================================================== + +nRF52 SDK v0.9.0 +---------------- +Release date: 17.06.2015 + +Highlights: + - Support for PCA10036 board v1.0.0 with nRF52832 QFAAAA + - Support for S132 SoftDevice v1.0.0-3.alpha (hex included) + - Support for S212 SoftDevice v0.2.0-1.alpha + - Support for Keil5 without CMSIS Packs + - Support for GCC + - Same structure as nRF51 SDK v8.1.0 + - New peripheral drivers + - Documentation moved to Infocenter + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM version 5.14.0.0 + - GCC: GCC ARM Embedded 4.9 2015q1 + - Windows 7 SP1 64-bit + +Supported SoftDevices: + - S132 v1.0.0-3.alpha + - S212 v0.2.0-1.alpha + +Supported boards: + - PCA10036 v1.0.0 + +Examples: + - Most examples are ported from nRF51 SDK v8.1.0 + - BLE examples run with the S132 SoftDevice + - ANT examples run with the S212 SoftDevice + - The following examples are included: + - BLE peripheral examples + - BLE central example + - New BLE combined central and peripheral example + - ANT examples + - HW peripheral examples + - New SAADC example + - New TWI master with TWI slave example + - BLE/serial DFU bootloader + - Direct Test Mode Application + +Drivers: + - Includes all drivers from nRF51 SDK v8.1.0 + - New drivers: + - SPI driver that supports SPI and SPIM + - UART driver that supports UART and UARTE + - SAADC HAL driver + - TWI slave driver + - SAADC driver + +Libraries/Services: + - Same functionality as for nRF51 SDK v8.1.0 + - The following libraries and services are included: + - BLE libraries + - BLE Services + - Transport Services + - Other libraries/components + +Known issues: + - Device might reset when a Bluetooth link layer procedure and flash operation happens in parallel. + - Inconsistent behavior with Nexus devices running Android v5.1.1, for example: + - DFU fails + - Link loss might reset the nRF52 device + (such behavior might occur with other devices as well) + - After a power cycle, a UART lockup between Segger J-Link and nRF52 might occur + - Before a serial DFU operation or DTM can be executed, "nrfjprog --reset" must be run + +======================================================================== + +nRF51 SDK v. 8.1.1 +------------------ +This is a supplement to the nRF51 SDK v8.1.0 release notes. +This release does not include any code changes compared to nRF51 SDK v8.1.0., except for a minor addition that is described in the "Changes" section. + +Fixed issues: + + - Project does not compile if nrf_drv_ppi is used together with SoftDevice S110, S120 or S210. + Issue exists only in CMSIS PACK release. + +Changes: + - Released new SoftDevice packs: nRF_SoftDevice_S110.8.0.1, nRF_SoftDevice_S120.2.0.1 and + nRF_SoftDevice_S210.4.0.1-5 with updated nrf_sd_def.h. + +Supported SoftDevices: + - S110 8.0.0 + - S120 2.0.0 + - S130 1.0.0 + - S210 4.0.1 + +======================================================================== + +nRF51 SDK v8.1.0 +---------------- + +Highlights: + - Support for SoftDevice S130 v1.0.0 + - Serialization supporting SoftDevice S110, S120, and S130 + - ANCS updated and no longer in experimental state + - GCC updated to new version: ARMGCC 4.9 q1-2015 + - DFU example now has support for IAR and GCC + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM version 4.72.10, 5.13.0.0, 5.14.0.0 + - GCC: gcc-arm-embedded 4.9 2015q1 + - IAR: IAR Embedded Workbench for ARM version 7.20.2 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported devices: + - This SDK is optimized for IC revision 3. + For details, see the "nRF51 Series Compatibility Matrix" document (ATTN-51) available on + www.nordicsemi.com. + + Note 1: To run the ANT examples, you must use an nRF51422 device. + Note 2: Some of the examples using the SoftDevice will not fit on the 128 kB variant of the + chip. + +Supported SoftDevices: + - S110 8.0.0 + - S120 2.0.0 + - S130 1.0.0 + - S210 4.0.1 + +Supported boards: + - PCA10028 + - PCA10031 + + For other devices and boards, see the SDK documentation, section "Using the SDK with other + boards", or use SDK v6.x.x. + +Changes: + ANT + BLE (dual stack): + - Not included in this release due to conflicting interface between SoftDevice S310 and S110. Use SDK v7.2.0 for S310 support. + - S310 support will be reintroduced in a future release. + BLE: + - SoftDevices: + - Support for S130 v1.0.0. + - Serialization: + - Fully serialized S110, S120, and S130 API. + - Modules/Services: + - New button module (bsp_btn_ble) that enables functionality such as disconnect, turn off whitelist, go to sleep. + - Advertising module now supports scan response data + - Examples: + - ANCS example is no longer in experimental state. + Proprietary: + - IAR support for proprietary examples. + +Peripheral drivers & libraries: + - New peripheral drivers: TWI, SWI, and GPIOTE. + - New PWM driver. PWM example updated to use the driver. + +Fixed issues: + - NRFFOSDK-2044: Fixed issue in app_gpiote. + - NRFFOSDK-3855: Fixed issue in Current Time Service. + +Known issues: + - Device Manager is not supported in multirole S130 operation. + - Device Manager works in peripheral or central only operation on S130. This must be decided at compile time. + - The DFU over BLE example has been tested to work with a minimum connection interval of + 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may + undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider + increasing the connection interval. + + - ANT: + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time. + + - BLE: + - A few APIs of the Device Manager are not implemented. Also, documentation providing + examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two + pages. + + - Proprietary: + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box + with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy + Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and + channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_timeslot_period() function in the nRF51 projects + (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v8.0.0 +---------------- + +Highlights: + - Support for the latest S110, S120, and S130 SoftDevices. (S310 is not supported.) + - SoftDevices included in the SDK. + - Greatly increased driver and HAL coverage. + - New service client and profile example: Current Time Service/Time Profile. + - IAR support for most examples. + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.72.10, 5.13.0.0, 5.14.0.0 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: IAR Embedded Workbench for ARM version 7.20.2 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported devices: + - This SDK is optimized for IC revision 3. + For details, see the "nRF51 Series Compatibility Matrix" document (ATTN-51) available on + www.nordicsemi.com. + + Note 1: To run the ANT examples, you must use an nRF51422 device. + Note 2: Some of the examples using the SoftDevice will not fit on the 128 kB variant of the + chip. + +Supported SoftDevices: + - S110 8.0.0 + - S120 2.0.0 + - S130 0.9.0-1.alpha + - S210 4.0.1 + +Supported boards: + - PCA10028 + - PCA10031 + + For other devices and boards, see the SDK documentation, section "Using the SDK with other + boards", or use SDK v6.x.x. + +Changes: + Toolchain/IDE: + - The nRF51 SDK now supports the following toolchains in most examples: + - Keil 5.14 (with packs) + - Keil 5.14 (without packs) + - Keil 4.72.10 + - ARM GCC 4.7 2013q1 + - IAR 7.20.2 + - The supported SoftDevices are now included in the SDK and can be flashed directly from + Keil, as a separate target. + + ANT + BLE (dual stack): + - Removed support for the S310 SoftDevice for BLE API compatibility reasons. For support, + use SDK v7.2.0. + + BLE: + - SoftDevices: + - The SDK now supports the S110 SoftDevice v8.0.0. + - The SDK now supports the S120 SoftDevice v2.0.0. + - The SDK now supports the S130 SoftDevice v0.9.0-1.alpha. + - Serialization: + - Serialization support has been removed. For support, use SDK v7.2.0 with appropriate + SoftDevices. + - Modules/Services: + - Added a new advertising module (ble_advertising) that provides automatic handling of + directed/fast/slow advertising, with and without whitelist. + - Nordic UART Service (ble_nus), detached from the UART over BLE Example. + - Added Current Time Service Client (ble_cts_c). + - Service Changed characteristic has been implemented for DFU, so that the indication is + sent when transitioning between application and bootloader. + - Implemented a mechanism for sharing of IRK and LTK from application to bootloader. + This allows for whitelist advertising and reconnection in DFU mode using existing + keys. + - Examples: + - The UART over BLE Example is no longer experimental. + - Added a Time Profile (ble_app_cts_c) example using the Current Time Service Client + implementation. + + Drivers/Libraries: + - Added hardware abstraction layer for the following hardware peripherals: + - ADC (Analog-to-digital converter) + - CLOCK (Clock management) + - LPCOMP (Low power comparator) + - PPI (Programmable Peripheral Interconnect) + - QDEC (Quadrature decoder) + - RNG (Random number generator) + - RTC (Real time counter) + - TIMER (Timer/counter) + - WDT (Watchdog timer) + - Added drivers for the following peripherals: + - CLOCK (Clock management) + - LPCOMP (Low power comparator) + - PPI (Programmable Peripheral Interconnect) + - QDEC (Quadrature decoder) + - RNG (Random number generator) + - RTC (Real time counter) + - TIMER (Timer/counter) + - WDT (Watchdog timer) + - Added modules: + - app_simple_timer (Simple timer based on TIMER1) + + Hardware Examples: + - Added: + - adc_simple (NRF_ADC) + - clock (NRF_DRV_CLOCK) + - lpcomp (NRF_DRV_LPCOMP) + - qdec (NRF_DRV_QDEC) + - simple_timer (APP_SIMPLE_TIMER) + - wdt (NRF_DRV_WDT) + - Modified: + - ppi (NRF_DRV_PPI) + - rng (NRF_DRV_RNG) + - rtc (NRF_DRV_RTC) + - timer (NRF_DRV_TIMER) + +Fixed issues: + - Fixed pstorage issue where different applications could write to the same page. + +Known issues: + - The DFU over BLE example has been tested to work with a minimum connection interval of + 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may + undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider + increasing the connection interval used by the master. + + - ANT: + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time + + - BLE: + - A few APIs of the Device Manager are not implemented. Also, documentation providing + examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two + pages. + + - Proprietary: + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box + with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy + Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and + channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_timeslot_period() function in the nRF51 projects + (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v7.2.0 +---------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.12, 5.13 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: no support in this release + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported devices + - This SDK is optimized for IC revision 3. + For details, see the "nRF51 Series Compatibility Matrix" document (ATTN-51) available on + www.nordicsemi.com. + + Note 1: To run the ANT examples, you must use an nRF51422 device. + Note 2: Some of the examples using the SoftDevice will not fit on the 128 kB variant of the + chip. + Note 3: Some of the serialization examples are too big to be compiled using the free version + of Keil. + +Supported SoftDevices: + - S110 7.1.0 + - S120 1.0.1 + - S130 0.5.0-1.alpha + - S210 4.0.1 + - S310 2.0.1 + +Supported boards: + - PCA10028 + - PCA10031 + - S110 connectivity support for Wavetek WT51822 + + For other devices and boards, see the SDK documentation, section "Using the SDK with other + boards", or use SDK v6.x.x. + +Changes: + - ANT: + - ANT-FS client example: Added callback to allow applications to execute custom code while + waiting for the burst to complete + - Major rework on ANT DFU example + - Added new ANT hub-2-hub/shared channel example + - Added S310 target support for DTM example + - BLE DFU is now supported for S310 + +Fixed issues: + - ANT: + - ANT-FS: Fixed bug with transfer sequence number error causing download failures + - ANT-FS: Fixed bug where upon exhaustion of m_retry, the link time-out has been mistakenly + disabled by a burst transfer + - Fixed issue in linker script for S310 + - Fixed memory corruption issue by using dedicated buffers for ANT and BLE stack events + respectively on S310 + - Fixed an issue where the ANT OTA Updater application v0.8 would not support hex files + with code size larger than 65535 bytes + +Known issues: + - SEGGER J-Link software has some issues with Keil. + See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for details. + - Keil 5.13 may issue a warning about missing packs even when all Nordic Semiconductor packs are + correctly installed. + - The DFU over BLE example has been tested to work with a minimum connection interval of + 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may + undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider + increasing the connection interval used by the master. + + - ANT: + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time + + - BLE: + - NRFFOSDK-3135: S120 examples: RAM is limited to 16 kB, because S120 V1.0.1 does not + support utilizing the whole flash on the QFACAB chip + - NRFFOSDK-119: Only the ble_app_proximity_low_power and ble_app_hrs applications are power + optimized + - S120 examples: Flash clear operation may fail when connected. Impact of this in the S120 + examples is that if the peer loses the bond and a rebonding occurs, flash clear fails and + a DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - A few APIs of the Device Manager are not implemented. Also, documentation providing + examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two + pages. + + - Proprietary: + - Temperature example does not give sane output values. This is a hardware-related issue + described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box + with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy + Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and + channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_timeslot_period() function in the nRF51 projects + (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v7.1.0 +---------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.12 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: no support in this release + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Tested with devices: + - nRF51422 QFACAB + + For others devices, use SDK 6.x.x. + +Supported SoftDevices: + - S110 7.1.0 + - S120 1.0.1 + - S130 0.5.0-1.alpha + - S210 4.0.1 + - S310 2.0.0 + +Supported boards: + - PCA10028 + - PCA10031 + - S110 connectivity support for Wavetek WT51822 + + For other boards, use SDK V6.x.x. + +Changes: + - Experimental support for over-the-air firmware update using the ANT radio protocol + - New experimental example ANT relay demo + - Support for S310 ANT+BLE version 2.0.0 + - Re-introduce Device Firmware Update via UART + - BLE DFU single bank support for bootloader+softdevice update + +Fixed issues: + - NRFFOSDK-3119 Fixed issue in app_timer where issuing start/stop from interrupt context caused long delays + +Known issues: + + - SEGGER J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider increasing the connection interval used by the master + + ANT + - The OTA Updater application v.0.8 does not support hex files with code size larger than 65535 bytes. + - NRFFOSDK-366: ANT-FS host: download sometimes fails when downloading a large file + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time + + BLE + - NRFFOSDK-3135: S120 examples: RAM is limited to 16 kB, because S120 V1.0.1 does not support utilizing the whole flash on the QFACAB chip + - NRFFOSDK-119: Only the ble_app_proximity_low_power and ble_app_hrs applications are power optimized + - S120 examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if the peer loses the bond and a rebonding occurs, flash clear fails and a DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - A few APIs of the Device Manager are not implemented. Also, documentation providing examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two pages. + + Proprietary: + - Temperature example does not give sane output values. This is a hardware-related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 7.0.1 +------------------ +This is a supplement to the nRF51 SDK v7.0.0 release notes. +This release does not include any code changes compared to nRF51 SDK v7.0.0, except for a minor addition that is described in the "Changes" section. + +Fixed issues: + + - Replaced DeviceFamilyPack v1.1.3, which has a wrong URL, with DeviceFamilyPack v1.1.4. + - Added a version field to Pack examples descriptions (NordicSemiconductor.nRF_Examples.pdsc). + - Added missing Nordic Semiconductor nRF51 MDK installer to the repository distribution (nRF51_SDK_x.x.x_xxxxxxx.zip). + - Added missing message sequence charts to the documentation. + - Changed incorrect description of supported SoftDevices in the release notes (see below for the correct list of supported SoftDevices). + +Changes: + + - Added all the register and bitfields for the SPIM peripheral (present in the nRF51802 device) to the HAL header files and replaced the pack nRF_Drivers v1.0.0 with nRF_Drivers v1.1.0. + +Supported SoftDevices: + + - S110 7.1.0 + - S120 1.0.1 + - S130 0.5.0-1.alpha + - S210 4.0.1 + +nRF51 SDK v7.0.0 +---------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.12 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: no support in this release + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Tested with devices: + + - nRF51422 QFACAB + + For others devices, use SDK 6.x.x. + +Supported SoftDevices: + + - S110 7.1.0 + - S120 1.0.0 S120 1.0.1 + - S130 0.5.0-1.alpha + - S210 4.0.1 + - S310 1.0.0 + +Supported boards: + + - PCA10028 + - PCA10031 + - S110 connectivity support for Wavetek WT51822 + + For other boards, use SDK V6.x.x. + + + +Changes: + + - New folder structure + - Moved from installer to CMSIS pack format + - Added support for PCA100028 and PCA10031 + - Deprecated support for previous boards + - Added support for RTX tickless + + ANT + - Changed the ANT examples to support S210 SoftDevice v4.0.1 + - Added experimental Background Scanning example + + ANT + BLE (Dual stack) + - Removed support for S310 SoftDevice (for support, use SDK v6.x.x) + + BLE + - DFU: Added experimental mechanism to exchange encryption keys between application and BootLoader + - DFU: Added identification of firmware versions in the init packet + - Added experimental BLE nRF UART example + - Added experimental ANCS example + - Added experimental example demonstrating usage of S130 SoftDevice + - Added HRS example with RTX + + Proprietary + - Deprecated the following examples (for support, use SDK v6.x.x): + * ADNS2080 Mouse Sensor Driver Application + * Cherry8x16 Keyboard Application + * Button Debouncer Example + * nRF6350 Radio Configuration Example + * PWM Analyzer Example + * Motor Control Example + * TWI Master Example + + +Fixed issues: + + - NRFFOSDK-362: Reset button won't work after programming without cycling the target power + - NRFFOETT-205: The nRF51822 installer will not run if no C:\ drive exists - No installer + - NRFFOSDK-236: When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear - No installer + - NRFFOSDK-363: Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + +Known issues: + + - SEGGER J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider increasing the connection interval used by the master + + ANT + - NRFFOSDK-366: ANT-FS host: download sometimes fails when downloading a large file + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time + + BLE + - NRFFOSDK-3135: S120 examples: RAM is limited to 16 kB, because S120 V1.0.1 does not support utilizing the whole flash on the QFACAB chip + - NRFFOSDK-119: Only the ble_app_proximity_low_power and ble_app_hrs applications are power optimized + - S120 examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if the peer loses the bond and a rebonding occurs, flash clear fails and a DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - A few APIs of the Device Manager are not implemented. Also, documentation providing examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two pages. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Temperature example does not give sane output values. This is a hardware-related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 6.1.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.10.x/5.11.x + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: Embedded Workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + +Tested with devices: + + - nRF51822 QFAAG0 + - nRF51822 QFAAGC + - nRF51822 QFAAFA + - nRF51422 QFAAE0 + + For others devices, use SDK 4.x.x + +Supported SoftDevices: + + - S110 7.0.0 + - S120 1.0.0 + - S210 3.0.0 + - S310 1.0.0 + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 and 2.2.0 + - PCA10003 v3.0.0 + + +Changes: + + - Added Keil 5 uvprojx files for most example projects. + - Extended GCC support, most examples now supplied with Makefiles. + + ANT + - None. + + ANT + BLE (Dual stack) + - None. + + BLE + - Device firmware upgrade with support for OTA update of SoftDevice, app and bootloader is no longer in experimental status. + - Buttonless bootloader mode, enter bootloader mode via over-the-air command (see ble_app_hrs example, using ble_app_hrs_dfu.uvproj project). + - Device manager (BLE bond handling) for S110 and S120 are no longer in experimental status. + - db_discovery module (for GATT database discovery) for S120 is no longer in experimental status. + - New reliable transport layer for S110 SoftDevice serialization. + - Example ble_app_hrs_c (heart rate collector) for S120 is no longer in experimental status. + - Example ble_app_multilink_central for S120 is no longer in experimental status. + - Example ble_app_multilink_peripheral for S110 is no longer in experimental status. + - Experimental examples ble_app_ancs and ble_app_multiactivity have been deprecated from this release. + - Experimental example ble_app_uart for pca10001 has been deprecated from this release. + + Proprietary + - None. + +Fixed issues: + - NRFFOSDK-2884: Fixed issue in app_button module (function app_button_is_pushed). + - NRFFOSDK-1341: Added missing characteristic in Blood Glucose application. + - NRFFOSDK-2859: Removed redundant code in Blood Glucose application. + - NRFFOSDK-2557: Fixed some doxygen documentation errors. + +Known issues: + + - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". + Solution: + - Write new flash algorithm settings to the uvopt file. + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Utilities". + Press "Settings" button to see flashing algorithms. + Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. + Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - S120 Examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if peer loses the bond and a re-bonding occurs, flash clear fails, and DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - Device manager has a few APIs unimplemented. Also documentation providing examples of how API can be used is missing. + - NRFFOSDK-2824: Device manager (pstorage) doesn't support update of bond split across two pages. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 6.0.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.10.x/5.11.x + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: Embedded Workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + +Tested with devices: + + - nRF51822 QFAAG0 + - nRF51822 QFAAGC + - nRF51822 QFAAFA + - nRF51422 QFAAE0 + + For others devices, use SDK 4.x.x + +Supported SoftDevices: + + - S110 7.0.0 + - S120 1.0.0 + - S210 3.0.0 + - S310 1.0.0 + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 and 2.2.0 + - PCA10003 v3.0.0 + + +Changes: + + - Added partial support for Keil 5 uvprojx files. + + ANT + - None + + ANT + BLE (Dual stack) + + BLE + - New module device manager replaces bond manager for storing persistent data + - Experimental device manager support for s120 (BLE central) + - S110 serialization solution has been reworked + - 100% s110 BLE APIs are now serialized + - S110 support for application concurrent multiprotocol radio access + - Pstorage module: Added API for doing range updates + - Experimental: Device firmware upgrade now supports updating both SoftDevice and bootloader for s110 + + Proprietary + - Enhanced ShockBurst: Added nrf_esb_reuse_pid() function to API, giving "reuse payload" functionality. + - Gazell: Added "suspend" mode enabling sharing of radio and PPI. + - Gazell: HW resources are released when Gazell is being disabled or entering suspend mode. + - Gazell: HW resources are reconfigured when Gazell is being enabled or exiting from suspend mode. + +Fixed issues: + + - NRFFOSDK-2542 - SoftDevice related documentation for S110, S120 and S310 BLE stack is not consistent. When looking up SoftDevice application interface or message sequence charts, it is possible that one is looking at incorrect interface. Recommendation hence is to look at SoftDevice headers to ensure correct appplication interface. This is also applicable for Serialization library references. This will be fixed in next release. + - SDK documentation has been splitted into 4 seperate documents with a common index page. + + ANT + - None + + ANT + BLE (Dual stack) + - S310 Heart Rate Relay Example: Bonding does not always function as expected. If bonding is enabled using compiler flag it is recommended to perform service discovery before bonding to minimize chances of unexpected behaviour. + + BLE + + Proprietary + - Enhanced ShockBurst/Gazell: Received packets in Host/PRX mode with CRC error can no longer return ACK to device. + - NRFFOSDK-2470: app_timer - Fixed issue where starting and stopping the timer repeatedly caused errors in the module + +Known issues: + + - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". + Solution: + - Write new flash algorithm settings to the uvopt file. + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Utilities". + Press "Settings" button to see flashing algorithms. + Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. + Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - S120 Examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if peer loses the bond and a re-bonding occurs, flash clear fails, and DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - Device manager has a few APIs unimplemented. Also documentation providing examples of how API can be used is missing. + - NRFFOSDK-2824: Device manager (pstorage) doesn't support update of bond split across two pages. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 5.2.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.10.x + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: Embedded Workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. + +Tested with devices: + + - nRF51822 QFAAG0 + - nRF51822 QFAAGC + - nRF51822 QFAAFA + - nRF51422 QFAAE0 + + For others devices, use SDK 4.x.x + +Supported SoftDevices: + + - S110 6.0.0 + - S120 1.0.0-1.alpha + - S210 3.0.0 + - S310 1.0.0 + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 and 2.2.0 + - PCA10003 v3.0.0 + + +Changes: + + - app_button module: Detect both push and release, instead of just push + - Persistent storage (pstorage) module: + - Support for writing to used memory regions with the new update API. + - Support for clearing single blocks. + - Added get_status API to identify pending flash operations. + + ANT + - None + + ANT + BLE (Dual stack) + - Support for s310 SoftDevice added. + - Heart rate monitor example project support added. + - Added Device Firmware Update (DFU) example for s310. + BLE + - New experimental device manager module for managing bonds on s120. + - Beacon example added. It is available at nrf51822\Board\nrf6310\s110\ble_app_beacon + and nrf51822\Board\pca10001\s110\ble_app_beacon. + - Multiple GATT clients: The Database Discovery module available in + nrf51822\Board\nrf6310\s120\experimental\common folder can now be used to + discover two GATT services at the peer. + - Serialized s110 advertisement example has been removed. + - HID Keyboard application modified to send upper case letters on pressing Button 2. + + Proprietary + - None + +Fixed issues: + + ANT + - None + + ANT + BLE (Dual stack) + - None + + BLE + - NRFFOSDK-1897: Glucose: Fixed bug where authentication was not initiated when connecting to already bonded master. + - NRFFOSDK-2318: Glucose Feature values had incorrect values for 'General Device Fault Supported', 'Time fault Supported', and 'Multiple Bond Supported'. This has been fixed. + - ANCS: The advertising interval of the Apple Notification Center Client example application is reduced to 25 ms. Previously it was 250 ms which made it hard to discover from the peer device. + - NRFFOSDK-2357: Blood Pressure application changed to check if indication is enabled before attempting to send an indication to the peer + - NRFFOSDK-2336: HID Keyboard application fixed to send the correct Input Report bytes when in Boot Mode. + - Fixed issue in bond manager related to clearing of whitelist on deleting all bonds. + - NRFFOSDK-2162: New pstorage get_status API used to allow for flash access to be completed before system off. + + Proprietary + - NRFFOETT-644 - Gazell / ESB: Fixed some documentation issues. + +Known issues: + + - NRFFOSDK-2542 - SoftDevice related documentation for S110, S120 and S310 BLE stack is not consistent. When looking up SoftDevice application interface or message sequence charts, it is possible that one is looking at incorrect interface. Recommendation hence is to look at SoftDevice headers to ensure correct appplication interface. This is also applicable for Serialization library references. This will be fixed in next release. + + - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". + Solution: + - Write new flash algorithm settings to the uvopt file. + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Utilities". + Press "Settings" button to see flashing algorithms. + Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. + Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + ANT + BLE (Dual stack) + - S310 Heart Rate Relay Example: Bonding does not always function as expected. If bonding is enabled using compiler flag it is recommended to perform service discovery before bonding to minimize chances of unexpected behavior. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + - S120 Examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if peer loses the bond and a re-bonding occurs, flash clear fails, and DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - Device manager is an experimental module and has a few APIs unimplemented. Also documentation providing examples of how API can be used is missing. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 5.1.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.0.5.x + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: Embedded Workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. + +Tested with devices: + + - nRF51822 QFAAGC (For others, use SDK 4.x.x) + - nRF51822 QFAAFA (For others, use SDK 4.x.x) + - nRF51422 QFAADA (For others, use SDK 4.x.x) + +Supported SoftDevices: + + - S110 6.0.0 + - S120 0.8.0-2.alpha + - S210 3.0.0-3.beta + - S310 1.0.0-2.alpha + + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 and 2.2.0 + + +Changes: + + - Moved and renamed SoftDevice header folders: + from nrf51822/Include/ble/softdevice to nrf51822/Include/s110 + from nrf51422/Include/ble/softdevice to nrf51422/Include/s210 + - Added SoftDevice headers for s120 and s310 at: + nrf51822/Include/s120 + nrf51422/Include/s310 + - Moved ANT examples from nrf51422/Board//ant to nrf51422/Board//s210 + - Moved s110 SoftDevice examples from nrf51822/Board//ble to nrf51822/Board//s110 + - Added folder for s310 examples in nrf51422/Board//s310 + - Added folder for s120 SoftDevice examples in nrf51822/Board//s120 + + ANT + - The flash layout settings of all ANT examples have been adapted to suit the new flash layout of S210 SoftDevice. + + + BLE + - Added experimental Multilink (up to 8) Central example which uses s120 SoftDevice. + - Added experimental Heart Rate collector example which uses s120 SoftDevice. + - Added prototype iBeacon example. + + Proprietary + +Fixed issues: + + - NRFFOETT-671: Added support for creating new nRF51 projects in Keil 5. + + ANT + - NRFFOETT-438: The API documentation of S210 SoftDevice is now correctly structured in the SDK documentation. + BLE + + Proprietary + +Known issues: + + - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". + Solution: + - Write new flash algorithm settings to the uvopt file. + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Utilities". + Press "Settings" button to see flashing algorithms. + Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. + Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + - NRFFOSDK-2162 - Heart Rate application for PCA10001 possible inconsistent system attributes on power cycle. It is possible that the system attributes on power cycle are not consistent with the ones updated during previous connection. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 5.0.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.72.1.0 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: embedded workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. + +Tested with devices: + + - nRF51822 QFAAGC (For others, use SDK 4.x.x) + - nRF51822 QFAAFA (For others, use SDK 4.x.x) + - nRF51422 QFAADA (For others, use SDK 4.x.x) + +Supported SoftDevices: + + - S110 6.0.0-3 Beta + - Expected to be Compatible with SoftDevice S110 V6.0.0 production version + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 + + NOTE: The ANT examples in this release will only work on nRF51422 QFAADA engineering samples. + Currently no official boards/kits exist that work with these examples. + + +Changes: + + - Added pstorage module for handling asynchronous non-volatile memory (flash) access via SoftDevice API + - Existing BLE event handler has been extended into the new SoftDevice handler module. The new SoftDevice handler module allows for fetching SoC, BLE and ANT events + - Restructured documentation + + + ANT + + BLE + - Changes for support of S110 V6.0.0-3 Beta + - Added Apple Notification Center in experimental + + Proprietary + - SPI slave driver and example code added + - Include new ESB library which uses the same peripherals as the S110 SoftDevice + +Fixed issues: + + ANT + + BLE + + Proprietary + +Known issues: + + - Creating a blank project with Keil V5.0 it is not possible to choose the nRF51 series. + Solution: + Start new projects by making a copy of any existing keil project from the SDK + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + - NRFFOSDK-2162 - Heart Rate application for PCA10001 possible inconsistent system attributes on power cycle. It is possible that the system attributes on power cycle are not consistent with the ones updated during previous connection. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.4.2 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.72.1.0 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: embedded workbench for ARM 6.60 + - N51822 QFAACA on PCA10004 module on nRF6310 motherboard + - N51822 QFAAFA on PCA10005 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + - BLE SoftDevice Version : s110_nrf51822_5.2.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. + +- Supported boards in nRF51 SDK v. 4.4.2: + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.0.0 + - PCA10001 v1.0 through v2.1.0 + - PCA10003 v1.0 through v2.0.0 + - PCA10004 v1.0 through v2.0.0 + - PCA10005 v1.0 through v2.1.0 + - PCA10006 v1.0 through v2.0.0 + - PCA10007 v1.0 through v2.0.0 + - PCA10014 v1.0 + - PCA10018 v1.0.0 through v1.1.0 + +Changes: + + ANT + None + + BLE + - Removed ble_dfu_send_hex.exe from device_firmware_update experimental folder. Similar feature is now available in latest Master Control Panel application. + + Proprietary + None + +Fixed issues: + + - NRFFOSDK-1750 - Added PAN-11 workaround in PPI, PWM, and Simple PWM motor control examples. + - NRFFOSDK-1633 - Added PAN-56 workaround in TWI master driver. + + ANT + None + + BLE + - NRFFOSDK-1025 - The field max_len in rep_char_add signature in ble_hids.c has been corrected to uint16_t. + - NRFFOSDK-1921 - In case IRK is distrubuted by a peer using public address whitelist is updated for both IRK and address. + - NRFFOSDK-1899 - System attributes re-initialized on rebonding. + - NRFFOSDK-1900 - Removed false detection of DIV collisions. + - NRFFOSDK-1993 - Increased buffer in hci_mem_pool_internal.h fix the serialization examples. + Proprietary + None + +Known issues: + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.4.1 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.71.2 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: embedded workbench for ARM 6.60 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.2.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1 Preview. + +Changes: + + - DFU documentation improved. + + ANT + None + + BLE + - NRFFOSDK-1759: Example IAR application for Heart Rate Service added. + - NRFFOSDK-1271: Speed and Cadence Control Point added to Cycling Speed and Cadence Service. + + Proprietary + - ESB: Improved tolerance to delayed interrupts. + + +Fixed issues: + + - NRFFOSDK-1592: Risk of losing timer interrupts when the resolution of the timer is very high, e.g. 1 ms resolution, is now fixed. + + ANT + None + + BLE + - NRFFOETT-399: An IRK is added to the bond manager's whitelist only if the address type of the master is 'resolvable'. + - NRFFOETT-552: DTM application is now implementing PCN_083 + - NRFFOSDK-1828: Key refresh was triggering a link failure when re-bonding to a master. This is now fixed. + - NRFFOETT-571: Premature disconnection scenario handling added to bond manager. Previously this was resulting in system attributes of a master to be cleared. + + Proprietary + - ESB: The nrf_esb_tx_failed() callback function was never called when dynamic acknowledgement was used. This is now fixed. + +Known issues: + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.4.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.71.2 + - GCC: gcc-arm-embedded 4.7 2013q1 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.2.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8. + +Changes: + + - Device Firmware Update example released as part of the main SDK. + - Added support for image transfer over BLE. + - HCI Transport Layer used for serial transfer. + - Note: This example is implemented to work on nRF6310 motherboard because it uses Button 7 to enter bootloader mode on reset. + This is because Button 0 and Button 1 are used by other SDK applications as wakeup buttons. + If this example is to be changed to work for evaluation kit board, then this should be taken into consideration. + - PC application examples for performing firmware updates using HCI and BLE added in nrf6310\device_firmware_updates\experimental folder. + + - UICR Configuration example added to the SDK. It can be found in nrf6310\uicr_config_example folder. + + ANT + None + + BLE + - NRFFOETT-507: ble_app_dtm missing bytes on UART fixed. + - NRFFOSDK-73 : HID keyboard application will now send one key press per notification. + + + Proprietary + None + +Fixed issues: + + ANT + None + + BLE + - NRFFOSDK-1432: Buffer overflow issue in ble_bondmngr_sys_attr_store() function fixed. + - NRFFOETT-339: CCCD values (System Atributes) are now restored on reconnection to a known master only after the link is encrypted. + + Proprietary + None + +Known issues: + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - NRFFOSDK-1774: During SDK installation, chosing custom install location for SDK examples will create Start Menu shortcuts that point to Keil installation location. + - NRFFOSDK-1592: There is a risk of losing timer interrupts when the resolution of the timer is very high, e.g. 1 ms resolution. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOETT-399 - The bond manager will use distrubted IRK in its whitelist regardless of the type of central's address and should actually use the irk if distributed and if the central's address is not public, and not random_static and not random_private_non_resovable. + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.3.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - GCC: gcc-arm-embedded 4.7 2013q1 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.2.0 + +Changes: + + - Supported GCC toolchain switched from CodeSourcery to gcc-arm-embedded. + - New gcc startup file, linker scripts, and makefiles. + - Updated CMSIS header files in Include/gcc to the latest revision (3.20). + - Makefile target "all" now runs "clean" and "debug" targets instead of incremental "release" target. + - nrf.h requires projects to have a define for a chip to enable some needed workarounds. + - SDK examples now support PCA10000 v2.0.0. To make the examples work on the older PCA10000 v1.0, the UART pins need to be remapped in the pca10000.h header file. + For v1.0 + #define RX_PIN_NUMBER 3 + #define TX_PIN_NUMBER 1 + #define CTS_PIN_NUMBER 2 + #define RTS_PIN_NUMBER 0 + For v2.0.0 + #define RX_PIN_NUMBER 11 + #define TX_PIN_NUMBER 9 + #define CTS_PIN_NUMBER 10 + #define RTS_PIN_NUMBER 8 + + ANT + - ANT examples have been updated to support the newest UART API. + BLE + - HCI Transport Layer from Bluetooth Specification v4.0 introduced for BLE S110 Serialized Applications. + - BLE S110 Serialization Examples released as part of the main SDK. + - Updated serialized ble_app_advertising and ble_app_hrs to use app_scheduler. + - Connection Parameter update module : Added possibility to request different connection parameters multiple times. A new event, BLE_CONN_PARAMS_EVT_SUCCEEDED has been created. Event handler implementation needs to take this into account, especially if they were implemented to trigger a disconnect regardless of the type of event. + - Added Makefile and Eclipse project file for ble_app_hrs. + - Changed hard coded flash pages to be FICR CODESIZE dependent. + + Proprietary + - Gazell: + - Added Gazell Pairing Host source code and board example. Backwards compatible with nRF24L Gazell Pairing Device and Host modules. + - Added function nrf_gzll_set_auto_disable(uint32_t num_ticks), to disable Gazell after a number of timeslots. + - Added function nrf_gzll_get_tick_count(). + - Gazell Pairing Device now uses nrf_gzll_get_tick_count() in order to implement a delay. This reduces current consumption. + - Default sync_lifetime value has been increased to 3*channel_table_size*number_of_timeslots_per_channel. This improves performance in high-interference environments. Current users who are satisfied with the performance may wish to maintain the minimum value of 1*channel_table_size*number_of_timeslots_per_channel, in order to avoid any slight increase in current consumption. + - Enhanced ShockBurst: + - ESB PTX now calls nrf_esb_tx_success() callback instead of nrf_esb_tx_failed() for NOACK packets. + - Fix in nrf_esb_set_mode() + - Information concerning backwards compatibility with nRF24L devices has been moved to the User Guide. + +Fixed issues: + + - Examples doing flash writes were not waiting for writes to finish. + + ANT + - NRFFOSDK-1312 - Changed ANTFS_TRANSMIT_POWER define in antfs.h from 0 to 3. The define previously had an incorrect definition which set the power value to -20dBm instead of 0dBm even though the comment indicated 0dBm. + + BLE + - NRFFOETT-402 - DFU Bootloader application in experimental project now sets stack pointer correctly before executing reset vector of application. + + Proprietary + - NRFFOETT-301 - Radio example uses obsolete RADIO_TXPOWER_TXPOWER_Neg40dBm definition. + - Fixed issue in TWI HW driver. Event was not cleared before waiting it to get cleared. + - Floating point ABI used by Makefiles was incorrect. Now using mabi-float=soft. + - Gazell/ESB: Fixed set_mode() functionality. + - Gazell GCC board examples startup and run correctly with the GCC libraries. + - A Gazell Device nows stop the RSSI measurement when no ACK is received, improving the base current consumption. + +Known issues: + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOETT-399 - The bond manager will use distrubted IRK in its whitelist regardless of the type of central's address and should actually use the irk if distributed and if the central's address is not public, and not random_static and not random_private_non_resovable. + - NRFFOSDK-1432 - A buffer overflow has been discovered in the BLE bond manager upon system attributes store. Workaround, define BLE_BONDMNGR_MAX_BONDED_MASTERS in ble_bondmngr_cfg.h to be 1 higher than the number of bond required by the applicaiton. + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.2.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.1.0 + +Changes: + + ANT + + BLE + - NRFFOSDK-623 - BLE S110 DFU Bootloader prototype added to experimental folder. + - NRFFOSDK-996 - Delete of individual bonds in Bond Manager. API extension. + Validity check of stored bond added to Bond Manager API. + - NRFFOSDK-745 - Extended BLE S110 Serialized API. + Added serialized Heartrate example to exprimental folder. + + Proprietary + +Fixed issues: + + - NRFFOSDK-1015 - nRFgo Display lock up after a reset + + ANT + + BLE + - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed. + + Proprietary + +Known issues: + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYTEM_OFF before flashing a new application. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.1.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.0.0 + +Changes: + - nRF51 device variant removed from KEIL device database and replaced with nRF51 series specific devices. + - Added nrf6310_experimental folder to the nRF51 SDK which contains examples and modules under development. + - Experimental version of the SoftDevice S110 serialization API with examples. + - Removed obsolete Master Emulator firmware from the release (nrf51822\Board\pca10000\ble\master_emulator\MEFW_nRF51822_firmware.hex). + - Renamed twi_sw_master_example to twi_master_example + ANT + + BLE + - Updated SoftDevice S110 specific documentation to include message sequence charts. + Proprietary + +Fixed issues: + - NRFFOETT-257 - twi_master_clear_bus() functionality fix done. + - NRFFOSDK-953 - twi_hw_master.c functionality fix done. + ANT + + BLE + - NRFFOSDK-758 - Button 1 does not wake up Bluetooth examples applications. To erase bonding information from system-off mode, press both button 0 and button 1. + + Proprietary + +Known issues: + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYTEM_OFF before flashing a new application. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + - NRFFOSDK-486 - All applications using the bond manager will assert when the maximum number of bonded masters is passed. See proximity application documentation. + + Proprietary: + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.0.1 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51422 QFAACA on PCA10006 module on nRF6310 motherboard + - N51822 QFAACA on PCA10001 evaluation kit board + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - BLE SoftDevice Version : s110_nrf51822_4.0.0-2.beta + +Changes: + - Adressed poor search functionality in the documentation by upgrading used Doxygen version and adding a CHM version of the documentation. + Proprietary + - ESB/Gazell: A hard PLL rampdown is now implemented which shortens the TX to RX switching time to match nRF24L devices. + +Fixed issues: + - NRFFOSDK-801 - Project memory layout was incorrect for S110 4.0.0 targets. + - NRFFOETT-249 - gcc_nrf51_s110.ld had wrong SoftDevice size. + + ANT + + BLE + - NRFFOSDK-807 - Made changes to the default assert handler. + - NRFFOSDK-800 - Bug when switching between BLE and Gazell mode on buttons presses fixed. + - NRFFOETT-225 - DTM didn't work with Tescom TC3000C and R&S CBT. + - NRFFOETT-262 - Evaluation kit BLE examples had button pin pullup resistors disabled. + - NRFFOSDK-804 - Excluded ble_sps.c and ble_sps.h from release as they have not been fully implemented. + + Proprietary + - ESB/Gazell: The peripherals are no longer prepared for use by the nrf_esb_init() and nrf_gzll_init() functions. This is performed in the SystemInit() function. + +Known issues: + - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51 SDK installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power + - NRFFOSDK-363 - Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode (implies to wake-up the current application from SYTEM_OFF before flashing a new application) + + ANT + - NRFFOSDK-366 - ANT-FS host: download some times fails when downloading large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application + If the bonding information are not erased manually - by pressing button 1 during start-up - the new application might assert. + - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed - See proximity application documentation. + - NRFFOSDK-758 - Button 1 does not wake up Bluetooth examples applications. To erase bonding information from system-off mode, press on both button 0 and button 1. + - NRFFOSDK-759 - Unable to switch to BLE mode from gazell mode in Multiprotocol application + + Proprietary: + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.0.0 +----------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51422 QFAACA on PCA10006 module on nRF6310 motherboard + - N51822 QFAACA on PCA10001 evaluation kit board + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + +Changes: + - NRFFOSDK-192 - Interrupt driven low power UART module added. + - NRFFOSDK-543 - Set of common modules used by nRF51xxx examples added. + + ANT + - NRFFOSDK-312 - adapt to renaming of SoftDevice S210 V2.0.0 APIs + + BLE + - NRFFOSDK-55 - adapt to renaming of SoftDevice S110 V4.0.0 APIs + + +Fixed issues: + - NRFFOSDK-563 - nRF51 SDK installer - Keil CDB not installing correctly on PC's running Win7 w/Asian Locales (prim: Japanese/Chinese). + + ANT + - NRFFOSDK-484 - HRM TX background pages are not following 65th packet rule according to spec + + BLE + - NRFFOSDK-361 - System attributes are stored in flash only after disconnect. API ble_bondmngr_sys_attr_store to save system attributes while in a connection is now available. + + + +Known issues: + - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power + - NRFFOSDK-363 - Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode (implies to wake-up the current application from SYTEM_OFF before flashing a new application) + + ANT + - NRFFOSDK-366 - ANT-FS host: download some times fails when downloading large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application + If the bonding information are not erased manually - by pressing button 1 during start-up - the new application might assert. + - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed - See proximity application documentation. + - NRFFOSDK-758 - Button 1 does not wake up Bluetooth examples applications. To erase bonding information from system-off mode, press on both button 0 and button 1. + - NRFFOSDK-759 - Unable to switch to BLE mode from gazell mode in Multiprotocol application + + Proprietary: + - ESB/Gazell: Calling nrf_esb_init() or nrf_gzll_init() will disable usage of the GPIOTE peripheral. + + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the + nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the + payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v3.0.0 +----------------- +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + +Changes: + + - Merged nRF514 and nRF518 SDKs + + - system_nrf51.c: GPIOTE peripheral turned on during system init. + + ANT + - Added ANT bicycle power-only sensor example + - Added ANT combined bicycle speed and cadence sensor example + + BLE + - Added Direct Test Mode (DTM) source code + - Added Glucose Meter service and example + - Added Health Thermometer service and example + - Added Blood Pressure service and example + - Added Proximity example for evaluation board + - Bond manager and flash module modified to write bonding information in flash while in a connection + +Fixed issues: + BLE + -NRFFOSDK-120 - ble_bondmngr_store_bonded_masters function from the bond manager cannot be used when advertising nor when in a connection + The bonding information are now written while in a connection but not the system attributes information. + + ANT + - Fixed incorrect event time generation in ANT HRM Tx example + - NRFFOSDK-469 - ANT - bicycle power rx: doxygen architecture picture defect + + - NRFFOSDK-470 - ANT - bicycle power tx: doxygen architecture picture defect + + Proprietary: + - twi_hw_master example : Fixed deadlock when stop condition was not issued. (NRFFOETT-167) + + - Bugfix: Polarity of on-air "no_ack" bit inverted to comply with legacy nRF24L01 + hardware ESB. + + +Known issues: + - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + + - NRFFOSDK-236 - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. + + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power + + - NRFFOSDK-363 - Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + (implies to wake-up the current application from SYTEM_OFF before flashing a new application) + ANT + - ARCH-506 - ANT-FS host; download could fail when downloading large files. + + - NRFFOSDK-484 - HRM TX background pages are not following 65th packet rule according to spec + + BLE + - NRFFOSDK-119 - Only the "....\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\Nordic\nrf51822\Board\pca10001\ble\ble_app_proximity\ ", and "....\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized + + - NRFFOSDK-361 - System attributes are stored in flash only after disconnect. + + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application + If the bonding information are not erased manually - by pressing button 1 during start-up - the new application might assert. + + - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed + For more information, see proximity application documentation. + + + + Proprietary: + - ESB/Gazell: Calling nrf_esb_init() or nrf_gzll_init() will disable usage of the GPIOTE peripheral. + + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the + nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the + payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + + - Gazell does not support "Low Power Host mode" (Host mode 1). + +Notification ANT: + - This is last release that will support N51422 QFAACA (ANT). Next release will contain API changes. + + + + + + +======================================================== +Old release notes from before SDK merge +======================================================== + + +nRF518 SDK v2.0.0 +----------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51822 QFAACA on PCA10000 evaluation kit USB dongle + - N51822 QFAACA on PCA10001 evaluation kit board + - N51822 QFAACA on PCA10004 module on nRF6310 motherboard + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + + Bluetooth: + - Bluetooth Low Energy SoftDevice S110_nRF51822_2.0.0_alpha1 + + Gazell / ESB libraries on-air compatible with the following SDKs for legacy nRF24Lxx devices: + - nRFgo SDK 2.3.0 + - nRFready Desktop 1.2.3 + +Changes: + + Bluetooth: + - Adapted examples for updated S110 API (S110_nRF51822_2.0.0_alpha1). + - Added Find Me (Immediate Alert Service as client) to Proximity Application. + - Added Alert Notification (client) service and example. + - Added Cycling Speed and Cadence service and example. + - Added Running Speed and Cadence service and example. + - Bond Manager modified to add Whitelist handling and CRC verification of flash. + - Bond Manager usage added to all examples except for power profiling application. + - Use of Whitelist added to Proximity, HID Mouse and HID Keyboard examples. + - Use of directed advertisement added to HID Mouse and HID Keyboard examples. + - Timer Module refactored. + + Proprietary: + - Added nRF24L series address conversion functions to radio_example. + - Added support for GCC to nRF51 Code Examples, ESB and Gazell examples. + - Examples no longer use deprecated PERPOWER register. + - Disabled "Download to flash" and "Verify Code Download" in JLink debug Download Options. + - All SDK release notes are now in this file. + - Added hardware flow control option to simple_uart. + - Fixed compilation problems with Keil ARM MDK v4.60 and ram retention, temperature and blinky examples. + - debouncer_example, ppi_example and timer_example now explicitly set timer bitmode. + - keil_arm_uv4.lnt include folder changed from C:\Keil\ARM\RV31\INC to C:\Keil\ARM\ARMCC\INC. + - Corrected location of SFR files in UV projects. + + - ESB: ESB PRX transceiver operations are shorted, removing continuous wave transmission and improving speed and current consumption. + - ESB: PRX starts listening immediately after sending an ACK, no longer waiting for the next timeslot. + - ESB: The NOACK bit is changed to an ACK bit to ensure compatibility with L01 radios. The L01 product specification is incorrect, only devices using dynamic ack will see this. + - ESB: esb_is_enabled function added. + - ESB: Disabling CRC checking on PRX/Host side works correctly + - ESB: Added support for controlling the XOSC outside the ESB library + + - Gazell: Added support for controlling the XOSC outside the Gazell library + - GZP: No longer deletes pairing data on gzp_init. Added functions to check if device has pairing data and delete all pairing info from flash. + - GZP: gzp_desktop_emulator example requires only one key press to pair and has been tested to work on SoftDevice. + - GZP: nrf_nvmc_write_bytes correctly iterates through bytes. + +Fixed issues: + - Examples use deprecated PERPOWER register. + + Proprietary: + - When using Keil ARM MDK v4.60 the ram retention, temperature and blinky examples might fail during compilation. + - Gazell and ESB examples point to wrong SFR file (should be SFD\Nordic\nRF51\nRF51822.sfr). + + Bluetooth: + - The buttons on the evaluation board are not debounced. + +Known issues: + - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. (DRGN-1807) + - Reset button won't work after programing without cycling the target power. (DRGN-1885) + - Flashing a software using SEGGER is possible only when NOT in SYSTEM_OFF mode (implies to wake-up the current application with a button press for example before flashing a new application).(DRGN-1925) + + Bluetooth: + - Only the ..\Nordic\nrf51822\Board\nrf6310\ble\ble_app_pwr_profiling\ and ..\Nordic\nrf51822\Board\pca10001\ble\ble_app_hrs\ applications are power optimized.(DRGN-1914) + - ble_bondmngr_store_bonded_masters function from the bond manager cannot be used when advertising nor when in a connection (DRGN-1915) + (flash erase/write prevents the CPU from running which means the stack will not be able to run properly.) + If ble_bondmngr_store_bonded_masters function is called while advertising or in a connection, the behavior is UNDEFINED. + + Proprietary: + - ESB/Gazell: Calling nrf_esb_init() or nrf_gzll_init() will disable usage of the GPIOTE peripheral. In order to use the GPIOTE peripheral, the workaround in PAN 22 must be performed after calling these functions. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + + - The nRF24Lxx ESB examples found in the legacy nRFready + SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + + The legacy examples need to add the following in order to work with the + nRF51 examples: + + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + + In addition, the legacy PTX example must add code for handling the + payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible + with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx + devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, + or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects + (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, + or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + + + + + + + +nRF518 SDK v1.1.1 +----------------- + +Changes: +- Master Control Panel updated to version 3.1.1. Includes fix for issue where pca10000 master emulator devices did not get detected. + +Known issues: +- When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. +- When using Keil ARM MDK v4.60 the ram retention, temperature and blinky examples might fail during compilation and leave an error message like this: + C3900U: Unrecognized option '--asm'. + C3900U: Unrecognized option '--interleave'. + To fix this Click Alt+F7, choose "Listing" tab. Uncheck "C Compiler Listing" +- Previous issues from v1.1.0 does still apply + + + + + + + +nRF518 SDK v1.1.0 +----------------- + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.54 +- N51822 QFAACA on PCA10004 module on nRF6310 motherboard +- N51822 QFAACA on PCA10000 USB dongle +- N51822 QFAACA on PCA10001 board +- Windows XP SP3 32-bit +- Windows 7 SP1 64-bit + +Known issues: +- Examples use depracated PERPOWER register. Future silicon will power up peripherals after reset and PERPOWER register will be removed. +- Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. +- Temperature example does not give sane output values. This is hardware related issue described in +- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. +- On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. +- Gazell and ESB examples point to wrong SFR file (should be SFD\Nordic\nRF51\nRF51822.sfr). +- Reset button wont work after programing without cycling the target power. Workaround is to update system_nrf51.c with + void SystemInit (void) + { + /* Switch ON both RAM banks */ + NRF_POWER->RESET = POWER_RESET_RESET_Enabled; + NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) | + (POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos); + } + +Bluetooth: + - The button on the evaluation board are not debounced in hardware and the application implementing for it does not debounce the button presses either (using software mechanisms). So there will be additional increments/decrements of heart rate measurement while pressing the buttons. + + + + + +nRF518 SDK v1.0.0 +----------------- + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.54 +- N51822 QFAACA on nRF2752 module on nRF6310 motherboard +- Windows XP SP3 32-bit +- Windows 7 SP1 64-bit +Bluetooth: + - S110 SoftDevice v1.0.0 + - J-Link ARM v4.52b or higher + +This release contains the following: +Bluetooth: + - Complete source code needed for writing applications on top of S110 SoftDevice (BLE Stack) + - Template application that can be used as a starting point to develop custom applications. + - Example application for Heart Rate Service + - Example application for Proximity profile + - Example application for HID Mouse + - Example application for HID Keyboard + - Power profiling application + - Example application using Heart Rate Service for Evaluation Board (PCA10001) + - Multiprotocol application that implements the Heart Rate profile in Bluetooth mode and the Gazell 'device' mode. + - Documentation + +Known issues: +- Examples use depracated PERPOWER register. Future silicon will power up peripherals after reset and PERPOWER register will be removed. +- Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. +- Temperature example does not give sane output values. This is hardware related issue described in +- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. +- On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. +- Gazell and ESB examples point to wrong SFR file (should be SFD\Nordic\nRF51\nRF51822.sfr). +- Reset button wont work after programing without cycling the target power. Workaround is to update system_nrf51.c with + void SystemInit (void) + { + /* Switch ON both RAM banks */ + NRF_POWER->RESET = POWER_RESET_RESET_Enabled; + NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) | + (POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos); + } +- Spi master function spi_master_init() sends two dummy bytes. This will be removed in a future release. +- timer_example nrf_timer_delay_ms() will not give expected results using parameter values over 65 ms. + +Bluetooth: + - The button on the evaluation board are not debounced in hardware and the application implementing for it does not debounce the button presses either (using software mechanisms). So there will be additional increments/decrements of heart rate measurement while pressing the buttons. + + + + +nRF514 SDK v.1.2.0 +------------------ + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.60 +- N51422 QFAACA on PCA10004 module on nRF6310 motherboard +- N51422 QFAACA on PCA10006 module on nRF6310 motherboard +- N51822 QFAACA on nRF2752 module on nRF6310 motherboard +- N51822 QFAACA on PCA10001 evaluation kit board +- Windows XP SP3 32-bit +- Windows 7 SP1 64-bit + +Changes: +- Added Bicycle Power minimal slave example. +- Added Stride and Distance Monitor minimal slave and master example. +- Removed deprecated PERPOWER register from examples and header files. + +Known issues: +- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. +- On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + - Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. +- When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. +- Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode (implies to wake-up the current application from SYTEM_OFF before flashing a new application) +- Reset button won't work after programming with Keil without cycling the target power. On the other hand if nrfjprog with -p (pin reset) is used to program the device, reset button will work. +- Using -p option in nrfjprog too heavily might block JLink. This block can be resolved by re-cycling the JLink power. + + +nRF514 SDK v1.1.0 +----------------- + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.54 +- N51422 QFAACA on PCA10001 module +- N51422 QFAACA on a PCA10005 modulea on nRF6310 motherboard + +Known issues: +- When having an application which starts up by putting the chip in SystemOff mode, and wakeup source is not configured correctly, the device cannot be programmed. + Workaround: Use nrfjprog with "recover" option to wipe the application keeping the application in SystemOff mode. +- For PCA10003 examples using UART, the terminal program on the PC has to release the COM port when PCA10003 is power cycled. It is not possible for the PCA10003 to keep a connection up when performing a power cycle. + Workaround: Close terminal program for each time you want to perform a power recycle + +Changes: +- Added examples for PCA10003 Evaluation kit. +- Added nrfjprog.exe - Nordic Semiconductor command line nRF51 programming tool using JLink dll's. +- Added custom system_nrf51422.c in templates folder for handling reset after flashing and turning all peripherals on (except GPIOTE) as described in PAN028. +- Removed references to depricated PERPOWER register in ANT code examples. +- Added compiler flag to the ANT examples, to easier being able to run examples without any UART. +- Modified simple_uart_config() parameters. Added new parameters for flow control +- Added include/boards folder for handling examples targeted for different boards +- Fixed bug in timer_example +- Fixed bug in spi_example + + +nRF514 SDK v1.0.0 +----------------- + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.54 +- N51822 QFAACA on nRF2754 module on nRF6310 motherboard +- Tested on Windows 7 64-bit + +Known issues: +- Examples use depracated PERPOWER register. Future silicon will power up peripherals after reset and PERPOWER register will be removed. +- Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. +- Temperature example does not give sane output values. This is hardware related issue described in +- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. +- Reset button wont work after programing without cycling the target power. Workaround is to update system_nrf51.c with + void SystemInit (void) + { + /* Switch ON both RAM banks */ + NRF_POWER->RESET = POWER_RESET_RESET_Enabled; + NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) | + (POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos); + } +- Spi master function spi_master_init() sends two dummy bytes. This will be removed in a future release. +- timer_example nrf_timer_delay_ms() will not give expected results using parameter values over 65 ms. + +Changes: +- First public release + diff --git a/softdevice/common/softdevice_handler/ant_stack_handler_types.h b/softdevice/common/softdevice_handler/ant_stack_handler_types.h new file mode 100644 index 0000000..0a41baa --- /dev/null +++ b/softdevice/common/softdevice_handler/ant_stack_handler_types.h @@ -0,0 +1,73 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup ant_stack_handler_types Types definitions for ANT support in SoftDevice handler. + * @{ + * @ingroup softdevice_handler + * @brief This file contains the declarations of types required for ANT stack support. These + * types will be defined when the preprocessor define ANT_STACK_SUPPORT_REQD is defined. + */ + +#ifndef ANT_STACK_HANDLER_TYPES_H__ +#define ANT_STACK_HANDLER_TYPES_H__ + +#ifdef ANT_STACK_SUPPORT_REQD + +#include + +#define ANT_STACK_EVT_MSG_BUF_SIZE 32 /**< Size of ANT event message buffer. This will be provided to the SoftDevice while fetching an event. */ +#define ANT_STACK_EVT_STRUCT_SIZE (sizeof(ant_evt_t)) /**< Size of the @ref ant_evt_t structure. This will be used by the @ref softdevice_handler to internal event buffer size needed. */ + +/**@brief ANT stack event type. */ +typedef struct +{ + union + { + uint32_t ulForceAlign; ///< force the evt_buffer to be 4-byte aligned, required for some casting to ANT_MESSAGE. + uint8_t evt_buffer[ANT_STACK_EVT_MSG_BUF_SIZE]; ///< Event message buffer. + } msg; + uint8_t channel; ///< Channel number. + uint8_t event; ///< Event code. +} ant_evt_t; + +/**@brief Application ANT stack event handler type. */ +typedef void (*ant_evt_handler_t) (ant_evt_t * p_ant_evt); + +/**@brief Function for registering for ANT events. + * + * @details The application should use this function to register for receiving ANT events from + * the SoftDevice. If the application does not call this function, then any ANT event + * that may be generated by the SoftDevice will NOT be fetched. Once the application has + * registered for the events, it is not possible to possible to cancel the registration. + * However, it is possible to register a different function for handling the events at + * any point of time. + * + * @param[in] ant_evt_handler Function to be called for each received ANT event. + * + * @retval NRF_SUCCESS Successful registration. + * @retval NRF_ERROR_NULL Null pointer provided as input. + */ +uint32_t softdevice_ant_evt_handler_set(ant_evt_handler_t ant_evt_handler); + +#else + +// The ANT Stack support is not required. + +#define ANT_STACK_EVT_STRUCT_SIZE 0 /**< Since the ANT stack support is not required, this is equated to 0, so that the @ref softdevice_handler.h can compute the internal event buffer size without having to care for ANT events.*/ + +#endif // ANT_STACK_SUPPORT_REQD + +#endif // ANT_STACK_HANDLER_TYPES_H__ + +/** @} */ diff --git a/softdevice/common/softdevice_handler/app_ram_base.h b/softdevice/common/softdevice_handler/app_ram_base.h new file mode 100644 index 0000000..b3e6d17 --- /dev/null +++ b/softdevice/common/softdevice_handler/app_ram_base.h @@ -0,0 +1,176 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +// ble_enable param app_ram_base + +#define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20001870 +#define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20001870 +#define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20001fe8 +#define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20001fe8 +#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20001ce0 +#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20001c98 +#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20001eb0 +#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20001e68 +#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20002418 +#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x200023d0 +#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x200025e0 +#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x200025a0 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20002110 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20002080 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x200022d8 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20002250 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x200024a8 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20002418 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20002840 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x200027b8 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20002a10 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20002980 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20002bd8 +#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20002b50 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20002538 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20002468 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20002708 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20002638 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x200028d0 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20002800 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20002aa0 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x200029d0 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20002c70 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20002ba0 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20002e40 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20002d68 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20003008 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20002f38 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x200031d8 +#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x20003100 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20002968 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20002850 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20002b30 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20002a18 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20002d00 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20002be8 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20002ec8 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20002db0 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x20003098 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20002f80 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x200030a0 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20002f88 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20003268 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20003150 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20003438 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20003320 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x20003600 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x200034e8 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_4_MID_BW 0x200037d0 +#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_4_LOW_BW 0x200036b8 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20002d98 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20002c38 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20002f60 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20002e00 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20003130 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20002fd0 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x200032f8 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20003198 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x200034c8 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20003368 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_5_MID_BW 0x20003690 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_5_LOW_BW 0x20003530 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x200034c8 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20003370 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20003698 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20003538 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20003860 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20003708 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x20003a30 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x200038d0 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_4_MID_BW 0x20003bf8 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_4_LOW_BW 0x20003aa0 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_5_MID_BW 0x20003dc8 +#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_5_LOW_BW 0x20003c68 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x200031c0 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20003020 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20003390 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x200031e8 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20003558 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x200033b8 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20003728 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20003580 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x200038f0 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20003750 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_5_MID_BW 0x20003ac0 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_5_LOW_BW 0x20003918 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_6_MID_BW 0x20003c88 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_6_LOW_BW 0x20003ae8 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x200038f8 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20003750 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20003ac0 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20003920 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20003c90 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20003ae8 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x20003e58 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x20003cb8 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_4_MID_BW 0x20004028 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_4_LOW_BW 0x20003e80 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_5_MID_BW 0x200041f0 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_5_LOW_BW 0x20004050 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_6_MID_BW 0x200043c0 +#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_6_LOW_BW 0x20004218 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x200035f0 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20003408 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x200037b8 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x200035d0 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20003988 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x200037a0 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20003b50 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20003968 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x20003d20 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20003b38 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_5_MID_BW 0x20003ee8 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_5_LOW_BW 0x20003d00 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_6_MID_BW 0x200040b8 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_6_LOW_BW 0x20003ed0 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_7_MID_BW 0x20004280 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_7_LOW_BW 0x20004098 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20003d28 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20003b38 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20003ef0 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20003d08 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x200040c0 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20003ed0 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x20004288 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x200040a0 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_4_MID_BW 0x20004458 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_4_LOW_BW 0x20004268 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_5_MID_BW 0x20004620 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_5_LOW_BW 0x20004438 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_6_MID_BW 0x200047f0 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_6_LOW_BW 0x20004600 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_7_MID_BW 0x200049b8 +#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_7_LOW_BW 0x200047d0 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20003a18 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x200037e8 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20003be8 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x200039b8 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20003db0 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20003b80 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20003f80 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20003d50 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x20004148 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20003f18 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_5_MID_BW 0x20004318 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_5_LOW_BW 0x200040e8 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_6_MID_BW 0x200044e0 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_6_LOW_BW 0x200042b0 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_7_MID_BW 0x200046b0 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_7_LOW_BW 0x20004480 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_8_MID_BW 0x20004878 +#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_8_LOW_BW 0x20004648 diff --git a/softdevice/common/softdevice_handler/ble_stack_handler_types.h b/softdevice/common/softdevice_handler/ble_stack_handler_types.h new file mode 100644 index 0000000..ede5b12 --- /dev/null +++ b/softdevice/common/softdevice_handler/ble_stack_handler_types.h @@ -0,0 +1,64 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup ble_stack_handler_types Types definitions for BLE support in SoftDevice handler. + * @{ + * @ingroup softdevice_handler + * @brief This file contains the declarations of types required for BLE stack support. These + * types will be defined when the preprocessor define BLE_STACK_SUPPORT_REQD is defined. + */ + +#ifndef BLE_STACK_HANDLER_TYPES_H__ +#define BLE_STACK_HANDLER_TYPES_H__ + +#ifdef BLE_STACK_SUPPORT_REQD + +#include +#include "ble.h" +#include "nrf_sdm.h" +#include "app_error.h" +#include "app_util.h" + +#define BLE_STACK_EVT_MSG_BUF_SIZE (sizeof(ble_evt_t) + (GATT_MTU_SIZE_DEFAULT)) /**< Size of BLE event message buffer. This will be provided to the SoftDevice while fetching an event. */ +#define BLE_STACK_HANDLER_SCHED_EVT_SIZE 0 /**< The size of the scheduler event used by SoftDevice handler when passing BLE events using the @ref app_scheduler. */ + +/**@brief Application stack event handler type. */ +typedef void (*ble_evt_handler_t) (ble_evt_t * p_ble_evt); + +/**@brief Function for registering for BLE events. + * + * @details The application should use this function to register for receiving BLE events from + * the SoftDevice. If the application does not call this function, then any BLE event + * that may be generated by the SoftDevice will NOT be fetched. Once the application has + * registered for the events, it is not possible to cancel the registration. + * However, it is possible to register a different function for handling the events at + * any point of time. + * + * @param[in] ble_evt_handler Function to be called for each received BLE event. + * + * @retval NRF_SUCCESS Successful registration. + * @retval NRF_ERROR_NULL Null pointer provided as input. + */ +uint32_t softdevice_ble_evt_handler_set(ble_evt_handler_t ble_evt_handler); + +#else + +#define BLE_STACK_EVT_MSG_BUF_SIZE 0 /**< Since the BLE stack support is not required, this is equated to 0, so that the @ref softdevice_handler.h can compute the internal event buffer size without having to care for BLE events.*/ +#define BLE_STACK_HANDLER_SCHED_EVT_SIZE 0 + +#endif // BLE_STACK_SUPPORT_REQD + +#endif // BLE_STACK_HANDLER_TYPES_H__ + +/** @} */ diff --git a/softdevice/common/softdevice_handler/softdevice_handler.c b/softdevice/common/softdevice_handler/softdevice_handler.c new file mode 100644 index 0000000..4499915 --- /dev/null +++ b/softdevice/common/softdevice_handler/softdevice_handler.c @@ -0,0 +1,492 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "softdevice_handler.h" +#include +#include +#include +#include +#include "nordic_common.h" +#include "app_error.h" +#include "nrf_assert.h" +#include "nrf_nvic.h" +#include "nrf.h" +#include "nrf_log.h" +#include "sdk_common.h" +#include "nrf_drv_config.h" +#if CLOCK_ENABLED +#include "nrf_drv_clock.h" +#endif + +#if defined(ANT_STACK_SUPPORT_REQD) && defined(BLE_STACK_SUPPORT_REQD) + #include "ant_interface.h" +#elif defined(ANT_STACK_SUPPORT_REQD) + #include "ant_interface.h" +#elif defined(BLE_STACK_SUPPORT_REQD) + #include "ble.h" +#endif + + +#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1 +#define SD_HANDLER_LOG(...) NRF_LOG_PRINTF(__VA_ARGS__) +#else +#define SD_HANDLER_LOG(...) +#endif + +#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1 +#define SD_HANDLER_LOG_INIT() NRF_LOG_INIT() +#else +#define SD_HANDLER_LOG_INIT() +#endif + + + +#define RAM_START_ADDRESS 0x20000000 +#define SOFTDEVICE_EVT_IRQ SD_EVT_IRQn /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */ +#define SOFTDEVICE_EVT_IRQHandler SD_EVT_IRQHandler +#define RAM_TOTAL_SIZE ((NRF_FICR->INFO.RAM)*1024) +#define RAM_END_ADDRESS (RAM_START_ADDRESS + RAM_TOTAL_SIZE) + + +#define SOFTDEVICE_VS_UUID_COUNT 0 +#define SOFTDEVICE_GATTS_ATTR_TAB_SIZE BLE_GATTS_ATTR_TAB_SIZE_DEFAULT +#define SOFTDEVICE_GATTS_SRV_CHANGED 0 +#define SOFTDEVICE_PERIPH_CONN_COUNT 1 +#define SOFTDEVICE_CENTRAL_CONN_COUNT 4 +#define SOFTDEVICE_CENTRAL_SEC_COUNT 1 + +/* Global nvic state instance, required by nrf_nvic.h */ +nrf_nvic_state_t nrf_nvic_state; + +static softdevice_evt_schedule_func_t m_evt_schedule_func; /**< Pointer to function for propagating SoftDevice events to the scheduler. */ + +static volatile bool m_softdevice_enabled = false; /**< Variable to indicate whether the SoftDevice is enabled. */ + +#ifdef BLE_STACK_SUPPORT_REQD +// The following three definitions is needed only if BLE events are needed to be pulled from the stack. +static uint8_t * mp_ble_evt_buffer; /**< Buffer for receiving BLE events from the SoftDevice. */ +static uint16_t m_ble_evt_buffer_size; /**< Size of BLE event buffer. */ +static ble_evt_handler_t m_ble_evt_handler; /**< Application event handler for handling BLE events. */ +#endif + +#ifdef ANT_STACK_SUPPORT_REQD +// The following two definition is needed only if ANT events are needed to be pulled from the stack. +static ant_evt_t m_ant_evt_buffer; /**< Buffer for receiving ANT events from the SoftDevice. */ +static ant_evt_handler_t m_ant_evt_handler; /**< Application event handler for handling ANT events. */ +#endif + +static sys_evt_handler_t m_sys_evt_handler; /**< Application event handler for handling System (SOC) events. */ + + +/**@brief Callback function for asserts in the SoftDevice. + * + * @details A pointer to this function will be passed to the SoftDevice. This function will be + * called by the SoftDevice if certain unrecoverable errors occur within the + * application or SoftDevice. + * + * See @ref nrf_fault_handler_t for more details. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault. + * @param[in] info Optional additional information regarding the fault. Refer to each fault + * identifier for details. + */ +void softdevice_fault_handler(uint32_t id, uint32_t pc, uint32_t info) +{ + app_error_fault_handler(id, pc, info); +} + + +void intern_softdevice_events_execute(void) +{ + if (!m_softdevice_enabled) + { + // SoftDevice not enabled. This can be possible if the SoftDevice was enabled by the + // application without using this module's API (i.e softdevice_handler_init) + + return; + } +#if CLOCK_ENABLED + bool no_more_soc_evts = false; +#else + bool no_more_soc_evts = (m_sys_evt_handler == NULL); +#endif +#ifdef BLE_STACK_SUPPORT_REQD + bool no_more_ble_evts = (m_ble_evt_handler == NULL); +#endif +#ifdef ANT_STACK_SUPPORT_REQD + bool no_more_ant_evts = (m_ant_evt_handler == NULL); +#endif + + for (;;) + { + uint32_t err_code; + + if (!no_more_soc_evts) + { + uint32_t evt_id; + + // Pull event from SOC. + err_code = sd_evt_get(&evt_id); + + if (err_code == NRF_ERROR_NOT_FOUND) + { + no_more_soc_evts = true; + } + else if (err_code != NRF_SUCCESS) + { + APP_ERROR_HANDLER(err_code); + } + else + { + // Call application's SOC event handler. +#if CLOCK_ENABLED + nrf_drv_clock_on_soc_event(evt_id); + if (m_sys_evt_handler) + { + m_sys_evt_handler(evt_id); + } +#else + m_sys_evt_handler(evt_id); +#endif + } + } + +#ifdef BLE_STACK_SUPPORT_REQD + // Fetch BLE Events. + if (!no_more_ble_evts) + { + // Pull event from stack + uint16_t evt_len = m_ble_evt_buffer_size; + + err_code = sd_ble_evt_get(mp_ble_evt_buffer, &evt_len); + if (err_code == NRF_ERROR_NOT_FOUND) + { + no_more_ble_evts = true; + } + else if (err_code != NRF_SUCCESS) + { + APP_ERROR_HANDLER(err_code); + } + else + { + // Call application's BLE stack event handler. + m_ble_evt_handler((ble_evt_t *)mp_ble_evt_buffer); + } + } +#endif + +#ifdef ANT_STACK_SUPPORT_REQD + // Fetch ANT Events. + if (!no_more_ant_evts) + { + // Pull event from stack + err_code = sd_ant_event_get(&m_ant_evt_buffer.channel, + &m_ant_evt_buffer.event, + m_ant_evt_buffer.msg.evt_buffer); + if (err_code == NRF_ERROR_NOT_FOUND) + { + no_more_ant_evts = true; + } + else if (err_code != NRF_SUCCESS) + { + APP_ERROR_HANDLER(err_code); + } + else + { + // Call application's ANT stack event handler. + m_ant_evt_handler(&m_ant_evt_buffer); + } + } +#endif + + if (no_more_soc_evts) + { + // There are no remaining System (SOC) events to be fetched from the SoftDevice. +#if defined(ANT_STACK_SUPPORT_REQD) && defined(BLE_STACK_SUPPORT_REQD) + // Check if there are any remaining BLE and ANT events. + if (no_more_ble_evts && no_more_ant_evts) + { + break; + } +#elif defined(BLE_STACK_SUPPORT_REQD) + // Check if there are any remaining BLE events. + if (no_more_ble_evts) + { + break; + } +#elif defined(ANT_STACK_SUPPORT_REQD) + // Check if there are any remaining ANT events. + if (no_more_ant_evts) + { + break; + } +#else + // No need to check for BLE or ANT events since there is no support for BLE and ANT + // required. + break; +#endif + } + } +} + +bool softdevice_handler_isEnabled(void) +{ + return m_softdevice_enabled; +} + +uint32_t softdevice_handler_init(nrf_clock_lf_cfg_t * p_clock_lf_cfg, + void * p_ble_evt_buffer, + uint16_t ble_evt_buffer_size, + softdevice_evt_schedule_func_t evt_schedule_func) +{ + uint32_t err_code; + + SD_HANDLER_LOG_INIT(); + + // Save configuration. +#if defined (BLE_STACK_SUPPORT_REQD) + // Check that buffer is not NULL. + if (p_ble_evt_buffer == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + + // Check that buffer is correctly aligned. + if (!is_word_aligned(p_ble_evt_buffer)) + { + return NRF_ERROR_INVALID_PARAM; + } + + mp_ble_evt_buffer = (uint8_t *)p_ble_evt_buffer; + m_ble_evt_buffer_size = ble_evt_buffer_size; +#else + // The variables p_ble_evt_buffer and ble_evt_buffer_size is not needed if BLE Stack support + // is not required. + UNUSED_PARAMETER(p_ble_evt_buffer); + UNUSED_PARAMETER(ble_evt_buffer_size); +#endif + + m_evt_schedule_func = evt_schedule_func; + + // Initialize SoftDevice. +#if defined(S212) || defined(S332) + err_code = sd_softdevice_enable(p_clock_lf_cfg, softdevice_fault_handler, ANT_LICENSE_KEY); +#else + err_code = sd_softdevice_enable(p_clock_lf_cfg, softdevice_fault_handler); +#endif + if (err_code != NRF_SUCCESS) + { + return err_code; + } + + m_softdevice_enabled = true; + + // Enable BLE event interrupt (interrupt priority has already been set by the stack). +#ifdef SOFTDEVICE_PRESENT + return sd_nvic_EnableIRQ((IRQn_Type)SOFTDEVICE_EVT_IRQ); +#else + //In case of Serialization NVIC must be accessed directly. + NVIC_EnableIRQ(SOFTDEVICE_EVT_IRQ); + return NRF_SUCCESS; +#endif +} + + +uint32_t softdevice_handler_sd_disable(void) +{ + uint32_t err_code = sd_softdevice_disable(); + + m_softdevice_enabled = !(err_code == NRF_SUCCESS); + + return err_code; +} + + +#ifdef BLE_STACK_SUPPORT_REQD +uint32_t softdevice_ble_evt_handler_set(ble_evt_handler_t ble_evt_handler) +{ + VERIFY_PARAM_NOT_NULL(ble_evt_handler); + + m_ble_evt_handler = ble_evt_handler; + + return NRF_SUCCESS; +} +#endif + + +#ifdef ANT_STACK_SUPPORT_REQD +uint32_t softdevice_ant_evt_handler_set(ant_evt_handler_t ant_evt_handler) +{ + VERIFY_PARAM_NOT_NULL(ant_evt_handler); + + m_ant_evt_handler = ant_evt_handler; + + return NRF_SUCCESS; +} +#endif + + +uint32_t softdevice_sys_evt_handler_set(sys_evt_handler_t sys_evt_handler) +{ + VERIFY_PARAM_NOT_NULL(sys_evt_handler); + + m_sys_evt_handler = sys_evt_handler; + + return NRF_SUCCESS; +} + + +/**@brief Function for handling the Application's BLE Stack events interrupt. + * + * @details This function is called whenever an event is ready to be pulled. + */ +void SOFTDEVICE_EVT_IRQHandler(void) +{ + if (m_evt_schedule_func != NULL) + { + uint32_t err_code = m_evt_schedule_func(); + APP_ERROR_CHECK(err_code); + } + else + { + intern_softdevice_events_execute(); + } +} + +#if 0 // S132 v500 change API +#if defined(BLE_STACK_SUPPORT_REQD) +uint32_t softdevice_enable_get_default_config(uint8_t central_links_count, + uint8_t periph_links_count, + ble_enable_params_t * p_ble_enable_params) +{ + memset(p_ble_enable_params, 0, sizeof(ble_enable_params_t)); + p_ble_enable_params->common_enable_params.vs_uuid_count = 1; + p_ble_enable_params->gatts_enable_params.attr_tab_size = SOFTDEVICE_GATTS_ATTR_TAB_SIZE; + p_ble_enable_params->gatts_enable_params.service_changed = SOFTDEVICE_GATTS_SRV_CHANGED; + p_ble_enable_params->gap_enable_params.periph_conn_count = periph_links_count; + p_ble_enable_params->gap_enable_params.central_conn_count = central_links_count; + if (p_ble_enable_params->gap_enable_params.central_conn_count != 0) + { + p_ble_enable_params->gap_enable_params.central_sec_count = SOFTDEVICE_CENTRAL_SEC_COUNT; + } + + return NRF_SUCCESS; +} + + +#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1 +static inline uint32_t ram_total_size_get(void) +{ +#ifdef NRF51 + uint32_t size_ram_blocks = (uint32_t)NRF_FICR->SIZERAMBLOCKS; + uint32_t total_ram_size = size_ram_blocks; + total_ram_size = total_ram_size*(NRF_FICR->NUMRAMBLOCK); + return total_ram_size; +#elif defined (NRF52) + return RAM_TOTAL_SIZE; +#endif /* NRF51 */ +} + +/*lint --e{528} -save suppress 528: symbol not referenced */ +/**@brief Function for finding the end address of the RAM. + * + * @retval ram_end_address Address of the end of the RAM. + */ +static inline uint32_t ram_end_address_get(void) +{ + uint32_t ram_end_address = (uint32_t)RAM_START_ADDRESS; + ram_end_address+= ram_total_size_get(); + return ram_end_address; +} +/*lint -restore*/ +#endif //ENABLE_DEBUG_LOG_SUPPORT + +/*lint --e{10} --e{19} --e{27} --e{40} --e{529} -save suppress Error 27: Illegal character */ +uint32_t sd_check_ram_start(uint32_t sd_req_ram_start) +{ +#if (defined(S130) || defined(S132) || defined(S332)) +#if defined ( __CC_ARM ) + extern uint32_t Image$$RW_IRAM1$$Base; + const volatile uint32_t ram_start = (uint32_t) &Image$$RW_IRAM1$$Base; +#elif defined ( __ICCARM__ ) + extern uint32_t __ICFEDIT_region_RAM_start__; + volatile uint32_t ram_start = (uint32_t) &__ICFEDIT_region_RAM_start__; +#elif defined ( __GNUC__ ) + extern uint32_t __data_start__; + volatile uint32_t ram_start = (uint32_t) &__data_start__; +#endif//__CC_ARM + if (ram_start != sd_req_ram_start) + { +#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1 + uint32_t app_ram_size= ram_end_address_get(); + SD_HANDLER_LOG("RAM START ADDR 0x%x should be adjusted to 0x%x\r\n", + ram_start, + sd_req_ram_start); + app_ram_size -= sd_req_ram_start; + SD_HANDLER_LOG("RAM SIZE should be adjusted to 0x%x \r\n", + app_ram_size); +#endif //NRF_LOG_USES_RTT + return NRF_SUCCESS; + } +#endif//defined(S130) || defined(S132) || defined(S332) + return NRF_SUCCESS; +} + +uint32_t softdevice_enable(ble_enable_params_t * p_ble_enable_params) +{ +#if (defined(S130) || defined(S132) || defined(S332)) + uint32_t err_code; + uint32_t app_ram_base; + +#if defined ( __CC_ARM ) + extern uint32_t Image$$RW_IRAM1$$Base; + const volatile uint32_t ram_start = (uint32_t) &Image$$RW_IRAM1$$Base; +#elif defined ( __ICCARM__ ) + extern uint32_t __ICFEDIT_region_RAM_start__; + volatile uint32_t ram_start = (uint32_t) &__ICFEDIT_region_RAM_start__; +#elif defined ( __GNUC__ ) + extern uint32_t __data_start__; + volatile uint32_t ram_start = (uint32_t) &__data_start__; +#endif + + app_ram_base = ram_start; + SD_HANDLER_LOG("sd_ble_enable: RAM START at 0x%x\r\n", + app_ram_base); + err_code = sd_ble_enable(p_ble_enable_params, &app_ram_base); + +#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1 + if (app_ram_base != ram_start) + { + uint32_t app_ram_size= ram_end_address_get(); + SD_HANDLER_LOG("sd_ble_enable: app_ram_base should be adjusted to 0x%x\r\n", + app_ram_base); + app_ram_size -= app_ram_base; + SD_HANDLER_LOG("ram size should be adjusted to 0x%x \r\n", + app_ram_size); + } + else if (err_code != NRF_SUCCESS) + { + SD_HANDLER_LOG("sd_ble_enable: error 0x%x\r\n", err_code); + while(1); + } +#endif // NRF_LOG_USES_RTT + return err_code; +#else + return NRF_SUCCESS; +#endif //defined(S130) || defined(S132) || defined(S332) + +} +/*lint -restore*/ +#endif + +#endif //BLE_STACK_SUPPORT_REQD diff --git a/softdevice/common/softdevice_handler/softdevice_handler.h b/softdevice/common/softdevice_handler/softdevice_handler.h new file mode 100644 index 0000000..7ed759e --- /dev/null +++ b/softdevice/common/softdevice_handler/softdevice_handler.h @@ -0,0 +1,215 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup softdevice_handler SoftDevice Event Handler + * @{ + * @ingroup app_common + * @brief API for initializing and disabling the SoftDevice + * + * @details This API contains the functions and defines exposed by the @ref lib_softdevice_handler. + * For more information on the library and how the application should use it, please refer + * @ref lib_softdevice_handler. + * + * @note Use the USE_SCHEDULER parameter of the SOFTDEVICE_HANDLER_INIT() macro to select if + * the @ref app_scheduler is to be used or not. + * + * @note Even if the scheduler is not used, softdevice_handler.h will include app_scheduler.h. + * So when compiling, app_scheduler.h must be available in one of the compiler include + * paths. + */ + +#ifndef SOFTDEVICE_HANDLER_H__ +#define SOFTDEVICE_HANDLER_H__ + +#include +#include "nordic_common.h" +#include "nrf_sdm.h" +#include "app_error.h" +#include "app_util.h" +#include "ble_stack_handler_types.h" +#include "ant_stack_handler_types.h" +#if defined(BLE_STACK_SUPPORT_REQD) + #include "ble.h" +#endif +#include "app_ram_base.h" +#define SOFTDEVICE_SCHED_EVT_SIZE 0 /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). For SoftDevice events, this size is 0, since the events are being pulled in the event handler. */ +#define SYS_EVT_MSG_BUF_SIZE sizeof(uint32_t) /**< Size of System (SOC) event message buffer. */ + + +#define CHECK_RAM_START_ADDR_INTERN(CENTRAL_LINK_COUNT, PERIPHERAL_LINK_COUNT) \ + do{ \ + uint32_t app_ram_start_addr = APP_RAM_BASE_CENTRAL_LINKS_##CENTRAL_LINK_COUNT##_PERIPH_LINKS_##PERIPHERAL_LINK_COUNT##_SEC_COUNT_0_MID_BW; \ + err_code = sd_check_ram_start(app_ram_start_addr); \ + APP_ERROR_CHECK(err_code); \ + } while (0) + +/** @brief Macro for checking the RAM requirement of the SoftDevice */ +#define CHECK_RAM_START_ADDR(C_LINK_CNT, P_LINK_CNT) CHECK_RAM_START_ADDR_INTERN(C_LINK_CNT, P_LINK_CNT) + + +/**@brief Function for checking the RAM requirement of the SoftDevice. + * + * @details Call this function to check if the project settings have the correct RAM start address in respect to what the SoftDevice requires. + * + * @note This function is called using the CHECK_RAM_START_ADDR_INTERN macro and should not be called directly. + */ +uint32_t sd_check_ram_start(uint32_t sd_req_ram_start); + +/**@brief Type of function for passing events from the stack handler module to the scheduler. */ +typedef uint32_t (*softdevice_evt_schedule_func_t) (void); + +/**@brief Application System (SOC) event handler type. */ +typedef void (*sys_evt_handler_t) (uint32_t evt_id); + + +/**@brief Macro for initializing the stack event handler. + * + * @details It will handle dimensioning and allocation of the memory buffer required for reading + * events from the stack, making sure the buffer is correctly aligned. It will also + * connect the stack event handler to the scheduler/RTOS (if specified). + * + * @param[in] CLOCK_SOURCE Low frequency clock source and accuracy (type nrf_clock_lf_cfg_t_t, + * see sd_softdevice_enable() for details). + * @param[in] EVT_HANDLER scheduler/RTOS event handler function. + * + * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it + * several times as long as it is from the same location, that is to do a + * reinitialization). + */ +/*lint -emacro(506, SOFTDEVICE_HANDLER_INIT) */ /* Suppress "Constant value Boolean */ +#define SOFTDEVICE_HANDLER_INIT(CLOCK_SOURCE, \ + EVT_HANDLER) \ + do \ + { \ + __ALIGN(4) static uint8_t BLE_EVT_BUFFER[ BLE_EVT_LEN_MAX(BLE_GATT_ATT_MTU_DEFAULT) ]; \ + uint32_t ERR_CODE; \ + ERR_CODE = softdevice_handler_init((CLOCK_SOURCE), \ + BLE_EVT_BUFFER, \ + sizeof(BLE_EVT_BUFFER), \ + EVT_HANDLER); \ + APP_ERROR_CHECK(ERR_CODE); \ + } while (0) + +/** + * @brief Function for retrieving the information about SD state + * + * The information about current state of softdevice. + * @retval false SD is not initialized and SD commands should not be called. + * @retval true SD is already initialized + */ +bool softdevice_handler_isEnabled(void); + +/**@brief Function for initializing the stack handler module. + * + * @details Enables the SoftDevice and the stack event interrupt handler. + * + * @note This function must be called before calling any function in the SoftDevice API. + * + * @note Normally initialization should be done using the SOFTDEVICE_HANDLER_INIT() macro, + * as that will both allocate the event buffer, and also align the buffer correctly. + * + * @param[in] p_clock_lf_cfg Low frequency clock source to be used by the SoftDevice. + * @param[in] p_ble_evt_buffer Buffer for holding one BLE stack event. Since heap is not being + * used, this buffer must be provided by the application. The + * buffer must be large enough to hold the biggest stack event the + * application is supposed to handle. The buffer must be aligned to + * a 4 byte boundary. This parameter is unused if BLE stack support + * is not required. + * @param[in] ble_evt_buffer_size Size of SoftDevice BLE event buffer. This parameter is unused if + * BLE stack support is not required. + * @param[in] evt_schedule_func Function for passing events to the scheduler. Point to + * ble_ant_stack_evt_schedule() to connect to the scheduler. + * Set to NULL to make the stack handler module call the event + * handler directly from the stack event interrupt handler. + * + * @retval NRF_SUCCESS Successful initialization. + * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte + * boundary) or NULL. + */ +uint32_t softdevice_handler_init(nrf_clock_lf_cfg_t * p_clock_lf_cfg, + void * p_ble_evt_buffer, + uint16_t ble_evt_buffer_size, + softdevice_evt_schedule_func_t evt_schedule_func); + + +/**@brief Function for disabling the SoftDevice. + * + * @details This function will disable the SoftDevice. It will also update the internal state + * of this module. + */ +uint32_t softdevice_handler_sd_disable(void); + +/**@brief Function for registering for System (SOC) events. + * + * @details The application should use this function to register for receiving System (SOC) + * events from the SoftDevice. If the application does not call this function, then any + * System (SOC) events that may be generated by the SoftDevice will NOT be fetched. Once + * the application has registered for the events, it is not possible to possible to + * cancel the registration. However, it is possible to register a different function for + * handling the events at any point of time. + * + * @param[in] sys_evt_handler Function to be called for each received System (SOC) event. + * + * @retval NRF_SUCCESS Successful registration. + * @retval NRF_ERROR_NULL Null pointer provided as input. + */ +uint32_t softdevice_sys_evt_handler_set(sys_evt_handler_t sys_evt_handler); + +#if 0 // S132 v500 change API +#if defined(BLE_STACK_SUPPORT_REQD) +/**@brief Function for fetching the default enable parameters for the SoftDevice. + * + * @details The default enable parameters will work for most projects in the SDK. + * They are not optimized with regards to RAM use. This function is meant as a way to abstract the + * details of p_ble_enable_params needed by @ref softdevice_enable. You might want to tweak + * the struct returned by this function or fill in the entire ble_enable_params_t + * instead of fetching it from this function. + * + * @param[in] central_links_count Number of central links used by the application. + * @param[in] periph_links_count Number of peripheral links used by the application. + * @param[out] p_ble_enable_params Default ble_enable_params_t to be used by @ref softdevice_enable. + * + * @retval NRF_SUCCESS If the operation was successful. + */ +uint32_t softdevice_enable_get_default_config(uint8_t central_links_count, + uint8_t periph_links_count, + ble_enable_params_t * p_ble_enable_params); + +/**@brief Function for enabling the SoftDevice. + * + * @details This function calls the @ref sd_ble_enable SVC call. It has been abstracted to give + * feedback on the app_ram_base. If the app_ram_base is too low, this function will + * return an error. Using a app_ram_base that is too high will not fail, but will + * result in RAM that is never used. If the DEBUG macro is enabled, this + * function will provide the correct app_ram_base as mandated by the SoftDevice. + * This is useful to tweak the RAM use of your application. + * + * @param[in] p_ble_enable_params Parameters for configuring links and bandwidths. + * + * @retval NRF_SUCCESS If the operation was successful. + */ +uint32_t softdevice_enable(ble_enable_params_t * p_ble_enable_params); +#endif //BLE_STACK_SUPPORT_REQD +#endif + +// Functions for connecting the Stack Event Handler to the scheduler: +/**@cond NO_DOXYGEN */ +void intern_softdevice_events_execute(void); + + +/**@endcond */ + +#endif // SOFTDEVICE_HANDLER_H__ + +/** @} */ diff --git a/softdevice/common/softdevice_handler/softdevice_handler_appsh.c b/softdevice/common/softdevice_handler/softdevice_handler_appsh.c new file mode 100644 index 0000000..c6da422 --- /dev/null +++ b/softdevice/common/softdevice_handler/softdevice_handler_appsh.c @@ -0,0 +1,26 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "softdevice_handler_appsh.h" +#include "app_scheduler.h" +#include + +void softdevice_evt_get(void * p_event_data, uint16_t event_size) +{ + APP_ERROR_CHECK_BOOL(event_size == 0); + intern_softdevice_events_execute(); +} + +uint32_t softdevice_evt_schedule(void) +{ + return app_sched_event_put(NULL, 0, softdevice_evt_get); +} diff --git a/softdevice/common/softdevice_handler/softdevice_handler_appsh.h b/softdevice/common/softdevice_handler/softdevice_handler_appsh.h new file mode 100644 index 0000000..7f3214e --- /dev/null +++ b/softdevice/common/softdevice_handler/softdevice_handler_appsh.h @@ -0,0 +1,24 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef SOFTDEVICE_HANDLER_APPSH_H +#define SOFTDEVICE_HANDLER_APPSH_H + +#include "softdevice_handler.h" +#include + +#define SOFTDEVICE_HANDLER_APPSH_INIT(CLOCK_SOURCE,USE_SCHEDULER) \ + SOFTDEVICE_HANDLER_INIT(CLOCK_SOURCE,(USE_SCHEDULER) ? softdevice_evt_schedule : NULL) + +uint32_t softdevice_evt_schedule(void); + +#endif //SOFTDEVICE_HANDLER_APPSH_H diff --git a/src/boards.h b/src/boards.h new file mode 100644 index 0000000..1fec4ea --- /dev/null +++ b/src/boards.h @@ -0,0 +1,65 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ +#ifndef BOARDS_H +#define BOARDS_H + +#include +#include +#include "nrf_gpio.h" + +#if defined BOARD_FEATHER52 +#include "feather52.h" +#elif defined BOARD_METRO52 +#include "metro52.h" +#else +#error No boards defined +#endif + +// Make sure we have at least two buttons (DFU + FRESET since DFU+FRST=OTA) +#if BUTTONS_NUMBER < 2 +#error "At least two buttons required in the BSP (see 'BUTTONS_NUMBER')" +#endif + +#define LED_RED LED_1 +#define LED_BLUE LED_2 + +#define bit(b) (1UL << (b)) + +static inline uint32_t bit_set(uint32_t value, uint8_t n) +{ + return value | bit(n); +} + +static inline uint32_t bit_clear(uint32_t value, uint8_t n) +{ + return value & (~bit(n)); +} + +static inline bool bit_test(uint32_t value, uint8_t n) +{ + return (value & bit(n)) ? true : false; +} + + +void led_control(uint32_t pin, bool state); + +static inline void led_on(uint32_t pin) +{ + led_control(pin, true); +} + +static inline void led_off(uint32_t pin) +{ + led_control(pin, false); +} + +#endif diff --git a/src/dfu_ble_svc.c b/src/dfu_ble_svc.c new file mode 100644 index 0000000..f37a167 --- /dev/null +++ b/src/dfu_ble_svc.c @@ -0,0 +1,205 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "dfu_ble_svc.h" +#include +#include "nrf_error.h" +#include "crc16.h" + +#if defined ( __CC_ARM ) +static dfu_ble_peer_data_t m_peer_data __attribute__((section("NoInit"), zero_init)); /**< This variable should be placed in a non initialized RAM section in order to be valid upon soft reset from application into bootloader. */ +static uint16_t m_peer_data_crc __attribute__((section("NoInit"), zero_init)); /**< CRC variable to ensure the integrity of the peer data provided. */ +#elif defined ( __GNUC__ ) +__attribute__((section(".noinit"))) static dfu_ble_peer_data_t m_peer_data; /**< This variable should be placed in a non initialized RAM section in order to be valid upon soft reset from application into bootloader. */ +__attribute__((section(".noinit"))) static uint16_t m_peer_data_crc; /**< CRC variable to ensure the integrity of the peer data provided. */ +#elif defined ( __ICCARM__ ) +__no_init static dfu_ble_peer_data_t m_peer_data @ 0x20003F80; /**< This variable should be placed in a non initialized RAM section in order to be valid upon soft reset from application into bootloader. */ +__no_init static uint16_t m_peer_data_crc @ 0x20003F80 + sizeof(dfu_ble_peer_data_t); /**< CRC variable to ensure the integrity of the peer data provided. */ +#endif + + +/**@brief Function for setting the peer data from application in bootloader before reset. + * + * @param[in] p_peer_data Pointer to the peer data containing keys for the connection. + * + * @retval NRF_SUCCES The data was set succesfully. + * @retval NRF_ERROR_NULL If a null pointer was passed as argument. + */ +static uint32_t dfu_ble_peer_data_set(dfu_ble_peer_data_t * p_peer_data) +{ + if (p_peer_data == NULL) + { + return NRF_ERROR_NULL; + } + + uint32_t src = (uint32_t)p_peer_data; + uint32_t dst = (uint32_t)&m_peer_data; + // Calculating length in order to check if destination is residing inside source. + // Source inside the the destination (calculation underflow) is safe a source is read before + // written to destination so that when destination grows into source, the source data is no + // longer needed. + uint32_t len = dst - src; + + if (src == dst) + { + // Do nothing as source and destination are identical, just calculate crc below. + } + else if (len < sizeof(dfu_ble_peer_data_t)) + { + uint32_t i = 0; + + dst += sizeof(dfu_ble_peer_data_t); + src += sizeof(dfu_ble_peer_data_t); + + // Copy byte wise backwards when facing overlapping structures. + while (i++ <= sizeof(dfu_ble_peer_data_t)) + { + *((uint8_t *)dst--) = *((uint8_t *)src--); + } + } + else + { + memcpy((void *)dst, (void *)src, sizeof(dfu_ble_peer_data_t)); + } + + m_peer_data_crc = crc16_compute((uint8_t *)&m_peer_data, sizeof(m_peer_data), NULL); + + return NRF_SUCCESS; +} + + +/**@brief Function for handling second stage of SuperVisor Calls (SVC). + * + * @details The function will use svc_num to call the corresponding SVC function. + * + * @param[in] svc_num SVC number for function to be executed + * @param[in] p_svc_args Argument list for the SVC. + * + * @return This function returns the error value of the SVC return. For further details, please + * refer to the details of the SVC implementation itself. + * @ref NRF_ERROR_SVC_HANDLER_MISSING is returned if no SVC handler is implemented for the + * provided svc_num. + */ +void C_SVC_Handler(uint8_t svc_num, uint32_t * p_svc_args) +{ + switch (svc_num) + { + case DFU_BLE_SVC_PEER_DATA_SET: + p_svc_args[0] = dfu_ble_peer_data_set((dfu_ble_peer_data_t *)p_svc_args[0]); + break; + + default: + p_svc_args[0] = NRF_ERROR_SVC_HANDLER_MISSING; + break; + } +} + + +/**@brief Function for handling the first stage of SuperVisor Calls (SVC) in assembly. + * + * @details The function will use the link register (LR) to determine the stack (PSP or MSP) to be + * used and then decode the SVC number afterwards. After decoding the SVC number then + * @ref C_SVC_Handler is called for further processing of the SVC. + */ +#if defined ( __CC_ARM ) +__asm void SVC_Handler(void) +{ +EXC_RETURN_CMD_PSP EQU 0xFFFFFFFD ; EXC_RETURN using PSP for ARM Cortex. If Link register contains this value it indicates the PSP was used before the SVC, otherwise the MSP was used. + + IMPORT C_SVC_Handler + LDR R0, =EXC_RETURN_CMD_PSP ; Load the EXC_RETURN into R0 to be able to compare against LR to determine stack pointer used. + CMP R0, LR ; Compare the link register with R0. If equal then PSP was used, otherwise MSP was used before SVC. + BNE UseMSP ; Branch to code fetching SVC arguments using MSP. + MRS R1, PSP ; Move PSP into R1. + B Call_C_SVC_Handler ; Branch to Call_C_SVC_Handler below. +UseMSP + MRS R1, MSP ; MSP was used, therefore Move MSP into R1. +Call_C_SVC_Handler + LDR R0, [R1, #24] ; The arguments for the SVC was stacked. R1 contains Stack Pointer, the values stacked before SVC are R0, R1, R2, R3, R12, LR, PC (Return address), xPSR. + ; R1 contains current SP so the PC of the stacked frame is at SP + 6 words (24 bytes). We load the PC into R0. + SUBS R0, #2 ; The PC before the SVC is in R0. We subtract 2 to get the address prior to the instruction executed where the SVC number is located. + LDRB R0, [R0] ; SVC instruction low octet: Load the byte at the address before the PC to fetch the SVC number. + LDR R2, =C_SVC_Handler ; Load address of C implementation of SVC handler. + BX R2 ; Branch to C implementation of SVC handler. R0 is now the SVC number, R1 is the StackPointer where the arguments (R0-R3) of the original SVC are located. + ALIGN +} +#elif defined ( __GNUC__ ) +void __attribute__ (( naked )) SVC_Handler(void) +{ + const uint32_t exc_return = 0xFFFFFFFD; // EXC_RETURN using PSP for ARM Cortex. If Link register contains this value it indicates the PSP was used before the SVC, otherwise the MSP was used. + + __asm volatile( + "cmp lr, %0\t\n" // Compare the link register with argument 0 (%0), which is exc_return. If equal then PSP was used, otherwise MSP was used before SVC. + "bne UseMSP\t\n" // Branch to code fetching SVC arguments using MSP. + "mrs r1, psp\t\n" // Move PSP into R1. + "b Call_C_SVC_Handler\t\n" // Branch to Call_C_SVC_Handler below. + "UseMSP: \t\n" // + "mrs r1, msp\t\n" // MSP was used, therefore Move MSP into R1. + "Call_C_SVC_Handler: \t\n" // + "ldr r0, [r1, #24]\t\n" // The arguments for the SVC was stacked. R1 contains Stack Pointer, the values stacked before SVC are R0, R1, R2, R3, R12, LR, PC (Return address), xPSR. + // R1 contains current SP so the PC of the stacked frame is at SP + 6 words (24 bytes). We load the PC into R0. + "sub r0, r0, #2\t\n" // The PC before the SVC is in R0. We subtract 2 to get the address prior to the instruction executed where the SVC number is located. + "ldrb r0, [r0]\t\n" // SVC instruction low octet: Load the byte at the address before the PC to fetch the SVC number. + "bx %1\t\n" // Branch to C implementation of SVC handler, argument 1 (%1). R0 is now the SVC number, R1 is the StackPointer where the arguments (R0-R3) of the original SVC are located. + ".align\t\n" + :: "r" (exc_return), "r" (C_SVC_Handler) // Argument list for the gcc assembly. exc_return is %0, C_SVC_Handler is %1. + : "r0", "r1" // List of register maintained manually. + ); +} +#elif defined ( __ICCARM__ ) +void SVC_Handler(void) +{ + asm("movs r0, #0x02\n" // Load 0x02 into R6 to prepare for exec return test. + "mvns r0, r0\n" // Invert R0 to obtain exec return code using PSP for ARM Cortex. + "cmp lr, r0\n" // Compare the link register with argument 0 (%0), which is exc_return. If equal then PSP was used, otherwise MSP was used before SVC. + "bne.n UseMSP\n" // Branch to code fetching SVC arguments using MSP. + "mrs r1, psp\n" // Move PSP into R1. + "b.n Call_C_SVC_Handler\t\n" // Branch to Call_C_SVC_Handler below. + "UseMSP: \n" // + "mrs r1, msp\n" // MSP was used, therefore Move MSP into R1. + "Call_C_SVC_Handler: \n" // + "ldr r0, [r1, #24]\n" // The arguments for the SVC was stacked. R1 contains Stack Pointer, the values stacked before SVC are R0, R1, R2, R3, R12, LR, PC (Return address), xPSR. + // R1 contains current SP so the PC of the stacked frame is at SP + 6 words (24 bytes). We load the PC into R0. + "subs r0, #0x02\n" // The PC before the SVC is in R0. We subtract 2 to get the address prior to the instruction executed where the SVC number is located. + "ldrb r0, [r0]\n" // SVC instruction low octet: Load the byte at the address before the PC to fetch the SVC number. + "bx %0\n" // Branch to C implementation of SVC handler, argument 1 (%1). R0 is now the SVC number, R1 is the StackPointer where the arguments (R0-R3) of the original SVC are located. + :: "r" (C_SVC_Handler) // Argument list for the gcc assembly. C_SVC_Handler is %0. + : "r0", "r1" // List of register maintained manually. + ); +} +#else +#error Compiler not supported. +#endif + + +uint32_t dfu_ble_peer_data_get(dfu_ble_peer_data_t * p_peer_data) +{ + uint16_t crc; + + if (p_peer_data == NULL) + { + return NRF_ERROR_NULL; + } + + crc = crc16_compute((uint8_t *)&m_peer_data, sizeof(m_peer_data), NULL); + if (crc != m_peer_data_crc) + { + return NRF_ERROR_INVALID_DATA; + } + + *p_peer_data = m_peer_data; + + // corrupt CRC to invalidate shared information. + m_peer_data_crc++; + + return NRF_SUCCESS; +} diff --git a/src/dualbank/Makefile b/src/dualbank/Makefile new file mode 100644 index 0000000..f66e401 --- /dev/null +++ b/src/dualbank/Makefile @@ -0,0 +1,7 @@ +#****************************************************************************** +# CONFIGURE +# - SINGLEBANK : 0 (dual), 1 (single) +#****************************************************************************** +VERSION_SINGLEBANK = 0 + +include ../make_common.mk diff --git a/src/feather52.h b/src/feather52.h new file mode 100644 index 0000000..70d4aa6 --- /dev/null +++ b/src/feather52.h @@ -0,0 +1,68 @@ +/**************************************************************************/ +/*! + @file feather52.h + @author hathach + + @section LICENSE + + Software License Agreement (BSD License) + + Copyright (c) ${year}, Adafruit Industries (adafruit.com) + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the copyright holders nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +/**************************************************************************/ + +#ifndef FEATHER52_H +#define FEATHER52_H + +/*------------------------------------------------------------------*/ +/* LED + *------------------------------------------------------------------*/ +#define LEDS_NUMBER 2 +#define LED_1 17 +#define LED_2 19 +#define LED_STATE_ON 1 + +/*------------------------------------------------------------------*/ +/* BUTTON + *------------------------------------------------------------------*/ +#define BUTTONS_NUMBER 2 +#define BUTTON_1 20 +#define BUTTON_2 22 +#define BUTTON_PULL NRF_GPIO_PIN_PULLUP + +/*------------------------------------------------------------------*/ +/* UART + *------------------------------------------------------------------*/ +#define RX_PIN_NUMBER 8 +#define TX_PIN_NUMBER 6 +#define CTS_PIN_NUMBER 7 +#define RTS_PIN_NUMBER 5 +#define HWFC false + +// Used as model string in OTA mode +#define DIS_MODEL "Bluefruit Feather 52" + +#endif // FEATHER52_H diff --git a/src/license.txt b/src/license.txt new file mode 100644 index 0000000..2ffb212 --- /dev/null +++ b/src/license.txt @@ -0,0 +1,117 @@ +This text contains two licenses (License #1, License #2). +License #1 applies to the whole SDK, except i) files including Dynastream copyright notices and ii) source files including BSD 3-clause license texts. +License #2 applies only to files including Dynastream copyright notices. +All must be read and accepted before proceeding. + + +License #1 + +License Agreement +Nordic Semiconductor ASA (“Nordic”) +Software Development Kit + + +You (“You” or “Licensee”) must carefully and thoroughly read this License Agreement (“Agreement”), and accept to adhere to this Agreement before downloading, installing and/or using any software or content in the Software Development Kit (“SDK”) provided herewith. + +YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SDK, IN THIS CASE YOU AGREE THAT THE USE OF THE SDK CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS. + +IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SDK OR RELATED CONTENT. + + +1. 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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; DAMAGE TO ANY DEVICE, LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +OF THE POSSIBILITY OF SUCH DAMAGE. SOME STATES DO NOT ALLOW +THE EXCLUSION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES, SO THE +ABOVE LIMITATIONS MAY NOT APPLY TO YOU. diff --git a/src/main.c b/src/main.c new file mode 100644 index 0000000..78cbc36 --- /dev/null +++ b/src/main.c @@ -0,0 +1,516 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * + * @defgroup ble_sdk_app_bootloader_main main.c + * @{ + * @ingroup dfu_bootloader_api + * @brief Bootloader project main file. + * + * -# Receive start data packet. + * -# Based on start packet, prepare NVM area to store received data. + * -# Receive data packet. + * -# Validate data packet. + * -# Write Data packet to NVM. + * -# If not finished - Wait for next packet. + * -# Receive stop data packet. + * -# Activate Image, boot application. + * + */ +#include +#include +#include +#include + +#include "dfu_transport.h" +#include "bootloader.h" +#include "bootloader_util.h" +#include "nordic_common.h" +#include "sdk_common.h" + +#include "nrf.h" +#include "nrf_soc.h" +#include "app_error.h" +#include "nrf_gpio.h" +#include "ble.h" +#include "nrf.h" +#include "ble_hci.h" +#include "app_scheduler.h" +#include "app_timer_appsh.h" +#include "nrf_error.h" +#include "boards.h" + +#include "softdevice_handler_appsh.h" +//#include "nrf_sdh.h" +//#include "nrf_sdh_ble.h" +//#include "nrf_sdh_soc.h" + + +#include "pstorage_platform.h" +#include "nrf_mbr.h" +//#include "nrf_log.h" + +#include "nrf_wdt.h" +#include "nrf_delay.h" +#include "pstorage.h" + + +#define BOOTLOADER_VERSION_REGISTER NRF_TIMER2->CC[0] + +#define LED_BLINK_INTERVAL 100 +#define BOOTLOADER_STARTUP_DFU_INTERVAL 1000 + +/* Magic that written to NRF_POWER->GPREGRET by application when it wish to go into DFU + * - BOOTLOADER_DFU_OTA_MAGIC used by BLEDfu service : SD is already init + * - BOOTLOADER_DFU_OTA_FULLRESET_MAGIC entered by soft reset : SD is not init + * - BOOTLOADER_DFU_SERIAL_MAGIC entered by soft reset : SD is not init + * + * Note: for BOOTLOADER_DFU_OTA_MAGIC Softdevice should not initialized. In other case SD must be initialized + */ +#define BOOTLOADER_DFU_OTA_MAGIC BOOTLOADER_DFU_START // 0xB1 +#define BOOTLOADER_DFU_OTA_FULLRESET_MAGIC 0xA8 +#define BOOTLOADER_DFU_SERIAL_MAGIC 0x4e + +#define BOOTLOADER_BUTTON BUTTON_1 // Button used to enter SW update mode. +#define FRESET_BUTTON BUTTON_2 // Button used in addition to DFU button, to force OTA DFU + +#define APP_TIMER_PRESCALER 0 /**< Value of the RTC1 PRESCALER register. */ +#define APP_TIMER_OP_QUEUE_SIZE 4 /**< Size of timer operation queues. */ + +#define SCHED_MAX_EVENT_DATA_SIZE MAX(APP_TIMER_SCHED_EVT_SIZE, 0) /**< Maximum size of scheduler events. */ +#define SCHED_QUEUE_SIZE 20 /**< Maximum number of events in the scheduler queue. */ + +// Helper function +#define memclr(buffer, size) memset(buffer, 0, size) +#define varclr(_var) memclr(_var, sizeof(*(_var))) +#define arrclr(_arr) memclr(_arr, sizeof(_arr)) +#define arrcount(_arr) ( sizeof(_arr) / sizeof(_arr[0]) ) + + +// These value must be the same with one in dfu_transport_ble.c +#define BLEGAP_EVENT_LENGTH 6 +#define BLEGATT_ATT_MTU_MAX 247 +enum { BLE_CONN_CFG_HIGH_BANDWIDTH = 1 }; + + + +// Adafruit for factory reset +#define APPDATA_ADDR_START (BOOTLOADER_REGION_START-DFU_APP_DATA_RESERVED) +STATIC_ASSERT( APPDATA_ADDR_START == 0x6D000); + +void adafruit_factory_reset(void); +volatile bool _freset_erased_complete = false; + +// Adafruit for Blink pattern +bool isBlinkFast = false; +bool isOTAConnected = false; + +APP_TIMER_DEF( blinky_timer_id ); + +// true if ble, false if serial +bool _ota_update = false; + +bool is_ota(void) { return _ota_update; } + +void assert_nrf_callback(uint16_t line_num, const uint8_t * p_file_name) +{ + app_error_handler(0xDEADBEEF, line_num, p_file_name); +} + +static void button_pin_init(uint32_t pin) +{ + nrf_gpio_cfg_sense_input(pin, BUTTON_PULL, NRF_GPIO_PIN_SENSE_LOW); +} + +bool button_pressed(uint32_t pin) +{ + return (nrf_gpio_pin_read(pin) == 0) ? true : false; +} + +static void led_pin_init(uint32_t pin) +{ +#ifdef BOARD_METRO52 + // LED BLUE is muxed with FRESET. We need to make sure it is + // not wired to GND before configuring it as output. + // Only check if it is not yet configured as OUTPUT + if (pin == LED_BLUE && !bit_test(NRF_GPIO->PIN_CNF[pin], GPIO_PIN_CNF_DIR_Pos)) + { + // skip and configure as input if grounded instead of output !!! + if ( button_pressed(pin) ) return; + } +#endif + + nrf_gpio_cfg_output(pin); + led_off(pin); +} + +void led_control(uint32_t pin, bool state) +{ +#ifdef BOARD_METRO52 + // Skip if LED_BLUE is configured as input and wiring to GND + // Otherwise configure it as output (it may just transition from hardware GND to open) + if ( pin == LED_2 && !bit_test(NRF_GPIO->PIN_CNF[pin], GPIO_PIN_CNF_DIR_Pos) ) + { + if ( button_pressed(pin) ) return; + + // configure as output + nrf_gpio_cfg_output(pin); + } +#endif + + nrf_gpio_pin_write(pin, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + + +/* + * Blinking function, there are a few patterns + * - DFU Serial : LED Status blink + * - DFU OTA : LED Status & Conn blink at the same time + * - DFU Flashing : LED Status blink 2x fast + * - Factory Reset : LED Status blink 2x fast + * - Fatal Error : LED Status & Conn blink one after another + */ +static void blinky_handler(void * p_context) +{ + static uint8_t state = 0; + static uint32_t count = 0; + + count++; + + // if not uploading then blink slow (interval/2) + if ( !isBlinkFast && count%2 ) return; + + state = 1-state; + + led_control(LED_RED, state); + + // Blink LED BLUE if OTA mode and not connected + if (is_ota() && !isOTAConnected) + { + led_control(LED_BLUE, state); + } + + // Feed all Watchdog just in case application enable it (WDT last through a soft reboot to bootloader) + if ( nrf_wdt_started() ) + { + for (uint8_t i=0; i<8; i++) nrf_wdt_reload_request_set(i); + } +} + +void blinky_fast_set(bool isFast) +{ + isBlinkFast = isFast; +} + +void blinky_ota_connected(void) +{ + isOTAConnected = true; +} + +void blinky_ota_disconneted(void) +{ + isOTAConnected = false; +} + + +/**@brief Function for dispatching a BLE stack event to all modules with a BLE stack event handler. + * + * @details This function is called from the scheduler in the main loop after a BLE stack + * event has been received. + * + * @param[in] p_ble_evt Bluetooth stack event. + */ +static void sys_evt_dispatch(uint32_t event) +{ + pstorage_sys_event_handler(event); +} + + +/**@brief Function for initializing the BLE stack. + * + * @details Initializes the SoftDevice and the BLE event interrupt. + * + * @param[in] init_softdevice true if SoftDevice should be initialized. The SoftDevice must only + * be initialized if a chip reset has occured. Soft reset from + * application must not reinitialize the SoftDevice. + */ +static uint32_t ble_stack_init(bool init_softdevice) +{ + uint32_t err_code; + nrf_clock_lf_cfg_t clock_lf_cfg = + { + .source = NRF_CLOCK_LF_SRC_RC, + .rc_ctiv = 16, + .rc_temp_ctiv = 2, + .accuracy = NRF_CLOCK_LF_ACCURACY_20_PPM + }; + + if (init_softdevice) + { + sd_mbr_command_t com = { .command = SD_MBR_COMMAND_INIT_SD }; + err_code = sd_mbr_command(&com); + APP_ERROR_CHECK(err_code); + } + + err_code = sd_softdevice_vector_table_base_set(BOOTLOADER_REGION_START); + APP_ERROR_CHECK(err_code); + + // equivalent to nrf_sdh_enable_request() + SOFTDEVICE_HANDLER_APPSH_INIT(&clock_lf_cfg, true); + + /*------------- Configure BLE params -------------*/ + extern uint32_t __data_start__[]; // defined in linker + uint32_t ram_start = (uint32_t) __data_start__; + + ble_cfg_t blecfg; + + // Configure the maximum number of connections. + varclr(&blecfg); + blecfg.gap_cfg.role_count_cfg.periph_role_count = 1; + blecfg.gap_cfg.role_count_cfg.central_role_count = 0; + blecfg.gap_cfg.role_count_cfg.central_sec_count = 0; + err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &blecfg, ram_start); + + // NRF_DFU_BLE_REQUIRES_BONDS + varclr(&blecfg); + blecfg.gatts_cfg.service_changed.service_changed = 1; + err_code = sd_ble_cfg_set(BLE_GATTS_CFG_SERVICE_CHANGED, &blecfg, ram_start); + VERIFY_SUCCESS(err_code); + + // ATT MTU + varclr(&blecfg); + blecfg.conn_cfg.conn_cfg_tag = BLE_CONN_CFG_HIGH_BANDWIDTH; + blecfg.conn_cfg.params.gatt_conn_cfg.att_mtu = BLEGATT_ATT_MTU_MAX; + err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATT, &blecfg, ram_start); + VERIFY_SUCCESS ( err_code ); + + // Event Length + HVN queue + WRITE CMD queue setting affecting bandwidth + varclr(&blecfg); + blecfg.conn_cfg.conn_cfg_tag = BLE_CONN_CFG_HIGH_BANDWIDTH; + blecfg.conn_cfg.params.gap_conn_cfg.conn_count = 1; + blecfg.conn_cfg.params.gap_conn_cfg.event_length = BLEGAP_EVENT_LENGTH; + err_code = sd_ble_cfg_set(BLE_CONN_CFG_GAP, &blecfg, ram_start); + VERIFY_SUCCESS ( err_code ); + + // Enable BLE stack. + err_code = sd_ble_enable(&ram_start); + VERIFY_SUCCESS(err_code); + + err_code = softdevice_sys_evt_handler_set(sys_evt_dispatch); + VERIFY_SUCCESS(err_code); + + return err_code; +} + + +/** + * @brief Function for event scheduler initialization. + */ +static void scheduler_init(void) +{ + APP_SCHED_INIT(SCHED_MAX_EVENT_DATA_SIZE, SCHED_QUEUE_SIZE); + + /* Initialize a blinky timer to show that we're in bootloader */ + (void) app_timer_create(&blinky_timer_id, APP_TIMER_MODE_REPEATED, blinky_handler); + app_timer_start(blinky_timer_id, APP_TIMER_TICKS(LED_BLINK_INTERVAL, APP_TIMER_PRESCALER), NULL); +} + + +/** + * @brief Function for bootloader main entry. + */ +int main(void) +{ + uint32_t err_code; + + // SD is already Initialized in case of BOOTLOADER_DFU_OTA_MAGIC + bool sd_inited = (NRF_POWER->GPREGRET == BOOTLOADER_DFU_OTA_MAGIC); + + // Start Bootloader in BLE OTA mode + _ota_update = (NRF_POWER->GPREGRET == BOOTLOADER_DFU_OTA_MAGIC) || + (NRF_POWER->GPREGRET == BOOTLOADER_DFU_OTA_FULLRESET_MAGIC); + + // start bootloader either serial or ble + bool dfu_start = _ota_update || (NRF_POWER->GPREGRET == BOOTLOADER_DFU_SERIAL_MAGIC); + + if (dfu_start) + { + // Clear GPREGRET if it is our values + NRF_POWER->GPREGRET = 0; + } + + // Save bootloader version to pre-defined register, retrieved by application + BOOTLOADER_VERSION_REGISTER = (BOOTLOADER_VERSION); + + // This check ensures that the defined fields in the bootloader corresponds with actual + // setting in the chip. + APP_ERROR_CHECK_BOOL(*((uint32_t *)NRF_UICR_BOOT_START_ADDRESS) == BOOTLOADER_REGION_START); + APP_ERROR_CHECK_BOOL(NRF_FICR->CODEPAGESIZE == CODE_PAGE_SIZE); + + /* Initialize GPIOs + * For metro52 LED_BLUE is muxed with FRESET + */ + button_pin_init(BOOTLOADER_BUTTON); + button_pin_init(FRESET_BUTTON); + nrf_delay_us(100); // wait for the pin state is stable + + led_pin_init(LED_RED); + led_pin_init(LED_BLUE); // on metro52 will override FRESET + + // Initialize timer module, already configred to use with the scheduler. + APP_TIMER_APPSH_INIT(APP_TIMER_PRESCALER, APP_TIMER_OP_QUEUE_SIZE, true); + + (void) bootloader_init(); + + if (bootloader_dfu_sd_in_progress()) + { + err_code = bootloader_dfu_sd_update_continue(); + APP_ERROR_CHECK(err_code); + + ble_stack_init(!sd_inited); + scheduler_init(); + + err_code = bootloader_dfu_sd_update_finalize(); + APP_ERROR_CHECK(err_code); + } + else + { + // If stack is present then continue initialization of bootloader. + ble_stack_init(!sd_inited); + scheduler_init(); + } + + /* For metro52 LED_BLUE is muxed with FRESET. We only init FRESET BUTTON + * as needed and reconfigure as LED BLUE when done. */ +#ifdef BOARD_METRO52 + button_pin_init(FRESET_BUTTON); + nrf_delay_us(100); // wait for the pin state is stable +#endif + + // DFU button pressed + dfu_start = dfu_start || button_pressed(BOOTLOADER_BUTTON); + + // DFU + FRESET are pressed --> OTA + _ota_update = _ota_update || ( button_pressed(BOOTLOADER_BUTTON) && button_pressed(FRESET_BUTTON) ) ; + +#ifdef BOARD_METRO52 + led_pin_init(LED_BLUE); +#endif + + if (dfu_start || (!bootloader_app_is_valid(DFU_BANK_0_REGION_START))) + { + // Initiate an update of the firmware. + err_code = bootloader_dfu_start(_ota_update, 0); + APP_ERROR_CHECK(err_code); + } + else + { + /* Adafruit Modification + * Even DFU is not active, we still force an 1000 ms dfu serial mode when startup + * to support auto programming from Arduino IDE + */ + (void) bootloader_dfu_start(false, BOOTLOADER_STARTUP_DFU_INTERVAL); + } + + // Adafruit Factory reset +#ifdef BOARD_METRO52 + button_pin_init(FRESET_BUTTON); + nrf_delay_us(100); // wait for the pin state is stable +#endif + + bool is_freset = ( !button_pressed(BOOTLOADER_BUTTON) && button_pressed(FRESET_BUTTON) ); + +#ifdef BOARD_METRO52 + led_pin_init(LED_BLUE); +#endif + + if (is_freset) + { + adafruit_factory_reset(); + } + + app_timer_stop(blinky_timer_id); + + if (bootloader_app_is_valid(DFU_BANK_0_REGION_START) && !bootloader_dfu_sd_in_progress()) + { + // Select a bank region to use as application region. + // @note: Only applications running from DFU_BANK_0_REGION_START is supported. + bootloader_app_start(DFU_BANK_0_REGION_START); + } + + NVIC_SystemReset(); +} + +/** + * Pstorage callback, fired after erased Application Data + */ +static void appdata_pstorage_cb(pstorage_handle_t * p_handle, uint8_t op_code, uint32_t result, + uint8_t * p_data, uint32_t data_len) +{ + if ( op_code == PSTORAGE_CLEAR_OP_CODE) + { + _freset_erased_complete = true; + } +} + +void freset_erase_and_wait(pstorage_handle_t* hdl, uint32_t addr, uint32_t size) +{ + _freset_erased_complete = false; + + // set address and start erasing + hdl->block_id = addr; + pstorage_clear(hdl, size); + + // Time to erase a page is 100 ms max + // It is better to force a timeout to prevent lock-up + uint32_t timeout_tck = (size/CODE_PAGE_SIZE)*100; + timeout_tck = APP_TIMER_TICKS(timeout_tck, APP_TIMER_PRESCALER); + + uint32_t start_tck; + app_timer_cnt_get(&start_tck); + + while(!_freset_erased_complete) + { + sd_app_evt_wait(); + app_sched_execute(); + + uint32_t now_tck; + app_timer_cnt_get(&now_tck); + if ( (now_tck - start_tck) > timeout_tck ) break; + } +} + +/** + * Perform factory reset to erase Application + Data + */ +void adafruit_factory_reset(void) +{ + // Blink fast RED and turn on BLUE when erasing + blinky_fast_set(true); + led_on(LED_BLUE); + + static pstorage_handle_t freset_handle = { .block_id = APPDATA_ADDR_START } ; + pstorage_module_param_t storage_params = { .cb = appdata_pstorage_cb}; + + pstorage_register(&storage_params, &freset_handle); + + // clear all App Data + freset_erase_and_wait(&freset_handle, APPDATA_ADDR_START, DFU_APP_DATA_RESERVED); + + // Only need to erase the 1st page of Application code to make it invalid + freset_erase_and_wait(&freset_handle, DFU_BANK_0_REGION_START, CODE_PAGE_SIZE); + + // back to normal + blinky_fast_set(false); + led_off(LED_BLUE); +} diff --git a/src/make_common.mk b/src/make_common.mk new file mode 100644 index 0000000..c3addaf --- /dev/null +++ b/src/make_common.mk @@ -0,0 +1,390 @@ +#****************************************************************************** +# CONFIGURE (no spaces!) +# - VERSION_MAJOR, VERSION_MINOR, VERSION_REVISION: e.g 5.0.0 or 5.1.0 (usually +# is the same to the SoftDevice if possible) +# +# - SDK_PATH : path to SDK directory +# - SRC_PATH : path to src folder +# +# - SD_NAME : e.g s132, s140 +# - SD_VERSION : e.g 5.1.0 +# - SD_HEX : path to bootloader hex binary +#****************************************************************************** +VERSION_MAJOR = 5 +VERSION_MINOR = 1 +VERSION_REVISION = 0 + +SDK_PATH = ../../nRF5_SDK_11.0.0_89a8197/components +SRC_PATH = .. + +SD_NAME = s132 +SD_VERSION = 5.1.0 + +SD_PATH = ../../softdevice/$(SD_NAME)/$(SD_VERSION) +SD_HEX = $(SD_PATH)/hex/$(SD_NAME)_nrf52_$(SD_VERSION)_softdevice.hex +LINKER_SCRIPT = $(SRC_PATH)/$(SD_NAME)_$(SD_VERSION).ld + +ifeq ($(VERSION_SINGLEBANK),1) +BANKMODE = single +C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/dfu_single_bank.c +else +BANKMODE = dual +C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/dfu_dual_bank.c +endif + +BOOTLOADER_S132_SUFFIX = $(VERSION_MAJOR).$(VERSION_MINOR).$(VERSION_REVISION)_$(SD_NAME)_$(BANKMODE) +FINAL_BIN_DIR := ../../bin + +TEMPLATE_PATH = $(SDK_PATH)/toolchain/gcc + + +#****************************************************************************** +# Tool configure +#****************************************************************************** +NRFUTIL = nrfutil + +ifeq ($(OS),Windows_NT) +PROGFILES = C:/Program Files (x86) +GNU_INSTALL_ROOT = $(PROGFILES)/GNU Tools ARM Embedded/6 2017-q2-update +else +GNU_INSTALL_ROOT = /usr +endif + +MK := mkdir +RM := rm -rf + +ifeq ("$(VERBOSE)","1") +NO_ECHO := +else +NO_ECHO := @ +endif + +GNU_PREFIX = arm-none-eabi + +# Toolchain commands +CC := '$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-gcc' +AS := '$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-as' +AR := '$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-ar' -r +LD := '$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-ld' +NM := '$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-nm' +OBJDUMP := '$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-objdump' +OBJCOPY := '$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-objcopy' +SIZE := '$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-size' + +#function for removing duplicates in a list +remduplicates = $(strip $(if $1,$(firstword $1) $(call remduplicates,$(filter-out $(firstword $1),$1)))) + + +#****************************************************************************** +# SOURCE FILES +#****************************************************************************** +#source common to all targets +C_SOURCE_FILES += $(SRC_PATH)/main.c +C_SOURCE_FILES += $(SRC_PATH)/dfu_ble_svc.c + +C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/bootloader.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/bootloader_settings.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/bootloader_util.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/dfu_init_template.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/dfu_transport_serial.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/dfu_transport_ble.c + +C_SOURCE_FILES += $(SDK_PATH)/libraries/timer/app_timer.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/timer/app_timer_appsh.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/scheduler/app_scheduler.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/util/app_error.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/util/app_error_weak.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/util/app_util_platform.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/crc16/crc16.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/hci/hci_mem_pool.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/hci/hci_slip.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/hci/hci_transport.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/util/nrf_assert.c +C_SOURCE_FILES += $(SDK_PATH)/libraries/uart/app_uart.c + +C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/delay/nrf_delay.c +C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/common/nrf_drv_common.c +C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/uart/nrf_drv_uart.c + +C_SOURCE_FILES += $(SDK_PATH)/ble/common/ble_advdata.c +C_SOURCE_FILES += $(SDK_PATH)/ble/common/ble_conn_params.c +C_SOURCE_FILES += $(SDK_PATH)/ble/common/ble_srv_common.c +C_SOURCE_FILES += $(SDK_PATH)/ble/ble_services/ble_dfu/ble_dfu.c +C_SOURCE_FILES += $(SDK_PATH)/ble/ble_services/ble_dis/ble_dis.c + +C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/pstorage/pstorage_raw.c +C_SOURCE_FILES += $(SDK_PATH)/toolchain/system_nrf52.c + +C_SOURCE_FILES += ../../softdevice/common/softdevice_handler/softdevice_handler.c +C_SOURCE_FILES += ../../softdevice/common/softdevice_handler/softdevice_handler_appsh.c + + + +#****************************************************************************** +# Assembly Files +#****************************************************************************** +ASM_SOURCE_FILES = $(SDK_PATH)/toolchain/gcc/gcc_startup_nrf52.S + +#****************************************************************************** +# INCLUDE PATH +#****************************************************************************** +INC_PATHS += -I$(SRC_PATH)/ + +INC_PATHS += -I$(SDK_PATH)/libraries/bootloader_dfu/hci_transport +INC_PATHS += -I$(SDK_PATH)/libraries/bootloader_dfu + +INC_PATHS += -I$(SDK_PATH)/libraries/timer +INC_PATHS += -I$(SDK_PATH)/libraries/scheduler +INC_PATHS += -I$(SDK_PATH)/libraries/crc16 +INC_PATHS += -I$(SDK_PATH)/libraries/util +INC_PATHS += -I$(SDK_PATH)/libraries/hci/config +INC_PATHS += -I$(SDK_PATH)/libraries/uart +INC_PATHS += -I$(SDK_PATH)/libraries/hci + +INC_PATHS += -I$(SDK_PATH)/drivers_nrf/common +INC_PATHS += -I$(SDK_PATH)/drivers_nrf/hal +INC_PATHS += -I$(SDK_PATH)/drivers_nrf/config +INC_PATHS += -I$(SDK_PATH)/drivers_nrf/delay +INC_PATHS += -I$(SDK_PATH)/drivers_nrf/uart + +INC_PATHS += -I../../softdevice/common +INC_PATHS += -I../../softdevice/common/softdevice_handler/ +INC_PATHS += -I$(SD_PATH)/headers +INC_PATHS += -I$(SD_PATH)/headers/nrf52 + +INC_PATHS += -I$(SDK_PATH)/device +INC_PATHS += -I$(SDK_PATH)/drivers_nrf/pstorage + +INC_PATHS += -I$(SDK_PATH)/toolchain/cmsis/include +INC_PATHS += -I$(SDK_PATH)/toolchain/gcc +INC_PATHS += -I$(SDK_PATH)/toolchain + +INC_PATHS += -I$(SDK_PATH)/ble/common +INC_PATHS += -I$(SDK_PATH)/ble/ble_services/ble_dfu +INC_PATHS += -I$(SDK_PATH)/ble/ble_services/ble_dis + +OBJECT_DIRECTORY = _build +LISTING_DIRECTORY = $(OBJECT_DIRECTORY) +OUTPUT_BINARY_DIRECTORY = $(OBJECT_DIRECTORY) + +# Sorting removes duplicates +BUILD_DIRECTORIES := $(sort $(OBJECT_DIRECTORY) $(OUTPUT_BINARY_DIRECTORY) $(LISTING_DIRECTORY)) + +#****************************************************************************** +# Compiler Flags +# - Additional compiler flags +#****************************************************************************** + +#flags common to all targets +#CFLAGS += -DENABLE_SWO + +#************************* +# Defined Symbol (MACROS) +#************************* +CFLAGS += -DBOOTLOADER_VERSION=0x0$(VERSION_MAJOR)0$(VERSION_MINOR)0$(VERSION_REVISION)0$(VERSION_SINGLEBANK)UL +CFLAGS += -DNRF52 +CFLAGS += -DNRF52_PAN_12 +CFLAGS += -DNRF52_PAN_15 +CFLAGS += -DNRF52_PAN_58 +CFLAGS += -DNRF52_PAN_55 +CFLAGS += -DNRF52_PAN_54 +CFLAGS += -DNRF52_PAN_31 +CFLAGS += -DNRF52_PAN_30 +CFLAGS += -DNRF52_PAN_51 +CFLAGS += -DNRF52_PAN_36 +CFLAGS += -DNRF52_PAN_53 +CFLAGS += -D__HEAP_SIZE=0 +CFLAGS += -DS132 +CFLAGS += -DCONFIG_GPIO_AS_PINRESET +CFLAGS += -DBLE_STACK_SUPPORT_REQD +CFLAGS += -DBSP_DEFINES_ONLY +CFLAGS += -DSWI_DISABLE0 +CFLAGS += -DNRF52_PAN_20 +CFLAGS += -DNRF52_PAN_64 +CFLAGS += -DSOFTDEVICE_PRESENT +CFLAGS += -DNRF52_PAN_62 +CFLAGS += -DNRF52_PAN_63 + +CFLAGS += -DDFU_APP_DATA_RESERVED=7*4096 + +CFLAGS += -mcpu=cortex-m4 +CFLAGS += -mthumb -mabi=aapcs --std=gnu99 +CFLAGS += -Wall -Werror -Os -g3 +CFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16 + +# keep every function in separate section. This will allow linker to dump unused functions +CFLAGS += -ffunction-sections -fdata-sections -fno-strict-aliasing +CFLAGS += -fno-builtin --short-enums + +#****************************************************************************** +# Linker Flags +# +#****************************************************************************** + +# keep every function in separate section. This will allow linker to dump unused functions +LDFLAGS += -Xlinker -Map=$(LISTING_DIRECTORY)/$(OUTPUT_FILENAME).map +LDFLAGS += -mthumb -mabi=aapcs -L $(TEMPLATE_PATH) -T$(LINKER_SCRIPT) +LDFLAGS += -mcpu=cortex-m4 +LDFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16 + +# let linker to dump unused sections +LDFLAGS += -Wl,--gc-sections + +# use newlib in nano version +LDFLAGS += --specs=nano.specs -lc -lnosys + +#****************************************************************************** +# Assembler flags +# +#****************************************************************************** +ASMFLAGS += -x assembler-with-cpp +ASMFLAGS += -DNRF52 +ASMFLAGS += -DNRF52_PAN_12 +ASMFLAGS += -DNRF52_PAN_15 +ASMFLAGS += -DNRF52_PAN_58 +ASMFLAGS += -DNRF52_PAN_55 +ASMFLAGS += -DNRF52_PAN_54 +ASMFLAGS += -DNRF52_PAN_31 +ASMFLAGS += -DNRF52_PAN_30 +ASMFLAGS += -DNRF52_PAN_51 +ASMFLAGS += -DNRF52_PAN_36 +ASMFLAGS += -DNRF52_PAN_53 +ASMFLAGS += -D__HEAP_SIZE=0 +ASMFLAGS += -DS132 +ASMFLAGS += -DCONFIG_GPIO_AS_PINRESET +ASMFLAGS += -DBLE_STACK_SUPPORT_REQD +ASMFLAGS += -DBSP_DEFINES_ONLY +ASMFLAGS += -DSWI_DISABLE0 +ASMFLAGS += -DNRF52_PAN_20 +ASMFLAGS += -DNRF52_PAN_64 +ASMFLAGS += -DSOFTDEVICE_PRESENT +ASMFLAGS += -DNRF52_PAN_62 +ASMFLAGS += -DNRF52_PAN_63 + +MAKEFILE_NAME := $(MAKEFILE_LIST) +MAKEFILE_DIR := $(dir $(MAKEFILE_NAME) ) + +#****************************************************************************** +# BUILD TARGETS +#****************************************************************************** + +ifeq ("$(VERBOSE)","1") +$(info CFLAGS $(CFLAGS)) +$(info ) +$(info LDFLAGS $(LDFLAGS)) +$(info ) +endif + +#default target - first one defined +default: all + +#building all targets +all: + @$(MAKE) -s -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e clean + @echo Making Feather52 board + @echo ---------------------- + @$(MAKE) -s -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e feather52 + @$(MAKE) -s -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e clean + @echo Making Metro52 board + @echo -------------------- + @$(MAKE) -s -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e metro52 + +#target for printing all targets +help: + @echo following targets are available: + @echo - feather52 : build for Feather nrf52 board + @echo - metro52 : build for Metro nrf52 board + @echo - flash_feather52 : flash Feather nrf52 board + @echo - flash_metro52 : flash Metro nrf52 board + +C_SOURCE_FILE_NAMES = $(notdir $(C_SOURCE_FILES)) +C_PATHS = $(call remduplicates, $(dir $(C_SOURCE_FILES) ) ) +C_OBJECTS = $(addprefix $(OBJECT_DIRECTORY)/, $(C_SOURCE_FILE_NAMES:.c=.o) ) + +ASM_SOURCE_FILE_NAMES = $(notdir $(ASM_SOURCE_FILES)) +ASM_PATHS = $(call remduplicates, $(dir $(ASM_SOURCE_FILES) )) +ASM_OBJECTS = $(addprefix $(OBJECT_DIRECTORY)/, $(ASM_SOURCE_FILE_NAMES:.S=.o) ) + +vpath %.c $(C_PATHS) +vpath %.S $(ASM_PATHS) + +OBJECTS = $(C_OBJECTS) $(ASM_OBJECTS) + +export OUTPUT_FILENAME +export FINAL_BIN_DIR +BOOTLOADER_WITH_S132_NAME := $(OUTPUT_FILENAME)_$(BOOTLOADER_S132_SUFFIX) + +# Target for Feather nrf52 board +feather52: OUTPUT_FILENAME := feather52_bootloader +feather52: FINAL_BIN_DIR := $(FINAL_BIN_DIR)/feather52/$(VERSION_MAJOR).$(VERSION_MINOR).$(VERSION_REVISION)/$(BANKMODE) +feather52: CFLAGS += -DBOARD_FEATHER52 +feather52: $(BUILD_DIRECTORIES) $(OBJECTS) + @echo Linking target: $(OUTPUT_FILENAME).out + $(NO_ECHO)$(CC) $(LDFLAGS) $(OBJECTS) $(LIBS) -lm -o $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out + $(NO_ECHO)$(MAKE) -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e finalize + +# Target for Metro nrf52 board +metro52: OUTPUT_FILENAME := metro52_bootloader +metro52: FINAL_BIN_DIR := $(FINAL_BIN_DIR)/metro52/$(BANKMODE) +metro52: CFLAGS += -DBOARD_METRO52 +metro52: $(BUILD_DIRECTORIES) $(OBJECTS) + @echo Linking target: $(OUTPUT_FILENAME).out + $(NO_ECHO)$(CC) $(LDFLAGS) $(OBJECTS) $(LIBS) -lm -o $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out + $(NO_ECHO)$(MAKE) -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e finalize + +## Create build directories +$(BUILD_DIRECTORIES): + @$(MK) $@ + +# Create objects from C SRC files +$(OBJECT_DIRECTORY)/%.o: %.c + @echo Compiling file: $(notdir $<) + $(NO_ECHO)$(CC) $(CFLAGS) $(INC_PATHS) -c -o $@ $< + +# Assemble files +$(OBJECT_DIRECTORY)/%.o: %.S + @echo Assembly file: $(notdir $<) + $(NO_ECHO)$(CC) $(ASMFLAGS) $(INC_PATHS) -c -o $@ $< + +# Link +$(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out: $(BUILD_DIRECTORIES) $(OBJECTS) + @echo Linking target: $(OUTPUT_FILENAME).out + $(NO_ECHO)$(CC) $(LDFLAGS) $(OBJECTS) $(LIBS) -lm -o $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out + +finalize: genhex genbin genpkg echosize + +## Create binary .hex file from the .out file +genhex: + @echo Preparing: $(OUTPUT_FILENAME).hex $(BOOTLOADER_WITH_S132_NAME).hex + $(NO_ECHO)$(OBJCOPY) -O ihex $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex + @mergehex -q -m $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex $(SD_HEX) -o $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex + @mkdir -p $(FINAL_BIN_DIR) + @cp $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex $(FINAL_BIN_DIR)/ + +## Create .bin file +genbin: + @echo Preparing: $(BOOTLOADER_WITH_S132_NAME).bin + $(NO_ECHO)$(OBJCOPY) -j .text -j .data -j .bss -O binary $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(FINAL_BIN_DIR)/$(BOOTLOADER_WITH_S132_NAME).bin + +## Create pkg file for bootloader only and bootloader+SD combo to use with DFU +genpkg: + @echo Preparing: $(BOOTLOADER_WITH_S132_NAME).zip + @$(NRFUTIL) dfu genpkg --dev-type 0x0052 --dev-revision 0xADAF --bootloader $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex --softdevice $(SD_HEX) $(FINAL_BIN_DIR)/$(BOOTLOADER_WITH_S132_NAME).zip + +echosize: + -@echo '' + $(NO_ECHO)$(SIZE) $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out + -@echo '' + +clean: + @$(RM) $(BUILD_DIRECTORIES) + +flash_feather52: BOOTLOADER_WITH_S132_NAME := feather52_bootloader_$(BOOTLOADER_S132_SUFFIX) +flash_feather52: feather52 + @echo Flashing: $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex + nrfjprog --program $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex -f nrf52 --chiperase --reset + +flash_metro52: BOOTLOADER_WITH_S132_NAME := metro52_bootloader_$(BOOTLOADER_S132_SUFFIX) +flash_metro52: metro52 + @echo Flashing: $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex + nrfjprog --program $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex -f nrf52 --chiperase --reset \ No newline at end of file diff --git a/src/metro52.h b/src/metro52.h new file mode 100644 index 0000000..2dc87d5 --- /dev/null +++ b/src/metro52.h @@ -0,0 +1,71 @@ +/**************************************************************************/ +/*! + @file metro52.h + @author hathach + + @section LICENSE + + Software License Agreement (BSD License) + + Copyright (c) 2017, Adafruit Industries (adafruit.com) + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the copyright holders nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +/**************************************************************************/ + +#ifndef METRO52_H +#define METRO52_H + +// Note: FRST and LED2 are on the same pin, so can't be used together +// LED2 will be disabled since it is less critical + +/*------------------------------------------------------------------*/ +/* LED + *------------------------------------------------------------------*/ +#define LEDS_NUMBER 2 +#define LED_1 29 +#define LED_2 22 +#define LED_STATE_ON 1 + +/*------------------------------------------------------------------*/ +/* BUTTON + *------------------------------------------------------------------*/ +#define BUTTONS_NUMBER 2 +#define BUTTON_1 18 +#define BUTTON_2 22 +#define BUTTON_PULL NRF_GPIO_PIN_PULLUP + +/*------------------------------------------------------------------*/ +/* UART + *------------------------------------------------------------------*/ +#define RX_PIN_NUMBER 23 +#define TX_PIN_NUMBER 8 +#define CTS_PIN_NUMBER 0 +#define RTS_PIN_NUMBER 0 +#define HWFC false + +// Used as model string in OTA mode +#define DIS_MODEL "Bluefruit Metro 52" + +#endif // METRO52_H diff --git a/src/nrf_drv_config.h b/src/nrf_drv_config.h new file mode 100644 index 0000000..494eb85 --- /dev/null +++ b/src/nrf_drv_config.h @@ -0,0 +1,464 @@ +/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_DRV_CONFIG_H +#define NRF_DRV_CONFIG_H + +/** + * Provide a non-zero value here in applications that need to use several + * peripherals with the same ID that are sharing certain resources + * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used + * simultaneously. Therefore, this definition allows to initialize the driver + * for another peripheral from a given group only after the previously used one + * is uninitialized. Normally, this is not possible, because interrupt handlers + * are implemented in individual drivers. + * This functionality requires a more complicated interrupt handling and driver + * initialization, hence it is not always desirable to use it. + */ +#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0 + +/* CLOCK */ +#define CLOCK_ENABLED 0 + +#if (CLOCK_ENABLED == 1) +#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default +#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal +#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + +/* GPIOTE */ +#define GPIOTE_ENABLED 0 + +#if (GPIOTE_ENABLED == 1) +#define GPIOTE_CONFIG_USE_SWI_EGU false +#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +/* TIMER */ +#define TIMER0_ENABLED 0 + +#if (TIMER0_ENABLED == 1) +#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit +#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER0_INSTANCE_INDEX 0 +#endif + +#define TIMER1_ENABLED 0 + +#if (TIMER1_ENABLED == 1) +#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit +#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED) +#endif + +#define TIMER2_ENABLED 0 + +#if (TIMER2_ENABLED == 1) +#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit +#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED) +#endif + +#define TIMER3_ENABLED 0 + +#if (TIMER3_ENABLED == 1) +#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit +#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) +#endif + +#define TIMER4_ENABLED 0 + +#if (TIMER4_ENABLED == 1) +#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz +#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer +#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit +#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) +#endif + + +#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED) + +/* RTC */ +#define RTC0_ENABLED 0 + +#if (RTC0_ENABLED == 1) +#define RTC0_CONFIG_FREQUENCY 32678 +#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define RTC0_CONFIG_RELIABLE false + +#define RTC0_INSTANCE_INDEX 0 +#endif + +#define RTC1_ENABLED 0 + +#if (RTC1_ENABLED == 1) +#define RTC1_CONFIG_FREQUENCY 32768 +#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define RTC1_CONFIG_RELIABLE false + +#define RTC1_INSTANCE_INDEX (RTC0_ENABLED) +#endif + +#define RTC2_ENABLED 0 + +#if (RTC2_ENABLED == 1) +#define RTC2_CONFIG_FREQUENCY 32768 +#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define RTC2_CONFIG_RELIABLE false + +#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED) +#endif + + +#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED) + +#define NRF_MAXIMUM_LATENCY_US 2000 + +/* RNG */ +#define RNG_ENABLED 0 + +#if (RNG_ENABLED == 1) +#define RNG_CONFIG_ERROR_CORRECTION true +#define RNG_CONFIG_POOL_SIZE 8 +#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + +/* PWM */ + +#define PWM0_ENABLED 0 + +#if (PWM0_ENABLED == 1) +#define PWM0_CONFIG_OUT0_PIN 2 +#define PWM0_CONFIG_OUT1_PIN 3 +#define PWM0_CONFIG_OUT2_PIN 4 +#define PWM0_CONFIG_OUT3_PIN 5 +#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz +#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP +#define PWM0_CONFIG_TOP_VALUE 1000 +#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON +#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO + +#define PWM0_INSTANCE_INDEX 0 +#endif + +#define PWM1_ENABLED 0 + +#if (PWM1_ENABLED == 1) +#define PWM1_CONFIG_OUT0_PIN 2 +#define PWM1_CONFIG_OUT1_PIN 3 +#define PWM1_CONFIG_OUT2_PIN 4 +#define PWM1_CONFIG_OUT3_PIN 5 +#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz +#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP +#define PWM1_CONFIG_TOP_VALUE 1000 +#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON +#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO + +#define PWM1_INSTANCE_INDEX (PWM0_ENABLED) +#endif + +#define PWM2_ENABLED 0 + +#if (PWM2_ENABLED == 1) +#define PWM2_CONFIG_OUT0_PIN 2 +#define PWM2_CONFIG_OUT1_PIN 3 +#define PWM2_CONFIG_OUT2_PIN 4 +#define PWM2_CONFIG_OUT3_PIN 5 +#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz +#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP +#define PWM2_CONFIG_TOP_VALUE 1000 +#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON +#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO + +#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED) +#endif + +#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED) + +/* SPI */ +#define SPI0_ENABLED 0 + +#if (SPI0_ENABLED == 1) +#define SPI0_USE_EASY_DMA 0 + +#define SPI0_CONFIG_SCK_PIN 2 +#define SPI0_CONFIG_MOSI_PIN 3 +#define SPI0_CONFIG_MISO_PIN 4 +#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPI0_INSTANCE_INDEX 0 +#endif + +#define SPI1_ENABLED 0 + +#if (SPI1_ENABLED == 1) +#define SPI1_USE_EASY_DMA 0 + +#define SPI1_CONFIG_SCK_PIN 2 +#define SPI1_CONFIG_MOSI_PIN 3 +#define SPI1_CONFIG_MISO_PIN 4 +#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPI1_INSTANCE_INDEX (SPI0_ENABLED) +#endif + +#define SPI2_ENABLED 0 + +#if (SPI2_ENABLED == 1) +#define SPI2_USE_EASY_DMA 0 + +#define SPI2_CONFIG_SCK_PIN 2 +#define SPI2_CONFIG_MOSI_PIN 3 +#define SPI2_CONFIG_MISO_PIN 4 +#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED) +#endif + +#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED) + +/* SPIS */ +#define SPIS0_ENABLED 0 + +#if (SPIS0_ENABLED == 1) +#define SPIS0_CONFIG_SCK_PIN 2 +#define SPIS0_CONFIG_MOSI_PIN 3 +#define SPIS0_CONFIG_MISO_PIN 4 +#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPIS0_INSTANCE_INDEX 0 +#endif + +#define SPIS1_ENABLED 0 + +#if (SPIS1_ENABLED == 1) +#define SPIS1_CONFIG_SCK_PIN 2 +#define SPIS1_CONFIG_MOSI_PIN 3 +#define SPIS1_CONFIG_MISO_PIN 4 +#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED +#endif + +#define SPIS2_ENABLED 0 + +#if (SPIS2_ENABLED == 1) +#define SPIS2_CONFIG_SCK_PIN 2 +#define SPIS2_CONFIG_MOSI_PIN 3 +#define SPIS2_CONFIG_MISO_PIN 4 +#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED) +#endif + +#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED) + +/* UART */ +#define UART0_ENABLED 1 + +#if (UART0_ENABLED == 1) +#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED +#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED +#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200 +#define UART0_CONFIG_PSEL_TXD 6 +#define UART0_CONFIG_PSEL_RXD 8 +#define UART0_CONFIG_PSEL_CTS 7 +#define UART0_CONFIG_PSEL_RTS 5 +#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#ifdef NRF52 +#define UART0_CONFIG_USE_EASY_DMA false +//Compile time flag +#define UART_EASY_DMA_SUPPORT 1 +#define UART_LEGACY_SUPPORT 1 +#endif //NRF52 +#endif + +#define TWI0_ENABLED 0 + +#if (TWI0_ENABLED == 1) +#define TWI0_USE_EASY_DMA 0 + +#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K +#define TWI0_CONFIG_SCL 0 +#define TWI0_CONFIG_SDA 1 +#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TWI0_INSTANCE_INDEX 0 +#endif + +#define TWI1_ENABLED 0 + +#if (TWI1_ENABLED == 1) +#define TWI1_USE_EASY_DMA 0 + +#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K +#define TWI1_CONFIG_SCL 0 +#define TWI1_CONFIG_SDA 1 +#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + +#define TWI1_INSTANCE_INDEX (TWI0_ENABLED) +#endif + +#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED) + +/* TWIS */ +#define TWIS0_ENABLED 0 + +#if (TWIS0_ENABLED == 1) + #define TWIS0_CONFIG_ADDR0 0 + #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */ + #define TWIS0_CONFIG_SCL 0 + #define TWIS0_CONFIG_SDA 1 + #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + + #define TWIS0_INSTANCE_INDEX 0 +#endif + +#define TWIS1_ENABLED 0 + +#if (TWIS1_ENABLED == 1) + #define TWIS1_CONFIG_ADDR0 0 + #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */ + #define TWIS1_CONFIG_SCL 0 + #define TWIS1_CONFIG_SDA 1 + #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW + + #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED) +#endif + +#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED) +/* For more documentation see nrf_drv_twis.h file */ +#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +/* For more documentation see nrf_drv_twis.h file */ +#define TWIS_NO_SYNC_MODE 0 + +/* QDEC */ +#define QDEC_ENABLED 0 + +#if (QDEC_ENABLED == 1) +#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10 +#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us +#define QDEC_CONFIG_PIO_A 1 +#define QDEC_CONFIG_PIO_B 2 +#define QDEC_CONFIG_PIO_LED 3 +#define QDEC_CONFIG_LEDPRE 511 +#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH +#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define QDEC_CONFIG_DBFEN false +#define QDEC_CONFIG_SAMPLE_INTEN false +#endif + +/* ADC */ +#define ADC_ENABLED 0 + +#if (ADC_ENABLED == 1) +#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + + +/* SAADC */ +#define SAADC_ENABLED 0 + +#if (SAADC_ENABLED == 1) +#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT +#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED +#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + +/* PDM */ +#define PDM_ENABLED 0 + +#if (PDM_ENABLED == 1) +#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO +#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING +#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K +#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#endif + +/* COMP */ +#define COMP_ENABLED 0 + +#if (COMP_ENABLED == 1) +#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8 +#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE +#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High +#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst +#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off +#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0 +#endif + +/* LPCOMP */ +#define LPCOMP_ENABLED 0 + +#if (LPCOMP_ENABLED == 1) +#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8 +#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN +#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW +#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0 +#endif + +/* WDT */ +#define WDT_ENABLED 0 + +#if (WDT_ENABLED == 1) +#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP +#define WDT_CONFIG_RELOAD_VALUE 2000 +#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH +#endif + +/* SWI EGU */ +#ifdef NRF52 + #define EGU_ENABLED 0 +#endif + +/* I2S */ +#define I2S_ENABLED 0 + +#if (I2S_ENABLED == 1) +#define I2S_CONFIG_SCK_PIN 22 +#define I2S_CONFIG_LRCK_PIN 23 +#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED +#define I2S_CONFIG_SDOUT_PIN 24 +#define I2S_CONFIG_SDIN_PIN 25 +#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH +#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER +#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S +#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT +#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT +#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO +#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8 +#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X +#endif + +#include "nrf_drv_config_validation.h" + +#endif // NRF_DRV_CONFIG_H diff --git a/src/pstorage_platform.h b/src/pstorage_platform.h new file mode 100644 index 0000000..75af90e --- /dev/null +++ b/src/pstorage_platform.h @@ -0,0 +1,78 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + + /** @cond To make doxygen skip this file */ + +/** @file + * This header contains defines with respect persistent storage that are specific to + * persistent storage implementation and application use case. + */ +#ifndef PSTORAGE_PL_H__ +#define PSTORAGE_PL_H__ + +#include +#include "nrf.h" + +static __INLINE uint16_t pstorage_flash_page_size() +{ + return (uint16_t)NRF_FICR->CODEPAGESIZE; +} + +#define PSTORAGE_FLASH_PAGE_SIZE pstorage_flash_page_size() /**< Size of one flash page. */ +#define PSTORAGE_FLASH_EMPTY_MASK 0xFFFFFFFF /**< Bit mask that defines an empty address in flash. */ + +static __INLINE uint32_t pstorage_flash_page_end() +{ + uint32_t bootloader_addr = NRF_UICR->NRFFW[0]; + + return ((bootloader_addr != PSTORAGE_FLASH_EMPTY_MASK) ? + (bootloader_addr/ PSTORAGE_FLASH_PAGE_SIZE) : NRF_FICR->CODESIZE); +} + +#define PSTORAGE_FLASH_PAGE_END pstorage_flash_page_end() + +#define PSTORAGE_NUM_OF_PAGES 4 //3 /**< Number of flash pages allocated for the pstorage module excluding the swap page, configurable based on system requirements. */ +#define PSTORAGE_MIN_BLOCK_SIZE 0x0010 /**< Minimum size of block that can be registered with the module. Should be configured based on system requirements, recommendation is not have this value to be at least size of word. */ + +#define PSTORAGE_DATA_START_ADDR ((PSTORAGE_FLASH_PAGE_END - PSTORAGE_NUM_OF_PAGES) \ + * PSTORAGE_FLASH_PAGE_SIZE) /**< Start address for persistent data, configurable according to system requirements. */ +#define PSTORAGE_DATA_END_ADDR (PSTORAGE_FLASH_PAGE_END * PSTORAGE_FLASH_PAGE_SIZE) /**< End address for persistent data, configurable according to system requirements. */ +#define PSTORAGE_SWAP_ADDR PSTORAGE_DATA_END_ADDR + +#define PSTORAGE_MAX_BLOCK_SIZE PSTORAGE_FLASH_PAGE_SIZE /**< Maximum size of block that can be registered with the module. Should be configured based on system requirements. And should be greater than or equal to the minimum size. */ +#define PSTORAGE_CMD_QUEUE_SIZE 10 /**< Maximum number of flash access commands that can be maintained by the module for all applications. Configurable. */ + +/**@breif Define this flag in case Raw access to persistent memory is to be enabled. Raw mode + * unlike the data mode is for uses other than storing data from various mode. This mode is + * employed when unpdating firmware or similar uses. Therefore, this mode shall be enabled + * only for these special usecases and typically disabled. + */ +#define PSTORAGE_RAW_MODE_ENABLE + +/** Abstracts persistently memory block identifier. */ +typedef uint32_t pstorage_block_t; + +typedef struct +{ + uint32_t module_id; /**< Module ID.*/ + pstorage_block_t block_id; /**< Block ID.*/ +} pstorage_handle_t; + +typedef uint32_t pstorage_size_t; /** Size of length and offset fields. */ + +/**@brief Handles Flash Access Result Events. To be called in the system event dispatcher of the application. */ +void pstorage_sys_event_handler (uint32_t sys_evt); + +#endif // PSTORAGE_PL_H__ + +/** @} */ +/** @endcond */ diff --git a/src/s132_2.0.1.ld b/src/s132_2.0.1.ld new file mode 100644 index 0000000..f8d0c69 --- /dev/null +++ b/src/s132_2.0.1.ld @@ -0,0 +1,78 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + /** Flash start address for the bootloader. This setting will also be stored in UICR to allow the + * MBR to init the bootloader when starting the system. This value must correspond to + * BOOTLOADER_REGION_START found in dfu_types.h. The system is prevented from starting up if + * those values do not match. The check is performed in main.c, see + * APP_ERROR_CHECK_BOOL(*((uint32_t *)NRF_UICR_BOOT_START_ADDRESS) == BOOTLOADER_REGION_START); + */ + FLASH (rx) : ORIGIN = 0x74000, LENGTH = 0xA000 /* 40 KB */ + + /** RAM Region for bootloader. This setting is suitable when used with s132. */ + RAM (rwx) : ORIGIN = 0x20002C00, LENGTH = 0x5380 + + /** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information + * from application to bootloader when using buttonluss DFU OTA. + */ + NOINIT (rwx) : ORIGIN = 0x20007F80, LENGTH = 0x80 + + /** Location of bootloader setting in flash. */ + BOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000 + + /** Location in UICR where bootloader start address is stored. */ + UICR_BOOTLOADER (r) : ORIGIN = 0x10001014, LENGTH = 0x04 + + /** Location of mbr params page in flash. */ + MBR_PARAMS_PAGE (rw) : ORIGIN = 0x0007E000, LENGTH = 0x1000 + + /** Location in UICR where mbr params page address is stored. */ + UICR_MBR_PARAM_PAGE(r) : ORIGIN = 0x10001018, LENGTH = 0x04 +} + +SECTIONS +{ + .fs_data_out ALIGN(4): + { + PROVIDE( __start_fs_data = .); + KEEP(*(fs_data)) + PROVIDE( __stop_fs_data = .); + } = 0 + + /* Place the bootloader settings page in flash. */ + .bootloaderSettings(NOLOAD) : + { + + } > BOOTLOADER_SETTINGS + + /* Write the bootloader address in UICR. */ + .uicrBootStartAddress : + { + KEEP(*(.uicrBootStartAddress)) + } > UICR_BOOTLOADER + + /* Place the mbr params page in flash. */ + .mbrParamsPage(NOLOAD) : + { + + } > MBR_PARAMS_PAGE + + /* Write the bootloader address in UICR. */ + .uicrMbrParamsPageAddress : + { + KEEP(*(.uicrMbrParamsPageAddress)) + } > UICR_MBR_PARAM_PAGE + + /* No init RAM section in bootloader. Used for bond information exchange. */ + .noinit(NOLOAD) : + { + + } > NOINIT + /* other placements follow here... */ +} + +INCLUDE "nrf52_common.ld" diff --git a/src/s132_5.1.0.ld b/src/s132_5.1.0.ld new file mode 100644 index 0000000..dce6bff --- /dev/null +++ b/src/s132_5.1.0.ld @@ -0,0 +1,78 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + /** Flash start address for the bootloader. This setting will also be stored in UICR to allow the + * MBR to init the bootloader when starting the system. This value must correspond to + * BOOTLOADER_REGION_START found in dfu_types.h. The system is prevented from starting up if + * those values do not match. The check is performed in main.c, see + * APP_ERROR_CHECK_BOOL(*((uint32_t *)NRF_UICR_BOOT_START_ADDRESS) == BOOTLOADER_REGION_START); + */ + FLASH (rx) : ORIGIN = 0x74000, LENGTH = 0xA000 /* 40 KB */ + + /** RAM Region for bootloader. This setting is suitable when used with s132. */ + RAM (rwx) : ORIGIN = 0x20003000, LENGTH = 0x4000 + + /** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information + * from application to bootloader when using buttonluss DFU OTA. + */ + NOINIT (rwx) : ORIGIN = 0x20007F80, LENGTH = 0x80 + + /** Location of bootloader setting in flash. */ + BOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000 + + /** Location in UICR where bootloader start address is stored. */ + UICR_BOOTLOADER (r) : ORIGIN = 0x10001014, LENGTH = 0x04 + + /** Location of mbr params page in flash. */ + MBR_PARAMS_PAGE (rw) : ORIGIN = 0x0007E000, LENGTH = 0x1000 + + /** Location in UICR where mbr params page address is stored. */ + UICR_MBR_PARAM_PAGE(r) : ORIGIN = 0x10001018, LENGTH = 0x04 +} + +SECTIONS +{ + .fs_data_out ALIGN(4): + { + PROVIDE( __start_fs_data = .); + KEEP(*(fs_data)) + PROVIDE( __stop_fs_data = .); + } = 0 + + /* Place the bootloader settings page in flash. */ + .bootloaderSettings(NOLOAD) : + { + + } > BOOTLOADER_SETTINGS + + /* Write the bootloader address in UICR. */ + .uicrBootStartAddress : + { + KEEP(*(.uicrBootStartAddress)) + } > UICR_BOOTLOADER + + /* Place the mbr params page in flash. */ + .mbrParamsPage(NOLOAD) : + { + + } > MBR_PARAMS_PAGE + + /* Write the bootloader address in UICR. */ + .uicrMbrParamsPageAddress : + { + KEEP(*(.uicrMbrParamsPageAddress)) + } > UICR_MBR_PARAM_PAGE + + /* No init RAM section in bootloader. Used for bond information exchange. */ + .noinit(NOLOAD) : + { + + } > NOINIT + /* other placements follow here... */ +} + +INCLUDE "nrf52_common.ld" diff --git a/src/sdk_config.h b/src/sdk_config.h new file mode 100644 index 0000000..2b3dc09 --- /dev/null +++ b/src/sdk_config.h @@ -0,0 +1,3233 @@ +/** + * Copyright (c) 2017 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + + +#ifndef SDK_CONFIG_H +#define SDK_CONFIG_H +// <<< Use Configuration Wizard in Context Menu >>>\n +#ifdef USE_APP_CONFIG +#include "app_config.h" +#endif +// nRF_BLE_DFU + +//========================================================== +// NRF_DFU_BLE_REQUIRES_BONDS - nrf_ble_dfu - BLE DFU module + + +#ifndef NRF_DFU_BLE_REQUIRES_BONDS +#define NRF_DFU_BLE_REQUIRES_BONDS 0 +#endif + +// +//========================================================== + +// nRF_Bootloader + +//========================================================== +// nrf_dfu - DFU Bootloader + +//========================================================== +// NRF_DFU_INACTIVITY_TIMEOUT_MS - Timeout in ms before automatically starting a valid application due to inactivity <100-60000000> + + +#ifndef NRF_DFU_INACTIVITY_TIMEOUT_MS +#define NRF_DFU_INACTIVITY_TIMEOUT_MS 120000 +#endif + +// NRF_DFU_POST_SD_BL_TIMEOUT_MS - Timeout in ms before automatically starting a valid application after a bootloader or SoftDevice update <100-60000000> + + +#ifndef NRF_DFU_POST_SD_BL_TIMEOUT_MS +#define NRF_DFU_POST_SD_BL_TIMEOUT_MS 10000 +#endif + +// DFU flash buffers + +//========================================================== +// FLASH_BUFFER_COUNT - Number of flash buffers. +// Must be a power of two. + +#ifndef FLASH_BUFFER_COUNT +#define FLASH_BUFFER_COUNT 4 +#endif + +// FLASH_BUFFER_LENGTH - Length of a flash buffer, in bytes. +// Must be a multiple of the word size. + +#ifndef FLASH_BUFFER_LENGTH +#define FLASH_BUFFER_LENGTH 128 +#endif + +// +//========================================================== + +// +//========================================================== + +// +//========================================================== + +// nRF_Crypto + +//========================================================== +// NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library +//========================================================== +#ifndef NRF_CRYPTO_ENABLED +#define NRF_CRYPTO_ENABLED 1 +#endif +// NRF_CRYPTO_BACKEND_CC310_LIB - Enable the ARM Cryptocell CC310 backend + + +// The hardware-accelerated cryptography backend is available only on nRF52840. + +#ifndef NRF_CRYPTO_BACKEND_CC310_LIB +#define NRF_CRYPTO_BACKEND_CC310_LIB 0 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC - Enable the micro-ecc software backend + +// The micro-ecc library provides a software implementation of ECC cryptography for nRF5 Series devices. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC +#define NRF_CRYPTO_BACKEND_MICRO_ECC 1 +#endif +// NRF_CRYPTO_BACKEND_MICRO_ECC_SHA256 - Enable SHA256 + + +// Enable SHA256 cryptographic hash functionality. +// Enable this setting if you need SHA256 support, for example to verify signatures. + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_SHA256 +#define NRF_CRYPTO_BACKEND_MICRO_ECC_SHA256 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_RNG - Enable random number generator + + +// Enable random number generation. +// Enable this setting if you need to generate cryptographic keys. +// This setting requires the RNG peripheral driver to be present. + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_RNG +#define NRF_CRYPTO_BACKEND_MICRO_ECC_RNG 0 +#endif + +// + +// + +// +//========================================================== + +// nRF_Drivers + +//========================================================== +// CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver +//========================================================== +#ifndef CLOCK_ENABLED +#define CLOCK_ENABLED 1 +#endif +// CLOCK_CONFIG_XTAL_FREQ - HF XTAL Frequency + +// <0=> Default (64 MHz) + +#ifndef CLOCK_CONFIG_XTAL_FREQ +#define CLOCK_CONFIG_XTAL_FREQ 0 +#endif + +// CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth + +#ifndef CLOCK_CONFIG_LF_SRC +#define CLOCK_CONFIG_LF_SRC 1 +#endif + +// CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef CLOCK_CONFIG_IRQ_PRIORITY +#define CLOCK_CONFIG_IRQ_PRIORITY 7 +#endif + +// + +// PERIPHERAL_RESOURCE_SHARING_ENABLED - nrf_drv_common - Peripheral drivers common module + + +#ifndef PERIPHERAL_RESOURCE_SHARING_ENABLED +#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0 +#endif + +// RNG_ENABLED - nrf_drv_rng - RNG peripheral driver +//========================================================== +#ifndef RNG_ENABLED +#define RNG_ENABLED 0 +#endif +// RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef RNG_CONFIG_ERROR_CORRECTION +#define RNG_CONFIG_ERROR_CORRECTION 0 +#endif + +// RNG_CONFIG_POOL_SIZE - Pool size +#ifndef RNG_CONFIG_POOL_SIZE +#define RNG_CONFIG_POOL_SIZE 64 +#endif + +// RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef RNG_CONFIG_IRQ_PRIORITY +#define RNG_CONFIG_IRQ_PRIORITY 7 +#endif + +// + +// +//========================================================== + +// nRF_Libraries + +//========================================================== +// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler +//========================================================== +#ifndef APP_SCHEDULER_ENABLED +#define APP_SCHEDULER_ENABLED 1 +#endif +// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature + + +#ifndef APP_SCHEDULER_WITH_PAUSE +#define APP_SCHEDULER_WITH_PAUSE 0 +#endif + +// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling + + +#ifndef APP_SCHEDULER_WITH_PROFILER +#define APP_SCHEDULER_WITH_PROFILER 0 +#endif + +// + +// APP_TIMER_ENABLED - app_timer - Application timer functionality +//========================================================== +#ifndef APP_TIMER_ENABLED +#define APP_TIMER_ENABLED 1 +#endif +// APP_TIMER_CONFIG_RTC_FREQUENCY - Configure RTC prescaler. + +// <0=> 32768 Hz +// <1=> 16384 Hz +// <3=> 8192 Hz +// <7=> 4096 Hz +// <15=> 2048 Hz +// <31=> 1024 Hz + +#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY +#define APP_TIMER_CONFIG_RTC_FREQUENCY 0 +#endif + +// APP_TIMER_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY +#define APP_TIMER_CONFIG_IRQ_PRIORITY 7 +#endif + +// APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. +// Size of the queue depends on how many timers are used +// in the system, how often timers are started and overall +// system latency. If queue size is too small app_timer calls +// will fail. + +#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE +#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10 +#endif + +// APP_TIMER_CONFIG_USE_SCHEDULER - Enable scheduling app_timer events to app_scheduler + + +#ifndef APP_TIMER_CONFIG_USE_SCHEDULER +#define APP_TIMER_CONFIG_USE_SCHEDULER 1 +#endif + +// APP_TIMER_WITH_PROFILER - Enable app_timer profiling + + +#ifndef APP_TIMER_WITH_PROFILER +#define APP_TIMER_WITH_PROFILER 0 +#endif + +// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on + + +// If option is enabled RTC is kept running even if there is no active timers. +// This option can be used when app_timer is used for timestamping. + +#ifndef APP_TIMER_KEEPS_RTC_ACTIVE +#define APP_TIMER_KEEPS_RTC_ACTIVE 0 +#endif + +// APP_TIMER_CONFIG_SWI_NUMBER - Configure SWI instance used. + +// <0=> 0 +// <1=> 1 + +#ifndef APP_TIMER_CONFIG_SWI_NUMBER +#define APP_TIMER_CONFIG_SWI_NUMBER 0 +#endif + +// + +// CRC32_ENABLED - crc32 - CRC32 calculation routines + + +#ifndef CRC32_ENABLED +#define CRC32_ENABLED 1 +#endif + +// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI +//========================================================== +#ifndef HCI_MEM_POOL_ENABLED +#define HCI_MEM_POOL_ENABLED 1 +#endif +// HCI_TX_BUF_SIZE - TX buffer size in bytes. +#ifndef HCI_TX_BUF_SIZE +#define HCI_TX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_SIZE - RX buffer size in bytes. +#ifndef HCI_RX_BUF_SIZE +#define HCI_RX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. +#ifndef HCI_RX_BUF_QUEUE_SIZE +#define HCI_RX_BUF_QUEUE_SIZE 4 +#endif + +// + +// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator +//========================================================== +#ifndef MEM_MANAGER_ENABLED +#define MEM_MANAGER_ENABLED 1 +#endif +// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> + + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT +#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 +#endif + +// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. +// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE +#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> + + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT +#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. +// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE +#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> + + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT +#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. +// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE +#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra large' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra large' block. +// Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra small' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra small' block. +// Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32 +#endif + +// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. + + +#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK +#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 +#endif + +// + +// NRF_BALLOC_ENABLED - nrf_balloc - Block allocator module +//========================================================== +#ifndef NRF_BALLOC_ENABLED +#define NRF_BALLOC_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_DEBUG_ENABLED - Enables debug mode in the module. +//========================================================== +#ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED +#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS +#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS +#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED - Enables basic checks in this module. + + +#ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED +#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED - Enables double memory free check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED - Enables free memory corruption check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0 +#endif + +// + +// + +// NRF_FSTORAGE_ENABLED - nrf_fstorage - Flash abstraction library +//========================================================== +#ifndef NRF_FSTORAGE_ENABLED +#define NRF_FSTORAGE_ENABLED 1 +#endif +// nrf_fstorage_sd - Implementation using the SoftDevice. + +// Configuration options for the fstorage implementation using the SoftDevice. +//========================================================== +// NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations. +// Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM. + +#ifndef NRF_FSTORAGE_SD_QUEUE_SIZE +#define NRF_FSTORAGE_SD_QUEUE_SIZE 8 +#endif + +// NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy. +// Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error. +// The SoftDevice might fail to schedule flash access due to high BLE activity. + +#ifndef NRF_FSTORAGE_SD_MAX_RETRIES +#define NRF_FSTORAGE_SD_MAX_RETRIES 8 +#endif + +// NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation. +// This value must be a multiple of four. +// Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity. +// This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write. +// That is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs. + +#ifndef NRF_FSTORAGE_SD_MAX_WRITE_SIZE +#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 20 +#endif + +// +//========================================================== + +// + +// NRF_MEMOBJ_ENABLED - nrf_memobj - Linked memory allocator module + + +#ifndef NRF_MEMOBJ_ENABLED +#define NRF_MEMOBJ_ENABLED 0 +#endif + +// NRF_QUEUE_ENABLED - nrf_queue - Queue module + + +#ifndef NRF_QUEUE_ENABLED +#define NRF_QUEUE_ENABLED 0 +#endif + +// NRF_SECTION_ITER_ENABLED - nrf_section_iter - Section iterator + + +#ifndef NRF_SECTION_ITER_ENABLED +#define NRF_SECTION_ITER_ENABLED 1 +#endif + +// NRF_STRERROR_ENABLED - nrf_strerror - Library for converting error code to string. + + +#ifndef NRF_STRERROR_ENABLED +#define NRF_STRERROR_ENABLED 1 +#endif + +// +//========================================================== + +// nRF_Log + +//========================================================== +// nrf_log - Logging + +//========================================================== +// NRF_LOG_ENABLED - Logging module for nRF5 SDK +//========================================================== +#ifndef NRF_LOG_ENABLED +#define NRF_LOG_ENABLED 0 +#endif +// NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string +//========================================================== +#ifndef NRF_LOG_USES_COLORS +#define NRF_LOG_USES_COLORS 0 +#endif +// NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_COLOR_DEFAULT +#define NRF_LOG_COLOR_DEFAULT 0 +#endif + +// NRF_LOG_ERROR_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_ERROR_COLOR +#define NRF_LOG_ERROR_COLOR 0 +#endif + +// NRF_LOG_WARNING_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_WARNING_COLOR +#define NRF_LOG_WARNING_COLOR 0 +#endif + +// + +// NRF_LOG_DEFAULT_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_LOG_DEFAULT_LEVEL +#define NRF_LOG_DEFAULT_LEVEL 3 +#endif + +// NRF_LOG_DEFERRED - Enable deffered logger. + + +// Log data is buffered and can be processed in idle. + +#ifndef NRF_LOG_DEFERRED +#define NRF_LOG_DEFERRED 1 +#endif + +// NRF_LOG_BUFSIZE - Size of the buffer for storing logs (in bytes). + + +// Must be power of 2 and multiple of 4. +// If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum. +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 +// <2048=> 2048 +// <4096=> 4096 +// <8192=> 8192 +// <16384=> 16384 + +#ifndef NRF_LOG_BUFSIZE +#define NRF_LOG_BUFSIZE 1024 +#endif + +// NRF_LOG_ALLOW_OVERFLOW - Configures behavior when circular buffer is full. + + +// If set then oldest logs are overwritten. Otherwise a +// marker is injected informing about overflow. + +#ifndef NRF_LOG_ALLOW_OVERFLOW +#define NRF_LOG_ALLOW_OVERFLOW 1 +#endif + +// NRF_LOG_USES_TIMESTAMP - Enable timestamping + + +// Function for getting the timestamp is provided by the user + +#ifndef NRF_LOG_USES_TIMESTAMP +#define NRF_LOG_USES_TIMESTAMP 0 +#endif + +// NRF_LOG_FILTERS_ENABLED - Enable dynamic filtering of logs. + + +#ifndef NRF_LOG_FILTERS_ENABLED +#define NRF_LOG_FILTERS_ENABLED 0 +#endif + +// NRF_LOG_CLI_CMDS - Enable CLI commands for the module. + + +#ifndef NRF_LOG_CLI_CMDS +#define NRF_LOG_CLI_CMDS 0 +#endif + +// Log message pool - Configuration of log message pool + +//========================================================== +// NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects. +// If a small value is set, then performance of logs processing +// is degraded because data is fragmented. Bigger value impacts +// RAM memory utilization. The size is set to fit a message with +// a timestamp and up to 2 arguments in a single memory object. + +#ifndef NRF_LOG_MSGPOOL_ELEMENT_SIZE +#define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20 +#endif + +// NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects +// If a small value is set, then it may lead to a deadlock +// in certain cases if backend has high latency and holds +// multiple messages for long time. Bigger value impacts +// RAM memory usage. + +#ifndef NRF_LOG_MSGPOOL_ELEMENT_COUNT +#define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8 +#endif + +// +//========================================================== + +// + +// nrf_log module configuration + +//========================================================== +// nrf_log in nRF_Core + +//========================================================== +// NRF_MPU_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_MPU_CONFIG_LOG_ENABLED +#define NRF_MPU_CONFIG_LOG_ENABLED 0 +#endif +// NRF_MPU_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_MPU_CONFIG_LOG_LEVEL +#define NRF_MPU_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_MPU_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MPU_CONFIG_INFO_COLOR +#define NRF_MPU_CONFIG_INFO_COLOR 0 +#endif + +// NRF_MPU_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MPU_CONFIG_DEBUG_COLOR +#define NRF_MPU_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_STACK_GUARD_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_STACK_GUARD_CONFIG_LOG_ENABLED +#define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0 +#endif +// NRF_STACK_GUARD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL +#define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_STACK_GUARD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR +#define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0 +#endif + +// NRF_STACK_GUARD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR +#define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TASK_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TASK_MANAGER_CONFIG_LOG_ENABLED +#define TASK_MANAGER_CONFIG_LOG_ENABLED 0 +#endif +// TASK_MANAGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TASK_MANAGER_CONFIG_LOG_LEVEL +#define TASK_MANAGER_CONFIG_LOG_LEVEL 3 +#endif + +// TASK_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TASK_MANAGER_CONFIG_INFO_COLOR +#define TASK_MANAGER_CONFIG_INFO_COLOR 0 +#endif + +// TASK_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR +#define TASK_MANAGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Drivers + +//========================================================== +// CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef CLOCK_CONFIG_LOG_ENABLED +#define CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef CLOCK_CONFIG_LOG_LEVEL +#define CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_INFO_COLOR +#define CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_DEBUG_COLOR +#define CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// COMMON_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef COMMON_CONFIG_LOG_ENABLED +#define COMMON_CONFIG_LOG_ENABLED 0 +#endif +// COMMON_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef COMMON_CONFIG_LOG_LEVEL +#define COMMON_CONFIG_LOG_LEVEL 3 +#endif + +// COMMON_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMMON_CONFIG_INFO_COLOR +#define COMMON_CONFIG_INFO_COLOR 0 +#endif + +// COMMON_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMMON_CONFIG_DEBUG_COLOR +#define COMMON_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef COMP_CONFIG_LOG_ENABLED +#define COMP_CONFIG_LOG_ENABLED 0 +#endif +// COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef COMP_CONFIG_LOG_LEVEL +#define COMP_CONFIG_LOG_LEVEL 3 +#endif + +// COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_INFO_COLOR +#define COMP_CONFIG_INFO_COLOR 0 +#endif + +// COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_DEBUG_COLOR +#define COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef GPIOTE_CONFIG_LOG_ENABLED +#define GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef GPIOTE_CONFIG_LOG_LEVEL +#define GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_INFO_COLOR +#define GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_DEBUG_COLOR +#define GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef I2S_CONFIG_LOG_ENABLED +#define I2S_CONFIG_LOG_ENABLED 0 +#endif +// I2S_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef I2S_CONFIG_LOG_LEVEL +#define I2S_CONFIG_LOG_LEVEL 3 +#endif + +// I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_INFO_COLOR +#define I2S_CONFIG_INFO_COLOR 0 +#endif + +// I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_DEBUG_COLOR +#define I2S_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef LPCOMP_CONFIG_LOG_ENABLED +#define LPCOMP_CONFIG_LOG_ENABLED 0 +#endif +// LPCOMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef LPCOMP_CONFIG_LOG_LEVEL +#define LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +// LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_INFO_COLOR +#define LPCOMP_CONFIG_INFO_COLOR 0 +#endif + +// LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_DEBUG_COLOR +#define LPCOMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PDM_CONFIG_LOG_ENABLED +#define PDM_CONFIG_LOG_ENABLED 0 +#endif +// PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PDM_CONFIG_LOG_LEVEL +#define PDM_CONFIG_LOG_LEVEL 3 +#endif + +// PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_INFO_COLOR +#define PDM_CONFIG_INFO_COLOR 0 +#endif + +// PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_DEBUG_COLOR +#define PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PPI_CONFIG_LOG_ENABLED +#define PPI_CONFIG_LOG_ENABLED 0 +#endif +// PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PPI_CONFIG_LOG_LEVEL +#define PPI_CONFIG_LOG_LEVEL 3 +#endif + +// PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_INFO_COLOR +#define PPI_CONFIG_INFO_COLOR 0 +#endif + +// PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_DEBUG_COLOR +#define PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PWM_CONFIG_LOG_ENABLED +#define PWM_CONFIG_LOG_ENABLED 0 +#endif +// PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PWM_CONFIG_LOG_LEVEL +#define PWM_CONFIG_LOG_LEVEL 3 +#endif + +// PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_INFO_COLOR +#define PWM_CONFIG_INFO_COLOR 0 +#endif + +// PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_DEBUG_COLOR +#define PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef QDEC_CONFIG_LOG_ENABLED +#define QDEC_CONFIG_LOG_ENABLED 0 +#endif +// QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef QDEC_CONFIG_LOG_LEVEL +#define QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_INFO_COLOR +#define QDEC_CONFIG_INFO_COLOR 0 +#endif + +// QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_DEBUG_COLOR +#define QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RNG_CONFIG_LOG_ENABLED +#define RNG_CONFIG_LOG_ENABLED 0 +#endif +// RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RNG_CONFIG_LOG_LEVEL +#define RNG_CONFIG_LOG_LEVEL 3 +#endif + +// RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_INFO_COLOR +#define RNG_CONFIG_INFO_COLOR 0 +#endif + +// RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_DEBUG_COLOR +#define RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED - Enables logging of random numbers. + + +#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED +#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0 +#endif + +// + +// RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RTC_CONFIG_LOG_ENABLED +#define RTC_CONFIG_LOG_ENABLED 0 +#endif +// RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RTC_CONFIG_LOG_LEVEL +#define RTC_CONFIG_LOG_LEVEL 3 +#endif + +// RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_INFO_COLOR +#define RTC_CONFIG_INFO_COLOR 0 +#endif + +// RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_DEBUG_COLOR +#define RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SAADC_CONFIG_LOG_ENABLED +#define SAADC_CONFIG_LOG_ENABLED 0 +#endif +// SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SAADC_CONFIG_LOG_LEVEL +#define SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_INFO_COLOR +#define SAADC_CONFIG_INFO_COLOR 0 +#endif + +// SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_DEBUG_COLOR +#define SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPIS_CONFIG_LOG_ENABLED +#define SPIS_CONFIG_LOG_ENABLED 0 +#endif +// SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPIS_CONFIG_LOG_LEVEL +#define SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_INFO_COLOR +#define SPIS_CONFIG_INFO_COLOR 0 +#endif + +// SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_DEBUG_COLOR +#define SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPI_CONFIG_LOG_ENABLED +#define SPI_CONFIG_LOG_ENABLED 0 +#endif +// SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPI_CONFIG_LOG_LEVEL +#define SPI_CONFIG_LOG_LEVEL 3 +#endif + +// SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_INFO_COLOR +#define SPI_CONFIG_INFO_COLOR 0 +#endif + +// SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_DEBUG_COLOR +#define SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SWI_CONFIG_LOG_ENABLED +#define SWI_CONFIG_LOG_ENABLED 0 +#endif +// SWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SWI_CONFIG_LOG_LEVEL +#define SWI_CONFIG_LOG_LEVEL 3 +#endif + +// SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SWI_CONFIG_INFO_COLOR +#define SWI_CONFIG_INFO_COLOR 0 +#endif + +// SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SWI_CONFIG_DEBUG_COLOR +#define SWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TIMER_CONFIG_LOG_ENABLED +#define TIMER_CONFIG_LOG_ENABLED 0 +#endif +// TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TIMER_CONFIG_LOG_LEVEL +#define TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_INFO_COLOR +#define TIMER_CONFIG_INFO_COLOR 0 +#endif + +// TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_DEBUG_COLOR +#define TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWIS_CONFIG_LOG_ENABLED +#define TWIS_CONFIG_LOG_ENABLED 0 +#endif +// TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWIS_CONFIG_LOG_LEVEL +#define TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_INFO_COLOR +#define TWIS_CONFIG_INFO_COLOR 0 +#endif + +// TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_DEBUG_COLOR +#define TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWI_CONFIG_LOG_ENABLED +#define TWI_CONFIG_LOG_ENABLED 0 +#endif +// TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWI_CONFIG_LOG_LEVEL +#define TWI_CONFIG_LOG_LEVEL 3 +#endif + +// TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_INFO_COLOR +#define TWI_CONFIG_INFO_COLOR 0 +#endif + +// TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_DEBUG_COLOR +#define TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef UART_CONFIG_LOG_ENABLED +#define UART_CONFIG_LOG_ENABLED 0 +#endif +// UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef UART_CONFIG_LOG_LEVEL +#define UART_CONFIG_LOG_LEVEL 3 +#endif + +// UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_INFO_COLOR +#define UART_CONFIG_INFO_COLOR 0 +#endif + +// UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_DEBUG_COLOR +#define UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// USBD_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef USBD_CONFIG_LOG_ENABLED +#define USBD_CONFIG_LOG_ENABLED 0 +#endif +// USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef USBD_CONFIG_LOG_LEVEL +#define USBD_CONFIG_LOG_LEVEL 3 +#endif + +// USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef USBD_CONFIG_INFO_COLOR +#define USBD_CONFIG_INFO_COLOR 0 +#endif + +// USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef USBD_CONFIG_DEBUG_COLOR +#define USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef WDT_CONFIG_LOG_ENABLED +#define WDT_CONFIG_LOG_ENABLED 0 +#endif +// WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef WDT_CONFIG_LOG_LEVEL +#define WDT_CONFIG_LOG_LEVEL 3 +#endif + +// WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_INFO_COLOR +#define WDT_CONFIG_INFO_COLOR 0 +#endif + +// WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_DEBUG_COLOR +#define WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Libraries + +//========================================================== +// APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED +#define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL +#define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_CDC_ACM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR +#define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR +#define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_MSC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_MSC_CONFIG_LOG_ENABLED +#define APP_USBD_MSC_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_MSC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL +#define APP_USBD_MSC_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_MSC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_MSC_CONFIG_INFO_COLOR +#define APP_USBD_MSC_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_MSC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR +#define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// MEM_MANAGER_ENABLE_LOGS - Enable debug trace in the module. + + +#ifndef MEM_MANAGER_ENABLE_LOGS +#define MEM_MANAGER_ENABLE_LOGS 0 +#endif + +// NRF_BALLOC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BALLOC_CONFIG_LOG_ENABLED +#define NRF_BALLOC_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BALLOC_CONFIG_LOG_LEVEL +#define NRF_BALLOC_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BALLOC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BALLOC_CONFIG_INFO_COLOR +#define NRF_BALLOC_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BALLOC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR +#define NRF_BALLOC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED +#define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL +#define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_BLE_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR +#define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR +#define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_UART_CONFIG_LOG_ENABLED +#define NRF_CLI_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL +#define NRF_CLI_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_UART_CONFIG_INFO_COLOR +#define NRF_CLI_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR +#define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_MEMOBJ_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_MEMOBJ_CONFIG_LOG_ENABLED +#define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0 +#endif +// NRF_MEMOBJ_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL +#define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_MEMOBJ_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR +#define NRF_MEMOBJ_CONFIG_INFO_COLOR 0 +#endif + +// NRF_MEMOBJ_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR +#define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_LOG_ENABLED +#define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL +#define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_PWR_MGMT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR +#define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0 +#endif + +// NRF_PWR_MGMT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR +#define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_ANT_LOG_ENABLED - Enable logging in SoftDevice handler (ANT) module. +//========================================================== +#ifndef NRF_SDH_ANT_LOG_ENABLED +#define NRF_SDH_ANT_LOG_ENABLED 0 +#endif +// NRF_SDH_ANT_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_ANT_LOG_LEVEL +#define NRF_SDH_ANT_LOG_LEVEL 3 +#endif + +// NRF_SDH_ANT_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_ANT_INFO_COLOR +#define NRF_SDH_ANT_INFO_COLOR 0 +#endif + +// NRF_SDH_ANT_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_ANT_DEBUG_COLOR +#define NRF_SDH_ANT_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_BLE_LOG_ENABLED - Enable logging in SoftDevice handler (BLE) module. +//========================================================== +#ifndef NRF_SDH_BLE_LOG_ENABLED +#define NRF_SDH_BLE_LOG_ENABLED 1 +#endif +// NRF_SDH_BLE_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_BLE_LOG_LEVEL +#define NRF_SDH_BLE_LOG_LEVEL 3 +#endif + +// NRF_SDH_BLE_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_BLE_INFO_COLOR +#define NRF_SDH_BLE_INFO_COLOR 0 +#endif + +// NRF_SDH_BLE_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_BLE_DEBUG_COLOR +#define NRF_SDH_BLE_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_LOG_ENABLED - Enable logging in SoftDevice handler module. +//========================================================== +#ifndef NRF_SDH_LOG_ENABLED +#define NRF_SDH_LOG_ENABLED 1 +#endif +// NRF_SDH_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_LOG_LEVEL +#define NRF_SDH_LOG_LEVEL 3 +#endif + +// NRF_SDH_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_INFO_COLOR +#define NRF_SDH_INFO_COLOR 0 +#endif + +// NRF_SDH_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_DEBUG_COLOR +#define NRF_SDH_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_SOC_LOG_ENABLED - Enable logging in SoftDevice handler (SoC) module. +//========================================================== +#ifndef NRF_SDH_SOC_LOG_ENABLED +#define NRF_SDH_SOC_LOG_ENABLED 1 +#endif +// NRF_SDH_SOC_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_SOC_LOG_LEVEL +#define NRF_SDH_SOC_LOG_LEVEL 3 +#endif + +// NRF_SDH_SOC_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_SOC_INFO_COLOR +#define NRF_SDH_SOC_INFO_COLOR 0 +#endif + +// NRF_SDH_SOC_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_SOC_DEBUG_COLOR +#define NRF_SDH_SOC_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// +//========================================================== + +// +//========================================================== + +// +//========================================================== + +// nRF_SoftDevice + +//========================================================== +// NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler +//========================================================== +#ifndef NRF_SDH_BLE_ENABLED +#define NRF_SDH_BLE_ENABLED 1 +#endif +// BLE Stack configuration - Stack configuration parameters + +// These values are not used directly by the SoftDevice handler but the application or other libraries might depend on them. +// Keep them up-to-date with the desired configuration. +//========================================================== +// NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links. +#ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT +#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 1 +#endif + +// NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links. +#ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT +#define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0 +#endif + +// NRF_SDH_BLE_TOTAL_LINK_COUNT - Maximum number of total concurrent connections using the default configuration. +#ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT +#define NRF_SDH_BLE_TOTAL_LINK_COUNT 1 +#endif + +// NRF_SDH_BLE_GAP_EVENT_LENGTH - The time set aside for this connection on every connection interval in 1.25 ms units. +#ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH +#define NRF_SDH_BLE_GAP_EVENT_LENGTH 3 +#endif + +// NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size. +#ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE +#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 23 +#endif + +// NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4. +#ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE +#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408 +#endif + +// NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs. +#ifndef NRF_SDH_BLE_VS_UUID_COUNT +#define NRF_SDH_BLE_VS_UUID_COUNT 0 +#endif + +// NRF_SDH_BLE_SERVICE_CHANGED - Include the Service Changed characteristic in the Attribute Table. + + +#ifndef NRF_SDH_BLE_SERVICE_CHANGED +#define NRF_SDH_BLE_SERVICE_CHANGED 0 +#endif + +// +//========================================================== + +// BLE Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers. +// This setting configures the number of priority levels available for BLE event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_BLE_OBSERVER_PRIO_LEVELS +#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS 3 +#endif + +// BLE Observers priorities - Invididual priorities + +//========================================================== +// BLE_ADV_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Advertising module. + +#ifndef BLE_ADV_BLE_OBSERVER_PRIO +#define BLE_ADV_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_ANCS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Apple Notification Service Client. + +#ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO +#define BLE_ANCS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_ANS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Alert Notification Service Client. + +#ifndef BLE_ANS_C_BLE_OBSERVER_PRIO +#define BLE_ANS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BAS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Battery Service. + +#ifndef BLE_BAS_BLE_OBSERVER_PRIO +#define BLE_BAS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BAS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Battery Service Client. + +#ifndef BLE_BAS_C_BLE_OBSERVER_PRIO +#define BLE_BAS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BPS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Blood Pressure Service. + +#ifndef BLE_BPS_BLE_OBSERVER_PRIO +#define BLE_BPS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_CONN_PARAMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Connection parameters module. + +#ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO +#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_CONN_STATE_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Connection State module. + +#ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO +#define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0 +#endif + +// BLE_CSCS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service. + +#ifndef BLE_CSCS_BLE_OBSERVER_PRIO +#define BLE_CSCS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_CTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Current Time Service Client. + +#ifndef BLE_CTS_C_BLE_OBSERVER_PRIO +#define BLE_CTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_DB_DISC_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Database Discovery module. + +#ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO +#define BLE_DB_DISC_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_DFU_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the DFU Service. + +#ifndef BLE_DFU_BLE_OBSERVER_PRIO +#define BLE_DFU_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_GLS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Glucose Service. + +#ifndef BLE_GLS_BLE_OBSERVER_PRIO +#define BLE_GLS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HIDS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Human Interface Device Service. + +#ifndef BLE_HIDS_BLE_OBSERVER_PRIO +#define BLE_HIDS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HRS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Heart Rate Service. + +#ifndef BLE_HRS_BLE_OBSERVER_PRIO +#define BLE_HRS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HRS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Heart Rate Service Client. + +#ifndef BLE_HRS_C_BLE_OBSERVER_PRIO +#define BLE_HRS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HTS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Health Thermometer Service. + +#ifndef BLE_HTS_BLE_OBSERVER_PRIO +#define BLE_HTS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_IAS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Immediate Alert Service. + +#ifndef BLE_IAS_BLE_OBSERVER_PRIO +#define BLE_IAS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_IAS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Immediate Alert Service Client. + +#ifndef BLE_IAS_C_BLE_OBSERVER_PRIO +#define BLE_IAS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LBS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the LED Button Service. + +#ifndef BLE_LBS_BLE_OBSERVER_PRIO +#define BLE_LBS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LBS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the LED Button Service Client. + +#ifndef BLE_LBS_C_BLE_OBSERVER_PRIO +#define BLE_LBS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LLS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Link Loss Service. + +#ifndef BLE_LLS_BLE_OBSERVER_PRIO +#define BLE_LLS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LNS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Location Navigation Service. + +#ifndef BLE_LNS_BLE_OBSERVER_PRIO +#define BLE_LNS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_NUS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the UART Service. + +#ifndef BLE_NUS_BLE_OBSERVER_PRIO +#define BLE_NUS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_NUS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the UART Central Service. + +#ifndef BLE_NUS_C_BLE_OBSERVER_PRIO +#define BLE_NUS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_OTS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Object transfer service. + +#ifndef BLE_OTS_BLE_OBSERVER_PRIO +#define BLE_OTS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_OTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Object transfer service client. + +#ifndef BLE_OTS_C_BLE_OBSERVER_PRIO +#define BLE_OTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_RSCS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Running Speed and Cadence Service. + +#ifndef BLE_RSCS_BLE_OBSERVER_PRIO +#define BLE_RSCS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_RSCS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Running Speed and Cadence Client. + +#ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO +#define BLE_RSCS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_TPS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the TX Power Service. + +#ifndef BLE_TPS_BLE_OBSERVER_PRIO +#define BLE_TPS_BLE_OBSERVER_PRIO 2 +#endif + +// BSP_BTN_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Button Control module. + +#ifndef BSP_BTN_BLE_OBSERVER_PRIO +#define BSP_BTN_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NRF_BLE_BMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Bond Management Service. + +#ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO +#define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_CGMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service. + +#ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO +#define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT Service Client. + +#ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO +#define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_GATT_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT module. + +#ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO +#define NRF_BLE_GATT_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_QWR_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Queued writes module. + +#ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO +#define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2 +#endif + +// PM_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Peer Manager module. + +#ifndef PM_BLE_OBSERVER_PRIO +#define PM_BLE_OBSERVER_PRIO 2 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// NRF_SDH_ENABLED - nrf_sdh - SoftDevice handler +//========================================================== +#ifndef NRF_SDH_ENABLED +#define NRF_SDH_ENABLED 1 +#endif +// Dispatch model + +// This setting configures how Stack events are dispatched to the application. +//========================================================== +// NRF_SDH_DISPATCH_MODEL + + +// NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context. +// NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler. +// NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually. +// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT +// <1=> NRF_SDH_DISPATCH_MODEL_APPSH +// <2=> NRF_SDH_DISPATCH_MODEL_POLLING + +#ifndef NRF_SDH_DISPATCH_MODEL +#define NRF_SDH_DISPATCH_MODEL 1 +#endif + +// +//========================================================== + +// Clock - SoftDevice clock configuration + +//========================================================== +// NRF_SDH_CLOCK_LF_SRC - SoftDevice clock source. + +// <0=> NRF_CLOCK_LF_SRC_RC +// <1=> NRF_CLOCK_LF_SRC_XTAL +// <2=> NRF_CLOCK_LF_SRC_SYNTH + +#ifndef NRF_SDH_CLOCK_LF_SRC +#define NRF_SDH_CLOCK_LF_SRC 0 +#endif + +// NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. +#ifndef NRF_SDH_CLOCK_LF_RC_CTIV +#define NRF_SDH_CLOCK_LF_RC_CTIV 16 +#endif + +// NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. +// How often (in number of calibration intervals) the RC oscillator shall be calibrated +// if the temperature has not changed. + +#ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV +#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 2 +#endif + +// NRF_SDH_CLOCK_LF_XTAL_ACCURACY - External crystal clock accuracy used in the LL to compute timing windows. + +// <0=> NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM +// <1=> NRF_CLOCK_LF_XTAL_ACCURACY_500_PPM +// <2=> NRF_CLOCK_LF_XTAL_ACCURACY_150_PPM +// <3=> NRF_CLOCK_LF_XTAL_ACCURACY_100_PPM +// <4=> NRF_CLOCK_LF_XTAL_ACCURACY_75_PPM +// <5=> NRF_CLOCK_LF_XTAL_ACCURACY_50_PPM +// <6=> NRF_CLOCK_LF_XTAL_ACCURACY_30_PPM +// <7=> NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM + +#ifndef NRF_SDH_CLOCK_LF_XTAL_ACCURACY +#define NRF_SDH_CLOCK_LF_XTAL_ACCURACY 7 +#endif + +// +//========================================================== + +// SDH Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers. +// This setting configures the number of priority levels available for the SoftDevice request event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_REQ_OBSERVER_PRIO_LEVELS +#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2 +#endif + +// NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers. +// This setting configures the number of priority levels available for the SoftDevice state event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_STATE_OBSERVER_PRIO_LEVELS +#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2 +#endif + +// NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers. +// This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC). +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_STACK_OBSERVER_PRIO_LEVELS +#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS 2 +#endif + + +// State Observers priorities - Invididual priorities + +//========================================================== +// CLOCK_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to the Clock driver. + +#ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO +#define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// POWER_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to the Power driver. + +#ifndef POWER_CONFIG_STATE_OBSERVER_PRIO +#define POWER_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// RNG_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to this module. + +#ifndef RNG_CONFIG_STATE_OBSERVER_PRIO +#define RNG_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// Stack Event Observers priorities - Invididual priorities + +//========================================================== +// NRF_SDH_ANT_STACK_OBSERVER_PRIO +// This setting configures the priority with which ANT events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC. +// Zero is the highest priority. + +#ifndef NRF_SDH_ANT_STACK_OBSERVER_PRIO +#define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0 +#endif + +// NRF_SDH_BLE_STACK_OBSERVER_PRIO +// This setting configures the priority with which BLE events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC. +// Zero is the highest priority. + +#ifndef NRF_SDH_BLE_STACK_OBSERVER_PRIO +#define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0 +#endif + +// NRF_SDH_SOC_STACK_OBSERVER_PRIO +// This setting configures the priority with which SoC events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE. +// Zero is the highest priority. + +#ifndef NRF_SDH_SOC_STACK_OBSERVER_PRIO +#define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// NRF_SDH_SOC_ENABLED - nrf_sdh_soc - SoftDevice SoC event handler +//========================================================== +#ifndef NRF_SDH_SOC_ENABLED +#define NRF_SDH_SOC_ENABLED 1 +#endif +// SoC Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers. +// This setting configures the number of priority levels available for the SoC event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_SOC_OBSERVER_PRIO_LEVELS +#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2 +#endif + +// SoC Observers priorities - Invididual priorities + +//========================================================== +// BLE_ADV_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Advertising module. + +#ifndef BLE_ADV_SOC_OBSERVER_PRIO +#define BLE_ADV_SOC_OBSERVER_PRIO 1 +#endif + +// BLE_DFU_SOC_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the DFU Service. + +#ifndef BLE_DFU_SOC_OBSERVER_PRIO +#define BLE_DFU_SOC_OBSERVER_PRIO 1 +#endif + +// CLOCK_CONFIG_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Clock driver. + +#ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO +#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0 +#endif + +// POWER_CONFIG_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Power driver. + +#ifndef POWER_CONFIG_SOC_OBSERVER_PRIO +#define POWER_CONFIG_SOC_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// +//========================================================== + +// <<< end of configuration section >>> +#endif //SDK_CONFIG_H + diff --git a/src/singlebank/Makefile b/src/singlebank/Makefile new file mode 100644 index 0000000..a313a1c --- /dev/null +++ b/src/singlebank/Makefile @@ -0,0 +1,7 @@ +#****************************************************************************** +# CONFIGURE +# - BOOT VERSION : 050: S132 v201, 055: S132 v500 +#****************************************************************************** +VERSION_SINGLEBANK = 1 + +include ../make_common.mk