xobs/s32k118.rs
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This commit is contained in:
Kjetil Kjeka
2017-09-23 20:31:10 +02:00
parent 7facea48b2
commit 2fc3ce22de
1658 changed files with 25191 additions and 42351 deletions
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37
src/scg/clkoutcnfg/mod.rs
View File

@ -22,7 +22,9 @@ impl super::CLKOUTCNFG {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,18 +45,12 @@ impl super::CLKOUTCNFG {
#[doc = "Possible values of the field `CLKOUTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKOUTSELR {
#[doc = "SCG SLOW Clock"]
_0000,
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "SCG SLOW Clock"] _0000,
#[doc = "System OSC (SOSC_CLK)"] _0001,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = "Fast IRC (FIRC_CLK)"] _0011,
#[doc = "System PLL (SPLL_CLK)"] _0110,
#[doc = r" Reserved"] _Reserved(u8),
}
impl CLKOUTSELR {
#[doc = r" Value of the field as raw bits"]
@ -110,16 +106,11 @@ impl CLKOUTSELR {
}
#[doc = "Values that can be written to the field `CLKOUTSEL`"]
pub enum CLKOUTSELW {
#[doc = "SCG SLOW Clock"]
_0000,
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = "SCG SLOW Clock"] _0000,
#[doc = "System OSC (SOSC_CLK)"] _0001,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = "Fast IRC (FIRC_CLK)"] _0011,
#[doc = "System PLL (SPLL_CLK)"] _0110,
}
impl CLKOUTSELW {
#[allow(missing_docs)]

142
src/scg/csr/mod.rs
View File

@ -6,30 +6,23 @@ impl super::CSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `DIVSLOW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVSLOWR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DIVSLOWR {
#[doc = r" Value of the field as raw bits"]
@ -107,38 +100,22 @@ impl DIVSLOWR {
#[doc = "Possible values of the field `DIVBUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVBUSR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVBUSR {
#[doc = r" Value of the field as raw bits"]
@ -271,38 +248,22 @@ impl DIVBUSR {
#[doc = "Possible values of the field `DIVCORE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVCORER {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVCORER {
#[doc = r" Value of the field as raw bits"]
@ -435,16 +396,11 @@ impl DIVCORER {
#[doc = "Possible values of the field `SCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCSR {
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "System OSC (SOSC_CLK)"] _0001,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = "Fast IRC (FIRC_CLK)"] _0011,
#[doc = "System PLL (SPLL_CLK)"] _0110,
#[doc = r" Reserved"] _Reserved(u8),
}
impl SCSR {
#[doc = r" Value of the field as raw bits"]

28
src/scg/firccfg/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FIRCCFG {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,14 +45,10 @@ impl super::FIRCCFG {
#[doc = "Possible values of the field `RANGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RANGER {
#[doc = "Fast IRC is trimmed to 48 MHz"]
_00,
#[doc = "Fast IRC is trimmed to 52 MHz"]
_01,
#[doc = "Fast IRC is trimmed to 56 MHz"]
_10,
#[doc = "Fast IRC is trimmed to 60 MHz"]
_11,
#[doc = "Fast IRC is trimmed to 48 MHz"] _00,
#[doc = "Fast IRC is trimmed to 52 MHz"] _01,
#[doc = "Fast IRC is trimmed to 56 MHz"] _10,
#[doc = "Fast IRC is trimmed to 60 MHz"] _11,
}
impl RANGER {
#[doc = r" Value of the field as raw bits"]
@ -98,14 +96,10 @@ impl RANGER {
}
#[doc = "Values that can be written to the field `RANGE`"]
pub enum RANGEW {
#[doc = "Fast IRC is trimmed to 48 MHz"]
_00,
#[doc = "Fast IRC is trimmed to 52 MHz"]
_01,
#[doc = "Fast IRC is trimmed to 56 MHz"]
_10,
#[doc = "Fast IRC is trimmed to 60 MHz"]
_11,
#[doc = "Fast IRC is trimmed to 48 MHz"] _00,
#[doc = "Fast IRC is trimmed to 52 MHz"] _01,
#[doc = "Fast IRC is trimmed to 56 MHz"] _10,
#[doc = "Fast IRC is trimmed to 60 MHz"] _11,
}
impl RANGEW {
#[allow(missing_docs)]

61
src/scg/firccsr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FIRCCSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::FIRCCSR {
#[doc = "Possible values of the field `FIRCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCENR {
#[doc = "Fast IRC is disabled"]
_0,
#[doc = "Fast IRC is enabled"]
_1,
#[doc = "Fast IRC is disabled"] _0,
#[doc = "Fast IRC is enabled"] _1,
}
impl FIRCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl FIRCENR {
#[doc = "Possible values of the field `FIRCREGOFF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCREGOFFR {
#[doc = "Fast IRC Regulator is enabled."]
_0,
#[doc = "Fast IRC Regulator is disabled."]
_1,
#[doc = "Fast IRC Regulator is enabled."] _0,
#[doc = "Fast IRC Regulator is disabled."] _1,
}
impl FIRCREGOFFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl FIRCREGOFFR {
#[doc = "Possible values of the field `LK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LKR {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
#[doc = "Control Status Register can be written."] _0,
#[doc = "Control Status Register cannot be written."] _1,
}
impl LKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,8 +180,7 @@ impl LKR {
#[doc = "Possible values of the field `FIRCVLD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCVLDR {
#[doc = "Fast IRC is not enabled or clock is not valid."]
_0,
#[doc = "Fast IRC is not enabled or clock is not valid."] _0,
#[doc = "Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog."]
_1,
}
@ -231,10 +226,8 @@ impl FIRCVLDR {
#[doc = "Possible values of the field `FIRCSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCSELR {
#[doc = "Fast IRC is not the system clock source"]
_0,
#[doc = "Fast IRC is the system clock source"]
_1,
#[doc = "Fast IRC is not the system clock source"] _0,
#[doc = "Fast IRC is the system clock source"] _1,
}
impl FIRCSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +271,8 @@ impl FIRCSELR {
#[doc = "Possible values of the field `FIRCERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCERRR {
#[doc = "Error not detected with the Fast IRC trimming."]
_0,
#[doc = "Error detected with the Fast IRC trimming."]
_1,
#[doc = "Error not detected with the Fast IRC trimming."] _0,
#[doc = "Error detected with the Fast IRC trimming."] _1,
}
impl FIRCERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -324,10 +315,8 @@ impl FIRCERRR {
}
#[doc = "Values that can be written to the field `FIRCEN`"]
pub enum FIRCENW {
#[doc = "Fast IRC is disabled"]
_0,
#[doc = "Fast IRC is enabled"]
_1,
#[doc = "Fast IRC is disabled"] _0,
#[doc = "Fast IRC is enabled"] _1,
}
impl FIRCENW {
#[allow(missing_docs)]
@ -382,10 +371,8 @@ impl<'a> _FIRCENW<'a> {
}
#[doc = "Values that can be written to the field `FIRCREGOFF`"]
pub enum FIRCREGOFFW {
#[doc = "Fast IRC Regulator is enabled."]
_0,
#[doc = "Fast IRC Regulator is disabled."]
_1,
#[doc = "Fast IRC Regulator is enabled."] _0,
#[doc = "Fast IRC Regulator is disabled."] _1,
}
impl FIRCREGOFFW {
#[allow(missing_docs)]
@ -440,10 +427,8 @@ impl<'a> _FIRCREGOFFW<'a> {
}
#[doc = "Values that can be written to the field `LK`"]
pub enum LKW {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
#[doc = "Control Status Register can be written."] _0,
#[doc = "Control Status Register cannot be written."] _1,
}
impl LKW {
#[allow(missing_docs)]
@ -498,10 +483,8 @@ impl<'a> _LKW<'a> {
}
#[doc = "Values that can be written to the field `FIRCERR`"]
pub enum FIRCERRW {
#[doc = "Error not detected with the Fast IRC trimming."]
_0,
#[doc = "Error detected with the Fast IRC trimming."]
_1,
#[doc = "Error not detected with the Fast IRC trimming."] _0,
#[doc = "Error detected with the Fast IRC trimming."] _1,
}
impl FIRCERRW {
#[allow(missing_docs)]

100
src/scg/fircdiv/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FIRCDIV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,22 +45,14 @@ impl super::FIRCDIV {
#[doc = "Possible values of the field `FIRCDIV1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCDIV1R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl FIRCDIV1R {
#[doc = r" Value of the field as raw bits"]
@ -135,22 +129,14 @@ impl FIRCDIV1R {
#[doc = "Possible values of the field `FIRCDIV2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCDIV2R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl FIRCDIV2R {
#[doc = r" Value of the field as raw bits"]
@ -226,22 +212,14 @@ impl FIRCDIV2R {
}
#[doc = "Values that can be written to the field `FIRCDIV1`"]
pub enum FIRCDIV1W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl FIRCDIV1W {
#[allow(missing_docs)]
@ -324,22 +302,14 @@ impl<'a> _FIRCDIV1W<'a> {
}
#[doc = "Values that can be written to the field `FIRCDIV2`"]
pub enum FIRCDIV2W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl FIRCDIV2W {
#[allow(missing_docs)]

274
src/scg/hccr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::HCCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,24 +45,15 @@ impl super::HCCR {
#[doc = "Possible values of the field `DIVSLOW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVSLOWR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DIVSLOWR {
#[doc = r" Value of the field as raw bits"]
@ -138,38 +131,22 @@ impl DIVSLOWR {
#[doc = "Possible values of the field `DIVBUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVBUSR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVBUSR {
#[doc = r" Value of the field as raw bits"]
@ -302,38 +279,22 @@ impl DIVBUSR {
#[doc = "Possible values of the field `DIVCORE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVCORER {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVCORER {
#[doc = r" Value of the field as raw bits"]
@ -466,16 +427,11 @@ impl DIVCORER {
#[doc = "Possible values of the field `SCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCSR {
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "System OSC (SOSC_CLK)"] _0001,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = "Fast IRC (FIRC_CLK)"] _0011,
#[doc = "System PLL (SPLL_CLK)"] _0110,
#[doc = r" Reserved"] _Reserved(u8),
}
impl SCSR {
#[doc = r" Value of the field as raw bits"]
@ -524,22 +480,14 @@ impl SCSR {
}
#[doc = "Values that can be written to the field `DIVSLOW`"]
pub enum DIVSLOWW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
}
impl DIVSLOWW {
#[allow(missing_docs)]
@ -620,38 +568,22 @@ impl<'a> _DIVSLOWW<'a> {
}
#[doc = "Values that can be written to the field `DIVBUS`"]
pub enum DIVBUSW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVBUSW {
#[allow(missing_docs)]
@ -782,38 +714,22 @@ impl<'a> _DIVBUSW<'a> {
}
#[doc = "Values that can be written to the field `DIVCORE`"]
pub enum DIVCOREW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVCOREW {
#[allow(missing_docs)]
@ -944,14 +860,10 @@ impl<'a> _DIVCOREW<'a> {
}
#[doc = "Values that can be written to the field `SCS`"]
pub enum SCSW {
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = "System OSC (SOSC_CLK)"] _0001,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = "Fast IRC (FIRC_CLK)"] _0011,
#[doc = "System PLL (SPLL_CLK)"] _0110,
}
impl SCSW {
#[allow(missing_docs)]

57
src/scg/mod.rs
View File

@ -2,49 +2,30 @@ use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Version ID Register"]
pub verid: VERID,
#[doc = "0x04 - Parameter Register"]
pub param: PARAM,
#[doc = "0x00 - Version ID Register"] pub verid: VERID,
#[doc = "0x04 - Parameter Register"] pub param: PARAM,
_reserved0: [u8; 8usize],
#[doc = "0x10 - Clock Status Register"]
pub csr: CSR,
#[doc = "0x14 - Run Clock Control Register"]
pub rccr: RCCR,
#[doc = "0x18 - VLPR Clock Control Register"]
pub vccr: VCCR,
#[doc = "0x1c - HSRUN Clock Control Register"]
pub hccr: HCCR,
#[doc = "0x20 - SCG CLKOUT Configuration Register"]
pub clkoutcnfg: CLKOUTCNFG,
#[doc = "0x10 - Clock Status Register"] pub csr: CSR,
#[doc = "0x14 - Run Clock Control Register"] pub rccr: RCCR,
#[doc = "0x18 - VLPR Clock Control Register"] pub vccr: VCCR,
#[doc = "0x1c - HSRUN Clock Control Register"] pub hccr: HCCR,
#[doc = "0x20 - SCG CLKOUT Configuration Register"] pub clkoutcnfg: CLKOUTCNFG,
_reserved1: [u8; 220usize],
#[doc = "0x100 - System OSC Control Status Register"]
pub sosccsr: SOSCCSR,
#[doc = "0x104 - System OSC Divide Register"]
pub soscdiv: SOSCDIV,
#[doc = "0x108 - System Oscillator Configuration Register"]
pub sosccfg: SOSCCFG,
#[doc = "0x100 - System OSC Control Status Register"] pub sosccsr: SOSCCSR,
#[doc = "0x104 - System OSC Divide Register"] pub soscdiv: SOSCDIV,
#[doc = "0x108 - System Oscillator Configuration Register"] pub sosccfg: SOSCCFG,
_reserved2: [u8; 244usize],
#[doc = "0x200 - Slow IRC Control Status Register"]
pub sirccsr: SIRCCSR,
#[doc = "0x204 - Slow IRC Divide Register"]
pub sircdiv: SIRCDIV,
#[doc = "0x208 - Slow IRC Configuration Register"]
pub sirccfg: SIRCCFG,
#[doc = "0x200 - Slow IRC Control Status Register"] pub sirccsr: SIRCCSR,
#[doc = "0x204 - Slow IRC Divide Register"] pub sircdiv: SIRCDIV,
#[doc = "0x208 - Slow IRC Configuration Register"] pub sirccfg: SIRCCFG,
_reserved3: [u8; 244usize],
#[doc = "0x300 - Fast IRC Control Status Register"]
pub firccsr: FIRCCSR,
#[doc = "0x304 - Fast IRC Divide Register"]
pub fircdiv: FIRCDIV,
#[doc = "0x308 - Fast IRC Configuration Register"]
pub firccfg: FIRCCFG,
#[doc = "0x300 - Fast IRC Control Status Register"] pub firccsr: FIRCCSR,
#[doc = "0x304 - Fast IRC Divide Register"] pub fircdiv: FIRCDIV,
#[doc = "0x308 - Fast IRC Configuration Register"] pub firccfg: FIRCCFG,
_reserved4: [u8; 756usize],
#[doc = "0x600 - System PLL Control Status Register"]
pub spllcsr: SPLLCSR,
#[doc = "0x604 - System PLL Divide Register"]
pub splldiv: SPLLDIV,
#[doc = "0x608 - System PLL Configuration Register"]
pub spllcfg: SPLLCFG,
#[doc = "0x600 - System PLL Control Status Register"] pub spllcsr: SPLLCSR,
#[doc = "0x604 - System PLL Divide Register"] pub splldiv: SPLLDIV,
#[doc = "0x608 - System PLL Configuration Register"] pub spllcfg: SPLLCFG,
}
#[doc = "Version ID Register"]
pub struct VERID {

4
src/scg/param/mod.rs
View File

@ -6,7 +6,9 @@ impl super::PARAM {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

274
src/scg/rccr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RCCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,24 +45,15 @@ impl super::RCCR {
#[doc = "Possible values of the field `DIVSLOW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVSLOWR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DIVSLOWR {
#[doc = r" Value of the field as raw bits"]
@ -138,38 +131,22 @@ impl DIVSLOWR {
#[doc = "Possible values of the field `DIVBUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVBUSR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVBUSR {
#[doc = r" Value of the field as raw bits"]
@ -302,38 +279,22 @@ impl DIVBUSR {
#[doc = "Possible values of the field `DIVCORE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVCORER {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVCORER {
#[doc = r" Value of the field as raw bits"]
@ -466,16 +427,11 @@ impl DIVCORER {
#[doc = "Possible values of the field `SCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCSR {
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "System OSC (SOSC_CLK)"] _0001,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = "Fast IRC (FIRC_CLK)"] _0011,
#[doc = "System PLL (SPLL_CLK)"] _0110,
#[doc = r" Reserved"] _Reserved(u8),
}
impl SCSR {
#[doc = r" Value of the field as raw bits"]
@ -524,22 +480,14 @@ impl SCSR {
}
#[doc = "Values that can be written to the field `DIVSLOW`"]
pub enum DIVSLOWW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
}
impl DIVSLOWW {
#[allow(missing_docs)]
@ -620,38 +568,22 @@ impl<'a> _DIVSLOWW<'a> {
}
#[doc = "Values that can be written to the field `DIVBUS`"]
pub enum DIVBUSW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVBUSW {
#[allow(missing_docs)]
@ -782,38 +714,22 @@ impl<'a> _DIVBUSW<'a> {
}
#[doc = "Values that can be written to the field `DIVCORE`"]
pub enum DIVCOREW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVCOREW {
#[allow(missing_docs)]
@ -944,14 +860,10 @@ impl<'a> _DIVCOREW<'a> {
}
#[doc = "Values that can be written to the field `SCS`"]
pub enum SCSW {
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = "System OSC (SOSC_CLK)"] _0001,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = "Fast IRC (FIRC_CLK)"] _0011,
#[doc = "System PLL (SPLL_CLK)"] _0110,
}
impl SCSW {
#[allow(missing_docs)]

16
src/scg/sirccfg/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SIRCCFG {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::SIRCCFG {
#[doc = "Possible values of the field `RANGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RANGER {
#[doc = "Slow IRC low range clock (2 MHz)"]
_0,
#[doc = "Slow IRC high range clock (8 MHz )"]
_1,
#[doc = "Slow IRC low range clock (2 MHz)"] _0,
#[doc = "Slow IRC high range clock (8 MHz )"] _1,
}
impl RANGER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -89,10 +89,8 @@ impl RANGER {
}
#[doc = "Values that can be written to the field `RANGE`"]
pub enum RANGEW {
#[doc = "Slow IRC low range clock (2 MHz)"]
_0,
#[doc = "Slow IRC high range clock (8 MHz )"]
_1,
#[doc = "Slow IRC low range clock (2 MHz)"] _0,
#[doc = "Slow IRC high range clock (8 MHz )"] _1,
}
impl RANGEW {
#[allow(missing_docs)]

64
src/scg/sirccsr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SIRCCSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::SIRCCSR {
#[doc = "Possible values of the field `SIRCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCENR {
#[doc = "Slow IRC is disabled"]
_0,
#[doc = "Slow IRC is enabled"]
_1,
#[doc = "Slow IRC is disabled"] _0,
#[doc = "Slow IRC is enabled"] _1,
}
impl SIRCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl SIRCENR {
#[doc = "Possible values of the field `SIRCSTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCSTENR {
#[doc = "Slow IRC is disabled in supported Stop modes"]
_0,
#[doc = "Slow IRC is enabled in supported Stop modes"]
_1,
#[doc = "Slow IRC is disabled in supported Stop modes"] _0,
#[doc = "Slow IRC is enabled in supported Stop modes"] _1,
}
impl SIRCSTENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl SIRCSTENR {
#[doc = "Possible values of the field `SIRCLPEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCLPENR {
#[doc = "Slow IRC is disabled in VLP modes"]
_0,
#[doc = "Slow IRC is enabled in VLP modes"]
_1,
#[doc = "Slow IRC is disabled in VLP modes"] _0,
#[doc = "Slow IRC is enabled in VLP modes"] _1,
}
impl SIRCLPENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl SIRCLPENR {
#[doc = "Possible values of the field `LK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LKR {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
#[doc = "Control Status Register can be written."] _0,
#[doc = "Control Status Register cannot be written."] _1,
}
impl LKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl LKR {
#[doc = "Possible values of the field `SIRCVLD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCVLDR {
#[doc = "Slow IRC is not enabled or clock is not valid"]
_0,
#[doc = "Slow IRC is enabled and output clock is valid"]
_1,
#[doc = "Slow IRC is not enabled or clock is not valid"] _0,
#[doc = "Slow IRC is enabled and output clock is valid"] _1,
}
impl SIRCVLDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl SIRCVLDR {
#[doc = "Possible values of the field `SIRCSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCSELR {
#[doc = "Slow IRC is not the system clock source"]
_0,
#[doc = "Slow IRC is the system clock source"]
_1,
#[doc = "Slow IRC is not the system clock source"] _0,
#[doc = "Slow IRC is the system clock source"] _1,
}
impl SIRCSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -324,10 +314,8 @@ impl SIRCSELR {
}
#[doc = "Values that can be written to the field `SIRCEN`"]
pub enum SIRCENW {
#[doc = "Slow IRC is disabled"]
_0,
#[doc = "Slow IRC is enabled"]
_1,
#[doc = "Slow IRC is disabled"] _0,
#[doc = "Slow IRC is enabled"] _1,
}
impl SIRCENW {
#[allow(missing_docs)]
@ -382,10 +370,8 @@ impl<'a> _SIRCENW<'a> {
}
#[doc = "Values that can be written to the field `SIRCSTEN`"]
pub enum SIRCSTENW {
#[doc = "Slow IRC is disabled in supported Stop modes"]
_0,
#[doc = "Slow IRC is enabled in supported Stop modes"]
_1,
#[doc = "Slow IRC is disabled in supported Stop modes"] _0,
#[doc = "Slow IRC is enabled in supported Stop modes"] _1,
}
impl SIRCSTENW {
#[allow(missing_docs)]
@ -440,10 +426,8 @@ impl<'a> _SIRCSTENW<'a> {
}
#[doc = "Values that can be written to the field `SIRCLPEN`"]
pub enum SIRCLPENW {
#[doc = "Slow IRC is disabled in VLP modes"]
_0,
#[doc = "Slow IRC is enabled in VLP modes"]
_1,
#[doc = "Slow IRC is disabled in VLP modes"] _0,
#[doc = "Slow IRC is enabled in VLP modes"] _1,
}
impl SIRCLPENW {
#[allow(missing_docs)]
@ -498,10 +482,8 @@ impl<'a> _SIRCLPENW<'a> {
}
#[doc = "Values that can be written to the field `LK`"]
pub enum LKW {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
#[doc = "Control Status Register can be written."] _0,
#[doc = "Control Status Register cannot be written."] _1,
}
impl LKW {
#[allow(missing_docs)]

100
src/scg/sircdiv/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SIRCDIV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,22 +45,14 @@ impl super::SIRCDIV {
#[doc = "Possible values of the field `SIRCDIV1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCDIV1R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SIRCDIV1R {
#[doc = r" Value of the field as raw bits"]
@ -135,22 +129,14 @@ impl SIRCDIV1R {
#[doc = "Possible values of the field `SIRCDIV2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCDIV2R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SIRCDIV2R {
#[doc = r" Value of the field as raw bits"]
@ -226,22 +212,14 @@ impl SIRCDIV2R {
}
#[doc = "Values that can be written to the field `SIRCDIV1`"]
pub enum SIRCDIV1W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SIRCDIV1W {
#[allow(missing_docs)]
@ -324,22 +302,14 @@ impl<'a> _SIRCDIV1W<'a> {
}
#[doc = "Values that can be written to the field `SIRCDIV2`"]
pub enum SIRCDIV2W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SIRCDIV2W {
#[allow(missing_docs)]

49
src/scg/sosccfg/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SOSCCFG {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::SOSCCFG {
#[doc = "Possible values of the field `EREFS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EREFSR {
#[doc = "External reference clock selected"]
_0,
#[doc = "Internal crystal oscillator of OSC selected."]
_1,
#[doc = "External reference clock selected"] _0,
#[doc = "Internal crystal oscillator of OSC selected."] _1,
}
impl EREFSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl EREFSR {
#[doc = "Possible values of the field `HGO`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HGOR {
#[doc = "Configure crystal oscillator for low-gain operation"]
_0,
#[doc = "Configure crystal oscillator for high-gain operation"]
_1,
#[doc = "Configure crystal oscillator for low-gain operation"] _0,
#[doc = "Configure crystal oscillator for high-gain operation"] _1,
}
impl HGOR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,14 +135,10 @@ impl HGOR {
#[doc = "Possible values of the field `RANGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RANGER {
#[doc = "Low frequency range selected for the crystal oscillator"]
_01,
#[doc = "Medium frequency range selected for the crytstal oscillator"]
_10,
#[doc = "High frequency range selected for the crystal oscillator"]
_11,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Low frequency range selected for the crystal oscillator"] _01,
#[doc = "Medium frequency range selected for the crytstal oscillator"] _10,
#[doc = "High frequency range selected for the crystal oscillator"] _11,
#[doc = r" Reserved"] _Reserved(u8),
}
impl RANGER {
#[doc = r" Value of the field as raw bits"]
@ -186,10 +180,8 @@ impl RANGER {
}
#[doc = "Values that can be written to the field `EREFS`"]
pub enum EREFSW {
#[doc = "External reference clock selected"]
_0,
#[doc = "Internal crystal oscillator of OSC selected."]
_1,
#[doc = "External reference clock selected"] _0,
#[doc = "Internal crystal oscillator of OSC selected."] _1,
}
impl EREFSW {
#[allow(missing_docs)]
@ -244,10 +236,8 @@ impl<'a> _EREFSW<'a> {
}
#[doc = "Values that can be written to the field `HGO`"]
pub enum HGOW {
#[doc = "Configure crystal oscillator for low-gain operation"]
_0,
#[doc = "Configure crystal oscillator for high-gain operation"]
_1,
#[doc = "Configure crystal oscillator for low-gain operation"] _0,
#[doc = "Configure crystal oscillator for high-gain operation"] _1,
}
impl HGOW {
#[allow(missing_docs)]
@ -302,12 +292,9 @@ impl<'a> _HGOW<'a> {
}
#[doc = "Values that can be written to the field `RANGE`"]
pub enum RANGEW {
#[doc = "Low frequency range selected for the crystal oscillator"]
_01,
#[doc = "Medium frequency range selected for the crytstal oscillator"]
_10,
#[doc = "High frequency range selected for the crystal oscillator"]
_11,
#[doc = "Low frequency range selected for the crystal oscillator"] _01,
#[doc = "Medium frequency range selected for the crytstal oscillator"] _10,
#[doc = "High frequency range selected for the crystal oscillator"] _11,
}
impl RANGEW {
#[allow(missing_docs)]

76
src/scg/sosccsr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SOSCCSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::SOSCCSR {
#[doc = "Possible values of the field `SOSCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCENR {
#[doc = "System OSC is disabled"]
_0,
#[doc = "System OSC is enabled"]
_1,
#[doc = "System OSC is disabled"] _0,
#[doc = "System OSC is enabled"] _1,
}
impl SOSCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl SOSCENR {
#[doc = "Possible values of the field `SOSCCM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCCMR {
#[doc = "System OSC Clock Monitor is disabled"]
_0,
#[doc = "System OSC Clock Monitor is enabled"]
_1,
#[doc = "System OSC Clock Monitor is disabled"] _0,
#[doc = "System OSC Clock Monitor is enabled"] _1,
}
impl SOSCCMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl SOSCCMR {
#[doc = "Possible values of the field `SOSCCMRE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCCMRER {
#[doc = "Clock Monitor generates interrupt when error detected"]
_0,
#[doc = "Clock Monitor generates reset when error detected"]
_1,
#[doc = "Clock Monitor generates interrupt when error detected"] _0,
#[doc = "Clock Monitor generates reset when error detected"] _1,
}
impl SOSCCMRER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl SOSCCMRER {
#[doc = "Possible values of the field `LK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LKR {
#[doc = "This Control Status Register can be written."]
_0,
#[doc = "This Control Status Register cannot be written."]
_1,
#[doc = "This Control Status Register can be written."] _0,
#[doc = "This Control Status Register cannot be written."] _1,
}
impl LKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl LKR {
#[doc = "Possible values of the field `SOSCVLD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCVLDR {
#[doc = "System OSC is not enabled or clock is not valid"]
_0,
#[doc = "System OSC is enabled and output clock is valid"]
_1,
#[doc = "System OSC is not enabled or clock is not valid"] _0,
#[doc = "System OSC is enabled and output clock is valid"] _1,
}
impl SOSCVLDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl SOSCVLDR {
#[doc = "Possible values of the field `SOSCSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCSELR {
#[doc = "System OSC is not the system clock source"]
_0,
#[doc = "System OSC is the system clock source"]
_1,
#[doc = "System OSC is not the system clock source"] _0,
#[doc = "System OSC is the system clock source"] _1,
}
impl SOSCSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +315,8 @@ impl SOSCSELR {
#[doc = "Possible values of the field `SOSCERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCERRR {
#[doc = "System OSC Clock Monitor is disabled or has not detected an error"]
_0,
#[doc = "System OSC Clock Monitor is enabled and detected an error"]
_1,
#[doc = "System OSC Clock Monitor is disabled or has not detected an error"] _0,
#[doc = "System OSC Clock Monitor is enabled and detected an error"] _1,
}
impl SOSCERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -371,10 +359,8 @@ impl SOSCERRR {
}
#[doc = "Values that can be written to the field `SOSCEN`"]
pub enum SOSCENW {
#[doc = "System OSC is disabled"]
_0,
#[doc = "System OSC is enabled"]
_1,
#[doc = "System OSC is disabled"] _0,
#[doc = "System OSC is enabled"] _1,
}
impl SOSCENW {
#[allow(missing_docs)]
@ -429,10 +415,8 @@ impl<'a> _SOSCENW<'a> {
}
#[doc = "Values that can be written to the field `SOSCCM`"]
pub enum SOSCCMW {
#[doc = "System OSC Clock Monitor is disabled"]
_0,
#[doc = "System OSC Clock Monitor is enabled"]
_1,
#[doc = "System OSC Clock Monitor is disabled"] _0,
#[doc = "System OSC Clock Monitor is enabled"] _1,
}
impl SOSCCMW {
#[allow(missing_docs)]
@ -487,10 +471,8 @@ impl<'a> _SOSCCMW<'a> {
}
#[doc = "Values that can be written to the field `SOSCCMRE`"]
pub enum SOSCCMREW {
#[doc = "Clock Monitor generates interrupt when error detected"]
_0,
#[doc = "Clock Monitor generates reset when error detected"]
_1,
#[doc = "Clock Monitor generates interrupt when error detected"] _0,
#[doc = "Clock Monitor generates reset when error detected"] _1,
}
impl SOSCCMREW {
#[allow(missing_docs)]
@ -545,10 +527,8 @@ impl<'a> _SOSCCMREW<'a> {
}
#[doc = "Values that can be written to the field `LK`"]
pub enum LKW {
#[doc = "This Control Status Register can be written."]
_0,
#[doc = "This Control Status Register cannot be written."]
_1,
#[doc = "This Control Status Register can be written."] _0,
#[doc = "This Control Status Register cannot be written."] _1,
}
impl LKW {
#[allow(missing_docs)]
@ -603,10 +583,8 @@ impl<'a> _LKW<'a> {
}
#[doc = "Values that can be written to the field `SOSCERR`"]
pub enum SOSCERRW {
#[doc = "System OSC Clock Monitor is disabled or has not detected an error"]
_0,
#[doc = "System OSC Clock Monitor is enabled and detected an error"]
_1,
#[doc = "System OSC Clock Monitor is disabled or has not detected an error"] _0,
#[doc = "System OSC Clock Monitor is enabled and detected an error"] _1,
}
impl SOSCERRW {
#[allow(missing_docs)]

100
src/scg/soscdiv/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SOSCDIV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,22 +45,14 @@ impl super::SOSCDIV {
#[doc = "Possible values of the field `SOSCDIV1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCDIV1R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SOSCDIV1R {
#[doc = r" Value of the field as raw bits"]
@ -135,22 +129,14 @@ impl SOSCDIV1R {
#[doc = "Possible values of the field `SOSCDIV2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCDIV2R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SOSCDIV2R {
#[doc = r" Value of the field as raw bits"]
@ -226,22 +212,14 @@ impl SOSCDIV2R {
}
#[doc = "Values that can be written to the field `SOSCDIV1`"]
pub enum SOSCDIV1W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SOSCDIV1W {
#[allow(missing_docs)]
@ -324,22 +302,14 @@ impl<'a> _SOSCDIV1W<'a> {
}
#[doc = "Values that can be written to the field `SOSCDIV2`"]
pub enum SOSCDIV2W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Output disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SOSCDIV2W {
#[allow(missing_docs)]

4
src/scg/spllcfg/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SPLLCFG {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

70
src/scg/spllcsr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SPLLCSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::SPLLCSR {
#[doc = "Possible values of the field `SPLLEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLENR {
#[doc = "System PLL is disabled"]
_0,
#[doc = "System PLL is enabled"]
_1,
#[doc = "System PLL is disabled"] _0,
#[doc = "System PLL is enabled"] _1,
}
impl SPLLENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl SPLLENR {
#[doc = "Possible values of the field `SPLLCM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLCMR {
#[doc = "System PLL Clock Monitor is disabled"]
_0,
#[doc = "System PLL Clock Monitor is enabled"]
_1,
#[doc = "System PLL Clock Monitor is disabled"] _0,
#[doc = "System PLL Clock Monitor is enabled"] _1,
}
impl SPLLCMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl SPLLCMR {
#[doc = "Possible values of the field `SPLLCMRE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLCMRER {
#[doc = "Clock Monitor generates interrupt when error detected"]
_0,
#[doc = "Clock Monitor generates reset when error detected"]
_1,
#[doc = "Clock Monitor generates interrupt when error detected"] _0,
#[doc = "Clock Monitor generates reset when error detected"] _1,
}
impl SPLLCMRER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl SPLLCMRER {
#[doc = "Possible values of the field `LK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LKR {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
#[doc = "Control Status Register can be written."] _0,
#[doc = "Control Status Register cannot be written."] _1,
}
impl LKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl LKR {
#[doc = "Possible values of the field `SPLLVLD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLVLDR {
#[doc = "System PLL is not enabled or clock is not valid"]
_0,
#[doc = "System PLL is enabled and output clock is valid"]
_1,
#[doc = "System PLL is not enabled or clock is not valid"] _0,
#[doc = "System PLL is enabled and output clock is valid"] _1,
}
impl SPLLVLDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl SPLLVLDR {
#[doc = "Possible values of the field `SPLLSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLSELR {
#[doc = "System PLL is not the system clock source"]
_0,
#[doc = "System PLL is the system clock source"]
_1,
#[doc = "System PLL is not the system clock source"] _0,
#[doc = "System PLL is the system clock source"] _1,
}
impl SPLLSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,8 +315,7 @@ impl SPLLSELR {
#[doc = "Possible values of the field `SPLLERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLERRR {
#[doc = "System PLL Clock Monitor is disabled or has not detected an error"]
_0,
#[doc = "System PLL Clock Monitor is disabled or has not detected an error"] _0,
#[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."]
_1,
}
@ -371,10 +360,8 @@ impl SPLLERRR {
}
#[doc = "Values that can be written to the field `SPLLEN`"]
pub enum SPLLENW {
#[doc = "System PLL is disabled"]
_0,
#[doc = "System PLL is enabled"]
_1,
#[doc = "System PLL is disabled"] _0,
#[doc = "System PLL is enabled"] _1,
}
impl SPLLENW {
#[allow(missing_docs)]
@ -429,10 +416,8 @@ impl<'a> _SPLLENW<'a> {
}
#[doc = "Values that can be written to the field `SPLLCM`"]
pub enum SPLLCMW {
#[doc = "System PLL Clock Monitor is disabled"]
_0,
#[doc = "System PLL Clock Monitor is enabled"]
_1,
#[doc = "System PLL Clock Monitor is disabled"] _0,
#[doc = "System PLL Clock Monitor is enabled"] _1,
}
impl SPLLCMW {
#[allow(missing_docs)]
@ -487,10 +472,8 @@ impl<'a> _SPLLCMW<'a> {
}
#[doc = "Values that can be written to the field `SPLLCMRE`"]
pub enum SPLLCMREW {
#[doc = "Clock Monitor generates interrupt when error detected"]
_0,
#[doc = "Clock Monitor generates reset when error detected"]
_1,
#[doc = "Clock Monitor generates interrupt when error detected"] _0,
#[doc = "Clock Monitor generates reset when error detected"] _1,
}
impl SPLLCMREW {
#[allow(missing_docs)]
@ -545,10 +528,8 @@ impl<'a> _SPLLCMREW<'a> {
}
#[doc = "Values that can be written to the field `LK`"]
pub enum LKW {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
#[doc = "Control Status Register can be written."] _0,
#[doc = "Control Status Register cannot be written."] _1,
}
impl LKW {
#[allow(missing_docs)]
@ -603,8 +584,7 @@ impl<'a> _LKW<'a> {
}
#[doc = "Values that can be written to the field `SPLLERR`"]
pub enum SPLLERRW {
#[doc = "System PLL Clock Monitor is disabled or has not detected an error"]
_0,
#[doc = "System PLL Clock Monitor is disabled or has not detected an error"] _0,
#[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."]
_1,
}

100
src/scg/splldiv/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SPLLDIV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,22 +45,14 @@ impl super::SPLLDIV {
#[doc = "Possible values of the field `SPLLDIV1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLDIV1R {
#[doc = "Clock disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Clock disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SPLLDIV1R {
#[doc = r" Value of the field as raw bits"]
@ -135,22 +129,14 @@ impl SPLLDIV1R {
#[doc = "Possible values of the field `SPLLDIV2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLDIV2R {
#[doc = "Clock disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Clock disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SPLLDIV2R {
#[doc = r" Value of the field as raw bits"]
@ -226,22 +212,14 @@ impl SPLLDIV2R {
}
#[doc = "Values that can be written to the field `SPLLDIV1`"]
pub enum SPLLDIV1W {
#[doc = "Clock disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Clock disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SPLLDIV1W {
#[allow(missing_docs)]
@ -324,22 +302,14 @@ impl<'a> _SPLLDIV1W<'a> {
}
#[doc = "Values that can be written to the field `SPLLDIV2`"]
pub enum SPLLDIV2W {
#[doc = "Clock disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
#[doc = "Clock disabled"] _000,
#[doc = "Divide by 1"] _001,
#[doc = "Divide by 2"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 8"] _100,
#[doc = "Divide by 16"] _101,
#[doc = "Divide by 32"] _110,
#[doc = "Divide by 64"] _111,
}
impl SPLLDIV2W {
#[allow(missing_docs)]

256
src/scg/vccr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::VCCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,24 +45,15 @@ impl super::VCCR {
#[doc = "Possible values of the field `DIVSLOW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVSLOWR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DIVSLOWR {
#[doc = r" Value of the field as raw bits"]
@ -138,38 +131,22 @@ impl DIVSLOWR {
#[doc = "Possible values of the field `DIVBUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVBUSR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVBUSR {
#[doc = r" Value of the field as raw bits"]
@ -302,38 +279,22 @@ impl DIVBUSR {
#[doc = "Possible values of the field `DIVCORE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVCORER {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVCORER {
#[doc = r" Value of the field as raw bits"]
@ -466,10 +427,8 @@ impl DIVCORER {
#[doc = "Possible values of the field `SCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCSR {
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = r" Reserved"] _Reserved(u8),
}
impl SCSR {
#[doc = r" Value of the field as raw bits"]
@ -497,22 +456,14 @@ impl SCSR {
}
#[doc = "Values that can be written to the field `DIVSLOW`"]
pub enum DIVSLOWW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
}
impl DIVSLOWW {
#[allow(missing_docs)]
@ -593,38 +544,22 @@ impl<'a> _DIVSLOWW<'a> {
}
#[doc = "Values that can be written to the field `DIVBUS`"]
pub enum DIVBUSW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVBUSW {
#[allow(missing_docs)]
@ -755,38 +690,22 @@ impl<'a> _DIVBUSW<'a> {
}
#[doc = "Values that can be written to the field `DIVCORE`"]
pub enum DIVCOREW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVCOREW {
#[allow(missing_docs)]
@ -917,8 +836,7 @@ impl<'a> _DIVCOREW<'a> {
}
#[doc = "Values that can be written to the field `SCS`"]
pub enum SCSW {
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
}
impl SCSW {
#[allow(missing_docs)]

4
src/scg/verid/mod.rs
View File

@ -6,7 +6,9 @@ impl super::VERID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]